US20020135394A1 - Memory modules and methods having a buffer clock that operates at different clock frequencies according to the operating mode - Google Patents
Memory modules and methods having a buffer clock that operates at different clock frequencies according to the operating mode Download PDFInfo
- Publication number
- US20020135394A1 US20020135394A1 US10/094,448 US9444802A US2002135394A1 US 20020135394 A1 US20020135394 A1 US 20020135394A1 US 9444802 A US9444802 A US 9444802A US 2002135394 A1 US2002135394 A1 US 2002135394A1
- Authority
- US
- United States
- Prior art keywords
- output
- buffer
- during
- memory
- read
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/12015—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising clock generation or timing circuitry
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4076—Timing circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/1201—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising I/O circuitry
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/14—Implementation of control logic, e.g. test mode decoders
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
Definitions
- the present invention relates to integrated circuit devices and methods of operating the same and, more particularly, to memory modules and methods of testing the same.
- a conventional memory module may include both memory devices and one or more data buffers and may operate at a double data rate (DDR). If the data rate of data input into the data buffer is different from that of the data output from the data buffer, the frequency of an operating clock for the data buffer may be different from the frequency of an operating clock for the memory devices during a normal mode of operation. Typically, during a normal mode operation, the frequency of the operating clock for the data buffer is at least twice the frequency of the operating clock for the memory devices.
- DDR double data rate
- a tester may need to operate using the frequency of the operating clock for the data buffer, thus, a high speed tester is typically used.
- a high speed tester may increase test costs and, therefore, increasing the manufacturing costs of a memory module.
- a block diagram illustrating a conventional memory module will be discussed.
- the frequency of a buffer clock signal CK_BUFFER which is an operating clock for a data buffer 15
- CK_MEMORY which is an operating clock for first and second memory devices 11 and 13 during a normal mode of operation.
- the conventional memory module 100 includes first and second Dynamic Random Access Memories (DRAMs) 11 and 13 and a data buffer 15 .
- the first and second DRAMs 11 and 13 input and/or output data in response to a memory clock signal CK_MEMORY.
- the data buffer 15 buffers write data input using an input/output pin DQ, and outputs the write data to the first and second DRAMs 11 and 13 in response to a buffer clock signal CK_BUFFER during a normal mode of operation.
- the data buffer 15 also buffers read data output from the first and second DRAMs 11 and 13 and outputs the read data to the input/output pin DQ in response to a buffer clock CK_BUFFER during a normal mode of operation.
- the data buffer 15 includes first through fourth registers ( 151 - 154 ), first through fourth delay units ( 155 - 158 ), and a multiplexer 159 .
- the first register 151 samples the write data input through the input/output pin DQ in response to a rising edge of the buffer clock CK_BUFFER
- the second register 152 samples the write data input through the input/output pin DQ in response to a falling edge of the buffer clock CK_BUFFER.
- FIG. 2 a timing diagram illustrating write operations of the memory module of FIG. 1, write data DI 0 and DI 2 is output REG 0 _Q from the first register 151 , and the write data DI 1 and DI 3 is output REG 1 _Q from the second register 152 .
- Output REG 0 _Q of the first register 151 is delayed 11 ⁇ 2 cycles of the buffer clock CK_BUFFER by a first delay unit 155 , and delayed data MIO 0 _Q is input into the first DRAM 11 at a rising and/or falling edge of the memory clock signal CK_MEMORY.
- output REG 1 _Q of the second register 152 is delayed 1 cycle of the buffer clock CK_BUFFER by a second delay unit 156 , and delayed data MIO 1 _Q is input into the second DRAM 13 at a rising and/or falling edge of the memory clock signal CK_MEMORY.
- read data MIO 0 _Q i.e., DO 0 and DO 2
- read data MIO 1 _Q i.e., DO 1 and DO 3
- Read data DO 0 and DO 2 is delayed 1 ⁇ 2 a cycle of the buffer clock CK_BUFFER by a third delay unit 157
- read data DO 1 and DO 3 is delayed 1 cycle of the buffer clock CK_BUFFER by a fourth delay unit 158 .
- Output REG 2 _D of the third delay unit 157 is sampled as output REG 2 _Q at a rising edge of the buffer clock CK_BUFFER by the third register 153 , and output REG 3 _D is sampled as output REG 3 _Q at a falling edge of the buffer clock CK_BUFFER by the fourth register 154 .
- the multiplexer 159 selects output REG 2 _Q at a rising edge of the buffer clock CK_BUFFER or output REG 3 _Q at a falling edge of the buffer clock CK_BUFFER and outputs REG 2 _Q or REG 3 _Q to the input/output pin DQ.
- the tester in order to test conventional memory modules, for example, the memory module of FIG. 1, the tester typically operates using the frequency of the buffer clock CK_BUFFER.
- the frequency of the buffer clock CK_BUFFER is typically at least twice the frequency of the memory clock signal CK_MEMORY, thus, a high-speed tester is typically used.
- the use of a high speed tester for a conventional memory module may increase test costs and, therefore, increasing the manufacturing costs of a memory module.
- Embodiments of the present invention provide memory modules and methods of testing memory modules.
- Memory modules according to embodiments of the present invention include at least one memory device responsive to a memory clock signal having a memory clock frequency and a data buffer.
- the data buffer is responsive to a buffer clock signal having a first buffer clock frequency that is different from the memory clock frequency during a normal mode of operation and having a second buffer clock frequency that is the same as the memory clock frequency during a test mode of operation.
- the first buffer clock frequency is at least double the memory clock frequency.
- Memory modules may include a plurality of memory devices and the data buffer may be configured to test each of the plurality of memory devices separately or simultaneously during the test mode of operation.
- the data buffer may include a write circuit and a read circuit.
- the write circuit may include a plurality of write registers responsive to a rising and/or falling edge of the first buffer clock signal and a plurality of write control buffers that transmit a plurality of write signals from the plurality of write registers.
- the write circuit may further include a write switch that couples and/or decouples the plurality of write control buffers responsive to a test enable signal and a plurality of write delay units that delay the plurality of write signals.
- the write circuit may include a plurality of write selectors that select a first of the plurality of write delay units during the normal mode of operation and select a second of the plurality of write delay units during the test mode of operation.
- the read circuit may include a plurality of read delay units that receive a plurality of read signals from the plurality of memory devices and a plurality of read selectors that select a first of the plurality of read delay units during normal mode of operation and select a second of the plurality of read delays units during test mode of operation.
- the read circuit may further comprise a plurality of read control buffers that transmit the plurality of read signals from the plurality of read selectors and a read switch that couples and/or decouples the plurality of read control buffers in response to the test enable signal.
- the read circuit may finally include a plurality of read registers that receives the plurality of read signals from the plurality of read control buffers responsive to the rising edge and/or the falling edge of the first buffer clock signal.
- the data buffer may include a write circuit and a read circuit.
- the write circuit may include a plurality of write registers responsive to a rising and/or falling edge of the first buffer clock signal and a plurality of write control buffers that transmit a plurality of write signals from the plurality of write registers.
- the write circuit may further include a switch that couples and/or decouples the plurality of write control buffers responsive to a test enable signal and a plurality of write delay units that delay the plurality of write signals.
- the write circuit may finally include a plurality of write selectors that select a first of the plurality of write delay units during the normal mode of operation and select a second of the plurality of write delay units during the test mode of operation.
- the read circuit may include a plurality of read delay units that receive a plurality of read signals from the plurality of memory devices and a first plurality of read selectors that select a first of the plurality of read delay units during normal mode of operation and select a second of the plurality of read delays units during test mode of operation.
- the read circuit may further include a device the performs a boolean operation on the plurality of read signals from the plurality of read selectors and a second plurality of read selectors that select an output of the device.
- the read circuit may finally include a plurality of read registers that receives the output of the device from the second plurality of read selectors.
- a method of testing memory modules including setting a frequency of a buffer clock signal equal to a frequency of a memory clock signal during a test mode of operation of the memory module.
- the frequency of the buffer clock signal is at least double the frequency of the memory clock signal during a normal mode of operation.
- FIG. 1 a block diagram illustrating a conventional memory module
- FIG. 2 is a timing diagram illustrating a write operation of the conventional memory module of FIG. 1;
- FIG. 3 is a timing diagram illustrating a read operation in the conventional memory module of FIG. 1;
- FIG. 4 is a block diagram illustrating memory modules according to embodiments of the present invention.
- FIG. 5 is a timing diagram illustrating a write operation of a test mode of operation in memory modules of FIG. 4 according to embodiments of the present invention
- FIG. 6 is a timing diagram illustrating a read operation of the test mode of operation in memory modules of FIG. 4 according to embodiments of the present invention
- FIG. 7 is a block diagram illustrating memory modules according to further embodiments of the present invention.
- FIG. 8 is a timing diagram illustrating a write operation of the test mode of operation in memory modules of FIG. 7 according to embodiments of the present invention.
- FIGS. 4 through 8 illustrate various embodiments of the present invention and various methods of testing embodiments of the present invention.
- Memory modules are provided that have the capability of operating in both a normal mode of operation and a test mode of operation.
- the frequency of a buffer clock may be set equal to the frequency of a memory clock.
- the memory clock typically operates at a frequency of about half the buffer clock frequency, thus, embodiments of the present invention may provide the capability of testing the memory module at lower speeds than typically available in conventional memory modules.
- memory modules 400 include first and second memory devices 41 and 43 , and a data buffer 45 .
- first and second memory devices 41 and 43 may be, for example, dynamic random access memories (DRAMs) and may input and/or output data in response to a memory clock signal CK_MEMORY.
- DRAMs dynamic random access memories
- the data buffer 45 buffers write data input through an input/output pin DQ, and outputs the write data to the first and second memory devices 41 and 43 in response to a buffer clock signal CK_BUFFER during a normal mode of operation.
- the data buffer 45 also buffers read data output from the first and second memory devices 41 and 43 and outputs the read data to the input/output pin DQ in response to a buffer clock signal CK_BUFFER during the normal mode of operation.
- the data buffer 45 may include a control circuit capable of operating the first and second memory devices 41 and 43 . Furthermore, the data buffer 45 may use the same clock frequency to test the first and second memory devices 41 and 43 during a test mode of operation.
- the data buffer 45 of FIG. 4 includes first through fourth registers ( 451 - 454 ), first through fourth control buffers ( 456 - 459 ), first through eighth delay units ( 460 - 467 ), first and second switches SW 0 and SW 1 , and first through fifth selectors ( 468 - 472 ) also referred to as multiplexers (MUX).
- MUX multiplexers
- First and second registers 451 and 452 , the first and second control buffer 456 and 457 , the first through fourth delay units ( 460 - 463 ), the first switch SW 0 , and the first and second selectors 468 and 469 are used during a write operation.
- third and fourth registers 453 and 454 , the third and fourth control buffers 458 and 459 , fifth through eighth delay units ( 464 - 467 ), the second switch SW 1 , and the third through fifth selectors ( 470 - 472 ) are used during a read operation.
- the first register 451 samples write data input through an input/output pin DQ in response to a rising edge of the buffer clock signal CK_BUFFER, and the second register 452 samples the write data in response to a falling edge of the buffer clock signal CK_BUFFER.
- the first control buffer 456 is typically enabled during the normal mode of operation when a test enable signal TEST is a logic “low”, and transmits an output of the first register 451 . Furthermore, the first control buffer 456 is enabled during the test mode of operation when the buffer clock signal CK_BUFFER is a logic “low, i.e., in a case where the test enable signal TEST is logic “high”, and transmits the output of the first register 451 .
- the first control buffer 456 includes an OR gate 456 a for receiving an inverted signal of a test enable signal TEST and an inverted signal of the buffer clock signal CK_BUFFER and includes a tri-state buffer 456 b.
- the second control buffer 457 is typically enabled during the normal mode of operation and transmits an output of the second register 452 . Furthermore, the second control buffer 457 is enabled during the test mode of operation when the buffer clock signal CK_BUFFER is logic “high” and transmits the output of the second register 452 .
- the second control buffer 457 includes an OR gate 457 a for receiving an inverted signal of the test enable signal TEST and the buffer clock signal CK_BUFFER and includes a tri-state buffer 457 b.
- the first switch SW 0 connects an output terminal of the first control buffer 456 to an output terminal of the second control buffer 457 during the test mode of operation, i.e., when the test enable signal TEST is logic “high”.
- Each of the first delay unit 460 and the second delay unit 461 delays a signal of the output terminal of the first control buffer 456 .
- the first selector 468 selects an output signal of the first delay unit 460 during the normal mode of operation and selects an output signal of the second delay unit 461 during the test mode of operation to output the selected output signal to the first memory device 41 .
- the third delay unit 462 and the fourth delay unit 463 delays a signal of the output terminal of the first control buffer 457 .
- the second selector 469 selects an output signal of the third delay unit 462 during the normal mode of operation and selects an output signal of the fourth delay unit 463 during the test mode of operation to output the selected output signal to the second memory device 43 .
- the fifth delay unit 464 and the sixth delay unit 465 delay read data output from the first memory device 41 .
- the third selector 470 selects an output signal of the fifth delay unit 464 during the normal mode of operation and selects an output signal of the sixth delay unit 465 during the test mode of operation.
- the third control buffer 458 is typically enabled during the normal mode of operation and transmits an output of the third selector 470 .
- the third control buffer 458 is enabled during a test mode of operation when a predetermined control signal IDSEL is logic “high” and transmits the output of the third selector 470 .
- the third control buffer 458 includes an OR gate 458 a for receiving an inverted signal of the test enable signal TEST and the predetermined control signal IDSEL and further includes a tri-state buffer 458 b.
- the seventh delay unit 466 and the eighth delay unit 467 delay read data output from the second memory device 43 .
- the fourth selector 471 selects an output signal of the seventh delay unit 466 during the normal mode of operation and selects an output signal of the eighth delay unit 467 during the test mode of operation.
- the fourth control buffer 459 is enabled during the normal mode of operation and transmits an output of the fourth selector 471 .
- the fourth control buffer 459 is enable during the test mode of operation when the control signal IDSEL is logic “low” and transmits the output of the fourth selector 471 .
- the fourth control buffer 459 includes an OR gate 459 a for receiving an inverted signal of the test enable signal TEST and an inverted signal of the predetermined control signal IDSEL and further includes a tri-state buffer 459 b.
- the second switch SW 1 connects an output terminal of the third control buffer 458 to an output terminal of the fourth control buffer 459 during the test mode of operation.
- the third register 453 samples a signal of the output terminal of the third control buffer 458 in response to a rising edge of the buffer clock signal CK_BUFFER
- the fourth register 454 samples a signal of the output terminal of the fourth control buffer 459 in response to a falling edge of the buffer clock signal CK_BUFFER.
- the fifth selector 472 selects an output of the third register 453 at a rising edge of the buffer clock signal CK_BUFFER and selects an output of the fourth register 454 at a falling edge of the buffer clock signal CK_BUFFER.
- the test enable signal TEST is logic “low”.
- the first through fourth control buffers ( 456 - 459 ) are enabled, and the first and second switches SW 0 and SW 1 are turned off.
- Output signals of the first, third, fifth, and seventh delay units 460 , 462 , 464 , and 466 are selected by the first through fourth selectors ( 468 - 471 ).
- the normal mode of operation of memory modules according to embodiments of the present invention may be similar to the normal mode of operation of conventional devices.
- FIG. 5 a timing diagram illustrating write operations of memory modules according to embodiments of the present invention, for example, memory modules 400 of FIG. 4, will be discussed further below.
- the test enable signal TEST is logic “high”.
- the first and second switches SW 0 and SW 1 are turned on.
- the output signals of the second, fourth, sixth, and eighth delay units 461 , 463 , 465 , and 467 are selected by the first through fourth selectors ( 468 - 471 ).
- the first register 451 samples write data input through the input/output pin DQ in response to a rising edge of the buffer clock signal CK_BUFFER
- the second register 452 samples the write data input through the input/output pin DQ in response to a falling edge of the buffer clock signal CK_BUFFER.
- the write data DI 0 and DI 2 is the output REG 0 _Q of the first register 451
- the write data DI 1 and DI 3 is output REG 1 _Q of the second register 452 .
- the first control buffer 456 transmits the output REG 0 _Q of the first register 451 to output B 0 _OUT when the buffer clock signal CK_BUFFER is logic “low” during the test mode of operation
- the second control buffer 457 transmits the output REG 1 _Q of the second register 457 to output B 1 _OUT when the buffer clock signal CK_BUFFER is logic “high” during the test mode of operation.
- the first switch SW 0 is turned on and connects the output terminal of the first control buffer 456 to the output of the second control buffer 457 and, thus, the output B 0 _OUT of the first control buffer 456 is merged into the output B 1 _OUT of the second control buffer 457 .
- Merged data SW 0 _Q is delayed 1 ⁇ 4 of a cycle of the buffer clock signal CK_BUFFER through the second delay unit 461 , and delayed data MIO 0 _Q is input into the first memory device 41 at a rising and/or falling edge of the memory clock signal CK_MEMORY. Furthermore, the merged data SW 0 _Q is delayed 1 ⁇ 4 of a cycle of the buffer clock signal CK_BUFFER through the fourth delay unit 463 , and delayed data MIO 1 _Q is input into the second memory device 43 at a rising and/or falling edge of the memory clock signal CK_MEMORY.
- Read data MIO 0 _Q is output from the first memory device 41 at a rising and/or falling edge of the memory clock signal CK_MEMORY, and the read data MIO 1 _Q is output from the second memory device 43 at a rising and/or falling edge of the memory clock signal CK_MEMORY.
- the read data MIO 0 _Q is delayed 3 ⁇ 4 of a cycle of the buffer clock signal CK_BUFFER through the sixth delay unit 465
- the read data MIO 1 _Q is delayed 3 ⁇ 4 of a cycle of the buffer clock signal CK_BUFFER through the eighth delay unit 467 .
- control signal IDSEL When the control signal IDSEL is logic “high”, the third control buffer 458 is enabled, and the fourth control buffer 459 is disabled. Thus, only the data MIO 0 _Q read from the first memory device 41 is output to the input/output pin DQ.
- control signal IDSEL When the control signal IDSEL is logic “low”, the third control buffer 458 is disabled, and the fourth control buffer 459 is enabled. Thus, only the data MIO 1 _Q read from the second memory device 43 is output to the input/output pin DQ.
- output of the sixth delay unit 465 is an input signal REG 2 _D of the third register 453 through the selector 470 and the third control buffer 458 .
- the second switch SW 1 is turned on, and thus the output of the sixth delay unit 465 is an input signal REG 3 _D of the fourth register 454 .
- output of the eighth delay unit 467 is an input signal REG 3 _D of the fourth register 454 through the selector 471 and the fourth control buffer 459 .
- the second switch SW 1 is turned on, and thus the output of the eighth delay unit 467 is an input signal REG 2 _D of the third register 453 .
- the input signal REG 2 _D is sampled as output REG 2 _Q at a rising edge of the buffer clock signal CK_BUFFER by the third register 453
- the input signal REG 3 _D is sampled as output REG 3 _Q at a falling edge of the buffer clock signal CK_BUFFER by the fourth register 454 .
- the fifth selector 472 selects the output REG 2 _Q at a rising edge of the buffer clock signal CK_BUFFER, selects the output REG 3 _Q at a falling edge of the buffer clock signal CK_BUFFER, and thus outputs REG 2 _Q and REG 3 _Q to the input/output pin DQ.
- Memory modules according embodiments of the present invention described above can be tested by setting the frequency of the buffer clock signal CK_BUFFER equal to the frequency of the memory clock signal CK_MEMORY during the test mode of operation.
- the first and second memory devices 41 and 43 can be separately tested, but may not be simultaneously tested in these embodiments.
- the memory module 700 includes first and second memory devices 41 and 43 , and a data buffer 75 .
- the data buffer 75 includes an exclusive NOR gate 751 and selectors 752 and 753 in place of the third and fourth control buffers 458 and 459 and the second switch SW 1 included in the embodiment of FIG. 4.
- Like reference numerals throughout the drawings refer to the like elements with respect to the memory module of FIG. 4.
- write operations in a normal mode of operation are the same as the operations discussed with respect to FIG. 4, thus, a description of these operations will be omitted.
- the selector 752 selects an output signal of the fifth delay unit 464 selected by the selector 470 and outputs the output signal of the fifth delay unit 464 to the third register 453
- the selector 753 selects an output signal of the seventh delay unit 466 selected by the selector 471 and outputs the output signal of the seventh delay unit 466 to the fourth register 454 .
- the exclusive NOR gate 751 performs an exclusive NOR operation on an output signal of the sixth delay unit 465 selected by the selector 470 and an output signal of the eighth delay unit 467 selected by the selector 471 .
- the selector 752 and the selector 753 select an output signal of the exclusive NOR gate 751 and outputs the signal of the exclusive NOR gate 751 to the third register 453 and the fourth register 454 .
- FIG. 8 a timing diagram illustrating operations of memory modules of FIG. 7 will be discussed below.
- an output signal D 5 _OUT of the sixth delay unit 465 which delays data MIO 0 _Q read from the first memory device 41
- an output signal D 7 _OUT of the eighth delay unit 467 which delays data MIO 1 _Q read from the second memory device 43
- the output of the exclusive NOR gate 751 is logic “high”. Otherwise, the output of the exclusive NOR gate 751 is logic “low”.
- a value finally output to the input/output pin DQ is logic “low”, it may be determined that a memory cell corresponding to the values is defective.
- embodiments of the present invention illustrated in FIG. 7 may be tested by setting the frequency of the buffer clock signal CK_BUFFER to be the same as that of the memory clock signal CK_MEMORY during the test mode of operation and the first and second memory devices 41 and 43 may be simultaneously tested.
- memory modules and methods of testing memory modules provide both a normal mode of operation and a test mode of operation.
- the frequency of a buffer clock which is typically at least 2 times the frequency of a memory clock, may be set equal to the frequency of the memory clock signal.
- the test may be performed at a fairly low speed.
- memory modules may be tested and manufactured at a reduced cost.
Abstract
Description
- This application is related to and claims priority from Korean Application No. 2001-12248, filed Mar. 9, 2001, the disclosure of which is hereby incorporated herein by reference.
- The present invention relates to integrated circuit devices and methods of operating the same and, more particularly, to memory modules and methods of testing the same.
- A conventional memory module may include both memory devices and one or more data buffers and may operate at a double data rate (DDR). If the data rate of data input into the data buffer is different from that of the data output from the data buffer, the frequency of an operating clock for the data buffer may be different from the frequency of an operating clock for the memory devices during a normal mode of operation. Typically, during a normal mode operation, the frequency of the operating clock for the data buffer is at least twice the frequency of the operating clock for the memory devices.
- Accordingly, in order to test the memory devices in a test mode of operation, a tester may need to operate using the frequency of the operating clock for the data buffer, thus, a high speed tester is typically used. However, the use of a high speed tester may increase test costs and, therefore, increasing the manufacturing costs of a memory module.
- Referring now to FIG. 1, a block diagram illustrating a conventional memory module will be discussed. In a conventional memory module the frequency of a buffer clock signal CK_BUFFER, which is an operating clock for a
data buffer 15, may be twice the frequency of a memory clock signal CK_MEMORY, which is an operating clock for first andsecond memory devices - As illustrated in FIG. 1, the
conventional memory module 100 includes first and second Dynamic Random Access Memories (DRAMs) 11 and 13 and adata buffer 15. The first andsecond DRAMs data buffer 15 buffers write data input using an input/output pin DQ, and outputs the write data to the first andsecond DRAMs data buffer 15 also buffers read data output from the first andsecond DRAMs data buffer 15 includes first through fourth registers (151-154), first through fourth delay units (155-158), and amultiplexer 159. - During a write operation, the
first register 151 samples the write data input through the input/output pin DQ in response to a rising edge of the buffer clock CK_BUFFER, and thesecond register 152 samples the write data input through the input/output pin DQ in response to a falling edge of the buffer clock CK_BUFFER. As shown in FIG. 2, a timing diagram illustrating write operations of the memory module of FIG. 1, write data DI0 and DI2 is output REG0_Q from thefirst register 151, and the write data DI1 and DI3 is output REG1_Q from thesecond register 152. - Output REG0_Q of the
first register 151 is delayed 1½ cycles of the buffer clock CK_BUFFER by afirst delay unit 155, and delayed data MIO0_Q is input into thefirst DRAM 11 at a rising and/or falling edge of the memory clock signal CK_MEMORY. Similarly, output REG1_Q of thesecond register 152 is delayed 1 cycle of the buffer clock CK_BUFFER by asecond delay unit 156, and delayed data MIO1_Q is input into thesecond DRAM 13 at a rising and/or falling edge of the memory clock signal CK_MEMORY. - Now referring to FIG. 3, a timing diagram of a read operation of the memory module of FIG. 1 will be discussed. During a read operation, read data MIO0_Q, i.e., DO0 and DO2, is output from the
first DRAM 11 at a rising and/or falling edge of the memory clock signal CK_MEMORY, and read data MIO1_Q, i.e., DO1 and DO3, is output from thesecond DRAM 13. Read data DO0 and DO2 is delayed ½ a cycle of the buffer clock CK_BUFFER by athird delay unit 157, and read data DO1 and DO3 is delayed 1 cycle of the buffer clock CK_BUFFER by afourth delay unit 158. - Output REG2_D of the
third delay unit 157 is sampled as output REG2_Q at a rising edge of the buffer clock CK_BUFFER by thethird register 153, and output REG3_D is sampled as output REG3_Q at a falling edge of the buffer clock CK_BUFFER by thefourth register 154. Themultiplexer 159 selects output REG2_Q at a rising edge of the buffer clock CK_BUFFER or output REG3_Q at a falling edge of the buffer clock CK_BUFFER and outputs REG2_Q or REG3_Q to the input/output pin DQ. - As described above, in order to test conventional memory modules, for example, the memory module of FIG. 1, the tester typically operates using the frequency of the buffer clock CK_BUFFER. However, the frequency of the buffer clock CK_BUFFER is typically at least twice the frequency of the memory clock signal CK_MEMORY, thus, a high-speed tester is typically used. The use of a high speed tester for a conventional memory module may increase test costs and, therefore, increasing the manufacturing costs of a memory module.
- Embodiments of the present invention provide memory modules and methods of testing memory modules. Memory modules according to embodiments of the present invention include at least one memory device responsive to a memory clock signal having a memory clock frequency and a data buffer. The data buffer is responsive to a buffer clock signal having a first buffer clock frequency that is different from the memory clock frequency during a normal mode of operation and having a second buffer clock frequency that is the same as the memory clock frequency during a test mode of operation.
- In some embodiments of the present invention the first buffer clock frequency is at least double the memory clock frequency. Memory modules may include a plurality of memory devices and the data buffer may be configured to test each of the plurality of memory devices separately or simultaneously during the test mode of operation.
- In further embodiments of the present invention the data buffer may include a write circuit and a read circuit. The write circuit may include a plurality of write registers responsive to a rising and/or falling edge of the first buffer clock signal and a plurality of write control buffers that transmit a plurality of write signals from the plurality of write registers. The write circuit may further include a write switch that couples and/or decouples the plurality of write control buffers responsive to a test enable signal and a plurality of write delay units that delay the plurality of write signals. Finally the write circuit may include a plurality of write selectors that select a first of the plurality of write delay units during the normal mode of operation and select a second of the plurality of write delay units during the test mode of operation.
- The read circuit may include a plurality of read delay units that receive a plurality of read signals from the plurality of memory devices and a plurality of read selectors that select a first of the plurality of read delay units during normal mode of operation and select a second of the plurality of read delays units during test mode of operation. The read circuit may further comprise a plurality of read control buffers that transmit the plurality of read signals from the plurality of read selectors and a read switch that couples and/or decouples the plurality of read control buffers in response to the test enable signal. The read circuit may finally include a plurality of read registers that receives the plurality of read signals from the plurality of read control buffers responsive to the rising edge and/or the falling edge of the first buffer clock signal.
- In still further embodiments of the present invention, the data buffer may include a write circuit and a read circuit. The write circuit may include a plurality of write registers responsive to a rising and/or falling edge of the first buffer clock signal and a plurality of write control buffers that transmit a plurality of write signals from the plurality of write registers. The write circuit may further include a switch that couples and/or decouples the plurality of write control buffers responsive to a test enable signal and a plurality of write delay units that delay the plurality of write signals. The write circuit may finally include a plurality of write selectors that select a first of the plurality of write delay units during the normal mode of operation and select a second of the plurality of write delay units during the test mode of operation.
- The read circuit may include a plurality of read delay units that receive a plurality of read signals from the plurality of memory devices and a first plurality of read selectors that select a first of the plurality of read delay units during normal mode of operation and select a second of the plurality of read delays units during test mode of operation. The read circuit may further include a device the performs a boolean operation on the plurality of read signals from the plurality of read selectors and a second plurality of read selectors that select an output of the device. The read circuit may finally include a plurality of read registers that receives the output of the device from the second plurality of read selectors.
- In some embodiments of the present invention a method of testing memory modules is provided including setting a frequency of a buffer clock signal equal to a frequency of a memory clock signal during a test mode of operation of the memory module. The frequency of the buffer clock signal is at least double the frequency of the memory clock signal during a normal mode of operation.
- FIG. 1 a block diagram illustrating a conventional memory module;
- FIG. 2 is a timing diagram illustrating a write operation of the conventional memory module of FIG. 1;
- FIG. 3 is a timing diagram illustrating a read operation in the conventional memory module of FIG. 1;
- FIG. 4 is a block diagram illustrating memory modules according to embodiments of the present invention;
- FIG. 5 is a timing diagram illustrating a write operation of a test mode of operation in memory modules of FIG. 4 according to embodiments of the present invention;
- FIG. 6 is a timing diagram illustrating a read operation of the test mode of operation in memory modules of FIG. 4 according to embodiments of the present invention;
- FIG. 7 is a block diagram illustrating memory modules according to further embodiments of the present invention; and
- FIG. 8 is a timing diagram illustrating a write operation of the test mode of operation in memory modules of FIG. 7 according to embodiments of the present invention.
- The present invention now will be described more fully with reference to the accompanying drawings, in which embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art. In the drawings, when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present. Like reference numerals refer to like elements throughout.
- Embodiments of the present invention will now be described in detail below with reference to FIGS. 4 through 8, which illustrate various embodiments of the present invention and various methods of testing embodiments of the present invention. Memory modules are provided that have the capability of operating in both a normal mode of operation and a test mode of operation. During the test mode of operation, the frequency of a buffer clock may be set equal to the frequency of a memory clock. The memory clock typically operates at a frequency of about half the buffer clock frequency, thus, embodiments of the present invention may provide the capability of testing the memory module at lower speeds than typically available in conventional memory modules.
- Now referring to FIG. 4, memory modules according to a embodiments of the present invention will be discussed. As illustrated,
memory modules 400 according to the embodiments of the present invention include first andsecond memory devices second memory devices second memory devices second memory devices - The data buffer45 may include a control circuit capable of operating the first and
second memory devices second memory devices second registers second control buffer second selectors fourth registers - The
first register 451 samples write data input through an input/output pin DQ in response to a rising edge of the buffer clock signal CK_BUFFER, and thesecond register 452 samples the write data in response to a falling edge of the buffer clock signal CK_BUFFER. - The
first control buffer 456 is typically enabled during the normal mode of operation when a test enable signal TEST is a logic “low”, and transmits an output of thefirst register 451. Furthermore, thefirst control buffer 456 is enabled during the test mode of operation when the buffer clock signal CK_BUFFER is a logic “low, i.e., in a case where the test enable signal TEST is logic “high”, and transmits the output of thefirst register 451. Thefirst control buffer 456 includes an ORgate 456 a for receiving an inverted signal of a test enable signal TEST and an inverted signal of the buffer clock signal CK_BUFFER and includes atri-state buffer 456 b. - The
second control buffer 457 is typically enabled during the normal mode of operation and transmits an output of thesecond register 452. Furthermore, thesecond control buffer 457 is enabled during the test mode of operation when the buffer clock signal CK_BUFFER is logic “high” and transmits the output of thesecond register 452. Thesecond control buffer 457 includes an ORgate 457 a for receiving an inverted signal of the test enable signal TEST and the buffer clock signal CK_BUFFER and includes atri-state buffer 457 b. - The first switch SW0 connects an output terminal of the
first control buffer 456 to an output terminal of thesecond control buffer 457 during the test mode of operation, i.e., when the test enable signal TEST is logic “high”. Each of thefirst delay unit 460 and thesecond delay unit 461 delays a signal of the output terminal of thefirst control buffer 456. Thefirst selector 468 selects an output signal of thefirst delay unit 460 during the normal mode of operation and selects an output signal of thesecond delay unit 461 during the test mode of operation to output the selected output signal to thefirst memory device 41. - The
third delay unit 462 and thefourth delay unit 463 delays a signal of the output terminal of thefirst control buffer 457. Thesecond selector 469 selects an output signal of thethird delay unit 462 during the normal mode of operation and selects an output signal of thefourth delay unit 463 during the test mode of operation to output the selected output signal to thesecond memory device 43. - The
fifth delay unit 464 and thesixth delay unit 465 delay read data output from thefirst memory device 41. Thethird selector 470 selects an output signal of thefifth delay unit 464 during the normal mode of operation and selects an output signal of thesixth delay unit 465 during the test mode of operation. - The
third control buffer 458 is typically enabled during the normal mode of operation and transmits an output of thethird selector 470. Thethird control buffer 458 is enabled during a test mode of operation when a predetermined control signal IDSEL is logic “high” and transmits the output of thethird selector 470. Thethird control buffer 458 includes an ORgate 458 a for receiving an inverted signal of the test enable signal TEST and the predetermined control signal IDSEL and further includes atri-state buffer 458 b. - The
seventh delay unit 466 and theeighth delay unit 467 delay read data output from thesecond memory device 43. Thefourth selector 471 selects an output signal of theseventh delay unit 466 during the normal mode of operation and selects an output signal of theeighth delay unit 467 during the test mode of operation. - The
fourth control buffer 459 is enabled during the normal mode of operation and transmits an output of thefourth selector 471. Thefourth control buffer 459 is enable during the test mode of operation when the control signal IDSEL is logic “low” and transmits the output of thefourth selector 471. Thefourth control buffer 459 includes an ORgate 459 a for receiving an inverted signal of the test enable signal TEST and an inverted signal of the predetermined control signal IDSEL and further includes atri-state buffer 459 b. - The second switch SW1 connects an output terminal of the
third control buffer 458 to an output terminal of thefourth control buffer 459 during the test mode of operation. Thethird register 453 samples a signal of the output terminal of thethird control buffer 458 in response to a rising edge of the buffer clock signal CK_BUFFER, and thefourth register 454 samples a signal of the output terminal of thefourth control buffer 459 in response to a falling edge of the buffer clock signal CK_BUFFER. Thefifth selector 472 selects an output of thethird register 453 at a rising edge of the buffer clock signal CK_BUFFER and selects an output of thefourth register 454 at a falling edge of the buffer clock signal CK_BUFFER. - Now referring to the timing diagrams of FIGS. 5 and 6, operations of the
memory module 400 according to embodiments of the present invention will be described further below. During the normal mode of operation, the test enable signal TEST is logic “low”. As a result, the first through fourth control buffers (456-459) are enabled, and the first and second switches SW0 and SW1 are turned off. Output signals of the first, third, fifth, andseventh delay units - Now referring to FIG. 5, a timing diagram illustrating write operations of memory modules according to embodiments of the present invention, for example,
memory modules 400 of FIG. 4, will be discussed further below. During the test mode of operation, the test enable signal TEST is logic “high”. As a result, the first and second switches SW0 and SW1 are turned on. Furthermore, the output signals of the second, fourth, sixth, andeighth delay units - During the write operation, the
first register 451 samples write data input through the input/output pin DQ in response to a rising edge of the buffer clock signal CK_BUFFER, and thesecond register 452 samples the write data input through the input/output pin DQ in response to a falling edge of the buffer clock signal CK_BUFFER. Thus, as shown in the timing diagram of FIG. 5, the write data DI0 and DI2 is the output REG0_Q of thefirst register 451, and the write data DI1 and DI3 is output REG1_Q of thesecond register 452. - The
first control buffer 456 transmits the output REG0_Q of thefirst register 451 to output B0_OUT when the buffer clock signal CK_BUFFER is logic “low” during the test mode of operation, and thesecond control buffer 457 transmits the output REG1_Q of thesecond register 457 to output B1_OUT when the buffer clock signal CK_BUFFER is logic “high” during the test mode of operation. Meanwhile, during the test mode of operation, the first switch SW0 is turned on and connects the output terminal of thefirst control buffer 456 to the output of thesecond control buffer 457 and, thus, the output B0_OUT of thefirst control buffer 456 is merged into the output B1_OUT of thesecond control buffer 457. - Merged data SW0_Q is delayed ¼ of a cycle of the buffer clock signal CK_BUFFER through the
second delay unit 461, and delayed data MIO0_Q is input into thefirst memory device 41 at a rising and/or falling edge of the memory clock signal CK_MEMORY. Furthermore, the merged data SW0_Q is delayed ¼ of a cycle of the buffer clock signal CK_BUFFER through thefourth delay unit 463, and delayed data MIO1_Q is input into thesecond memory device 43 at a rising and/or falling edge of the memory clock signal CK_MEMORY. - Now referring to FIG. 6, a timing diagram of a read operation of memory modules according to embodiments of the present invention will be discussed further below. Read data MIO0_Q is output from the
first memory device 41 at a rising and/or falling edge of the memory clock signal CK_MEMORY, and the read data MIO1_Q is output from thesecond memory device 43 at a rising and/or falling edge of the memory clock signal CK_MEMORY. The read data MIO0_Q is delayed ¾ of a cycle of the buffer clock signal CK_BUFFER through thesixth delay unit 465, and the read data MIO1_Q is delayed ¾ of a cycle of the buffer clock signal CK_BUFFER through theeighth delay unit 467. - When the control signal IDSEL is logic “high”, the
third control buffer 458 is enabled, and thefourth control buffer 459 is disabled. Thus, only the data MIO0_Q read from thefirst memory device 41 is output to the input/output pin DQ. When the control signal IDSEL is logic “low”, thethird control buffer 458 is disabled, and thefourth control buffer 459 is enabled. Thus, only the data MIO1_Q read from thesecond memory device 43 is output to the input/output pin DQ. - When the control signal IDSEL is logic “high”, output of the
sixth delay unit 465 is an input signal REG2_D of thethird register 453 through theselector 470 and thethird control buffer 458. Here, the second switch SW1 is turned on, and thus the output of thesixth delay unit 465 is an input signal REG3_D of thefourth register 454. When the control signal IDSEL is logic “low”, output of theeighth delay unit 467 is an input signal REG3_D of thefourth register 454 through theselector 471 and thefourth control buffer 459. Here, the second switch SW1 is turned on, and thus the output of theeighth delay unit 467 is an input signal REG2_D of thethird register 453. - The input signal REG2_D is sampled as output REG2_Q at a rising edge of the buffer clock signal CK_BUFFER by the
third register 453, and the input signal REG3_D is sampled as output REG3_Q at a falling edge of the buffer clock signal CK_BUFFER by thefourth register 454. Thefifth selector 472 selects the output REG2_Q at a rising edge of the buffer clock signal CK_BUFFER, selects the output REG3_Q at a falling edge of the buffer clock signal CK_BUFFER, and thus outputs REG2_Q and REG3_Q to the input/output pin DQ. - Memory modules according embodiments of the present invention described above can be tested by setting the frequency of the buffer clock signal CK_BUFFER equal to the frequency of the memory clock signal CK_MEMORY during the test mode of operation. The first and
second memory devices - Now referring to FIG. 7, memory modules according to further embodiments of the present invention will be discussed below. Memory modules of FIG. 7 have been supplemented so that the first and
second memory devices memory module 700 includes first andsecond memory devices gate 751 andselectors - Write operations in a normal mode of operation are the same as the operations discussed with respect to FIG. 4, thus, a description of these operations will be omitted. During a read operation in the normal mode of operation, the
selector 752 selects an output signal of thefifth delay unit 464 selected by theselector 470 and outputs the output signal of thefifth delay unit 464 to thethird register 453, and theselector 753 selects an output signal of theseventh delay unit 466 selected by theselector 471 and outputs the output signal of theseventh delay unit 466 to thefourth register 454. - During a read operation in the test mode of operation, the exclusive NOR
gate 751 performs an exclusive NOR operation on an output signal of thesixth delay unit 465 selected by theselector 470 and an output signal of theeighth delay unit 467 selected by theselector 471. Theselector 752 and theselector 753 select an output signal of the exclusive NORgate 751 and outputs the signal of the exclusive NORgate 751 to thethird register 453 and thefourth register 454. - Now referring to FIG. 8, a timing diagram illustrating operations of memory modules of FIG. 7 will be discussed below. As illustrated, if an output signal D5_OUT of the
sixth delay unit 465, which delays data MIO0_Q read from thefirst memory device 41, is the same as an output signal D7_OUT of theeighth delay unit 467, which delays data MIO1_Q read from thesecond memory device 43, the output of the exclusive NORgate 751 is logic “high”. Otherwise, the output of the exclusive NORgate 751 is logic “low”. Thus, if a value finally output to the input/output pin DQ is logic “low”, it may be determined that a memory cell corresponding to the values is defective. Thus, embodiments of the present invention illustrated in FIG. 7 may be tested by setting the frequency of the buffer clock signal CK_BUFFER to be the same as that of the memory clock signal CK_MEMORY during the test mode of operation and the first andsecond memory devices - It will be understood that although embodiments of the present invention have been described where the frequency of the buffer clock signal CK_BUFFER is twice the frequency of the memory clock signal CK_MEMORY during the normal mode of operation, embodiments of the present invention may also be applied to cases where the frequency of the buffer clock signal CK_BUFFER is, for example, four times, six times, and more than sixteen times the frequency of memory clock signal CK_MEMORY.
- As described above, memory modules and methods of testing memory modules according to embodiments of the present invention provide both a normal mode of operation and a test mode of operation. During the test mode of operation, the frequency of a buffer clock, which is typically at least 2 times the frequency of a memory clock, may be set equal to the frequency of the memory clock signal. Thus, the test may be performed at a fairly low speed. Thus, according to embodiments of the present invention memory modules may be tested and manufactured at a reduced cost.
- In the drawings and specification, there have been disclosed typical preferred embodiments of the invention and, although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention being set forth in the following claims.
Claims (16)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR01-12248 | 2001-03-09 | ||
KR10-2001-0012248A KR100393217B1 (en) | 2001-03-09 | 2001-03-09 | Memory module having control circuit for operating memory devices and data buffer by same clock frequency |
Publications (2)
Publication Number | Publication Date |
---|---|
US20020135394A1 true US20020135394A1 (en) | 2002-09-26 |
US6944737B2 US6944737B2 (en) | 2005-09-13 |
Family
ID=19706695
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/094,448 Expired - Lifetime US6944737B2 (en) | 2001-03-09 | 2002-03-08 | Memory modules and methods having a buffer clock that operates at different clock frequencies according to the operating mode |
Country Status (2)
Country | Link |
---|---|
US (1) | US6944737B2 (en) |
KR (1) | KR100393217B1 (en) |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050010737A1 (en) * | 2000-01-05 | 2005-01-13 | Fred Ware | Configurable width buffered module having splitter elements |
US20070070669A1 (en) * | 2005-09-26 | 2007-03-29 | Rambus Inc. | Memory module including a plurality of integrated circuit memory devices and a plurality of buffer devices in a matrix topology |
US20070176661A1 (en) * | 2006-02-01 | 2007-08-02 | Jong-Chul Shin | Data delay control circuit and method |
US20080080261A1 (en) * | 2005-09-26 | 2008-04-03 | Rambus Inc. | Memory system topologies including a buffer device and an integrated circuit memory device |
US20080159025A1 (en) * | 2006-12-27 | 2008-07-03 | Hynix Semiconductor Inc. | Semiconductor memory device with various delay values |
CN102422360A (en) * | 2009-05-13 | 2012-04-18 | 飞思卡尔半导体公司 | Method to calibrate start values for write leveling in a memory system |
TWI508067B (en) * | 2012-02-03 | 2015-11-11 | Mediatek Inc | Electronic apparatus, dram controller, and dram |
US11328764B2 (en) | 2005-09-26 | 2022-05-10 | Rambus Inc. | Memory system topologies including a memory die stack |
Families Citing this family (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7301831B2 (en) * | 2004-09-15 | 2007-11-27 | Rambus Inc. | Memory systems with variable delays for write data signals |
KR100605512B1 (en) * | 2005-02-14 | 2006-07-28 | 삼성전자주식회사 | Semiconductor memory device and memory system comprising the same |
JP4949707B2 (en) * | 2006-03-22 | 2012-06-13 | ルネサスエレクトロニクス株式会社 | Semiconductor device and test method thereof |
KR100868251B1 (en) * | 2007-03-22 | 2008-11-12 | 주식회사 하이닉스반도체 | Semiconductor Memory Device |
US8086936B2 (en) | 2007-08-31 | 2011-12-27 | International Business Machines Corporation | Performing error correction at a memory device level that is transparent to a memory channel |
US8082482B2 (en) | 2007-08-31 | 2011-12-20 | International Business Machines Corporation | System for performing error correction operations in a memory hub device of a memory module |
US20100269021A1 (en) * | 2007-09-05 | 2010-10-21 | Gower Kevin C | Method for Performing Error Correction Operations in a Memory Hub Device of a Memory Module |
US8019919B2 (en) * | 2007-09-05 | 2011-09-13 | International Business Machines Corporation | Method for enhancing the memory bandwidth available through a memory module |
US7668025B2 (en) * | 2007-10-04 | 2010-02-23 | Hynix Semiconductor Inc. | Input circuit of semiconductor memory apparatus and control method of the same |
US8140936B2 (en) | 2008-01-24 | 2012-03-20 | International Business Machines Corporation | System for a combined error correction code and cyclic redundancy check code for a memory channel |
US7881127B2 (en) | 2008-05-20 | 2011-02-01 | Hynix Semiconductor Inc. | Nonvolatile memory device and method of testing the same |
US7937632B2 (en) * | 2008-06-24 | 2011-05-03 | International Business Machines Corporation | Design structure and apparatus for a robust embedded interface |
JP5102789B2 (en) | 2009-01-16 | 2012-12-19 | ルネサスエレクトロニクス株式会社 | Semiconductor device and data processor |
JP5310439B2 (en) * | 2009-09-18 | 2013-10-09 | ソニー株式会社 | Semiconductor memory device and chip stacked semiconductor device |
KR20110119406A (en) * | 2010-04-27 | 2011-11-02 | 삼성전자주식회사 | Nonvolatile memory device having operation mode change function and operation mode change method |
KR20130046122A (en) * | 2011-10-27 | 2013-05-07 | 에스케이하이닉스 주식회사 | Semiconductor memory device and operating method thereof |
KR102641515B1 (en) * | 2016-09-19 | 2024-02-28 | 삼성전자주식회사 | Memory device and clock distribution method thereof |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4894830A (en) * | 1987-01-17 | 1990-01-16 | Nec Corporation | LSI chip with scanning circuitry for generating reversals along activated logical paths |
US5402458A (en) * | 1993-10-08 | 1995-03-28 | Cyrix Corporation | Mechanism to accelerate counter testing without loss of fault coverage |
US6069829A (en) * | 1998-09-29 | 2000-05-30 | Texas Instruments Incorporated | Internal clock multiplication for test time reduction |
US6185703B1 (en) * | 1997-10-10 | 2001-02-06 | Intel Corporation | Method and apparatus for direct access test of embedded memory |
US6331958B2 (en) * | 2000-04-10 | 2001-12-18 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor memory device having data parallel/serial conversion function and capable of efficiently performing operational test |
US6658611B1 (en) * | 1998-11-19 | 2003-12-02 | Samsung Electronics Co., Ltd. | Programmable built-in self-test system for semiconductor memory device |
US6894945B2 (en) * | 2001-08-09 | 2005-05-17 | Renesas Technology Corp. | Clock synchronous semiconductor memory device |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3078934B2 (en) * | 1992-12-28 | 2000-08-21 | 富士通株式会社 | Synchronous random access memory |
KR0164807B1 (en) * | 1995-12-22 | 1999-02-01 | 김광호 | Data output buffer control circuit for semiconductor memory device |
KR100394064B1 (en) * | 1996-10-01 | 2003-10-17 | 주식회사 하이닉스반도체 | Data output buffer circuit |
JPH1116349A (en) * | 1997-06-26 | 1999-01-22 | Mitsubishi Electric Corp | Synchronous semiconductor memory device |
KR100283191B1 (en) * | 1997-08-25 | 2001-03-02 | 윤종용 | Internal clock generating circuit in semiconductor device |
KR19990053199A (en) * | 1997-12-23 | 1999-07-15 | 김영환 | High-Speed Synchronous Memory Devices for Testing |
JP2000091912A (en) * | 1998-09-17 | 2000-03-31 | Hitachi Ltd | Semiconductor device |
-
2001
- 2001-03-09 KR KR10-2001-0012248A patent/KR100393217B1/en not_active IP Right Cessation
-
2002
- 2002-03-08 US US10/094,448 patent/US6944737B2/en not_active Expired - Lifetime
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4894830A (en) * | 1987-01-17 | 1990-01-16 | Nec Corporation | LSI chip with scanning circuitry for generating reversals along activated logical paths |
US5402458A (en) * | 1993-10-08 | 1995-03-28 | Cyrix Corporation | Mechanism to accelerate counter testing without loss of fault coverage |
US6185703B1 (en) * | 1997-10-10 | 2001-02-06 | Intel Corporation | Method and apparatus for direct access test of embedded memory |
US6069829A (en) * | 1998-09-29 | 2000-05-30 | Texas Instruments Incorporated | Internal clock multiplication for test time reduction |
US6658611B1 (en) * | 1998-11-19 | 2003-12-02 | Samsung Electronics Co., Ltd. | Programmable built-in self-test system for semiconductor memory device |
US6331958B2 (en) * | 2000-04-10 | 2001-12-18 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor memory device having data parallel/serial conversion function and capable of efficiently performing operational test |
US6894945B2 (en) * | 2001-08-09 | 2005-05-17 | Renesas Technology Corp. | Clock synchronous semiconductor memory device |
Cited By (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050010737A1 (en) * | 2000-01-05 | 2005-01-13 | Fred Ware | Configurable width buffered module having splitter elements |
US10381067B2 (en) | 2005-09-26 | 2019-08-13 | Rambus Inc. | Memory system topologies including a buffer device and an integrated circuit memory device |
US9865329B2 (en) | 2005-09-26 | 2018-01-09 | Rambus Inc. | Memory system topologies including a buffer device and an integrated circuit memory device |
US11328764B2 (en) | 2005-09-26 | 2022-05-10 | Rambus Inc. | Memory system topologies including a memory die stack |
US11043258B2 (en) | 2005-09-26 | 2021-06-22 | Rambus Inc. | Memory system topologies including a memory die stack |
US10672458B1 (en) | 2005-09-26 | 2020-06-02 | Rambus Inc. | Memory system topologies including a buffer device and an integrated circuit memory device |
US7685364B2 (en) | 2005-09-26 | 2010-03-23 | Rambus Inc. | Memory system topologies including a buffer device and an integrated circuit memory device |
US10535398B2 (en) | 2005-09-26 | 2020-01-14 | Rambus Inc. | Memory system topologies including a buffer device and an integrated circuit memory device |
US7729151B2 (en) | 2005-09-26 | 2010-06-01 | Rambus Inc. | System including a buffered memory module |
US20070070669A1 (en) * | 2005-09-26 | 2007-03-29 | Rambus Inc. | Memory module including a plurality of integrated circuit memory devices and a plurality of buffer devices in a matrix topology |
US8539152B2 (en) | 2005-09-26 | 2013-09-17 | Rambus Inc. | Memory system topologies including a buffer device and an integrated circuit memory device |
US20080080261A1 (en) * | 2005-09-26 | 2008-04-03 | Rambus Inc. | Memory system topologies including a buffer device and an integrated circuit memory device |
US11727982B2 (en) | 2005-09-26 | 2023-08-15 | Rambus Inc. | Memory system topologies including a memory die stack |
US8108607B2 (en) | 2005-09-26 | 2012-01-31 | Rambus Inc. | Memory system topologies including a buffer device and an integrated circuit memory device |
US9117035B2 (en) | 2005-09-26 | 2015-08-25 | Rambus Inc. | Memory system topologies including a buffer device and an integrated circuit memory device |
US9563583B2 (en) | 2005-09-26 | 2017-02-07 | Rambus Inc. | Memory system topologies including a buffer device and an integrated circuit memory device |
US20070176661A1 (en) * | 2006-02-01 | 2007-08-02 | Jong-Chul Shin | Data delay control circuit and method |
US20100182064A1 (en) * | 2006-02-01 | 2010-07-22 | Jong-Chul Shin | Data delay control circuit and method |
US7696802B2 (en) | 2006-02-01 | 2010-04-13 | Samsung Electronics Co., Ltd. | Data delay control circuit and method |
US8305127B2 (en) | 2006-02-01 | 2012-11-06 | Samsung Electronics Co., Ltd. | Data delay control circuit and method |
US7649789B2 (en) * | 2006-12-27 | 2010-01-19 | Hynix Semiconductor, Inc. | Semiconductor memory device with various delay values |
US20080159025A1 (en) * | 2006-12-27 | 2008-07-03 | Hynix Semiconductor Inc. | Semiconductor memory device with various delay values |
CN102422360A (en) * | 2009-05-13 | 2012-04-18 | 飞思卡尔半导体公司 | Method to calibrate start values for write leveling in a memory system |
TWI508067B (en) * | 2012-02-03 | 2015-11-11 | Mediatek Inc | Electronic apparatus, dram controller, and dram |
Also Published As
Publication number | Publication date |
---|---|
KR100393217B1 (en) | 2003-07-31 |
US6944737B2 (en) | 2005-09-13 |
KR20020072371A (en) | 2002-09-14 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6944737B2 (en) | Memory modules and methods having a buffer clock that operates at different clock frequencies according to the operating mode | |
US6671787B2 (en) | Semiconductor memory device and method of controlling the same | |
US6219288B1 (en) | Memory having user programmable AC timings | |
US6421291B1 (en) | Semiconductor memory device having high data input/output frequency and capable of efficiently testing circuit associated with data input/output | |
US6457141B1 (en) | Semiconductor device with embedded memory cells | |
US6252805B1 (en) | Semiconductor memory device including programmable output pin determining unit and method of reading the same during test mode | |
US5928373A (en) | High speed test circuit for a semiconductor memory device | |
US7151713B2 (en) | Semiconductor memory device | |
US6456560B2 (en) | Semiconductor integrated circuit device with test interface circuit for performing test on embedded memory from outside | |
US6671836B1 (en) | Method and apparatus for testing memory | |
EP0921528B1 (en) | A memory device using direct access mode test and a method of testing the same | |
US5926420A (en) | Merged Memory and Logic (MML) integrated circuits including data path width reducing circuits and methods | |
US5848016A (en) | Merged Memory and Logic (MML) integrated circuits and methods including serial data path comparing | |
US5936975A (en) | Semiconductor memory device with switching circuit for controlling internal addresses in parallel test | |
US8050135B2 (en) | Semiconductor memory device | |
US7782685B2 (en) | Semiconductor device and operating method thereof | |
US20090254784A1 (en) | Semiconductor memory device and system using semiconductor memory device | |
US6914834B2 (en) | System and method for the functional testing of semiconductor memory chips | |
US7246277B2 (en) | Test bus architecture for embedded RAM and method of operating same | |
US6876564B2 (en) | Integrated circuit device and method for applying different types of signals to internal circuit via one pin | |
US7948912B2 (en) | Semiconductor integrated circuit with test mode | |
US7227810B2 (en) | Semiconductor device and testing method for semiconductor device | |
US20090303806A1 (en) | Synchronous semiconductor memory device | |
US6175524B1 (en) | Merged memory and logic (MML) integrated circuit devices including buffer memory and methods of detecting errors therein | |
KR100524936B1 (en) | The simultaneous bi-directional buffer having input signal generation function for self test and the self testing method of the simultaneous bi-directional buffer |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: SAMSUNG ELECTRONICS CO., LTD., KOREA, REPUBLIC OF Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:AHN, YOUNG-MAN;SO, JIN-HO;SO, BYUNG-SE;REEL/FRAME:012848/0337 Effective date: 20020401 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
FEPP | Fee payment procedure |
Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
FPAY | Fee payment |
Year of fee payment: 8 |
|
FPAY | Fee payment |
Year of fee payment: 12 |