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Publication numberUS20020142569 A1
Publication typeApplication
Application numberUS 09/820,305
Publication dateOct 3, 2002
Filing dateMar 29, 2001
Priority dateMar 29, 2001
Also published asUS6461949
Publication number09820305, 820305, US 2002/0142569 A1, US 2002/142569 A1, US 20020142569 A1, US 20020142569A1, US 2002142569 A1, US 2002142569A1, US-A1-20020142569, US-A1-2002142569, US2002/0142569A1, US2002/142569A1, US20020142569 A1, US20020142569A1, US2002142569 A1, US2002142569A1
InventorsKent Chang, Chia-Hsing Chen
Original AssigneeChang Kent Kuohua, Chia-Hsing Chen
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Method for fabricating a nitride read-only -memory (nrom)
US 20020142569 A1
Abstract
The present invention provides a method of fabricating an improved gate of a nitride read only memory (NROM) in a semiconductor wafer. A bottom oxide and a silicon nitride layer are first formed on the surface of a silicon substrate in the semiconductor wafer, respectively, followed by injecting a tantalum penta ethoxide (Ta(OC2H5)5), under the condition of 300 mTorr and 200-650 C., to form a tantalum pentaoxide (Ta2O5) layer as a top oxide layer. The top oxide layer, silicon nitride layer and the bottom oxide layer compose an oxide-nitride-oxide (ONO) dielectric structure. Finally, a gate conductor layer is formed on the surface of the ONO structure to complete the fabrication of the NROM of the present invention. The tantalum pentaoxide has a high dielectric constant and is used to reduce the control gate voltage and thermal budget so as to increase the coupling ratio and yield of the semiconductor wafer.
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Claims(7)
What is claimed is:
1. A method for fabricating a nitride read only memory (NROM), the method comprising:
providing a substrate;
forming a oxide-nitride-oxide (ONO) layer on the surface of the substrate, the ONO layer composed of a bottom oxide layer, a silicon nitride layer and a top oxide layer; and
forming a gate conductor layer on the surface of the ONO layer;
wherein, the top oxide layer is composed of tantalum pentaoxide (Ta2O5), deposited by a chemical vapor deposition (CVD) method.
2. The method of claim 1 wherein the fabrication temperature of the CVD method is between 200-650 C. and the pressure is between 200-600 mTorr.
3. The method of claim 1 wherein the thickness of the top oxide layer is between 60-800 angstroms.
4. The method of claim 1 wherein the top oxide layer is formed by the reaction of tantalum penta ethoxide (Ta(OC2H5)5) with oxygen, and the flow rate of the tantalum penta ethoxide is about 5-20 mg/min, and the flow rate of the oxygen gas is about 500-2000 mg/min.
5. The method of claim 4 wherein the reaction uses helium (He) as a carrier gas, and the flow rate of He is about 200-600 mg/min.
6. The method of claim 1 wherein the method further comprises an anneal process after forming the top oxide layer.
7. The method of claim 7 wherein the annealing process is a rapid thermal nitridation (RTN) process, performed by using nitrous oxide gas at a temperature of 800 C. for a duration of 60 seconds.
Description

[0001] 1. Field of the Invention

[0002] The present invention provides a method of fabricating a gate in a nitride read only memory (NROM).

[0003] 2. Description of the Prior Art

[0004] A read only memory (ROM) device, composed of a plurality of memory cells, is a kind of semiconductor wafer device that functions in data storage. The ROM device is widely applied to computer data storage and memory. Depending on the method of storing data, the ROM can be divided into several types such as a mask ROM, programmable ROM (PROM), erasable programmable ROM (EPROM), and an electrically erasable programmable ROM (EEPROM).

[0005] Differing from other types of ROMs that use a polysilicon or metal floating gate, a nitride read only memory (NROM) uses an insulating dielectric layer as a charge-trapping medium. Due to the highly-compacted nature of the silicon nitride layer, hot electrons tunneling from the MOS transistor into the silicon nitride layer are trapped within to form an unequal concentration distribution to hasten data reading speed and to avoid current leakage.

[0006] Please refer to FIG. 1. FIG. 1 is a schematic diagram of a standard structure of an NROM according to the prior art. A semiconductor wafer 10 comprises a P-type silicon substrate 12, two N-type doped areas 14, 16 positioned on the surface of the silicon substrate 12, an ONO dielectric structure 24, and a gate conductor layer 26 positioned on the ONO dielectric structure 24. The ONO dielectric structure 24 is composed of a bottom oxide layer 18, a silicon nitride layer 20 and a top oxide layer 22.

[0007] Please refer to FIG. 2 and FIG. 3. FIG. 2 and FIG. 3 are schematic diagrams of a method for fabricating an NROM using the standard structure shown in FIG. 1. As shown in FIG. 2, according to the prior art for fabricating a gate of the NROM, a semiconductor wafer 30 comprising a P-type silicon 32 is first provided. A high temperature oxidation process is then performed to form an oxide layer with a thickness of 50-150 angstroms as a bottom oxide layer 34 on the surface of the silicon substrate 32. Next, a low-pressure chemical vapor deposition (LPCVD) is used to deposit a silicon nitride layer 36 with a thickness of 50-150 angstroms on the bottom oxide layer 34. An annealing process is then used under a high temperature of 950 C. for a duration of 30 minutes to repair the structure of the silicon nitride layer 36. As well, water steam is injected to perform a wet oxidation process to form a silicon oxy-nitride layer with a thickness of the 50-150 angstroms as a top oxide layer 38. The bottom oxide layer 34, the silicon nitride layer 36 and the top oxide layer 38 compose the ONO dielectric structure 40 on the surface of the silicon substrate 32.

[0008] As shown in FIG. 3, a photolithographic and etching process is performed to form a gate pattern in the top oxide layer 38 and silicon nitride layer 36. An ion implantation process is then performed to form a plurality of doped areas 42 as a source and drain in the MOS transistor. Thereafter, a thermal oxidation process is used to form a field oxide (FOX) 44 on the surface of the source/drain to isolate each silicon nitride layer 36. Finally, a doped polysilicon layer 46 is deposited as a gate conductor layer.

[0009] According to the prior art for forming a top oxide layer, the process requires higher temperature and thermal budget to form an oxide layer on the surface of the nitride compound. Thus, not only is greater cost needed, but the higher temperature may lead to the degradation of the gate oxide layer and affect the reliability of the NROM. Moreover, because of the low dielectric constant of silicon oxide, the top oxide layer comprises lower coupling ratio and higher control gate voltage.

SUMMARY OF THE INVENTION

[0010] It is therefore a primary objective of the present invention to provide a gate fabrication method of an NROM with high dielectric constant of the top oxide layer to solve the above-mentioned problems.

[0011] In accordance with the claim invention, the method first forms a bottom oxide layer and a silicon nitride layer on the surface of a silicon substrate in the semiconductor wafer, respectively, followed by injecting a tantalum penta ethoxide (Ta(OC2H5)5), under the condition of 300 mTorr and 200-650 C., to deposit a tantalum pentoxde (Ta2O5) layer as a top oxide layer. The top oxide layer, silicon nitride layer and the bottom oxide layer compose an oxide-nitride-oxide (ONO) dielectric structure. Finally, a gate conductor layer is formed on the surface of the ONO structure to complete the fabrication of the NROM according to the present invention. It is an advantage of the present invention that the present invention uses tantalum pentaoxide, having a high dielectric constant, as a top oxide layer of the ONO dielectric layer, to thereby increase the coupling ratio, reduce both the control gate voltage and thermal budget of the fabrication, and to avoid the problem of gate oxide degradation due to high temperature so as to improve the production yield of the semiconductor wafer.

[0012] These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment, which is illustrated in the various figures and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0013]FIG. 1 is a schematic diagram of a standard structure of an NROM according to the prior art.

[0014]FIG. 2 and FIG. 3 are schematic diagrams of a method for fabricating an NROM using the standard structure shown in FIG. 1.

[0015]FIG. 4 to FIG. 6 are schematic diagrams of a method for fabricating an NROM according to the prior invention.

DESCRIPTION OF THE PREFERRED EMBODIMENT

[0016] Please refer to FIG. 4 to FIG. 6. FIG. 4 to FIG. 6 are the schematic diagrams of a method for fabricating an NROM according to the present invention. As shown in FIG. 4, the NROM according to the present invention is fabricated on the surface of the silicon substrate 52 in a semiconductor wafer 50. The silicon substrate 52 is a P-type silicon substrate, but the present invention is not limited to only this substrate type.

[0017] The present invention first forms an ONO dielectric layer 60 with a thickness of 150-250 angstroms on the surface of the silicon substrate 52. The method of fabricating an ONO dielectric structure 60 according to the present invention first involves performing a high temperature oxidation process to form an oxide layer with a thickness of 50-150 angstroms as a bottom oxide layer 54 on the surface of the substrate 52. A LPCVD process is then performed by injecting a reaction gas mixture of dichlorosilane (SiH2Cl2) and ammonia (NH3) under the condition of 700-800 C. temperature and low pressure to form a silicon nitride layer 56 with a thickness of 50-150 angstroms on the surface of the bottom oxide layer 54.

[0018] Next, a chemical vapor deposition (CVD) process is used under the condition of 200-650 C. temperature and 200-600 mTorr by injecting tantalum penta ethoxide (Ta(OC2H5)5) with a flowrate of 5-20 mg/min, oxygen with a flowrate of 500-2000 sccm(standard cubic centimeter per minute) and helium gas (He) as a carrier gas with a flowrate of 200-600 sccm, to form a tantalum pentaoxide layer(Ta2O5) with a thickness of 60-800 angstroms as a top oxide layer 58 on the surface of the silicon nitride layer 56. The reaction step is as follows:

2Ta(OC2H5)5+3002→Ta2O5+20CO2+25H2O

[0019] In the preferred embodiment of the present invention, a reaction is performed at a temperature of 480 C., a pressure of 300 mTorr and a carrier gas (He) flowrate of 300 sccm, and tantalum penta ethoxide is injected at 7.5 mg/min and oxygen is injected at 1000 sccm to a form tantalum pentaoxide layer via CVD deposition with a thickness of 100 angstroms. The bottom oxide layer 54, silicon nitride 56 and the top oxide layer 58 compose an ONO dielectric structure 60 on the surface of the substrate 52. Since the tantalum pentaoxide, which functions as a top oxide layer 58, is of a high dielectric constant of 25, or equal to 6-fold of silicon oxide (dielectric constant 3.9) and 3-fold of silicon nitride (dielectric constant 7.5), the control gate voltage is efficiently reduced and both the coupling ratio and charge gain are increased.

[0020] Next, nitrous oxide (N2O) is injected at a temperature of 800 C. for a duration of 30 seconds to perform a rapid thermal nitridation (RTN)process, functioning as an annealing process, to repair the ONO dielectric structure, and thereby reduce the probability of current leakage of the tantalum pentaoxide and achieve an improved time-dependent dielectric breakdown (TDDB) characteristic of the tantalum pentaoxide film.

[0021] As shown in FIG. 5, a photoresist layer (not shown) is formed on the surface of the ONO dielectric structure 60, followed by a photolithographic and etching process to form a column pattern in the photoresist layer on the surface of the ONO dielectric layer 60. Then, the photoresist layer is used as a mask to perform a ion implantation process 62 so as to form a plurality of doped area 64 functioning as a drain (i.e. bit line) and source. As shown in FIG. 6, after removing the photoresist layer, a thermal oxidation process is used to form an oxide layer 66 on the surface of the doped area 64 to isolate each silicon nitride layer 56. Finally, a doped polysilicon layer 68 is deposited as a gate conductor layer (i.e. Word line).

[0022] In contrast to the prior art method for fabricating a gate of an NROM, the present invention uses a simpler process requiring a lower temperature to replace the higher-temperature wet oxidation. As a result, the thermal budget of NROM fabrication is reduced and the degradation of the gate oxide due to high temperature is prevented so as to improve the problems caused by the prior art. Moreover, because of the high dielectric constant property of tantalum pentaoxide, both the coupling ratio and charge gain greatly increase and both the gate control voltage and the defect density decrease so as to improve both the production yield of NROM and fabrication cost.

[0023] Those skilled in the art will readily observe that numerous modifications and alterations of the device may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.

Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US6830963Oct 9, 2003Dec 14, 2004Micron Technology, Inc.Fully depleted silicon-on-insulator CMOS logic
US6842370May 4, 2004Jan 11, 2005Micron Technology, Inc.Vertical NROM having a storage density of 1 bit per 1F2
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Classifications
U.S. Classification438/585, 257/E21.679, 257/E27.103, 257/E21.267
International ClassificationH01L21/8246, H01L21/314, H01L27/115
Cooperative ClassificationH01L27/115, H01L21/3143, H01L27/11568
European ClassificationH01L27/115, H01L27/115G4
Legal Events
DateCodeEventDescription
Mar 28, 2014FPAYFee payment
Year of fee payment: 12
Nov 3, 2009FPAYFee payment
Year of fee payment: 8
Mar 1, 2006FPAYFee payment
Year of fee payment: 4
Mar 29, 2001ASAssignment
Owner name: MACRONIX INTERNATIONAL CO. LTD., TAIWAN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:CHANG, KENT KUOHUA;CHEN, CHIA-HSING;REEL/FRAME:011659/0670
Effective date: 20010302
Owner name: MACRONIX INTERNATIONAL CO. LTD. SCIENCE-BASED INDU
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:CHANG, KENT KUOHUA /AR;REEL/FRAME:011659/0670