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Publication numberUS20020149959 A1
Publication typeApplication
Application numberUS 09/833,657
Publication dateOct 17, 2002
Filing dateApr 13, 2001
Priority dateApr 13, 2001
Also published asUS6466472
Publication number09833657, 833657, US 2002/0149959 A1, US 2002/149959 A1, US 20020149959 A1, US 20020149959A1, US 2002149959 A1, US 2002149959A1, US-A1-20020149959, US-A1-2002149959, US2002/0149959A1, US2002/149959A1, US20020149959 A1, US20020149959A1, US2002149959 A1, US2002149959A1
InventorsJohnson Lin
Original AssigneeJohnson Lin
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Common module for ddr sdram and sdram
US 20020149959 A1
Abstract
A common module for DDR SDRM and SDRAM on a motherboard, which computes and determines the resistance of the terminators on the motherboard so that the work current is controlled within the range allowed by an SDRAM controller, and can achieve the object of a DDR DRAM and SDRAM common layout without the need of an extra quick switch IC.
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Claims(5)
What is claimed is:
1. A common module for DDR SDRAM and SDRAM, which comprises:
at least one DDR SDRAM DIMM;
at least one SDRAM DIMM; and
terminators coupling to the common module and outputting a termination voltage;
wherein CMD signals/ADD signals and DATA signals are transmitted to the common module through a controller.
2. The common module of claim 1, wherein the termination voltage for the DDR SDRAM is 1.25 V.
3. The common module of claim 1, wherein the termination voltage for the SDRAM is 3.3 V.
4. The common module of claim 1, wherein the terminator is used to inform a computer where signal transmissions should end and to ensure the stability of the whole circuit signals.
5. The common module of claim 1, wherein the resistance of the terminators is between 220Ω and 1250Ω.
Description
BACKGROUND OF THE INVENTION

[0001] 1. Field of Invention

[0002] The invention relates to a common module for DDR SDRAM and SDRAM. In particular, the invention achieves the object of a DDR SDRAM and SDRAM common layout without the need for an extra IC or increasing the cost.

[0003] 2. Related Art

[0004] As the CPU (Central Processing Unit) is driven to high frequencies, the increases in the bus bandwidth and memory speed also become a key factor of the system efficiency. An analysis of the Rambus structure and the SDRAM-II, or DDR SDRAM (Double Data Rate Synchronous DRAM), indicates that both of them have the advantage of increasing data transmission rates.

[0005] On the other hand, since the DDR SDRAM structure is compatible with the current SDRAM structure, unlike Rambus which requires to redefine the socket standard, the application of the former is thus much easier than the later.

[0006] SDRAM (Synchronous DRAM) is a new model of the DRAM and has a much faster clock rate then conventional memory. Since it can be synchronous with the CPU bus and can simultaneously open two memory pages, the operation speed can reach 133 MHz.

[0007] The current Intel Pentium CPU series uses the 100 MHz and 133 MHz CPU buses, therefore the SDRAM can still support the system. However, future personal computers may use over 200 MHz buses, then the SDRAM will not be able to support the standard. Therefore, developing higher speed memory such as DDR SDRAM is more and more urgent.

[0008] Since the DDR SDRAM is able to support data transmissions according to the clock rates on both ends, the data transmission quantity of the memory chip is thus doubled. So it is also called the SDRAM II.

[0009] The state-of-art method for simultaneously supporting the DDR SDRAM and the SDRAM is to use a quick switch IC to control and switch the terminators to achieve the object of a DDR SDRAM and SDRAM common layout.

SUMMARY OF THE INVENTION

[0010] An object of the invention is to provide a common module for DDR SDRAM and SDRAM that achieves the goal of a DDR SDRAM and SDRAM common layout without the need of an extra quick switch IC.

[0011] After testing the disclosed common module, the terminators on a motherboard can be set to be between 220Ω and 1250Ω. A preferred value is 330Ω. Within the preferred range, both the DDR SDRAM and the SDRAM can function normally and the work current falls within the range allowed by the SDRAM controller.

BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The present invention will become more fully understood from the detailed description given hereinbelow illustration only, and thus are not limitative of the present invention, and wherein:

[0013]FIG. 1 shows a structure of the first embodiment common module for DDR SDRAM and SDRAM according to the invention; and

[0014]FIG. 2 shows a structure of the second embodiment common module for DDR SDRAM and SDRAM according to the invention.

DETAILED DESCRIPTION OF THE INVENTION

[0015] In general, the termination voltage for the CMD (command) signals/ADD (address) signals, and DATA signals in DDR SDRAM is 1.25 V. The termination voltage for the CMD (command) signals/ADD (address) signals, and DATA signals in SDRAM is 3.3 V. However, the DDR SDRAM requires a terminator of 33Ω while the SDRAM does not.

[0016] The terminator is a special resistor package or block that tells a computer where signal transmissions should end and ensures the stability of the whole circuit signal. The terminator functions like a filter, eliminating electric noises produced by many surrounding cables and equipment.

[0017] Therefore, the DDR SDRAM and the SDRAM need a common layout to share CMD signals/ADD signals and DATA signals. A proper terminator has to be chosen so that the DDR SDRAM and the SDRAM can function correctly under an invariant termination voltage.

[0018] Aside from utilizing the terminal function of the terminators, they are also used to detect DDR SDRAM devices. When a DDR SDRAM device is detected, it automatically switches the bus transmission mode into the DDR SDRAM mode. Of course, the whole bus will use the fast speed to transmit data. With the disclosed design, the SDRAM device can be connected to the same channel to achieve the goal of a common layout.

[0019] As shown in FIG. 1, CMD signals/ADD signals and DATA signal are transmitted to a common module 12 through a controller 10. The common module 12 includes at least one DDR SDRAM DIMM (Dual In-line Memory Module) and at least one SDRAM DIMM.

[0020] In a first embodiment, the common module 12 a first DIMM 20, a second DIMM 30, a third DIMM 30, and a fourth DIMM 50 for the configuration of different numbers of DDR SDRAM and SDRAM devices. For example, two DDR SDRAM devices (first DDR SDRAM DIMM and second DDR SDRAM DIMM) go with two SDRAM devices (first SDRAM DIMM and second SDRAM DIMM); one DDR SDRAM (DDR SDRAM DIMM) goes with three SDRAM devices (first SDRAM DIMM, second SDRAM DIMM, and third SDRAM DIMM); or three DDR SDRAM devices (first DDR SDRAM DIMM, second DDR SDRAM DIMM, and third DDR SDRAM DIMM) go with one SDRAM device (SDRAM DIMM). Furthermore, through the design of the terminators 60, 62, the object of a common module can be obtained while keeping the termination voltage 70 invariant.

[0021] With reference to FIG. 2, the common module 12 further contains a fifth DIMM 52 for a user to select different numbers of DR SDRAM and SDRAM devices, as in the previous embodiment.

[0022] According to the results of computations and tests for the disclosed common module, the DDR SDRAM and the SDRAM can function normally when the terminator 60, 62 have resistance between 220Ω and 1250Ω. This takes into account the concern that the electric current for the SDRAM signal to be at HIGH and LOW has to fall in the allowed range set by an SDRAM controller.

[0023] The results for SDRAM CMD signals/ADD signals and DATA signals to be HIGH (IH) and to be LOW (IL) are listed as follows:

[0024] for terminators of 330Ω:

IH=(3.3−1.25)/0.33K=6.21 mA;

IL=1.25/0.33K=3.79 mA;

[0025] for terminators of 220Ω:

IH=(3.3−1.25)/0.22K=9.31 mA;

IL=1.25/0.22K=5.68 mA;

[0026] for terminators of 1250Ω:

IH=(3.3−1.25)/1.25K=1.64 mA;

IL=1.25/1.25K=1 mA;

[0027] The DRAM has to be continuously refreshed in its potential difference. Otherwise, the potential difference may fall down to so low that it is insufficient to have enough energy representing in which state a memory unit is. According to the above calculation, IH and IL are both between 9.31 mA and 1 mA when varying the terminators 60, 62 from 220Ω to 1250Ω. This does not affect the signal transmission quality of the DDR SDRAM and the electric current falls within the allowed range enforced by the SDRAM controller. Thus, it is indeed a feasible common module.

[0028] Effects of the Invention

[0029] 1. The invention provides users a cheaper motherboard memory environment with a greater compatibility. Users can select the best memory module according to their own needs, which is quite different from the conventional unique motherboard memory environments. The invention provides two memory modules for selection. For computer makers, the price is more flexible. For DIY users, it serves as a good tool to assemble a computer on one's own with an optimal performance/cost ratio.

[0030] 2. The invention does not need to rely on any other IC. So it can achieve the DDR DRAM and SDRAM common layout without increasing the cost.

[0031] 3. The invention reduces the design of quick switch IC, lowers the cost, provides more layout space for the motherboard, and decreases the electromagnetic interference caused by complicated circuits.

[0032] The invention being thus described, it will be obvious that the same may be varied in many ways. Such variations are not to be regarded as a departure from the spirit and scope of the invention, and all such modifications as would be obvious to one skilled in the art are intended to be included within the scope of the following claims.

Classifications
U.S. Classification365/63
International ClassificationG11C29/50, G11C5/06, G11C29/48
Cooperative ClassificationG11C29/50, G11C29/48, G11C11/401, G11C5/063
European ClassificationG11C29/50, G11C29/48, G11C5/06H
Legal Events
DateCodeEventDescription
Dec 7, 2010FPExpired due to failure to pay maintenance fee
Effective date: 20101015
Oct 15, 2010LAPSLapse for failure to pay maintenance fees
May 24, 2010REMIMaintenance fee reminder mailed
Apr 5, 2006FPAYFee payment
Year of fee payment: 4
Apr 13, 2001ASAssignment
Owner name: GIGA-BYTE TECHNOLOGY CO., LTD., TAIWAN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:LIN, JOHNSON;REEL/FRAME:011713/0644
Effective date: 20010320
Owner name: GIGA-BYTE TECHNOLOGY CO., LTD. NO. 6, PAO-CHIANG R
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:LIN, JOHNSON /AR;REEL/FRAME:011713/0644