FIELD OF THE INVENTION
The present invention relates to semiconductor devices, and, more particularly, to a fast-settling, low power, biasing circuit for single-ended circuits.
BACKGROUND OF THE INVENTION
Radio Frequency (RF) receivers include preamplifiers to boost an incoming signal level prior to the frequency conversion process. The presence of intermodulation products produced by large interfering signals compromises the receiver's ability to process very weak signals. This is what is conventionally known as desensitization. Third-order intermodulation occurs when two interfering signals at differing frequencies combine in the amplifier third-order nonlinearity to produce an intermodulation product close to the desired signal.
Desensitization may also occur when a single large interfering signal (i.e. a blocker or jammer) is present. The reduction in sensitivity arises through two separate mechanisms. The first, gain compression, is caused by third-order nonlinearity in the circuit, allowing the existing noise source in the amplifier and mixer to exert a larger influence, thus degrading the overall noise performance. The second mechanism, second-order nonlinearity in the circuit, promotes mixing between relatively low-frequency noise sources in the amplifier and the interfering signal. As a result, low-frequency noise is up-converted to the desired signal frequency which degrades the circuit noise performance. More on the study of blocking and desensitization can be found in “Blocking and Desensitization in RF Amplifiers,” R. G. Meyer and A. K. Wong, IEEE (1995), which is incorporated by reference herein.
Particularly, desensitization occurs in single-ended circuits, such as single-ended front-end Low-Noise Amplifiers (LNAs) for wireless receivers, that operate in the presence of jammers due to an increase in the noise floor at the output of the circuit and gain compression. Essentially, distortion in the circuit causes an up-conversion of low-frequency noise into the band of interest. This added noise increases the noise-floor of the circuit, that causes the Signal-to-Noise Ratio (SNR) at the output of the amplifier to degrade considerably in the presence of large amplitude jammers.
A primary source of low-frequency noise is noise generated in the bias circuit of the single-ended circuit. A new technique for reducing bias noise in a conventional LNA circuit is presented in FIG. 1a. The bias circuit shown prevents desensitization from occurring. This single-transistor LNA circuit includes a transistor Qin as its primary gain device. As shown, power supply Ps applies a voltage input to the circuit. An output is observed at output node Pout. The bias circuit is composed of transistors Q1 and Q2, that act as mirror devices. If the device area of transistors Qin and Q1 is Ain and A1, respectively, then the current flowing through transistor Qin is Iref(Ain/A1). A resistor Rx1 is added in series with the bias circuit, to ensure that the incoming Radio Frequency (RF) power is not diverted into the bias circuit and is supplied primarily to transistor Qin for proper amplification. Since a base current flows into transistor Qin, a static voltage drop develops across resistor Rx1. In order to balance this drop, a resistor Rx2 is added in series with the base of transistor Q1. Note that the base current in transistor Qin equals the base current of transistor Q1 multiplied by Ain/A1. Therefore in order to balance the base-current drops, resistor Rx2 must equal Rx1(Ain/A1).
In practice, an RF signal represented by va cos(ωt) may be applied to the input of the LNA circuit; meanwhile a jammer signal of strength va′ cos((ω+Δω)t) may be applied to the input of the LNA as well. The jammer is much larger than the incoming RF signals in most wireless standards. For example, the Global System for Global Communication (GSM) standard requires that the LNA should not suffer any degradation in the output SNR in the presence of a −23 dBm jammer that is at a frequency 3 MHz away from the incoming RF signal having a power level of −98 dBm. With this level of jammer signal, low-frequency noise can be up-converted as explained above. At node 1, there exists low-frequency noise from the bias circuit output. Due to second-order harmonic distortion inherent in the LNA, the jammer tone beats with low-frequency noise at frequency Δω, and converts the noise upward to ω+Δω+Δω and ω+Δω−Δω. The latter term is at the same frequency as the desired signal. Thus, the SNR ratio at the desired output frequency suffers. It should be noted that this effect scales with the strength of the jammer, such that is the SNR degrades more for larger jammer strengths. This effect is shown in FIGS. 1b and 1 c.
The following noise sources impact the total noise at low frequencies in the bias circuit: a) the noise of the reference bias (Iref), b) the noise of bias resistor Rx2, c) the base shot-noise of transistor Q1, and d) the collector shot-noise of transistor Q1. Several other noise sources, however, may exist in a LNA circuit; yet, their impact is negligible. As a consequence of the tightly coupled feedback loop formed by transistors Q1 and Q2 and resistor Rx2, the impedance seen by the reference current source, Iref, is of the order of the inverse of the transconductance gm of transistor Q1. This is a small quantity in most bias circuits. Consequently, the noise of the reference bias circuit is small at its output, node X. In addition, as a result, the collector shot-noise of transistor Q1 is mitigated. The remaining noise sources noted above in b) and c) are major noise sources in the LNA circuit shown in FIG. 1a, since this circuit presents these noise sources with a relatively high impedance at the base of transistor Q1. Thus, noise current at this node develops a large noise voltage, which is effectively amplified by transistor Q1 at its collector node. Since transistor's Q2 placement with adjacent elements is such that it represents a voltage follower circuit, any noise at its base appears on its emitter with little attenuation. Hence, a large noise voltage develops at the base of transistor Qin. As explained above, this low-frequency noise can be up-converted to RF frequencies.
An approach that has been used to mitigate the noise up-conversion, is the use of external passive LC filters at the input node of the LNA circuit, or at the collector of transistor Q1 is shown in FIG. 2. The indicated LC circuit including inductor Ln and capacitor Cn creates a notch in the frequency domain at the frequency equal to the difference between the jammer and the signal-frequency. Thus, any noise on the bias line is filtered off at this frequency. The notch LC filter is so designed, that it appears as a very high impedance at the radio-frequency, and hence has a minimal impact on circuit performance. The LC notch circuit is effective in reducing the influence of the jammer.
This approach, however, has several disadvantages. First, it requires the use of external inductor and capacitor elements which add to the total cost of the solution. Second, the value of the capacitor in the notch filter is relatively high, since the filtering action is required at low frequencies. As a consequence, when the amplifier is powered on, it requires a long time to settle to its steady state, often in the order of hundreds of microseconds, which may be unacceptable in the overall system. Third, parasitics introduced by the large external components can degrade RF performance.
It should also be pointed out, that the solution of using a tuned series LC circuit applied at the input of the amplifier is very effective in suppressing the noise of resistor Rx1 and the base shot noise of transistor Qin as well, in addition to suppressing the noise of the bias circuit. However, there are several practical problems with this implementation as mentioned above namely increase in the cost because of added external components, slow turn-on time, and worsened RF performance due to added parasitics of the external tank components. If a noise filter is used at the collector of transistor Q1, it will show the same small increase due to the noise from resistor Rx1 and the base shot noise of transistor Qin.
Thus, a need exists for a fast settling, low power biasing technique for a single-ended circuit.
SUMMARY OF THE INVENTION
To address the above-discussed deficiencies of the biasing circuitry for single-ended circuits, the present invention teaches a fast settling, low power biasing circuit and method for single-ended circuits. In particular, a LNA in accordance with the present invention includes an input power matching circuit, an output transistor, a bias circuit, a degeneration inductance, and a load impedance. The input power matching circuit and the bias circuit couple to the output transistor which provides the amplification. The degeneration inductance and load impedance couple to the emitter and collector of the output transistor, respectively. The bias circuit is configured to eliminate base shot-noise of the output transistor which generates the amplification. The bias circuit in accordance with the present invention also eliminates the noise of the bias resistor that is included within the bias circuit.
Specifically, the bias circuit includes a current mirror circuit, a current reference source, the bias resistor, and an emitter follower circuit. The current reference source and the emitter follower circuit are connected to the current mirror circuit which connects to the bias resistor. This biasing circuit can be implemented in a wide-class of single-ended circuits.
Advantages of this design include but are not limited to a fully integratable solution which eliminates up-converted noise due to the presence of jammer signals. Since an LNA circuit in accordance with the present invention can be fully integrated on-chip, the additional cost is negligible and, hence, acceptable. Further, the turn-on time of the circuit is small, and acceptable in most systems.