US 20020154704 A1 Abstract An apparatus for and method of reducing the soft output information packet to be computed by a soft symbol generator. The reduced soft output information packet generated by the soft symbol generator is subsequently used by a soft symbol to soft bit mapper which functions to convert soft symbol decision information into soft bit decision information. A symbol competitor table is constructed that includes the most likely symbol competitors for each bit of the symbol. The table is populated with m entries for each possible symbol value, where m represents the number of bits per symbol. Symbol competitors are retrieved from the table in accordance with the hard decision. Soft symbol information is generated only for the symbol competitors rather than for all possible symbol thus substantially reducing the size of the information packet. The method of the invention can be performed in either hardware or software. A computer comprising a processor, memory, etc. is operative to execute software adapted to perform the reduced information packet method of the present invention.
Claims(48) 1. A method of generating a symbol competitor table for use in reducing the complexity of an information packet used to generate soft bit values from soft symbol information for am M-ary symbol alphabet, said method comprising the steps of:
for each of M possible symbol decisions:
for each bit position j of m bits per symbol:
calculating the Euclidean distance to the M/2 symbol decisions whose bit in position j is opposite to that of the j
^{th }bit in the current symbol; selecting the symbol decision yielding a minimum Euclidean distance;
placing said symbol decision in said table in accordance with the current symbol and the current bit position; and
wherein m, M and j are positive integers. 2. The method according to 3. The method according to 4. The method according to 5. A method of reducing a soft output information packet generated by a soft symbol output generator, said method comprising the steps of:
pre-computing a symbol competitor table comprising the most likely symbol competitors for each possible symbol decision; looking up in said symbol competitor table, for each hard decision, the most likely symbol competitors corresponding to each of m bit positions; generating and outputting soft symbol decision values corresponding to each of said m symbol competitors; and wherein m is a positive integer. 6. The method according to 7. The method according to 8. The method according to 9. The method according to 10. The method according to 11. The method according to 12. The method according to 13. The method according to for each of M possible symbol decisions:
for each bit position j of m bits per symbol:
calculating the Euclidean distance to the M/2 symbol decisions whose bit in position j is opposite to that of the j
_{th }bit in the current symbol; selecting the symbol decision yielding a minimum Euclidean distance;
placing said symbol decision in said table in accordance with the current symbol and the current bit position; and
wherein M and j are positive integers. 14. A method of generating soft bit decisions from hard decisions for an M-ary symbol alphabet, said method comprising the steps of:
pre-computing a symbol competitor table comprising the most likely symbol competitors for each possible symbol decision; looking up in said symbol competitor table, for each hard decision, the most likely symbol competitors corresponding to each of m bit positions; calculating soft output values corresponding to each symbol competitor; calculating a soft bit decision value for each of m bits as a function of the hard decision and the competitor symbols corresponding to the particular bit position; and wherein m and M are positive integers. 15. The method according to 16. The method according to 17. The method according to 18. The method according to 19. The method according to 20. The method according to 21. The method according to 22. The method according to 23. The method according to 24. The method according to 25. The method according to wherein LLR(S
_{k}=A_{l}) is the log likelihood ratio of symbol S_{k}=A_{l}, A_{l }represents the symbol value, b_{j }represents the bit value for the j^{th }bit of the symbol, D_{j0 }and D_{j1 }represent the set of symbols wherein bit j=0 and 1, respectively, ∀l εD_{j1 }and b_{j}(A_{l})=i for i=0, 1; j=0, . . . , m−1; l=0, . . . , M−1. 26. The method according to for each of M possible symbol decisions:
for each bit position j of m bits per symbol:
calculating the Euclidean distance to the M/2 symbol decisions whose bit in position j is opposite to that of the j
^{th }bit in the current symbol; selecting the symbol decision yielding a minimum Euclidean distance;
placing said symbol decision in said table in accordance with the current symbol and the current bit position; and
wherein j is a positive integer. 27. A communications receiver for receiving and decoding an M-ary transmitted signal, comprising:
a radio frequency (RF) front end circuit for receiving and converting said M-ary transmitted signal to a baseband signal; a demodulator adapted to receive said baseband signal and to generate a received signal therefrom in accordance with the M-ary modulation scheme used to generate said transmitted signal; a first decoder operative to receive said received signal and to generate a sequence of soft symbol decisions therefrom; a soft output computation module comprising processing means programmed to:
pre-compute a symbol competitor table comprising the most likely symbol competitors for each possible symbol decision;
look up in said symbol competitor table, for each hard decision, the most likely symbol competitors corresponding to each of m bit positions;
calculate soft output values corresponding to each symbol competitor;
calculate a soft bit decision value for each of m bits as a function of the hard decision and the competitor symbols corresponding to the particular bit position;
a second decoder adapted to receive said soft bit values and to generate binary received data therefrom; and wherein m and M are positive integers. 28. The receiver according to 29. The receiver according to 30. The receiver according to 31. The receiver according to 32. The receiver according to 33. The receiver according to 34. The receiver according to 35. The receiver according to 36. The receiver according to 37. The receiver according to wherein LLR(S
_{k}=A_{l}) is the log likelihood ratio of symbol S_{k}=A_{l}, A_{l }represents the symbol value, b_{j }represents the bit value for the j^{th }bit of the symbol, D_{j0 }and D_{j1 }represent the set of symbols wherein bit j=0 and 1, respectively, ∀l εD_{ji }and b_{j}(A_{l})=i for i=0, 1; j=0, . . . , m−1; l=0, . . . , M−1. 38. The receiver according to 39. The receiver according to for each of M possible symbol decisions:
for each bit position j of m bits per symbol:
calculating the Euclidean distance to the M/2 symbol decisions whose bit in position j is opposite to that of the j
^{th }bit in the current symbol; selecting the symbol decision yielding a minimum Euclidean distance;
wherein j is a positive integer. 40. An electronic data storage media storing a computer program adapted to program a computer to execute the soft output computation process of 41. A computer readable storage medium having a computer program embodied thereon for causing a suitably programmed system to generate soft bit decisions from hard decisions by performing the following steps when such program is executed on said system:
providing a symbol competitor table comprising the most likely symbol competitors for each possible symbol decision; looking up in said symbol competitor table, for each hard decision, the most likely symbol competitors corresponding to each of m bit positions; calculating soft output values corresponding to each symbol competitor; calculating a soft bit decision value for each of m bits as a function of the hard decision and the competitor symbols corresponding to the particular bit position; and wherein m is a positive integer. 42. The computer readable storage medium according to 43. The computer readable storage medium according to ^{th }bit in the current symbol; selecting the symbol decision yielding a minimum Euclidean distance;
wherein j is a positive integer. 44. The computer readable storage medium according to wherein LLR(S
_{k}=A_{l}) is the log likelihood ratio of symbol S_{k}=A_{l}, A_{l }represents the symbol value, b_{j }represents the bit value for the j^{th }bit of the symbol, D_{j0 }and D_{j1 }represent the set of symbols wherein bit j=0 and 1, respectively, ∀l εD_{jl }and b_{j}(A_{l})=i for i=0, 1; j=0, . . . , m−1. 45. The computer readable storage medium according to 46. The computer readable storage medium according to 47. The computer readable storage medium according to 48. A method of generating soft bit decisions from hard decisions for an M-ary symbol alphabet, said method comprising the steps of:
generating a full soft information packet comprising a soft decision for each possible symbol in said alphabet; pre-computing a symbol competitor table comprising the most likely symbol competitors for each possible symbol decision; looking up in said symbol competitor table, for each hard decision, the most likely symbol competitors corresponding to each of q bit positions; calculating a soft bit decision value for each of q bits for the soft symbol decisions in a partial reduced soft information packet comprising soft symbol decisions corresponding to said most likely symbol competitors; and wherein q and M are positive integers. Description [0001] The subject matter of the present application is related to and may be advantageously combined with the subject matter of copending and commonly owned application U.S. patent application Ser. No. 09/616,161, to Yakhnich et al, filed Jul. 14, 2000, entitled Method of Channel Order Selection and Channel Order Estimation in a Wireless Communication System, incorporated herein by reference in its entirety. [0002] The present invention relates generally to communication systems and more particularly relates to an apparatus for and a method of reducing the soft output information packet to be computed by a soft symbol generator that is subsequently used by a soft symbol to soft bit mapper. [0003] In recent years, the world has witnessed explosive growth in the demand for wireless communications and it is predicted that this demand will increase in the future. There are already over 500 million users that subscribe to cellular telephone services and the number is continually increasing. Eventually, in the not too distant future the number of cellular subscribers will exceed the number of fixed line telephone installations. Already, in many cases, the revenues from mobile services already exceeds that for fixed line services even though the amount of traffic generated through mobile phones is much less than in fixed networks. [0004] Other related wireless technologies have experienced growth similar to that of cellular. For example, cordless telephony, two way radio trunking systems, paging (one way and two way), messaging, wireless local area networks (WLANs) and wireless local loops (WLLs). In addition, new broadband communication schemes are rapidly being deployed to provide users with increased bandwidth and faster access to the Internet. Broadband services such as xDSL, short range high speed wireless connections, high rate satellite downlink (and the uplink in some cases) are being offered to users in more and more locations. [0005] In connection with cellular services, the majority of users currently subscribe to digital cellular networks. Almost all new cellular handsets sold to digital technology, typically second generation digital technology. Currently, third generation digital networks are being designed and tested which will be able to support data packet networks and much higher data rates. The first generation analog systems comprise the well known protocols AMPS, TACS, etc. The digital systems comprise GSM, TDMA (IS-136) or CDMA (IS-95), for example. [0006] A diagram illustrating an example prior art communication system employing an inner and outer encoder in the transmitter, inner and outer decoding stages in the receiver and a noise source after the channel is shown in FIG. 1. The communication system, generally referenced [0007] It is noted that both the inner and outer decoders in the receiver have complimentary encoders in the system. The outer encoder in the system comprises the encoder [0008] The bits output from the encoder are then interleaved wherein the order of the bits are changed so as to more efficiently combat burst errors. The rearrangement of the bits caused by interleaving improves the resistance to error bursts while adding latency and delay to the transmission. [0009] The bits output from the interleaver are then mapped to symbols by the bit to symbol mapper [0010] The output from the mapper is input to the modulator [0011] At the receiver [0012] Equalizers can be adapted to output hard symbol decisions or soft symbol decisions. Examples of types of commonly used hard decision equalizers include the maximum likelihood sequence estimation (MLSE) equalizer that utilize the well known Viterbi Algorithm (VA), linear equalizer and decision feedback equalizer (DFE). Examples of soft output type equalizers include Soft Output Viterbi Algorithm (SOVA) type equalizers and equalizers based on the more computational expensive Maximum A Posteriori (MAP) algorithm. [0013] In the case of a hard decision equalizer, the output of the inner decoder comprises symbols s(k) [0014] The output of the soft output generator is then input to a de-interleaver [0015] Examples of the outer decoder include turbo decoders and convolutional decoders that utilize the Viterbi Algorithm. This class of decoders provides better performance by taking into account soft information about the reliability of the received symbol. The improved performance of the decoder cannot be realized, however, when soft information about the received symbols is not available. Note that the Viterbi algorithm is widely used in communication systems and has been adapted to perform functions including demodulation, decoding, equalization, etc. Many systems utilize the Viterbi Algorithm in both the inner and outer decoding stages. [0016] As described above, the outer decoder, in some systems, is adapted to utilize the symbol decisions output from the inner decoder, e.g., the equalizer. Optimal decoders, however, require soft decisions rather than hard decisions. For example, an outer decoder that utilizes the Viterbi Algorithm to perform convolutional forward error correction decoding, requires soft decisions as input. The advantage of a Viterbi decoder is that it can efficiently process soft decision information. In order to provide soft symbol decisions, the inner decoder typically comprises a soft output equalizer such as a SOVA or MAP based equalizer. [0017] In some cases however, such as when either a punctured code is used or bit based rather symbol based interleaving is used, soft symbol decisions cannot be used by the outer decoder. Further, it is well known that an optimal decoder requires soft bit decisions rather than hard bit decisions. Thus, optimal outer decoders require soft bit inputs rather than soft symbol inputs or hard decisions. Note that a hard decision comprises a bit value (i.e. 0 or 1) and a soft bit decision may comprise a bit value in addition to the reliability of the decision. Alternately, a soft bit decision may comprise only the reliability value for a 1 decision or alternately a 0 decision. [0018] The problem is illustrated when considering a receiver adapted to handle a GSM EGPRS signal. Such a system utilizes a bitwise interleaver and punctured convolutional coding for performing Forward Error Correction (FEC) over channels that require equalization. Assume that the equalizer used employs a Soft Output Viterbi Algorithm in its operation and that the outer FEC decoder employs the Viterbi Algorithm. After de-interleaving, the soft symbol decision information output of the equalizer is no longer related to the bits output of the de-interleaver. [0019] In a system employing an optimal decoder, the equalizer is adapted to provide soft outputs, i.e. soft symbol decisions. As described above, well known soft output equalizers include those based on Maximum Likelihood Sequence Detection or methods such as MAP. However, the use of such techniques is impractical in communication systems having a large symbol alphabet or those systems with channels having a time spread of several symbol periods. Such criteria demand that a reduced complexity soft output equalizer be used. [0020] A prior art technique for generating soft bit decisions is described in A Soft-Decision State-Space Equalizer for FIR Channels, J. Thielecke, IEEE Transactions on Communications, Vol. 45, No. Oct. 10, 1997. A nonlinear equalizer is described that is intended for FIR channels which is based on a state-space description of the channel. The algorithm utilizes equations that resemble a Kalman hard decision feedback equalizer wherein the probability estimates of the received bits are incorporated. [0021] A disadvantage of this prior art technique is that the level of computational complexity is very high making it difficult to implement in practical communication systems. In addition, the technique is restricted to a particular type of channel and to a particular way of describing the channel. [0022] It is therefore desirable to further reduce the complexity of the soft symbol generator and the number of computations required to generate the soft bit information while maintaining optimality in the results. [0023] The present invention is a novel and useful apparatus for and method of reducing the soft output information packet to be computed by a soft symbol generator. The reduced soft output information packet generated by the soft symbol generator is subsequently used by a soft symbol to soft bit mapper which functions to convert soft symbol decision information into soft bit decision information. [0024] The invention is operative to construct (preferably a priori) a symbol competitor table that includes the most likely symbol competitors for each bit of the symbol. The table is populated with m entries for each possible symbol value, where m represents the number of bits per symbol. Symbol competitors are retrieved from the table in accordance with the hard decision. Soft symbol information is generated only for the symbol competitors rather than for all possible symbol thus substantially reducing the size of the information packet. [0025] The invention permits the soft symbol generator to provide fewer soft symbol values. As described above, only m+1 (m in some cases) rather than M soft symbol values are required to compute the bit log likelihood ratios. For each symbol, the hard decision symbol is required along with m soft symbol values. The additional m soft symbol values correspond to the symbol competitors (i.e. nearest neighbors) having a bit opposite to that of the symbol corresponding to the maximum soft symbol value. For the case of 8-PSK, each hard decision has associated with it 3 competing symbols. As shown by simulations, the method of the invention provides for improved performance of several dBs. [0026] The soft symbol information is subsequently input to a soft symbol to soft bit converter. Use of such a converter in the present invention enables the use of soft decoding in systems that incorporate a bit-wise rather than a symbol-wise interleaver. An example of such a system is the GSM Enhanced General Packet Radio System (EGPRS). The present invention is also applicable in systems wherein the encoder uses a different size alphabet than the modulator. A system may have, for example, a ½ rate code encoder concatenated with an 8-PSK modulator. In such a system, the soft symbol decision information output of the equalizer in the receiver does not match the type of soft decision information required by the decoder. [0027] The method of the invention can be performed in either hardware or software. A computer comprising a processor, memory, etc. is operative to execute software adapted to perform the reduced information packet method of the present invention. [0028] The invention provides several advantages. A key advantage is that a bit-wise or symbol-wise interleaver can be used in the system while nevertheless providing soft bit information to a soft input FEC decoder, e.g., soft decoder for turbo codes, convolutional codes, etc. Another advantage of the invention is that it is independent of the type of soft symbol generator used. Thus, the invention can be used with low complexity soft output generating mechanisms as well as with full complexity SOVA type mechanisms. [0029] Another benefit is that the approximation method and resulting table are computationally efficient in that a minimum number of arithmetic operations are required for their implementation. The symbol competitor table is relatively small and can be easily ROM based. The size of the table is Mlog [0030] There is thus provided in accordance with the present invention a method of generating a symbol competitor table for use in reducing the complexity of an information packet used to generate soft bit values from soft symbol information for am M-ary symbol alphabet, the method comprising the steps of for each of M possible symbol decisions: for each bit positions of m bits per symbol: calculating the Euclidean distance to the M/2 symbol decisions whose bit in position j is opposite to that of the j [0031] There is also provided in accordance with the present invention a method of reducing a soft output information packet generated by a soft symbol output generator, the method comprising the steps of pre-computing a symbol competitor table comprising the most likely symbol competitors for each possible symbol decision, looking up in the symbol competitor table, for each hard decision, the most likely symbol competitors corresponding to each of m bit positions, generating and outputting soft symbol decision values corresponding to each of the m symbol competitors and wherein m is a positive integer. [0032] There is further provided in accordance with the present invention a method of generating soft bit decisions from hard decisions for an M-ary symbol alphabet, the method comprising the steps of pre-computing a symbol competitor table comprising the most likely symbol competitors for each possible symbol decision, looking up in the symbol competitor table, for each hard decision, the most likely symbol competitors corresponding to each of m bit positions, calculating soft output values corresponding to each symbol competitor, calculating a soft bit decision value for each of m bits as a function of the hard decision and the competitor symbols corresponding to the particular bit position and wherein m and M are positive integers. [0033] There is also provided in accordance with the present invention a communications receiver for receiving and decoding an M-ary transmitted signal comprising a radio frequency (RF) front end circuit for receiving and converting the M-ary transmitted signal to a baseband signal, a demodulator adapted to receive the baseband signal and to generate a received signal therefrom in accordance with the M-ary modulation scheme used to generate the transmitted signal, a first decoder operative to receive the received signal and to generate a sequence of soft symbol decisions therefrom, a soft output computation module comprising processing means programmed to: pre-compute a symbol competitor table comprising the most likely symbol competitors for each possible symbol decision, look up in the symbol competitor table, for each hard decision, the most likely symbol competitors corresponding to each of m bit positions, calculate soft output values corresponding to each symbol competitor, calculate a soft bit decision value for each of m bits as a function of the hard decision and the competitor symbols corresponding to the particular bit position, a second decoder adapted to receive the soft bit values and to generate binary received data therefrom and wherein m and M are positive integers. [0034] There is still further provided in accordance with the present invention a computer readable storage medium having a computer program embodied thereon for causing a suitably programmed system to generate soft bit decisions from hard decisions by performing the following steps when such program is executed on the system: providing a symbol competitor table comprising the most likely symbol competitors for each possible symbol decision, looking up in the symbol competitor table, for each hard decision, the most likely symbol competitors corresponding to each of m bit positions, calculating soft output values corresponding to each symbol competitor, calculating a soft bit decision value for each of m bits as a function of the hard decision and the competitor symbols corresponding to the particular bit position and wherein m is a positive integer. [0035] There is also provided in accordance with the present invention a method of generating soft bit decisions from hard decisions for an M-ary symbol alphabet, the method comprising the steps of generating a full soft information packet comprising a soft decision for each possible symbol in the alphabet, pre-computing a symbol competitor table comprising the most likely symbol competitors for each possible symbol decision, looking up in the symbol competitor table, for each hard decision, the most likely symbol competitors corresponding to each of q bit positions, calculating a soft bit decision value for each of q bits for the soft symbol decisions in a partial reduced soft information packet comprising soft symbol decisions corresponding to the most likely symbol competitors and wherein q and M are positive integers. [0036] The invention is herein described, by way of example only, with reference to the accompanying drawings, wherein: [0037]FIG. 1 is a diagram illustrating an example prior art communication system employing an inner and outer encoder in the transmitter, inner and outer decoding stages in the receiver and a noise source added to the channel; [0038]FIG. 2 is a block diagram illustrating a concatenated receiver incorporating a soft output computation module constructed in accordance with the present invention; [0039]FIG. 3 is a block diagram illustrating the soft output computation module of the present invention in more detail; [0040]FIG. 4 is a diagram illustrating the symbol mapping of modulating bits for Gray coded 8-PSK modulation and their arrangement into two groups of MSB=0 and MSB=1; [0041]FIG. 5 is a diagram illustrating the symbol mapping of modulating bits for Gray coded 8-PSK modulation and their arrangement into two groups of SSB=0 and SSB=1; [0042]FIG. 6 is a diagram illustrating the symbol mapping of modulating bits for Gray coded 8-PSK modulation and their arrangement into two groups of LSB=0 and LSB=1; [0043]FIG. 7 is a flow diagram illustrating the symbol competitor table generation method of the present invention; [0044]FIG. 8 is a flow diagram illustrating the bit log likelihood ratio computation method of the present invention; [0045]FIG. 9 is a block diagram illustrating the functional processing blocks in a GSM EGPRS mobile station; [0046]FIG. 10 is a diagram illustrating the elements of a GSM message including tail, data and training symbols; [0047]FIG. 11 is a graph illustrating simulation results showing BER at the output of the outer decoder versus SNR for a concatenated communications receiver constructed with and without the reduced information packet method of the present invention; and [0048]FIG. 12 is a block diagram illustrating an example computer processing system adapted to perform the reduced information packet method of the present invention.
[0049] The present invention is an apparatus for and method of reducing the soft output information packet to be computed by a soft symbol generator that overcomes the disadvantages of the prior art. The reduced soft output information packet generated by the soft symbol generator is subsequently used by a soft symbol to soft bit mapper which functions to convert soft symbol decision information into soft bit decision information. [0050] The present invention is suitable for use with a wide range of communication systems and is particularly useful in communication systems having large symbol alphabets or in systems with channels having time spreads of several symbol periods. In addition, the invention is applicable to receivers that comprise concatenated coding schemes utilizing bitwise interleaving whereby the output of an inner decoder is subsequently processed by an outer decoder wherein the outer decoder is a soft decision decoder whose performance is optimized when soft decision values are available. [0051] The present invention provides a method of computing only the portion of the complete information packet actually needed by the soft symbol to soft bit mapper. Therefore, use of the invention reduces the requirements of the soft symbol generator. The soft symbol generator need only generate a reduced information packet rather than a complete information packet. Depending on the system and especially the size of the constellation, this can potentially result in large reductions in the number of computations and in the complexity of the processor. [0052] To aid in understanding the principles of the present invention, the method is described in the context of a soft output computation module. As described in more detail below, the soft output computation module is adapted to perform the following functions: noise power estimation, partial information packet calculation, soft symbol value generation and soft symbol to soft bit conversion. [0053] Note that the receiver configuration presented herein is intended for illustration purposes only and is not meant to limit the scope of the present invention. It is appreciated that one skilled in the communication signal processing arts can apply the method of the invention to numerous other topologies and scenarios as well. [0054] A block diagram illustrating a concatenated receiver incorporating a soft output computation module constructed in accordance with the present invention is shown in FIG. 2. The communication system, generally referenced [0055] Input data bits to be transmitted are input to the encoder [0056] The bits output of the encoder [0057] The symbols output from the mapper are input to the modulator [0058] The channel may comprise a mobile wireless channel, e.g., cellular, cordless, fixed wireless channel, e.g., satellite, or may comprise a wired channel, e.g., xDSL, ISDN, Ethernet, etc. It is assumed that noise is present and added to the signal in the channel. The transmitter is adapted to generate a signal that can be transmitted over the channel so as to provide robust, error free detection by the receiver. [0059] It is noted that both the inner and outer decoders in the receiver have complimentary encoders in the system. The outer encoder in the system comprises the encoder [0060] At the receiver [0061] The channel estimation [0062] Several methods of channel estimation that are known in the art and suitable for use with the present invention include, for example, a correlation method and a least squares method. The correlation method is described in detail in GSM System Engineering, A. Mehrotra, 1997, Chapter 6 and in the article On the Minimization of Overhead in Channel Impulse response Measurement, Y. Han, IEEE Transactions on Vehicular Technology, Vol. 47, No. [0063] Another channel estimation technique suitable for use with the present invention is described in U.S. patent application Ser. No. 09/616,161, to Yakhnich et al, filed Jul. 14, 2000, entitled Method of Channel Order Selection and Channel Order Estimation in a Wireless Communication System, similarly assigned and incorporated herein by reference in its entirety. [0064] The inner decoder is operative to use the channel estimate h(k) in generating the hard decisions. Note that a hard decision is one of the possible values a symbol s(k) can take. An example of an inner decoder is an equalizer which compensates for the ISI caused by the delay and time spreading of the channel. The function of the equalizer is to attempt to detect the symbols that were originally transmitted by the modulator. [0065] Note that the equalizer is adapted to output hard symbol decisions [0066] Equalization is a well known technique used to combat intersymbol interference whereby the receiver attempts to compensate for the effects of the channel on the transmitted symbols. An equalizer attempts to determine the transmitted data from the received distorted symbols using an estimate of the channel that caused the distortions. In communications systems where ISI arises due to partial response modulation or a frequency selective channel, a maximum likelihood sequence estimation (MLSE) equalizer is optimal. This is the form of equalizer generally used in GSM systems. [0067] The MLSE technique is a nonlinear equalization technique which is applicable when the radio channel can be modeled as a Finite Impulse Response (FIR) system. Such a FIR system requires knowledge of the channel impulse response tap values. The channel estimate is obtained using a known training symbol sequence to estimate the channel impulse response. Other equalization techniques such as DFE or linear equalization require precise knowledge of channel. [0068] The hard decisions are input to the soft output computation module [0069] The soft bit decisions are then input to a bitwise de-interleaver [0070] The outer decoder is a soft decision decoder, i.e. it takes soft bit values as input, which functions to detect and correct errors using the redundancy bits inserted by the encoder. The outer decoder [0071] A block diagram illustrating the soft output computation module of the present invention in more detail is shown in FIG. 3. The soft output computation module [0072] In operation, the equalizer [0073] Soft symbol values [0074] The soft symbol values are input to the soft symbol to soft bit converter [0075] The soft bit decision information [0076] In accordance with the invention, however, the requirement of generating the soft symbol information can be reduced from generating soft symbol information for all possible symbols to that of generating soft symbol information for only a partial subset of possible symbol. The soft symbol to soft bit converter [0077] The partial information packet calculator [0078] The complexity and number of required computation can be drastically reduced depending on the size of the alphabet and the constellation. In systems having large M-ary alphabets with large constellations, a significant reduction can be achieved in the size of the information packet generated and in the number of computations that are necessary. For example, in the case of 256 QAM, M=256 and m=8, only 8 (or 9 in some cases) soft symbols are generated using the partial information packet generator of the present invention rather than 256 soft symbols in the case of a full information packet. [0079] Note that any suitable soft symbol generator may be used with the present invention that is operative to generate soft symbol information from hard decisions. A technique for generating the soft decisions is described in U.S. Pat. No. 5,457,704 to Hoeher et al., entitled Post Processing Method and Apparatus for Symbol Reliability Generation, incorporated herein by reference in its entirety. Another suitable soft symbol generation technique is described in U.S. application Serial No. X, to Yakhnich et al., filed X, entitled Soft Decision Output Generator, incorporated herein by reference in its entirety. [0080] The operation of the soft output computation module A={A [0081] Each symbol can then be represented by m number of bits. Note that the modulation scheme used in GSM EDGE systems is 8-PSK with m=3. [0082] The Log Likelihood Ratio of a symbol S [0083] where [0084] y is a vector representation of the input; [0085] S [0086] A [0087] The soft output generator is capable of generating, at some time k, for the symbol S [0088] In a similar fashion, the log likelihood ratio of a bit b [0089] where B [0090] The conditional probability function of the input given a particular bit can be expressed as [0091] An optimal transformation of symbol LLR to bit LLR is thus given by
[0092] where [0093] D [0094] ∀lεD [0095] Thus, the log likelihood ratio for a bit is expressed as a function of the log likelihood ratios of the symbols. [0096] Due to the exponential nature of the conditional probability function in Equations 3 and 4, however, the expression for the bit LLR can be closely approximated by the following [0097] Thus, the log likelihood ratio for a bit can be approximated as the difference between a soft symbol value wherein the bit of interest is a one and a soft symbol value wherein the bit of interest is a zero. Note that this expression represents a suboptimal expression for the bit LLR. Note also that other types of soft bit output other than log likelihood ratios can also be generated. Other types of soft bit output derived using the principles of the present invention are intended to be within the scope of the invention. [0098] Since only C [0099] The derivation of Equation 5 will now be described in more detail. The method described herein is performed by the soft output computation module. Considering the assumption made above and the expressions for the symbol and bit LLRs in Equations 1 and 2, respectively, the conditional probability of the input y is determined given a bit is equal to a zero and a one. Let it be defined that symbol S [0100] where [0101] y is a vector representation of the input; [0102] S [0103] A [0104] b [0105] D [0106] ∀lεD [0107] A reasonable assumption can be made that the a priori probability of symbols and bits are equal (this is a valid assumption for most practical communication systems).
[0108] Therefore, the following expression for the conditional probability of the input as expressed in Equation 6 can be rewritten in terms of Equation 7.
[0109] Then, the bit Log Likelihood Ratio (LLR) as defined above in Equation 2 can be expressed as follows
[0110] Substituting Equation 1 into Equation 10 yields an optimal transformation of symbol LLR to bit LLR
[0111] Thus, the log likelihood ratio for a bit is expressed as a function of the log likelihood ratios of the symbols. The soft symbol to soft bit converter is operative to generate at each time k, for symbol S [0112] Note that the bit LLR derived using Equation 4 is the optimal transformation of symbol LLR to bit LLR. In accordance with the invention, a suboptimal expression for the bit LLR is derived which enables a significant reduction in complexity of computing the bit LLR. The suboptimal expression is derived by performing an approximation of the symbol probabilities. The approximation takes advantage of the rapid increase of the exponential functions in Equation 4. The maximum symbol value for the symbol where the bit of interest is a one and the maximum symbol value where the bit of interest is a zero are used instead as expressed in Equation 5 above. [0113] From above, it is assumed that a priori probability of symbols and bits are equal, allowing the expression for the conditional probability of the input to be rewritten as in Equations 8 and 9. The bit Log Likelihood Ratio (LLR) as defined above in Equation 2 is determined as expressed below
[0114] Consider the following which embodies the nearest neighbor approximation
[0115] where n represents the second largest soft symbol after the maximum. Due to the rapidly increasing exponential functions in the expression for the bit LLR, the maximum symbol value is by far the most dominate probability and the remaining
[0116] soft symbol values can be ignored. Therefore, the following approximation is valid
[0117] Thus, the maximum symbol values are substituted for the zero-symbol and one-symbol sums. Substituting Equation 14 into Equation 12 yields
[0118] Further substituting Equation 1 into Equation 15 yields an approximation of the transformation of symbol LLR to bit LLR.
[0119] Thus, the log likelihood ratio for a bit can be approximated as the difference between a soft symbol value wherein the bit of interest is a one and a soft symbol value wherein the bit of interest is a zero. [0120] Further, from a geometric point of view, the constellation of the symbol can be analyzed and computed a priori using
[0121] where A [0122] To aid in illustrating the approximation of the method of the present invention, diagrams in FIGS. 4, 5 and [0123] The symbol mapping diagrams are divided according to bit position. Referring to FIG. 4, dashed line [0124] The diagrams are used to determine which of the soft symbol values to use in computing the bit LLR. For each bit LLR that is to be computed, two symbol LLR values are required: one for the 0 bit and one for the 1 bit of the particular bit position of interest. Both are the maximum soft symbol values for the respective bits. The overall maximum soft symbol value is used for one of the bits while the soft symbol value of the nearest neighbor symbol whose bit is opposite to that of the overall maximum is used for the other. [0125] To illustrate, consider the symbol 101 whose corresponding soft symbol value, denoted by S [0126] For the MSB, in accordance with the method, the zero-symbol value is the maximum of all symbols whose MSB=0. The symbol most likely to yield the maximum value is the symbol closest to symbol [0127] The symbol competitors (or nearest neighbors) can be pre-calculated in accordance with the modulation scheme and the number of symbols in the constellation. To illustrate, the complete list of nearest neighbors for the GSM modulation of 8-PSK is presented below in Table 1.
[0128] Thus, for each symbol, only m+1 soft symbol values (the hard decision and m soft symbols) are required which results in reduced complexity for the equalizer and the soft symbol to soft bit converter. Note that m+1 soft symbol values are needed when the symbol conditional probabilities are referenced to the A [0129] The method of generating the symbol competitor table will now be described in more detail. The method can be performed on a computing device external to the soft output computation module a priori or can be performed by the soft output computation module itself. A flow diagram illustrating the symbol competitor table generation method of the present invention is shown in FIG. 7. The method is performed over all M possible symbols (step [0130] For each bit position, the Euclidean distance (i.e. decision distance) to the M/2 symbol decisions whose bit in position j is opposite to that of the j [0131] A pseudocode listing of the method of generating the symbol competitor table is shown below in Listing 1. It is appreciated that one skilled in the computer programming arts can easily generate source code for a variety of programming languages using the pseudocode presented below.
[0132] Note that as in the method of FIG. 7 (step [0133] A method of utilizing the symbol competitor table in computing the soft bit information will now be described. A flow diagram illustrating the bit log likelihood ratio computation method of the present invention is shown in FIG. 8. It is assumed that the symbol competitor table such as the one shown in Table 1 above has been pre-computed and stored in memory for use by the soft output computation module [0134] In operation, the partial information packet calculator [0135] The soft output symbol values are then input to the soft symbol to soft bit converter [0136] The invention provides several advantages. A key advantage is that a bit-wise or symbol-wise interleaver can be used in the system while nevertheless providing soft bit information to a soft input FEC decoder, e.g., soft decoder for turbo codes, convolutional codes, etc. Another advantage of the invention is that it is independent of the type of soft symbol generator used. Thus, the invention can be used with low complexity soft output generating mechanism as well as with full complexity SOVA type mechanism. Another benefit is that the approximation method and resulting table are computationally efficient in that a minimum number of arithmetic operations are required for their implementation. The symbol competitor table is relatively small and can be easily ROM based. The size of the table is Mlog [0137] In another embodiment of the invention, the symbol competitor data presented in Table 1 above is used to reduce the number of soft bit decisions input to the soft outer decoder. In this embodiment, the soft symbol generator receives a full information packet comprising a soft decision for each possible symbol in the alphabet. The method of the present invention is used to reduce the number of soft bit values that need to be computed. In accordance with the invention, soft bit decisions are computed only for those symbols found to be competitors for the particular hard decision. Thus, the output comprises soft bit decisions for a reduced soft information packet corresponding to the symbol competitors found using the particular hard decision. [0138] A GSM EGPRS mobile station constructed to comprise means for performing the reduced information packet method of the present invention is presented. A block diagram illustrating the functional processing blocks in a GSM EGPRS mobile radio station is shown in FIG. 9. The system is designed to provide reliable data communications at rates of up to 384 kbit/s. The GSM EGPRS mobile station, generally referenced [0139] In the transmit direction, the signal processing portion functions to protect the data so as to provide reliable communications from the transmitter to the base station [0140] In the receive direction, the output of the baseband codec is demodulated using a complementary 8-PSK demodulator [0141] The baseband codec converts the transmit and receive data into analog and digital signals, respectively, via D/A converter [0142] In the receive direction, the signal transmitted by the base station over the channel is received by the receiver circuitry [0143] In addition, the mobile station performs other functions that may be considered higher level such as synchronization, frequency and time acquisition and tracking, monitoring, measurements of received signal strength and control of the radio. Other functions include handling the user interface, signaling between the mobile station and the network, the SIM interface, etc. [0144] To illustrate the benefits of the present invention, a GSM Enhanced General Packet Radio System (EGPRS) was simulated and the results are presented herein. The simulation was performed assuming a GSM EGPRS transmitter and a 6 tap TU50iFH standard channel in sensitivity conditions. [0145] The EGPRS system is a Time Division Multiple Access (TDMA) system wherein eight users are able to share the same carrier frequency. In an EGPRS transmitter, the data bits are encoded with a rate ⅓ convolutional encoder, interleaved and mapped to 8-ary symbols. The resultant coded data symbols together with the training sequence are assembled into a burst of 142 symbols as shown in FIG. 10. [0146] In GSM, the training sequence is sent in the middle of each burst. Each fixed length burst [0147] The burst is then modulated using 3π/8-offset 8-PSK with Gaussian pulse shaping in accordance with the GSM standard. The modulated output is transmitted over a frequency selective static Gaussian channel utilizing punctured rate ⅓ convolutional coding. An equalizer operative to generate soft symbol values was used in the receiver. The receiver was adapted to convert the soft symbol information into soft bit information in accordance with the present invention. A soft input Viterbi Algorithm based convolutional decoder was used as the outer decoder. The soft bit values output from the converter were used as input for the soft decoder. [0148] A graph illustrating simulation results showing BER at the output of the outer decoder versus SNR for a concatenated communications receiver constructed with and without the reduced information packet method of the present invention is shown in FIG. 11. The solid curve with square boxes [0149] It can be seen that performance gains of 3 to 4 dB can be achieved using the present invention when compared to hard decision decoding. For example, at a BER of 10 [0150] In another embodiment, a computer is operative to execute software adapted to perform the reduced information packet method of the present invention. A block diagram illustrating an example computer processing system adapted to perform the reduced information packet method of the present invention is shown in FIG. 12. The system may be incorporated within a communications device such as a receiver or transceiver, part of which is implemented in software. [0151] The computer system, generally referenced [0152] One or more communication lines [0153] The reduced information packet method software is adapted to reside on a computer readable medium, such as a magnetic disk within a disk drive unit. Alternatively, the computer readable medium may comprise a floppy disk, Flash memory card, EEROM, EPROM or EEPROM based memory, bubble memory storage, ROM storage, etc. The software adapted to perform the reduced information packet method of the present invention may also reside, in whole or in part, in the static or dynamic main memories or in firmware within the processor of the computer system (i.e. within microcontroller, microprocessor, microcomputer, DSP, etc. internal memory). [0154] In alternative embodiments, the method of the present invention may be applicable to implementations of the invention in integrated circuits, field programmable gate arrays (FPGAs), chip sets or application specific integrated circuits (ASICs), wireless implementations and other communication system products. [0155] It is intended that the appended claims cover all such features and advantages of the invention that fall within the spirit and scope of the present invention. As numerous modifications and changes will readily occur to those skilled in the art, it is intended that the invention not be limited to the limited number of embodiments described herein. Accordingly, it will be appreciated that all suitable variations, modifications and equivalents may be resorted to, falling within the spirit and scope of the present invention. Referenced by
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