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Publication numberUS20020160571 A1
Publication typeApplication
Application numberUS 09/976,446
Publication dateOct 31, 2002
Filing dateOct 12, 2001
Priority dateApr 30, 2001
Also published asUS6596589
Publication number09976446, 976446, US 2002/0160571 A1, US 2002/160571 A1, US 20020160571 A1, US 20020160571A1, US 2002160571 A1, US 2002160571A1, US-A1-20020160571, US-A1-2002160571, US2002/0160571A1, US2002/160571A1, US20020160571 A1, US20020160571A1, US2002160571 A1, US2002160571A1
InventorsHorng-Huei Tseng
Original AssigneeHorng-Huei Tseng
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
High coupling ratio stacked-gate flash memory and the method of making the same
US 20020160571 A1
Abstract
A stacked-gate flash memory cell includes a trench formed in a substrate and a tunneling oxide is formed on the substrate. A first part of the floating gate is formed on the tunneling dielectric layer. A protruding isolation filler is formed in the trench and protruding over the upper surface of the first part of the floating gate, thereby forming a cavity between the two adjacent raised isolation filler. A second part of the floating gate formed of HSG-Si is formed along the surface of the cavity to have a U-shaped structure in cross sectional view. A dielectric layer is conformally formed on the surface of the second part of the floating gate and a control gate is formed on the dielectric layer.
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Claims(20)
What is claimed is:
1. A stacked-gate flash memory comprising:
a substrate having trenches formed therein;
a tunneling oxide formed on a surface of said substrate and adjacent to said trenches;
raised isolation fillers formed in said trenches and protruding over an upper surface of said substrate, thereby forming a cavity between two adjacent raised isolation fillers;
a floating gate formed along a surface of said cavity to have a U-shaped structure in cross sectional view, wherein said floating gate with roughness surface formed by HSG-Si;
a dielectric layer conformally formed on a surface of said floating gate; and
a control gate formed on said dielectric layer.
2. The stacked-gate flash memory of claim 1, wherein said raised isolation filler includes oxide.
3. The stacked-gate flash memory of claim 1, wherein said floating gate includes a first part formed of polysilicon.
4. The stacked-gate flash memory of claim 1, wherein said floating gate includes second part formed of said HSG-Si.
5. The stacked-gate flash memory of claim 1, wherein said dielectric layer includes oxide/nitride/oxide.
6. The stacked-gate flash memory of claim 1, wherein said dielectric layer includes oxide/nitride.
7. A method of manufacturing a stacked-gate flash memory, comprising:
forming a first dielectric layer on a semiconductor substrate as a tunneling dielectric;
forming a conductive layer on said first dielectric layer;
forming a sacrificed layer on said conductive layer;
patterning said sacrificed layer, said first dielectric layer, said conductive layer and said substrate to form trenches in said substrate;
forming isolations into said trenches;
removing said sacrificed layer, thereby forming a cavity between said isolations and said isolations protruding over said first conductive layer;
forming a HSG-Si along a surface of said cavity and said isolation;
removing a portion of said HSG-Si to a surface of said isolation, wherein said HSG-Si and said first conductive layer act as a floating gate;
forming a second dielectric layer on a surface of said floating gate; and
forming a second conductive layer on said second dielectric layer as a control gate.
8. The method of claim 7, wherein said sacrificed layer comprises nitride.
9. The method of claim 8, wherein said sacrificed layer is removed by hot phosphorus acid solution.
10. The method of claim 7, wherein said HSG-Si is removed by chemical mechanical polishing.
11. The method of claim 7, wherein said second dielectric layer comprises oxide/nitride.
12. The method of claim 7, wherein said second dielectric layer comprises oxide/nitride/oxide.
13. The method of claim 7, further comprising a step of removing the upper portion of the isolations prior to form said second dielectric layer.
14. A method of manufacturing a stacked-gate flash memory, comprising:
forming a first dielectric layer on a semiconductor substrate as a tunneling dielectric;
forming a sacrificed layer on said first dielectric layer;
patterning said sacrificed layer, said first dielectric layer and said substrate to form trenches in said substrate;
forming isolations into said trenches;
removing said sacrificed layer, thereby forming a cavity between said isolations and said isolations protruding over said first dielectric layer;
forming a HSG-Si along a surface of said cavity and said isolation;
removing a portion of said HSG-Si to a surface of said isolation, wherein said HSG-Si and said first conductive layer act as a floating gate;
forming a second dielectric layer on a surface of said floating gate; and
forming a first conductive layer on said second dielectric layer as a control gate.
15. The method of claim 14, further comprising a step of removing the upper portion of the isolations prior to form said second dielectric layer.
16. The method of claim 14, further comprising a step of forming a second conductive layer after forming said first dielectric layer.
17. The method of claim 14, wherein said sacrificed layer comprises nitride.
18. The method of claim 17, wherein said sacrificed layer is removed by hot phosphorus acid solution.
19. The method of claim 14, wherein said HSG-Si is removed by chemical mechanical polishing.
20. The method of claim 14, wherein said second dielectric layer comprises oxide/nitride or oxide/nitride/oxide.
Description

[0001] This is a continuous in part application of Ser. No. 09/846,468, filed on Apr. 4, 2001.

[0002] The present invention relates to a semiconductor device, and more specifically, to a flash memory having high coupling ratio and the method of fabricating the nonvolatile memory.

BACKGROUND OF THE INVENTION

[0003] The semiconductor industry has been advanced to the field of Ultra Large Scale Integrated (ULSI) technologies. The fabrication of the nonvolatile memories also follows the trend of the reduction of the size of a device. The high-density nonvolatile memories can be applied as the mass storage of portable handy terminals, solid state camera and PC cards. That is because that the nonvolatile memories exhibit many advantages, such as a fast access time, low power dissipation, and robustness. Further, it can be used to replace magnetic disk memory. The nonvolatile memories include various types of devices, such as EAROM (electrically alterable read only memory), EEPROM (electrically erasable programmable read only memory), EEPROM-EAROMs and non-volatile SRAMs.

[0004] Different types of devices have been developed for specific applications requirements in each of the segments of memory. In the device, electrical alterability is achieved by Fowler-Nordheim tunneling which is cold electron tunneling through the energy barrier at a silicon-thin dielectric interface and into the oxide conduction band. Typically, the thin dielectric layer is composed of silicon dioxide and the thin silicon dioxide layer allows charges to tunnel through when a voltage is applied to the gate. These charges are trapped in the silicon dioxide and remain trapped there since the materials are high quality insulators. A conventional flash memory is a type of erasable programmable read-only memory (EPROM) One of the advantages of flash memory is its capacity for block-by-block memory erasure. Furthermore, the speed of memory erasure is fast. For other EPROM, the memory erasure can take up to several minutes due to the erase mode of such type memory is done by bit-by-bit.

[0005] Various flash memories have been disclosed in the prior art, the type of the flash includes separated-gate and stacked-gate structure. U.S. Pat. No. 6,180,454 to Chang, et al, entitled “Method for forming flash memory devices”, and filed on Oct. 29, 1999. A further U.S. Pat. No. 6,153,906 to Chang, filed on Dec. 8, 1998. The device includes an oxide layer on a substrate. A stacked gate is formed on the substrate. A tunnel diffusion region is formed in the substrate next to a first side of the stacked gate. The tunnel diffusion region extends to a portion of the substrate under the stacked gate. A doped region is formed in the substrate next to a second side of the stacked gate. The doped region is distant away from the stacked gate by a lateral distance. U.S. Pat. No. 5,956,268 disclosed a Nonvolatile memory structure. The prior art allows for array, block erase capabilities.

[0006] U.S. Pat. No. 6,153,494 to Hsieh, et al., entitled “Method to increase the coupling ratio of word line to floating gate by lateral coupling in stacked-gate flash” and filed on Feb. 11, 1998. The object of this invention is to provide a method of forming a stacked-gate flash memory having a shallow trench isolation with a high-step in order to increase the lateral coupling between the word line and the floating gate. Hsieh disclosed a step of forming nitride layer and then forming hallow trench isolation (STI) through the nitride layer into the substrate. Then, oxide is filled into the STI, the nitride is then removed leaving behind a deep opening about the filled STI. The detailed description may refer to the prior art. A stacked-gate flash memory cell is provided having a shallow trench isolation with a high-step of oxide and high lateral coupling.

[0007] Hemispherical grain (HSG-Si) is a silicon layer with roughness surface to increase surface area. It has been applied in the field of DRAM. For example, the article entitled “A Capacitor-Over-Bit-Line Cell with a Hemispherical Grain Storage Node For 64 Mb Drams”, IEDM Tech Dig., December 1990, pp 655-658). The HSG-Si is deposited by low pressure chemical vapor deposition method at the transition temperature from amorphous Si to polycrystalline Si. This memory cell provides large storage capacitance by increasing the effective surface area of a simple storage node and is manufactured by optical delineation. The HSG-Si storage node can be fabricated by addition of two process steps, i.e. HSG-Si deposition and a etchback. HSG-Si appeared on silicon surface by using seeding method.

SUMMARY OF THE INVENTION

[0008] The object of the present invention is to form flash memory with higher coupling ratio.

[0009] It is another object of this invention to provide a method of forming a stacked-gate flash memory having HSG-Si to increase the coupling ratio between the control gate and the floating gate of the cell.

[0010] The stacked-gate flash memory cell includes a trench formed in a substrate and a tunneling oxide is formed on the substrate. A first part of the floating gate is formed on the tunneling oxide. A raised isolation filler is formed in the trench and protruding over the upper surface of the first part of the floating gate, thereby forming a cavity between the two adjacent raised isolation filler. A second part of the floating gate is formed along the surface of the cavity to have a U-shaped structure in cross sectional view. A dielectric layer is conformally formed on the surface of the second part of the floating gate and a control gate is formed on the dielectric layer.

[0011] The method comprises forming a first dielectric layer on a semiconductor substrate as a tunneling dielectric and forming a first conductive layer and a sacrificed layer on the first dielectric layer. Next step is to pattern the sacrificed layer, the first dielectric layer, the first conductive layer and the substrate to form a trench in the substrate. An isolation is refilled into the trench, a portion of isolation is removed to a surface of the sacrificed layer. The sacrificed layer is then removed, thereby forming a cavity between adjacent isolations. A second conductive layer is formed along a surface of the cavity and the isolation. Next, a portion of the second conductive layer is removed to a surface of the isolation. Subsequently, a second dielectric layer is formed on a surface of the floating gate, a third conductive layer is formed on the second dielectric layer as a control gate.

BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The foregoing aspects and many of the attendant advantages of this invention will become more readily appreciated as the same becomes better understood by reference to the following detailed description, when taken in conjunction with the accompanying drawings, wherein:

[0013]FIG. 1 is a cross section view of a semiconductor wafer illustrating the steps of forming a trench in a substrate according to the present invention.

[0014]FIG. 2 is a cross section view of a semiconductor wafer illustrating the step of forming protruding isolation according to the present invention.

[0015]FIG. 3 is a cross section views of a semiconductor wafer illustrating the step of forming HSG-Si according to the present invention.

[0016]FIG. 4 is a cross section views of a semiconductor wafer illustrating the step of removing a portion of the HSG-Si according to the present invention.

[0017]FIG. 5 is a cross section views of a semiconductor wafer illustrating the step of forming control gate according to the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

[0018] The present invention proposes a novel structure and method to fabricate the stacked-gate flash memory. The stacked-gate flash memory cell includes a trench formed in a substrate 2, please refer to FIG. 3. A tunneling oxide 4 is formed on the surface of the substrate 2 and adjacent to the trench 4. A first part of the floating gate 6 is formed on the tunneling gate oxide 4. A protruding isolation (filler) 10 is formed in the trench and protruding over the upper surface of the first part of the floating gate 6, thereby forming a cavity 14 between the adjacent protruding isolation filler 10. A second part of the floating gate 16 is formed along the surface of the cavity 14 to have a U-shaped structure in cross sectional view. The second part of the floating gate 16 is formed by HSG-Si. A dielectric layer 18 is conformally formed on the surface of the second part of the floating gate 16 and a control gate is formed on the dielectric layer 20.

[0019] The method of forming the structure is described as follows. In the method, a trench is formed and a floating gate is formed in the trench to increase the coupling ratio. The detail description of the method will be seen as follows. In a preferred embodiment, as shown in the FIG. 1, a single crystal silicon substrate 2 with a <100> or <111> crystallographic orientation is provided. A dielectric such as oxide layer 4 is formed on the substrate 2 as tunneling dielectric layer. Typically, the oxide 4 can be grown in oxygen ambient in a furnace at a temperature of about 800 to 1100 degrees centigrade. The thickness of the silicon oxide layer 4 is about 50 to 500 angstroms. Other method, such as chemical vapor deposition, can be used to form the oxide 4. It is appreciated that any suitable material such as silicon oxynitride may be used as the gate dielectric. Preferably, the silicon oxynitride layer is formed by thermal oxidation in N2O or NO environment. The temperature for forming the silicon oxynitride layer 4 ranges from 700 to 1150 degrees centigrade.

[0020] Next, as can be seen by reference to FIG. 1, a conductive layer, such as doped polysilicon layer 6, is formed on the oxide layer 4. The doped polysilicon layer 6 can be chosen from doped polysilicon or in-situ doped polysilicon. This is achieved preferably through a LPCVD method employing silane as a silicon source material at a temperature range between about 500 to 650 degree C. The thickness of the polysilicon is about 2000-6000 angstroms. Next, a sacrificed layer 8 is subsequently formed on the doped polysilicon layer 6. Preferably, the material used to form the sacrificed layer 8 is nitride. The silicon nitride layer 8 is deposited by any suitable process. For example, Low Pressure Chemical Vapor Deposition (LPCVD), Plasma Enhance Chemical Vapor Deposition (PECVD), High Density Plasma Chemical Vapor Deposition (HDPCVD). In the preferred embodiment, the reaction gases of the step to form silicon nitride layer include SiH4, NH3, N2 or SiH2Cl2, NH3, N2.

[0021] A photoresist is patterned on the sacrificed layer 8 to define trench region, followed by etching the stacked layer consisting of the sacrificed layer 8, the polysilicon layer 6, dielectric layer 4 and the substrate 2 to form trenches 10 in the substrate 2. The photoresist is next removed by oxygen plasma ashing. Subsequently, the trench 10 is filled with isolation oxide 12, using the method of high density plasma (HDP) deposition or LPCVD. Next, the substrate 2 is subjected to chemical-mechanical polishing (CMP), thus forming shallow trench isolation (STI) 12 as shown in FIG. 2. Then, the sacrificed layer 8 is removed by hot phosphorus acid solution, thereby forming protruding isolation filler 12 protruding over the surface the polysilicon 6. A cavity 14 is therefore formed between the raised isolation filler 10. The step high of the protruding isolation filler 12 can be defined by the thickness of the sacrificed layer 8. Hence, the coupling ratio can be controlled by the present invention.

[0022] Next, referring to FIG. 3, a conductive layer 16 such as in-situ doped polysilicon along the surface of the cavity 14 and the protruding isolation filler 12. Preferably, the conductive layer 16 is formed by HSG-Si to increase the surface area. The thickness of the conductive layer 16 is about 100-1000 angstroms. Next, the HSG-Si 16 is removed to expose the upper surface of the protruding isolation filler 12 by CMP. The HSG-Si 16 only remains on side wall and bottom of the cavity 14, as shown in FIG. 4.

[0023] The polysilicon layer 6 and the remained HSG-Si 16 serve as a floating gate and isolated by the protruding isolation filler 12. As another key aspect of the present invention, remained HSG-Si 16 is conformally formed so as to follow the contours of the cavity 14, thus providing additional surface to the control gate dielectric that is to be formed later. In another words, HSG-Si should not fill the totally the cavity 14.

[0024] Turning to FIG. 5, the upper portion of the protruding isolation filler 12 is removed by selectively etching, thereby increasing the coupling ratio due to the side surface of the HSG-Si is exposed. An interpoly dielectric layer 18 is next formed over the contours of the conformal floating gate and the upper surface of the protruding isolation filler 12, as shown in FIG. 5. It is preferred that the interpoly dielectric layer 18 comprises but not limited to oxide/nitride/oxide (ONO), ON. Then, a further polysilicon layer 20 is formed over the interpoly dielectric layer 18 to act as the control gate and word line. Thus, a stacked-gate flash is formed as shown in the cross-sectional view of FIG. 5. A further patterning may be used to define the control gate.

[0025] The higher coupling can be obtained due to the floating gate formed against the high-step oxide protruding over the isolation trench of the present invention. The HSG-Si with larger surface area is used. Further, the filler 12 is etched prior to form the interpoly dielectric layer 18 to expose the side surface of the HSG-Si.

[0026] It has to be noted that the first conductive layer 6 can be omitted and to increase the thickness of the sacrificed layer 8 in order increase the coupling surface. After the isolation 12 is formed, followed by removing the entire sacrificed layer 8. The following sequences are similar to the aforementioned embodiment to deposit the conductive layer 16, polish the layer 16 and to form the ONO 18, the control gate 20.

[0027] The stacked-gate flash memory cell includes trenches formed in a substrate 2, a tunneling oxide 4 is formed on the surface of the substrate 2 and adjacent to the trench 4. A protruding isolation (filler) 12 is formed in the trench and protruding over the upper surface of the tunneling oxide 4, thereby forming a cavity 14 between the adjacent protruding isolation filler 10. A floating gate 16 is formed along the surface of the cavity 14 to have a U-shaped structure with roughness surface in cross sectional view. A dielectric layer 18 is conformally formed on the surface of the second part of the floating gate 16 and a control gate is formed on the dielectric layer 20.

[0028] As will be understood by persons skilled in the art, the foregoing preferred embodiment of the present invention is illustrative of the present invention rather than limiting the present invention. Having described the invention in connection with a preferred embodiment, modification will now suggest itself to those skilled in the art. Thus, the invention is not to be limited to this embodiment, but rather the invention is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims, the scope of which should be accorded the broadest interpretation so as to encompass all such modifications and similar structures.

[0029] While the preferred embodiment of the invention has been illustrated and described, it will be appreciated that various changes can be made therein without departing from the spirit and scope of the invention.

Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US6781189Jan 22, 2002Aug 24, 2004Micron Technology, Inc.Floating gate transistor with STI
US6812095 *Jun 4, 2002Nov 2, 2004Micron Technology, Inc.Methods of forming floating gate transistors using STI
US7985670 *May 16, 2008Jul 26, 2011Dongbu Hitek Co., Ltd.Method of forming U-shaped floating gate with a poly meta-stable polysilicon layer
US8129242 *May 12, 2006Mar 6, 2012Macronix International Co., Ltd.Method of manufacturing a memory device
US20120264264 *Jun 28, 2012Oct 18, 2012Maxchip Electronics Corp.Method of fabricating non-volatile memory device
Classifications
U.S. Classification438/257, 257/E21.682, 257/E27.103, 257/E29.129, 438/259
International ClassificationH01L27/115, H01L23/31, H01L29/423, H01L21/8247
Cooperative ClassificationH01L2924/0002, H01L29/42324, H01L23/3114, H01L27/11521, H01L2924/19041, H01L27/115
European ClassificationH01L27/115, H01L29/423D2B2, H01L23/31H1, H01L27/115F4
Legal Events
DateCodeEventDescription
Dec 24, 2010FPAYFee payment
Year of fee payment: 8
Dec 21, 2006FPAYFee payment
Year of fee payment: 4
Oct 12, 2001ASAssignment
Owner name: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION,
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:TSENG, HORNG-HUEI;REEL/FRAME:012269/0490
Effective date: 20011002
Owner name: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION S
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:TSENG, HORNG-HUEI /AR;REEL/FRAME:012269/0490