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Publication numberUS20020167836 A1
Publication typeApplication
Application numberUS 09/855,165
Publication dateNov 14, 2002
Filing dateMay 14, 2001
Priority dateSep 29, 1999
Also published asUS6487107
Publication number09855165, 855165, US 2002/0167836 A1, US 2002/167836 A1, US 20020167836 A1, US 20020167836A1, US 2002167836 A1, US 2002167836A1, US-A1-20020167836, US-A1-2002167836, US2002/0167836A1, US2002/167836A1, US20020167836 A1, US20020167836A1, US2002167836 A1, US2002167836A1
InventorsRaj Jain
Original AssigneeJain Raj Kumar
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Retention time of memory cells by reducing leakage current
US 20020167836 A1
Abstract
A memory cell having first and second access transistors coupled to a storage transistor is disclosed. During a write 0 operation, a degraded logic 0 is written into the memory cell. By storing a degraded logic 0, the leakage current is reduced.
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Claims(1)
What is claimed is:
1. A memory cell comprising:
first and second access transistors, each with a gate and first and second terminals
first and second bit lines, the first bit line coupled to the first terminal of the first access transistor and the second bit line coupled to a first terminal of the second transistor;
first and second word lines, the first word line coupled to the first access transistor and the second word line coupled to the second access transistor;
a storage transistor having a gate and first and second terminals, the first and second terminals respectively coupled to the second terminals of the first and second access transistors; and
sense amplifiers coupled to the first and second bit lines, the sense amplifier, during a write logic 0 operation, causes a degraded logic 0 to be stored in the storage transistor.
Description

[0001] This is a continuation-in-part of patent applications, titled: “Dual-Port Memory Cell”, U.S. Ser. No. ______ (attorney docket number: 98P 02816US; “Single-Port Memory Cell”, U.S. Ser. No. ______ (attorney docket number: 98P 02842US) and “Layout for a SemiConductor Memory”, U.S. Ser. No. 09/615,987 (attorney docket number: 98P 02864US).

FIELD OF THE INVENTION

[0002] The present invention relates generally to integrated circuits. More particularly, the invention relates to reducing leakage current in integrated circuits.

BACKGROUND OF THE INVENTION

[0003] Integrated circuits (ICs) such as digital signal processors (DSPs) include on-chip memory to store information. The on-chip memory typically comprises, for example, an array of static random access memory (SRAM) cells connected by word lines in one direction and bit lines in another direction. The information stored in the SRAM cells are maintained until power is removed from the IC. Sense amplifiers are coupled to the bit lines to facilitate memory accesses, such as reads or writes. A sense amplifier is coupled to a pair of bit lines and senses a differential voltage indicative of the information stored in the selected memory cell on the bit line pair.

[0004]FIG. 1 shows a conventional SRAM cell 101. The SRAM cell comprises first and second transistors 110 and 120 coupled to a latch 130, which stores a bit of information. One transistor is coupled to a bit line 140 and the other is coupled to a bit line complement 141 while the gates are coupled to a word line 135. The latch includes first and second inverters 133 and 134, each implemented with two transistors. As such, the SRAM cell is realized using six transistors.

[0005] Smaller SRAM cells using less than six transistors have been proposed to reduce chip size. However, the charge stored in such cells dissipates overtime. In order to restore the information stored in the cell, a refresh operation is required. Typically, refreshing of memory cells interrupt the normal operation, adversely impacting performance.

[0006] As evidenced from the above discussion, it is desirable to provide a memory cell with reduced leakage current in order to improve retention time.

SUMMARY OF THE INVENTION

[0007] The present invention relates generally to memory cells. More particularly, the invention relates to improving retention time in memory cells. In one embodiment, the memory cell comprises first and second access transistors coupled to respective first and second terminals of a storage transistor. Bit lines are coupled to first terminals of the access transistors and word lines are coupled to the gates of the access transistors. In one embodiment, a degraded logic 0 is written to the memory cell during a write 0, causing the memory cell to store a degraded logic 0. Storing a degraded logic 0 in the memory cell reduces leakage current.

BRIEF DESCRIPTION OF THE DRAWINGS

[0008]FIG. 1 shows a conventional SRAM cell; and

[0009]FIG. 2 shows a memory cell in accordance with one embodiment of the invention.

PREFERRED EMBODIMENTS OF THE INVENTION

[0010]FIG. 2 shows a memory cell 201 in accordance with one embodiment of the invention. The memory cell comprises first and second access transistors 220 and 260 coupled in series to a storage transistor 240. The transistors, in one embodiment, comprise n-FETs. The memory cell can also be implemented with p-FETs or a combination of n and p-FETs.

[0011] The access transistors can serve as memory access ports, each coupled to a bit line (240 or 241) and a word line (235 or 236). In one embodiment, the first access transistor's first terminal 221 is coupled to the bit line 240 and its gate is coupled to the word line 235. Similarly, the second access transistor's first terminal 261 is coupled to bit line 241 and its gate is coupled to word line 236. The memory cell can be accessed either through the first or second port. Refreshing of the memory cell can also be performed through the access ports.

[0012] Second terminals 222 and 262 of the access transistors are coupled respectively to first and second terminals 241 and 242 of the storage transistor. A gate 243 of the storage transistor is coupled to an active signal to render the transistor conductive. In one embodiment, the storage transistor is an n-FET with its gate coupled to an active signal. In one embodiment, the active signal comprises VDD. As such, when power is applied to the IC, the storage transistor is rendered conductive to couple the first and second terminals together to form node A. When power is removed from the IC, the first and second terminals are isolated from each other.

[0013] A memory access from the first port is performed by activating the word line 235 (e.g., logic 1) to render the first access transistor conductive. As a result, node A is coupled to the bit line via the first access transistor's first terminal 221. The charge stored at node A is transferred to the bit line for a read access or the charge on the bit line is transferred to node A for a write access by write circuitry. Accessing the second port of the memory cell is achieved by selecting the word line 236 to couple node A to the bit line 241. A refresh can be performed in the first or second port by activating the first or second word line.

[0014] In another embodiment, the first port of the memory cell serves as an access port and the second port of the memory cell serves as a dedicated refresh port from which refreshes are performed. The first port is coupled to a bit line and a word line while the refresh port is coupled to a refresh bit line and a refresh word line. The operation of such a memory cell is described in concurrently filed patent application “Memory Architecture with Refresh and Sense Amplifiers”, U.S. Ser. No. ______ (attorney docket number 00E 16984SG), which is herein incorporated by reference for all purposes.

[0015] In accordance with the invention, write circuitry 280 coupled to the bit lines, is designed to write a degraded logic 0 into the memory cell during a write zero operation. In one embodiment, the degraded logic 0 is greater than Vss (0V). The degraded logic 0 is equal to Vss+Vd, where Vd is greater than 0V and less than gate threshold voltage of the access transistor. In one embodiment Vd is from 0.1-0.4V. By writing a degraded logic 0 into the memory cell, the gate to source voltage of the access transistors is reduced. This reduces the leakage current through the channels of the access transistors, thereby improving the cells retention time as well as reducing power consumption.

[0016] The memory cell is fabricated on a substrate using conventional techniques. Various cell arrangements or layouts, such as those described in, for example, parent patent application, titled: “Layout for a SemiConductor Memory”, U.S. Ser. No. 09/615,987 (attorney docket number: 98P 02864US) and which is herein incorporated by reference for all purposes, are also useful.

[0017] While the invention has been particularly shown and described with reference to various embodiments, it will be recognized by those skilled in the art that modifications and changes may be made to the present invention without departing from the spirit and scope thereof. The scope of the invention should therefore be determined not with reference to the above description but with reference to the appended claims along with their full scope of equivalents.

Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US7277990Sep 30, 2004Oct 2, 2007Sanjeev JainMethod and apparatus providing efficient queue descriptor memory access
US7418543Dec 21, 2004Aug 26, 2008Intel CorporationProcessor having content addressable memory with command ordering
US7467256Dec 28, 2004Dec 16, 2008Intel CorporationProcessor having content addressable memory for block-based queue structures
US7555630Dec 21, 2004Jun 30, 2009Intel CorporationMethod and apparatus to provide efficient communication between multi-threaded processing elements in a processor unit
Classifications
U.S. Classification365/154, 257/E27.098, 257/E27.084, 257/E21.654
International ClassificationH01L21/8242, G11C11/406, H01L27/11, G11C11/405, G11C11/4091, H01L27/108
Cooperative ClassificationG11C11/405, H01L27/108, H01L27/11, G11C11/406, G11C11/403, G11C11/404, G11C11/4091, H01L27/10873
European ClassificationG11C11/404, G11C11/403, G11C11/406, G11C11/4091, G11C11/405, H01L27/108, H01L27/11
Legal Events
DateCodeEventDescription
May 23, 2014FPAYFee payment
Year of fee payment: 12
May 21, 2010FPAYFee payment
Year of fee payment: 8
May 18, 2006FPAYFee payment
Year of fee payment: 4
Jun 4, 2003ASAssignment
Owner name: INFINEON TECHNOLOGIES AKTIENGESELLSCHAFT, GERMANY
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:JAIN, RAJ KUMAR;REEL/FRAME:013701/0146
Effective date: 20020911
Owner name: INFINEON TECHNOLOGIES AKTIENGESELLSCHAFT ST. MARTI