US20020173087A1 - System to improve SER immunity and punchthrough - Google Patents
System to improve SER immunity and punchthrough Download PDFInfo
- Publication number
- US20020173087A1 US20020173087A1 US10/191,107 US19110702A US2002173087A1 US 20020173087 A1 US20020173087 A1 US 20020173087A1 US 19110702 A US19110702 A US 19110702A US 2002173087 A1 US2002173087 A1 US 2002173087A1
- Authority
- US
- United States
- Prior art keywords
- well tub
- deposited
- tub
- additional
- depth
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76237—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0921—Means for preventing a bipolar, e.g. thyristor, action between the different transistor regions, e.g. Latchup prevention
Definitions
- This invention relates to the field of semiconductor wafer processing. More particularly the invention relates to a system for improving the electrical characteristics of static random access memory devices.
- One issue that is always of high priority is that of maintaining electrical pathway integrity within the device. In other words, ensuring that charge carrier flow is limited to those pathways and those times at which it is desired.
- the size of the semiconductor device decreases, the size of these structures must also preferably decrease, which tends to reduce the inherent effectiveness of the isolation structure. This may result in a number of different problems, such as an increase in the soft error rate (SER), where devices become unstable and lose their specified state.
- SER soft error rate
- the ability to open and close the current pathway in a semiconductor device is fundamental to the proper operation of the device.
- the standard structures that were developed for larger devices tend to be less effectual in preventing inadvertent leakage through the isolation region of smaller transistors.
- current interwell punchthrough in the isolation tends to become a bigger problem as the devices are made smaller.
- additional systems are needed to augment the strength of the isolation region.
- the additional well tub is deposited using an ion implantation process to a depth that is shallower than the standard well tub.
- the SRAM device is preferably isolated from adjacent devices with a shallow trench isolation structure that extends to a depth, and the additional well tub is deposited to a depth that is deeper than the depth of the shallow trench isolation structure.
- the additional well tub is implanted using the same mask set as that used for the threshold voltage adjustment deposition of the SRAM device. Thus, in the preferred embodiment, no additional mask layer is required to deposit the additional well tub, and all of the expenses normally associated with an additional mask layer are avoided.
- FIG. 1 is a cross-sectional dopant profile of a standard well tub
- FIG. 2 is a cross-sectional dopant profile of a semiconductor device receiving the additional well tub deposition
- FIG. 3 is a cross-sectional dopant profile of a semiconductor device after receiving the additional well tub deposition
- FIG. 4 is a dopant profile chart.
- FIG. 1 a cross-sectional view of a substrate 10 having semiconductor device regions 22 , 24 , 26 , and 28 in a wafer 14 .
- the devices that will be formed in device regions 22 , 24 , 26 , and 28 are only in the very beginning phases of construction.
- isolation structures 16 such as shallow trench isolation oxide structures, have been formed in the semiconductor material 14 .
- Wells 18 and 20 have also been formed. In the embodiment depicted, wells 18 represent N doped wells and wells 20 represent P doped wells.
- a layer of sacrificial oxide 12 has been deposited over the surface of the substrate 14 .
- a layer of photoresist 30 has been deposited on the sacrificial oxide 12 .
- the photoresist 30 has been cured, exposed, developed, and baked to provide a deposition mask on the substrate 10 .
- a dopant 32 is deposited through the sacrificial oxide layer 12 and into the semiconductor material 14 .
- the dopant material 32 is selected to be of the same type, either P or N, as the well of the device region into which it is deposited. Therefore, in the embodiment depicted in FIG. 2, the dopant 32 is a P type species, because the well 20 is P type.
- the dopant 32 is preferably deposited to a depth that is greater than the isolation structure 16 and shallower than the well 20 .
- the additional dopant 32 is concentrated within a region 34 of the device 24 where it provides a higher junction capacitance for the device 24 , thus enhancing SER immunity, and also strengthens the channel region that is to be further defined at later stages of the processing, thus enhancing deep channel punchthrough resistance as well as increasing interwell punchthrough resistance.
- This region 34 is essentially the deposition of an additional well 34 .
- An additional benefit of this system is that the mask layers and methods used to form the photoresist layer 30 are not in addition to those required for the standard processing of the devices 22 , 24 , 26 , and 28 .
- an SRAM device such as device 24
- typically requires a threshold depletion deposition which uses a mask structure that is identical to that described above and depicted in FIG. 2.
- the threshold depletion dopant can be deposited. In this manner, only a single deposition step is added to the fabrication process, without any additional mask layer processing required.
- this system is compatible with the fabrication of SRAM devices 22 and 24 that are formed on the same substrate 10 as logic devices 26 and 28 , which do not typically require a threshold depletion deposition.
- the processing used to enhance the electrical characteristics of the SRAM devices 22 and 24 does not add complexity to the processing of or degrade the performance of the logic devices 26 and 28 .
- a similar mask layer is used to provide a photoresist mask layer through which to deposit a similar well structure 33 into the SRAM device 22 as depicted in FIG. 3. As mentioned above, this is the same mask layer through which the threshold adjustment layer for the SRAM device 22 is deposited. Thus, the formation of the additional well 33 does not require any additional masking steps, and likewise does not impact the fabrication or reliability of the logic devices 26 and 28 . Similar to that as described above, because the dopant used for the well 18 is N type, the dopant used for the additional well 33 is also N type. FIG.
- FIG. 3 depicts the devices 22 , 24 , 26 , and 28 at a later stage of processing, where the sacrificial oxide layer 12 has been removed, gate structures 40 have been created, and source and drain regions have been deposited with P+ dopant 36 and N+ dopant 38 .
- FIG. 4 depicts the relative concentration of the various dopants as a function of depth in semiconductor material 14 , as viewed along section 35 in FIG. 3.
- Line 42 represents the concentration of the N+ source/drain region 38
- line 44 represents the concentration of the P additional well 34
- line 46 represents the concentration of the standard P well 20 .
- Line 48 represents the depth of the bottom of the isolation structure 16 .
- that portion of the additional well 34 at which the concentration of dopant is the greatest as represented by line 44 on the chart of FIG. 4 extends to a depth in the semiconductor material 14 that is greater than the depth of the isolation structure 16 as represented by line 48 on the chart of FIG. 4. Further, that portion of the additional well 34 at which the concentration of dopant is the greatest, as represented by line 44 on the chart of FIG. 4, extends to a depth in the semiconductor material 14 that is shallower or less than the depth of that portion of the standard well 20 at which the concentration of dopant is the greatest, as represented by line 46 on the chart of FIG. 4.
- the dopants for the various structures are deposited using an ion implantation process.
- the additional P well 34 of SRAM device 24 may be preferably formed by ion implantation of Boron (B 11 ) at an energy of between about 25 keV and about 190 keV and a ion dose of between about 10 11 ions/cm 2 and about 10 14 ions/cm 2 , which implants the species at a nominal depth of between about 0.1 microns and about 0.5 microns.
- the additional N well 33 of SRAM device 22 may be preferably formed by ion implantation of Phosphorus (P 31 ) at an energy of between about 80 keV and about 360 keV and a ion dose of between about 10 11 ions/cm 2 and about 10 14 ions/cm 2 , which implants the species at a nominal depth of between about 0.1 microns and about 0.5 microns.
- P 31 Phosphorus
- the dopant type of the additional well tubs 33 or 34 is the same as the dopant type of the corresponding standard well tubs 18 or 20 , respectively.
- other dopant species of the corresponding dopant type whether P or N, may be used in place of those specifically described in the example above.
- the doses described above yield a resultant concentration of between about 10 17 ions/cm 3 and about 10 20 ions/cm 3 within the additional well tubs 33 and 34 .
- the processes described above are preferably used when the nominal depth of the standard well tubs 18 and 20 is between about 0.2 microns and about 1.0 microns, and the depth of the isolation structures 16 is between about 0.08 microns and about 0.45 microns.
- the processes described above for the deposition of the additional well tubs 33 and 34 would be adjusted commensurately.
Abstract
Description
- This invention relates to the field of semiconductor wafer processing. More particularly the invention relates to a system for improving the electrical characteristics of static random access memory devices.
- As semiconductor device geometries shrink, design engineers encounter new problems that tend to reduce the reliability of the devices. In addition, solutions that were developed to overcome previously identified problems may become ineffectual or create other problems as the geometries shrink and other processing constraints change. Thus, there is a continual need to improve upon the methods and structures relied upon in the past.
- One issue that is always of high priority is that of maintaining electrical pathway integrity within the device. In other words, ensuring that charge carrier flow is limited to those pathways and those times at which it is desired. For example, it is typically desired to electrically isolate semiconductor devices that are formed adjacent to one another in a semiconducting substrate. This is accomplished in a variety of ways, such as by using locos oxidation or shallow trench isolation techniques. However, as the size of the semiconductor device decreases, the size of these structures must also preferably decrease, which tends to reduce the inherent effectiveness of the isolation structure. This may result in a number of different problems, such as an increase in the soft error rate (SER), where devices become unstable and lose their specified state. Thus, additional systems need to be found to augment the isolation provided by these structures.
- As a further example, the ability to open and close the current pathway in a semiconductor device such as a MOS transistor is fundamental to the proper operation of the device. Again, however, as device geometries are reduced, the standard structures that were developed for larger devices tend to be less effectual in preventing inadvertent leakage through the isolation region of smaller transistors. Thus, current interwell punchthrough in the isolation tends to become a bigger problem as the devices are made smaller. Here again, additional systems are needed to augment the strength of the isolation region.
- While there may be many systems that could be devised to alleviate these and other problems, they tend to add complexity, expense and time to the device fabrication process. Typically, these added steps come in the form of additional mask layers that must be developed and used. Thus, the financial pressures inherent in semiconductor device fabrication must also be weighed in finding solutions to these conditions.
- What is needed, therefore, is a system to improve the soft error rate immunity and isolation punchthrough tolerance of a device, without requiring additional mask layers.
- The above and other needs are met by a method for fabricating an SRAM device having a standard well tub, where an additional well tub is deposited within the standard well tub. The additional well tub is deposited to a depth that is shallower than the standard well tub. In this manner, the dopant concentration is increased in the well area of the SRAM device, which increases both the isolation punchthrough tolerance and the SER immunity of the device.
- In a preferred embodiment, the additional well tub is deposited using an ion implantation process to a depth that is shallower than the standard well tub. Further, the SRAM device is preferably isolated from adjacent devices with a shallow trench isolation structure that extends to a depth, and the additional well tub is deposited to a depth that is deeper than the depth of the shallow trench isolation structure. In a most preferred embodiment, the additional well tub is implanted using the same mask set as that used for the threshold voltage adjustment deposition of the SRAM device. Thus, in the preferred embodiment, no additional mask layer is required to deposit the additional well tub, and all of the expenses normally associated with an additional mask layer are avoided.
- Further advantages of the invention are apparent by reference to the detailed description when considered in conjunction with the figures, which are not to scale so as to more clearly show the details, wherein like reference numbers indicate like elements throughout the several views, and wherein:
- FIG. 1 is a cross-sectional dopant profile of a standard well tub,
- FIG. 2 is a cross-sectional dopant profile of a semiconductor device receiving the additional well tub deposition,
- FIG. 3 is a cross-sectional dopant profile of a semiconductor device after receiving the additional well tub deposition, and
- FIG. 4 is a dopant profile chart.
- Turning now to the drawings, there is depicted in FIG. 1 a cross-sectional view of a
substrate 10 havingsemiconductor device regions wafer 14. In the depiction of FIG. 1, the devices that will be formed indevice regions isolation structures 16, such as shallow trench isolation oxide structures, have been formed in thesemiconductor material 14. Wells 18 and 20 have also been formed. In the embodiment depicted,wells 18 represent N doped wells andwells 20 represent P doped wells. A layer ofsacrificial oxide 12 has been deposited over the surface of thesubstrate 14. - In FIG. 2, a layer of
photoresist 30 has been deposited on thesacrificial oxide 12. Thephotoresist 30 has been cured, exposed, developed, and baked to provide a deposition mask on thesubstrate 10. Through the openings in thephotoresist 30, such as the opening that is overlying thesemiconductor device region 24, adopant 32 is deposited through thesacrificial oxide layer 12 and into thesemiconductor material 14. Thedopant material 32 is selected to be of the same type, either P or N, as the well of the device region into which it is deposited. Therefore, in the embodiment depicted in FIG. 2, thedopant 32 is a P type species, because thewell 20 is P type. - The
dopant 32 is preferably deposited to a depth that is greater than theisolation structure 16 and shallower than the well 20. In this manner, theadditional dopant 32 is concentrated within aregion 34 of thedevice 24 where it provides a higher junction capacitance for thedevice 24, thus enhancing SER immunity, and also strengthens the channel region that is to be further defined at later stages of the processing, thus enhancing deep channel punchthrough resistance as well as increasing interwell punchthrough resistance. Thisregion 34 is essentially the deposition of anadditional well 34. - An additional benefit of this system is that the mask layers and methods used to form the
photoresist layer 30 are not in addition to those required for the standard processing of thedevices device 24, typically requires a threshold depletion deposition, which uses a mask structure that is identical to that described above and depicted in FIG. 2. Thus, after thedopant 32 for theadditional well 34 has been deposited, the threshold depletion dopant can be deposited. In this manner, only a single deposition step is added to the fabrication process, without any additional mask layer processing required. - Further, this system is compatible with the fabrication of
SRAM devices same substrate 10 aslogic devices SRAM devices logic devices - A similar mask layer is used to provide a photoresist mask layer through which to deposit a
similar well structure 33 into theSRAM device 22 as depicted in FIG. 3. As mentioned above, this is the same mask layer through which the threshold adjustment layer for theSRAM device 22 is deposited. Thus, the formation of theadditional well 33 does not require any additional masking steps, and likewise does not impact the fabrication or reliability of thelogic devices well 18 is N type, the dopant used for theadditional well 33 is also N type. FIG. 3 depicts thedevices sacrificial oxide layer 12 has been removed,gate structures 40 have been created, and source and drain regions have been deposited withP+ dopant 36 andN+ dopant 38. FIG. 4 depicts the relative concentration of the various dopants as a function of depth insemiconductor material 14, as viewed alongsection 35 in FIG. 3.Line 42 represents the concentration of the N+ source/drain region 38, line 44 represents the concentration of the Padditional well 34, andline 46 represents the concentration of thestandard P well 20.Line 48 represents the depth of the bottom of theisolation structure 16. - As seen in FIG. 4, that portion of the additional well34 at which the concentration of dopant is the greatest as represented by line 44 on the chart of FIG. 4, extends to a depth in the
semiconductor material 14 that is greater than the depth of theisolation structure 16 as represented byline 48 on the chart of FIG. 4. Further, that portion of the additional well 34 at which the concentration of dopant is the greatest, as represented by line 44 on the chart of FIG. 4, extends to a depth in thesemiconductor material 14 that is shallower or less than the depth of that portion of the standard well 20 at which the concentration of dopant is the greatest, as represented byline 46 on the chart of FIG. 4. - In a most preferred embodiment, the dopants for the various structures are deposited using an ion implantation process. Thus, for example, the additional P well34 of
SRAM device 24 may be preferably formed by ion implantation of Boron (B11) at an energy of between about 25 keV and about 190 keV and a ion dose of between about 1011 ions/cm2 and about 1014 ions/cm2, which implants the species at a nominal depth of between about 0.1 microns and about 0.5 microns. The additional N well 33 ofSRAM device 22 may be preferably formed by ion implantation of Phosphorus (P31) at an energy of between about 80 keV and about 360 keV and a ion dose of between about 1011 ions/cm2 and about 1014 ions/cm2, which implants the species at a nominal depth of between about 0.1 microns and about 0.5 microns. - As is apparent from the foregoing discussion, the dopant type of the additional
well tubs well tubs standard well tub well tubs well tubs isolation structures 16 is between about 0.08 microns and about 0.45 microns. For standardwell tubs isolation structures 16 having different depths, the processes described above for the deposition of the additionalwell tubs - The foregoing description of preferred embodiments for this invention have been presented for purposes of illustration and description. They are not intended to be exhaustive or to limit the invention to the precise form disclosed. Obvious modifications or variations are possible in light of the above teachings. The embodiments are chosen and described in an effort to provide the best illustrations of the principles of the invention and its practical application, and to thereby enable one of ordinary skill in the art to utilize the invention in various embodiments and with various modifications as is suited to the particular use contemplated. All such modifications and variations are within the scope of the invention as determined by the appended claims when interpreted in accordance with the breadth to which they are fairly, legally, and equitably entitled.
Claims (20)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/191,107 US20020173087A1 (en) | 2000-07-03 | 2002-07-09 | System to improve SER immunity and punchthrough |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/609,527 US6455363B1 (en) | 2000-07-03 | 2000-07-03 | System to improve ser immunity and punchthrough |
US10/191,107 US20020173087A1 (en) | 2000-07-03 | 2002-07-09 | System to improve SER immunity and punchthrough |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/609,527 Division US6455363B1 (en) | 2000-07-03 | 2000-07-03 | System to improve ser immunity and punchthrough |
Publications (1)
Publication Number | Publication Date |
---|---|
US20020173087A1 true US20020173087A1 (en) | 2002-11-21 |
Family
ID=24441171
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/609,527 Expired - Lifetime US6455363B1 (en) | 2000-07-03 | 2000-07-03 | System to improve ser immunity and punchthrough |
US10/191,107 Abandoned US20020173087A1 (en) | 2000-07-03 | 2002-07-09 | System to improve SER immunity and punchthrough |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/609,527 Expired - Lifetime US6455363B1 (en) | 2000-07-03 | 2000-07-03 | System to improve ser immunity and punchthrough |
Country Status (1)
Country | Link |
---|---|
US (2) | US6455363B1 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2020029226A1 (en) * | 2018-08-10 | 2020-02-13 | 深圳市为通博科技有限责任公司 | Field-effect device, antifuse and random number generation apparatus |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7230303B1 (en) | 2004-10-15 | 2007-06-12 | Gsi Technology, Inc. | Semiconductor memory device with reduced soft error rate (SER) and method for fabricating same |
US20060234467A1 (en) * | 2005-04-15 | 2006-10-19 | Van Gompel Toni D | Method of forming trench isolation in a semiconductor device |
US20070158779A1 (en) * | 2006-01-12 | 2007-07-12 | International Business Machines Corporation | Methods and semiconductor structures for latch-up suppression using a buried damage layer |
US7648869B2 (en) * | 2006-01-12 | 2010-01-19 | International Business Machines Corporation | Method of fabricating semiconductor structures for latch-up suppression |
US7491618B2 (en) * | 2006-01-26 | 2009-02-17 | International Business Machines Corporation | Methods and semiconductor structures for latch-up suppression using a conductive region |
US7276768B2 (en) * | 2006-01-26 | 2007-10-02 | International Business Machines Corporation | Semiconductor structures for latch-up suppression and methods of forming such semiconductor structures |
US20070194403A1 (en) * | 2006-02-23 | 2007-08-23 | International Business Machines Corporation | Methods for fabricating semiconductor device structures with reduced susceptibility to latch-up and semiconductor device structures formed by the methods |
US7818702B2 (en) * | 2007-02-28 | 2010-10-19 | International Business Machines Corporation | Structure incorporating latch-up resistant semiconductor device structures on hybrid substrates |
US7754513B2 (en) * | 2007-02-28 | 2010-07-13 | International Business Machines Corporation | Latch-up resistant semiconductor structures on hybrid substrates and methods for forming such semiconductor structures |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5130268A (en) * | 1991-04-05 | 1992-07-14 | Sgs-Thomson Microelectronics, Inc. | Method for forming planarized shallow trench isolation in an integrated circuit and a structure formed thereby |
US5726475A (en) * | 1987-07-10 | 1998-03-10 | Kabushiki Kaisha Toshiba | Semiconductor device having different impurity concentration wells |
US5741735A (en) * | 1995-07-27 | 1998-04-21 | Micron Technology, Inc. | Local ground and VCC connection in an SRAM cell |
US20020011633A1 (en) * | 1999-06-09 | 2002-01-31 | Seiko Epson Corporation | Semiconductor memory device and method of manufacturing the same |
US20040147077A1 (en) * | 1997-04-10 | 2004-07-29 | Kozo Watanabe | Semiconductor integrated circuitry and method for manufacturing the circuitry |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
SG64409A1 (en) * | 1996-11-29 | 1999-04-27 | Motorola Inc | A read only memory array and a method of manufacturing the array |
US6140188A (en) * | 1998-05-20 | 2000-10-31 | Philips Semiconductors, Inc. | Semiconductor device having load device with trench isolation region and fabrication thereof |
US6218866B1 (en) * | 1999-10-12 | 2001-04-17 | National Semiconductor Corporation | Semiconductor device for prevention of a floating gate condition on an input node of a MOS logic circuit and a method for its manufacture |
-
2000
- 2000-07-03 US US09/609,527 patent/US6455363B1/en not_active Expired - Lifetime
-
2002
- 2002-07-09 US US10/191,107 patent/US20020173087A1/en not_active Abandoned
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5726475A (en) * | 1987-07-10 | 1998-03-10 | Kabushiki Kaisha Toshiba | Semiconductor device having different impurity concentration wells |
US5130268A (en) * | 1991-04-05 | 1992-07-14 | Sgs-Thomson Microelectronics, Inc. | Method for forming planarized shallow trench isolation in an integrated circuit and a structure formed thereby |
US5741735A (en) * | 1995-07-27 | 1998-04-21 | Micron Technology, Inc. | Local ground and VCC connection in an SRAM cell |
US20040147077A1 (en) * | 1997-04-10 | 2004-07-29 | Kozo Watanabe | Semiconductor integrated circuitry and method for manufacturing the circuitry |
US20020011633A1 (en) * | 1999-06-09 | 2002-01-31 | Seiko Epson Corporation | Semiconductor memory device and method of manufacturing the same |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2020029226A1 (en) * | 2018-08-10 | 2020-02-13 | 深圳市为通博科技有限责任公司 | Field-effect device, antifuse and random number generation apparatus |
Also Published As
Publication number | Publication date |
---|---|
US6455363B1 (en) | 2002-09-24 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US4534824A (en) | Process for forming isolation slots having immunity to surface inversion | |
US6323106B1 (en) | Dual nitrogen implantation techniques for oxynitride formation in semiconductor devices | |
US4385947A (en) | Method for fabricating CMOS in P substrate with single guard ring using local oxidation | |
US6010926A (en) | Method for forming multiple or modulated wells of semiconductor device | |
US6287908B1 (en) | Transistor device configurations for high voltage applications and improved device performance | |
US6514810B1 (en) | Buried channel PMOS transistor in dual gate CMOS with reduced masking steps | |
US20020042184A1 (en) | Reduction in well implant channeling and resulting latchup characteristics in shallow trench ilolation by implanting wells through nitride | |
WO1983003709A1 (en) | Process for forming complementary integrated circuit devices | |
KR100227621B1 (en) | Method for manufacturing transistor of semiconductor device | |
CA2658567A1 (en) | Jfet with built in back gate in either soi or bulk silicon | |
KR100525216B1 (en) | Nitrogen implantation using a shadow effect to control gate oxide thickness in sti dram semiconductors | |
KR19990044184A (en) | EEPROM - Manufacturing Method of Semiconductor Structure | |
US6455363B1 (en) | System to improve ser immunity and punchthrough | |
KR0170457B1 (en) | Method of manufacturing semiconductor device with mosfet | |
US5104818A (en) | Preimplanted N-channel SOI mesa | |
US5827763A (en) | Method of forming a multiple transistor channel doping using a dual resist fabrication sequence | |
US6281555B1 (en) | Integrated circuit having isolation structures | |
US6249025B1 (en) | Using epitaxially grown wells for reducing junction capacitances | |
US6686252B2 (en) | Method and structure to reduce CMOS inter-well leakage | |
EP0110103B1 (en) | Method of making complementary transistor metal oxide semiconductor structures | |
US6967380B2 (en) | CMOS device having retrograde n-well and p-well | |
US6617214B2 (en) | Integrated circuit structure and method therefore | |
US6083795A (en) | Large angle channel threshold implant for improving reverse narrow width effect | |
US6281094B1 (en) | Method of fabricating semiconductor device capable of providing MOSFET which is improved in a threshold voltage thereof | |
KR19990007421A (en) | CMOS integrated circuit with reduced board defects |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |
|
AS | Assignment |
Owner name: BELL SEMICONDUCTOR, LLC, ILLINOIS Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.;BROADCOM CORPORATION;REEL/FRAME:044886/0608 Effective date: 20171208 |
|
AS | Assignment |
Owner name: CORTLAND CAPITAL MARKET SERVICES LLC, AS COLLATERA Free format text: SECURITY INTEREST;ASSIGNORS:HILCO PATENT ACQUISITION 56, LLC;BELL SEMICONDUCTOR, LLC;BELL NORTHERN RESEARCH, LLC;REEL/FRAME:045216/0020 Effective date: 20180124 |
|
AS | Assignment |
Owner name: BELL NORTHERN RESEARCH, LLC, ILLINOIS Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:CORTLAND CAPITAL MARKET SERVICES LLC;REEL/FRAME:059720/0719 Effective date: 20220401 Owner name: BELL SEMICONDUCTOR, LLC, ILLINOIS Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:CORTLAND CAPITAL MARKET SERVICES LLC;REEL/FRAME:059720/0719 Effective date: 20220401 Owner name: HILCO PATENT ACQUISITION 56, LLC, ILLINOIS Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:CORTLAND CAPITAL MARKET SERVICES LLC;REEL/FRAME:059720/0719 Effective date: 20220401 |