US 20020178201 A1 Abstract A method and system determine a high part of a floating point operand. Exponent field bits and fraction field bits of a result are set to a zero if the determined format is an infinity format or an overflow format. The exponent field bits and the fraction field bits of the result are set to corresponding exponent field bits and corresponding fraction field bits of the floating point operand if the determined format is a not-a-number (NaN) format. At least one of the fraction field bits of the result is adaptively cleared if the determined format is a denormalized format or a delimited format.
Claims(24) 1. A method for determining a high part of a floating point operand comprising:
determining a format of the floating point operand; setting a plurality of exponent field digits and a plurality of fraction field digits of a result to a zero if the determined format is one of a first group comprising an infinity format and an overflow format; setting the exponent field digits and the fraction field digits of the result to corresponding exponent field digits and corresponding fraction field digits of the floating point operand if the determined format is a not-a-number (NaN) format; and adaptively clearing at least one of the fraction field digits of the result if the determined format is one of a second group comprising a denormalized format and a delimited format, wherein the high part of the floating point operand is the result. 2. The method of 3. The method of 4. The method of 5. The method of 6. The method of 7. The method of 8. The method of 9. A computer-readable medium having instructions, which when executed perform a method for determining a high part of a floating point operand comprising:
determining a format of the floating point operand; setting a plurality of exponent field digits and a plurality of fraction field digits of a result to a zero if the determined format is one of a first group comprising an infinity format and an overflow format; setting the exponent field digits and the fraction field digits of the result to corresponding exponent field digits and corresponding fraction field digits of the floating point operand if the determined format is a not-a-number (NaN) format; and adaptively clearing at least one of the fraction field digits of the result if the determined format is one of a second group comprising a denormalized format and a delimited format, wherein the high part of the floating point operand is the result. 10. The computer-readable medium of 11. The computer-readable medium of 12. The computer-readable medium of 13. The computer-readable medium of 14. The computer-readable medium of 15. The computer-readable medium of 16. The computer-readable medium of 17. A system for determining a high part of a floating point operand, comprising:
an operand analysis circuit that determines a format associated with the floating point operand; a processing circuit that adaptively sets at least one digit of an intermediate result; and a result generator circuit that assembles a final result equal to the high part of the floating point operand based on the format of the floating point operand and the intermediate result. 18. The system of 19. The system of 20. The system of 21. The system of 22. The system of 23. The system of 24. The system of Description [0001] U.S. patent application Ser. No. ______, filed on even date herewith in the name of Guy L. Steele Jr. and entitled “Floating Point Unit in which Floating Point Status Information is Encoded in Floating Point Representations,” assigned to the assignee of the present application, is hereby incorporated by reference. [0002] 1. Field of the Invention [0003] The present invention relates to floating point processing, and, more particularly, to systems and methods for computing the high part of a floating point number. [0004] 2. Background of the Invention [0005] IEEE Standard 754 (hereinafter “IEEE Std. 754” or “the Standard”) published in 1985 by the Institute of Electrical and Electronic Engineers, and adopted by the American National Standards Institute (ANSI), defines several standard formats for expressing values as a floating point number. In accordance with IEEE Std. 754, a floating point format is represented by a plurality of binary digits, or “bits,” having the structure: [0006] se [0007] where “msb” represents “most significant bit” and “lsb” represents “least significant bit.” The bit string comprises a sign bit, s, which indicates whether the number is positive or negative. The bit string further comprises an exponent field having bits e [0008] IEEE Std. 754 defines two general formats for expressing a value, namely, a “single” format, which comprises thirty-two bits, and a “double” format, which comprises sixty-four bits. In the single format, there is one sign bit, s, eight bits, e [0009] The value of a number represented in accordance with IEEE Std. 754 is determined based on the bit patterns of the exponent field bits, e [0010] Further, if the exponent bits, e [0011] Still further, if the exponent field bits, e [0012] Finally, if the exponent field bits, e [0013] In some floating-point computations, particularly in carefully written numerical libraries, it is desirable to extract a “high part” of an input floating point number to obtain a resulting floating point number with the same sign and exponent as the input floating point number and a smaller fraction than the input floating point number. The fraction of the resulting floating point number is chosen so that the difference between the fraction of the resulting floating point number and the fraction of the input floating point number is very small and the significand of the resulting floating point number can be squared exactly without loss of precision. [0014] Conventionally, the high part of an input floating point number is determined by clearing a predetermined number of least significant fraction field bits of the input floating point number. For example, in the well-known “fdlibm” numerical library, the high part of a 64-bit input floating point number is computed by first storing the 64-bit input floating point number in memory. Type-cast operations are then used to regard the variable as two 32-bit integers. The 32-bit integer represented by the least significant fraction field bits is set equal to zero. Finally, the 64-bit floating point variable is read again, containing the high part of the 64-bit input floating point number originally stored. [0015] There are several drawbacks to the conventional approach. First, setting the 32-bit integer represented by the least significant fraction field bits equal to zero produces a less accurate high part. In particular, it causes the difference between the fraction of the resulting floating point number and the fraction of the input floating point number to undesirably become too large. Second, storing the 64-bit input floating point number to memory typically requires more time than an operation performed in registers on most computers with their associated programming language compilers. Third, sensible results are not always obtained when the input floating point number is in a denormalized, NaN, infinity, or overflow format according to the floating-point number system disclosed in related U.S. patent application Ser. No. ______ or in an infinity or NaN format according to IEEE Std. 754. For example, typically, to compute the “low part” of a number, the “high part” of the number is subtracted from the number. However, if the number is infinity, the high part of the number will also be infinity using the conventional approach. The subtraction of the high part of the number from the number will produce a floating point number having the NaN format. Also, clearing the low bits of a NaN formatted operand may lose valuable information. Therefore, inputs in a denormalized, NaN, infinity, or overflow format according to the floating-point number system disclosed in related U.S. patent application Ser. No. ______ or in an infinity or NaN format according to IEEE Std. 754 must be tested for and handled separately as special cases in the conventional approach, which introduces additional undesirable costs in memory space and time. [0016] There is provided a method for determining a high part of a floating point operand. The method comprises determining a format of the floating point operand and setting a plurality of exponent field digits and a plurality of fraction field digits of a result to a zero if the determined format is one of a first group comprising an infinity format and an overflow format. The method further comprises setting the exponent field digits and the fraction field digits of the result to corresponding exponent field digits and corresponding fraction field digits of the floating point operand if the determined format is a not-a-number (NaN) format. Still further, the method comprises adaptively clearing at least one of the fraction field digits of the result if the determined format is one of a second group comprising a denormalized format and a delimited format, wherein the high part of the floating point operand is the result. [0017] Additional advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the appended claims. [0018] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed. [0019] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate several embodiments of the invention and together with the description, serve to explain the principles of the invention. [0020]FIG. 1 illustrates an exemplary floating point unit for computing the high part of a floating point operand according to an embodiment of the present invention. [0021]FIG. 2 illustrates an exemplary floating point operand. [0022]FIG. 3 illustrates an exemplary operand analysis circuit for analyzing a floating point operand according to an exemplary embodiment of the present invention. [0023]FIG. 4 illustrates an exemplary operand analysis circuit for analyzing a floating point operand according to an exemplary embodiment of the present invention. [0024]FIG. 5 illustrates an exemplary processing circuit for processing a floating point operand according to an exemplary embodiment of the present invention. [0025]FIG. 6 illustrates an exemplary processing circuit for processing a floating point operand according to an exemplary embodiment of the present invention. [0026]FIG. 7 illustrates an exemplary result generator for assembling a result according to an exemplary embodiment of the present invention. [0027]FIG. 8 illustrates a first embodiment of a floating point unit for computing the high part of a floating point operand according to an exemplary embodiment of the present invention. [0028]FIG. 9 illustrates a second embodiment of a floating point unit for computing the high part of a floating point operand according to an exemplary embodiment of the present invention. [0029]FIG. 10 illustrates a third embodiment of a floating point unit for computing the high part of a floating point operand according to an exemplary embodiment of the present invention. [0030]FIG. 11 illustrates a fourth embodiment of a floating point unit for computing the high part of a floating point operand according to an exemplary embodiment of the present invention. [0031]FIG. 12 illustrates exemplary formats for representing a floating point operand. [0032]FIG. 13 illustrates additional exemplary formats for representing a floating point operand. [0033] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts. [0034]FIG. 1 illustrates an exemplary floating point unit [0035] Additionally, the floating point unit [0036] Referring to FIG. 1, the exemplary floating point unit [0037] The operand analysis circuit [0038] The processing circuit [0039] The result generator [0040]FIG. 3 illustrates a first exemplary embodiment of the operand analysis circuit [0041]FIG. 12 illustrates several exemplary formats for an operand, such as the zero format [0042]FIG. 13 illustrates an example of a delimited format [0043] Returning to FIG. 3, the exemplary operand analysis circuit [0044] Further, the comparator [0045] Still further, the comparator [0046] The combinatorial logic elements [0047]FIG. 4 illustrates a second embodiment of the operand analysis circuit [0048]FIG. 5 illustrates a first embodiment of processing circuit [0049]FIG. 6 illustrates a second embodiment of processing circuit [0050] More specifically, processing circuit [0051] The most significant resulting fraction field low part bit equals the most significant fraction field low part bit, f [0052]FIG. 7 illustrates an exemplary embodiment of the result generator [0053] Generally, the result generator [0054] Multiplexer [0055] Similarly, multiplexer [0056] The selector [0057] FIGS. [0058] In summary, floating point unit [0059] An embodiment of the present invention produces a zero result when the operand is in an infinity or overflow format. Accordingly, when computing the low part of an operand that is in an infinity or overflow format by subtracting the high part of the operand from the operand, the result is not in a NaN format. Further, an embodiment of the present invention produces a result equal to the operand when the operand is in a NaN format, thereby preserving useful status information stored in the operand. Further, when computing the low part of an operand that is in the NaN format by subtracting the high part of the operand from the operand, the result is in the NaN format, if the subtraction operation is performed according to the IEEE Std. 754. Finally, an embodiment of the present invention receives a floating point operand from an operand buffer [0060] The above description of the floating point unit [0061] Further, the above description of the floating point unit [0062] Still further, the above description of the floating point unit [0063] Finally, the floating point unit [0064] Other embodiments of the invention will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. For example, the floating point unit Patent Citations
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