US20020190376A1 - Package having terminated plating layer and its manufacturing method - Google Patents
Package having terminated plating layer and its manufacturing method Download PDFInfo
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- US20020190376A1 US20020190376A1 US10/226,258 US22625802A US2002190376A1 US 20020190376 A1 US20020190376 A1 US 20020190376A1 US 22625802 A US22625802 A US 22625802A US 2002190376 A1 US2002190376 A1 US 2002190376A1
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- Prior art keywords
- layer
- interposer substrate
- plating
- package
- terminal
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/24—Reinforcing the conductive pattern
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15172—Fan-out arrangement of the internal vias
- H01L2924/15173—Fan-out arrangement of the internal vias in a single layer of the multilayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/24—Reinforcing the conductive pattern
- H05K3/241—Reinforcing the conductive pattern characterised by the electroplating method; means therefor, e.g. baths or apparatus
- H05K3/242—Reinforcing the conductive pattern characterised by the electroplating method; means therefor, e.g. baths or apparatus characterised by using temporary conductors on the printed circuit for electrically connecting areas which are to be electroplated
Definitions
- the present invention relates to a package for mounting a semiconductor device (chip) and a solder bump, and its manufacturing method.
- an interposer substrate having a first surface for mounting the semiconductor device is prepared.
- a conductive layer is formed on a second surface of the interposer substrate, and the conductive layer is patterned to form a wiring layer capable of being connected to the semiconductor device, a terminal connected to the wiring layer, and a plating layer connected to the terminal and terminated at an end of the package.
- a mask layer having an opening exposing the terminal is coated, and the terminal is electroplated by supplying a current from the plating layer to the terminal (see: JP-A-5-95025 & JP-A-8-288422). This will be explained later in detail.
- an interposer substrate in a package for mounting a semiconductor device and a bump, has a first surface for mounting the semiconductor device.
- a wiring layer capable of being connected to the semiconductor device, a terminal connected to the wiring layer for mounting the bump, and a plating layer are formed on a second surface of the interposer substrate.
- the plating layer is connected to one of the terminal and the wiring layer. The plating layer is terminated within the interposer substrate.
- an interposer substrate having a first surface for mounting the semiconductor device is prepared.
- a conductive layer is formed on a second surface of the interposer substrate, and the conductive layer is patterned to form a wiring layer capable of being connected to the semiconductor device, a terminal connected to the wiring layer, and a plating layer connected to the terminal or the wiring layer and terminated at an end of the package.
- a mask layer having an opening exposing the terminal is coated, and the terminal is electroplated by supplying a current from the plating layer to the terminal. Finally, the plating layer is terminated within the package.
- FIGS. 1A through 1I are cross-sectional views for explaining a prior art method for manufacturing a BGA type semiconductor device
- FIG. 2 is a plan view illustrating the interposer substrate of FIG. 1A;
- FIG. 3 is a plan view illustrating the pattern layer of FIG. 1B;
- FIG. 4 is a plan view illustrating the Au plating layers of FIG. 1H;
- FIG. 5A is a plan view illustrating the BGA type semiconductor device obtained by the method as illustrated in FIGS. 1A through 1I;
- FIGS. 5B and 5C are side views of the device of FIG. 5A;
- FIGS. 6A through 6J are cross-sectional views for explaining a first embodiment of the method for manufacturing a BGA type semiconductor device according to the present invention.
- FIG. 7 is a plan view illustrating the pattern layer of FIG. 6B;
- FIG. 8 is a plan view illustrating the Au plating layers of FIG. 6H;
- FIG. 9 is a plan view illustrating the Au plating layers of FIG. 6J;
- FIG. 10A is a plan view illustrating the BGA type semiconductor device obtained by the method as illustrated in FIGS. 6A through 6J;
- FIGS. 10B and 10C are side views of the device of FIG. 10A;
- FIGS. 11, 12 and 13 are plan views illustrating modifications of FIGS. 7, 8 and 9 , respectively;
- FIGS. 14, 15 and 16 are plan views illustrating other modifications of FIGS. 7, 8 and 9 , respectively;
- FIGS. 17A through 17J are cross-sectional views for explaining a second embodiment of the method for manufacturing a BGA type semiconductor device according to the present invention.
- FIG. 18 is a plan view illustrating the pattern layer of FIG. 17B;
- FIG. 19 is a plan view illustrating the Au plating layers of FIG. 17H;
- FIG. 20 is a plan view illustrating the Au plating layer of FIG. 17J;
- FIGS. 21, 22 and 23 are plan views illustrating modifications of FIGS. 18, 19 and 20 , respectively.
- FIGS. 24, 25 and 26 are plan views illustrating other modifications of FIGS. 18, 19 and 20 , respectively.
- an interposer substrate 101 made of polyamide as illustrated in FIG. 2 is prepared. Note that a dotted area PA designates a package area, and CA designates a current supply area.
- an adhesive layer 102 is coated on a back surface of the interposer substrate 101 .
- a copper foil layer 103 is formed on a front surface of the interposer substrate 101 .
- the copper foil layer 103 is patterned by a photolithography and etching process to form a pattern layer as illustrated in FIG. 3.
- Each pattern of the pattern layer is constructed by wiring layers 103 a , terminals 103 b for mounting solder balls (outer bumps) and plating layers 103 c.
- solder resist layer 104 is coated on the entire front surface.
- openings 104 a and 104 b are perforated in the solder resist layer 104 .
- the opening 104 a is used for forming an innerhole INH (see FIG. 1E), and the opening 104 b exposes the terminal 103 b.
- an innerhole INH is perforated in the adhesive layer 102 and the interposer substrate 101 by a laser trimming process or the like. Note that the innerhole INH does not penetrate the wiring layer 103 a. Also, the innerhole INH corresponds to a terminal of a semiconductor chip which will be mounted on the back of the interposer substrate 101 .
- a plating mask layer 105 made of insulating material is coated on the entire front surface. Then, an electroplating process is carried out by supplying a current to the pattern layer ( 103 a , 103 b , 103 c ) from the current supply area CA of FIG. 2 while the interposer substrate 101 is dipped into a plating solution. As a result, a bump (plug layer) 106 is buried in the innerhole INH.
- an Au electroplating process is carried out by supplying a current to the pattern layer ( 103 a , 103 b , 103 c ) from the current supply area CA of FIG. 2 while the interposer substrate 101 is dipped into an Au plating solution.
- an Au plating layer 107 a is formed on the terminal 103 b on the front surface of the interposer substrate 101
- an Au plating layer 107 b is formed on the plug layer 106 on the back surface of the interposer substrate 101 .
- the current supply area CA of FIG. 2 is electrically separated from the package areas PA of FIG. 2.
- a terminal of a flip-chip type semiconductor chip 2 is mounted on the back surface of the interposer substrate 101 by using an ultrasonic pushing tool. Then, the semiconductor chip 2 is molded by resin. Also, a solder ball 3 is provided on the front surface of the interposer substrate 101 .
- FIGS. 5A, 5B and 5 C are side views of FIG. 5A.
- the plating layer 103 c is left. Therefore, when the operation frequency of this BGA type semiconductor device is higher, the amount of signals reflected by the plating layer 103 c is increased. Also, the parasitic capacitance of the plating layer 103 c adversely affects signals from the semiconductor chip 2 to the solder bump 3 and vice versa.
- FIGS. 6A through 6J A first embodiment of the method for manufacturing a BGA type semiconductor device will be explained next with reference to FIGS. 6A through 6J.
- an interposer substrate 11 made of polyimide as illustrated in FIG. 2 is prepared.
- an adhesive layer 12 is coated on a back surface of the interposer substrate 11 .
- a copper foil layer 13 is formed on a front surface of the interposer substrate 11 .
- the copper foil layer 13 is patterned by a photolithography and etching process to form a pattern layer as illustrated in FIG. 7.
- Each pattern of the pattern layer is constructed by wiring layers 13 a , terminals 13 b for mounting solder balls (outer bumps), plating layers 13 c , and a ground plate 13 d .
- the ground plate 13 d is connected to the plating layers 13 c .
- the terminals 13 b marked by “G” are ground terminals
- the terminals 13 b marked by “V cc ” are power supply terminals
- the terminals 13 b marked by “S” are signal input/output terminals.
- solder resist layer 14 is coated on the entire front surface.
- openings 14 a and 14 b are perforated in the solder resist layer 14 .
- the opening 14 a is used for forming an innerhole INH (see FIG. 6E), and the opening 14 b exposes the terminal 13 b.
- an innerhole INH is perforated in the adhesive layer 12 and the interposer substrate 11 by a laser trimming process or the like. Note that the innerhole INH does not penetrate the wiring layer 13 a . Also, the innerhole INH corresponds to a terminal of a semiconductor chip which will be mounted on the back of the interposer substrate 11 .
- a plating mask layer 15 made of insulating material is coated on the entire front surface. Then, an electroplating process is carried out by supplying a current to the pattern layer ( 13 a , 13 b , 13 c , 13 d ) from the current supply area CA of FIG. 2 while the interposer substrate 11 is dipped into a plating solution. As a result, a bump 16 is buried in the innerhole INH.
- an Au electroplating process is carried out by supplying a current to the pattern layer ( 13 a , 13 b , 13 c , 13 d ) from the current supply area CA of FIG. 2 while the interposer substrate 11 is dipped into an Au plating solution.
- an Au plating layer 17 a is formed on the terminal 13 b on the front surface of the interposer substrate 11
- an Au plating layer 17 b is formed on the plug layer 16 on the back surface of the interposer substrate 11 .
- the current supply area CA of FIG. 2 is electrically separated from the package areas PA of FIG. 2.
- throughholes TH are perforated in the interposer substrate 11 , the adhesive layer 12 and the solder resist layer 14 by using metal molds.
- the plating layers 13 c connected to the power supply terminals V cc and the signal input/output terminals S are terminated at the throughholes TH.
- these plating layers 13 c serve as stubs.
- the plating layers 13 c connected to the ground terminals G remains and is still connected to the plate ground layer 13 d.
- a terminal of a flip-chip type semiconductor chip 2 is mounted on the back surface of the interposer substrate 11 by using an ultrasonic pushing tool. Then, the semiconductor chip 2 is molded by resin. Also, a solder ball 3 is provided on the front surface of the interposer substrate 11 .
- FIGS. 10A, 10B and 10 C are side views of FIG. 10A.
- the plating layers 13 c connected to the power supply terminal V cc and the signal input/output terminals S are terminated at the throughholes TH. Therefore, even when the operation frequency of this BGA type semiconductor device is higher, the amount of signals reflected by the plating layers 13 c is decreased. Also, since the parasitic capacitance of the plating layers 13 c is decreased, signals from the semiconductor chip 2 to the solder bump 3 and vice versa are hardly affected thereby.
- the ground plate 13 d covers a large area of the package, the noise at the signal input/output terminals S can be remarkably suppressed.
- a length L of each of the pattern layers 13 between the bump 16 and the throughhole TH should be as small as possible to decrease the capacitance, thus enabling a high speed operation. Also, a length L1 of each of the remaining plating layers 13 c connected to the signal input/output terminals S should be as small as possible to decrease the amount of reflected signals. Further, the length L of each of the pattern layers 13 connected to the signal input/output terminals S are equalized to homogenize the capacitance thereof, which is helpful in a high speed operation.
- the first embodiment can be modified as illustrated in FIGS. 11, 12 and 13 , which correspond to FIGS. 7, 8 and 9 , respectively. That is, the ground plate 13 d of FIGS. 7, 8 and 9 is replaced by wiring layers 13 e . Even in this modification, the same effect except for the noise characteristics by the ground plate 13 d can be expected.
- the first embodiment can be also modified as illustrated in FIGS. 14, 15 and 16 , which correspond to FIGS. 7, 8 and 9 , respectively. That is, the ground plate 13 d of FIGS. 7, 8 and 9 is replaced by plating layers 13 f .
- the plating layers 13 f are used in the Au electroplating process, and the plating layers 13 f as well as the plating layers 13 c are terminated by forming a throughhole TH.
- FIGS. 14, 15 and 16 which correspond to FIGS. 7, 8 and 9 , respectively. That is, the ground plate 13 d of FIGS. 7, 8 and 9 is replaced by plating layers 13 f .
- the plating layers 13 f are used in the Au electroplating process, and the plating layers 13 f as well as the plating layers 13 c are terminated by forming a throughhole TH.
- each of the terminals 13 b provided in the periphery of the package PA can be any of a ground terminal G, a power supply terminal V cc and a signal input/output terminal S, while each of the terminals 13 b provided at the center of the package PA can be a signal input/output terminal S or a power supply terminal G. Even in this modification, the same effect except for the noise characteristics by the ground plate 13 d can be expected.
- FIGS. 17A through 17J A second embodiment of the method for manufacturing a BGA type semiconductor device will be explained next with reference to FIGS. 17A through 17J.
- an interposer substrate 21 made of polyimide as illustrated in FIG. 2 is prepared.
- an adhesive layer 22 is coated on a back surface of the interposer substrate 21 .
- a copper foil layer 23 is formed on a front surface of the interposer substrate 21 .
- the copper foil layer 23 is patterned by a photolithography and etching process to form a pattern layer as illustrated in FIG. 18.
- Each pattern of the pattern layer is constructed by wiring layers 23 a , terminals 23 b for mounting solder balls (outer bumps), plating layers 23 c , and a ground plate 23 d .
- the ground plate 23 d is connected to the plating layers 23 c .
- the terminals 23 b marked by “S” are signal input/output terminals.
- the ground plate 23 d surrounds the pattern layer ( 23 a , 23 b , 23 c ) so that the pattern layer is shielded by the ground plate 23 d , the inductance of the package can be decreased.
- solder resist layer 24 is coated on the entire front surface.
- openings 24 a and 24 b are perforated in the solder resist layer 24 .
- the opening 24 a is used for forming an innerhole INH (see FIG. 17E), and the opening 24 b exposes the terminal 23 b.
- an innerhole INH is perforated in the adhesive layer 22 and the interposer substrate 21 by a laser trimming process or the like. Note that the innerhole INH does not penetrate the wiring layer 23 a . Also, the innerhole INH corresponds to a terminal of a semiconductor chip which will be mounted on the back of the interposer substrate 21 .
- a plating mask layer 25 made of insulating material is coated on the entire front surface. Then, an electroplating process is carried out by supplying a current to the pattern layer ( 23 a , 23 b , 23 c , 23 d ) from the current supply area CA of FIG. 2 while the interposer substrate 21 is dipped into a plating solution. As a result, a bump 26 is buried in the innerhole INH.
- an Au electroplating process is carried out by supplying a current to the pattern layer ( 23 a , 23 b , 23 c , 23 d ) from the current supply area CA of FIG. 2 while the interposer substrate 21 is dipped into an Au plating solution.
- an Au plating layer 27 a is formed on the terminal 23 b on the front surface of the interposer substrate 21
- an Au plating layer 27 b is formed on the plug layer 26 on the back surface of the interposer substrate 21 .
- the current supply area CA of FIG. 2 is electrically separated from the package areas PA of FIG. 2.
- a part of the plating layer 27 c on the side of the terminals S is removed by a laser trimming process or a photolithography and etching process. Note that a part of the solder resist layer 24 is also removed. As a result, the plating layer 23 c connected to the signal input/output terminal S is terminated at a location indicated by X. In this case, the plating layer 23 c serves as a stub.
- a terminal of a flip-chip type semiconductor chip 2 is mounted on the back surface of the interposer substrate 21 by using an ultrasonic pushing tool. Then, the semiconductor chip 2 is molded by resin. Also, a solder ball 3 is provided on the front surface of the interposer substrate 21 .
- a plurality of the package areas PA are separated by a cutting apparatus to obtain a plurality of BGA type semiconductor devices.
- the plating layers 23 c connected to the signal input/output terminal S is terminated at the location X. Therefore, even when the operation frequency of this BGA type semiconductor device is higher, the amount of signals reflected by the plating layers 23 c is decreased. Also, since the parasitic capacitance of the plating layers 23 c is decreased, signals from the semiconductor chip 2 to the solder bump 3 and vice versa are hardly affected thereby.
- the ground plate 23 d covers a large area of the package, the noise at the signal input/output terminals S can be remarkably suppressed.
- a length L of the pattern layers 23 between the bump 26 and the location X should be as small as possible to decrease the capacitance, thus enabling a high speed operation. Also, a length L1 of each of the remaining plating layers 23 c should be as small as possible to decrease the amount of reflected signals.
- the second embodiment can be modified as illustrated in FIGS. 21, 22 and 23 , which correspond to FIGS. 18, 19 and 20 , respectively. That is, the plating layer 23 c is connected between the ground plate 23 d and a portion of the wiring layer 23 a where the bump 26 will be provided.
- the second embodiment can be also modified as illustrated in FIGS. 24, 25 and 26 , which correspond to FIGS. 18, 19 and 20 , respectively. That is, the plating layer 23 c is connected between the ground plate 23 d and a center portion of the wiring layer 23 a.
- the same effect can be expected.
- the length L of the pattern layers 23 are equalized to homogenize the capacitance thereof, which is helpful in a high speed operation.
- the interposer substrate is made of single polyamide
- the present invention can be applied to an interposer substrate made of other material or multi-structured materials. Additionally, the present invention can be applied to other packages than a BGA type package, such as a land grid array (LGA) type package.
- LGA land grid array
- plating layers for supplying currents during an electroplating operation are finally terminated, even when the operation frequency of a semiconductor device is higher, the amount of signals reflected by the plating layers can be decreased. Also, since the parasitic capacitance of the plating layers is decreased, signals from the semiconductor device to its solder bumps and vice versa are hardly affected thereby.
Abstract
In a package for mounting a semiconductor device and a bump, an interposer substrate has a first surface for mounting the semiconductor device. A wiring layer capable of being connected to the semiconductor device, a terminal connected to the wiring layer for mounting the bump, and a plating layer are formed on a second surface of the interposer substrate. The plating layer is connected to one of the terminal and the siring layer. The plating layer is terminated within the interposer substrate
Description
- 1. Field of the Invention
- The present invention relates to a package for mounting a semiconductor device (chip) and a solder bump, and its manufacturing method.
- 2. Description of the Related Art
- Generally, when a semiconductor chip and solder bumps are mounted on terminals of a package by soldering or the like, it is impossible to mount the semiconductor chip and the solder bumps directly on the terminals, because the terminals are not made of rust proof material. Therefore, it is essential to electroplate Au or Ni/Au on the terminals before the semiconductor chip and the solder bumps are mounted.
- In a prior art method for manufacturing a package for mounting a semiconductor device and a bump, an interposer substrate having a first surface for mounting the semiconductor device is prepared. Then, a conductive layer is formed on a second surface of the interposer substrate, and the conductive layer is patterned to form a wiring layer capable of being connected to the semiconductor device, a terminal connected to the wiring layer, and a plating layer connected to the terminal and terminated at an end of the package. Then, a mask layer having an opening exposing the terminal is coated, and the terminal is electroplated by supplying a current from the plating layer to the terminal (see: JP-A-5-95025 & JP-A-8-288422). This will be explained later in detail.
- In the above-described prior art method, however, the plating layer is finally left. Therefore, when the operation frequency of this semiconductor chip is higher, the amount of signals reflected by the plating layer is increased. Also, the parasitic capacitance of the plating layer adversely affects signals from the semiconductor chip to the solder bump and vice versa.
- It is an object of the present invention to provide a package and its manufacturing method capable of decreasing the amount of reflected signals and reducing the parasitic capacitance by plating layers.
- According to the present invention, in a package for mounting a semiconductor device and a bump, an interposer substrate has a first surface for mounting the semiconductor device. A wiring layer capable of being connected to the semiconductor device, a terminal connected to the wiring layer for mounting the bump, and a plating layer are formed on a second surface of the interposer substrate. The plating layer is connected to one of the terminal and the wiring layer. The plating layer is terminated within the interposer substrate.
- Also, in a method for manufacturing a package for mounting a semiconductor device and a bump, an interposer substrate having a first surface for mounting the semiconductor device is prepared. Then, a conductive layer is formed on a second surface of the interposer substrate, and the conductive layer is patterned to form a wiring layer capable of being connected to the semiconductor device, a terminal connected to the wiring layer, and a plating layer connected to the terminal or the wiring layer and terminated at an end of the package. Then, a mask layer having an opening exposing the terminal is coated, and the terminal is electroplated by supplying a current from the plating layer to the terminal. Finally, the plating layer is terminated within the package.
- The present invention will be more clearly understood from the description set forth below, as compared with the prior art, with reference to the accompanying drawings, wherein:
- FIGS. 1A through 1I are cross-sectional views for explaining a prior art method for manufacturing a BGA type semiconductor device;
- FIG. 2 is a plan view illustrating the interposer substrate of FIG. 1A;
- FIG. 3 is a plan view illustrating the pattern layer of FIG. 1B;
- FIG. 4 is a plan view illustrating the Au plating layers of FIG. 1H;
- FIG. 5A is a plan view illustrating the BGA type semiconductor device obtained by the method as illustrated in FIGS. 1A through 1I;
- FIGS. 5B and 5C are side views of the device of FIG. 5A;
- FIGS. 6A through 6J are cross-sectional views for explaining a first embodiment of the method for manufacturing a BGA type semiconductor device according to the present invention;
- FIG. 7 is a plan view illustrating the pattern layer of FIG. 6B;
- FIG. 8 is a plan view illustrating the Au plating layers of FIG. 6H;
- FIG. 9 is a plan view illustrating the Au plating layers of FIG. 6J;
- FIG. 10A is a plan view illustrating the BGA type semiconductor device obtained by the method as illustrated in FIGS. 6A through 6J;
- FIGS. 10B and 10C are side views of the device of FIG. 10A;
- FIGS. 11, 12 and13 are plan views illustrating modifications of FIGS. 7, 8 and 9, respectively;
- FIGS. 14, 15 and16 are plan views illustrating other modifications of FIGS. 7, 8 and 9, respectively;
- FIGS. 17A through 17J are cross-sectional views for explaining a second embodiment of the method for manufacturing a BGA type semiconductor device according to the present invention;
- FIG. 18 is a plan view illustrating the pattern layer of FIG. 17B;
- FIG. 19 is a plan view illustrating the Au plating layers of FIG. 17H;
- FIG. 20 is a plan view illustrating the Au plating layer of FIG. 17J;
- FIGS. 21, 22 and23 are plan views illustrating modifications of FIGS. 18, 19 and 20, respectively; and
- FIGS. 24, 25 and26 are plan views illustrating other modifications of FIGS. 18, 19 and 20, respectively.
- Before the description of the preferred embodiments, a prior art method for manufacturing a ball grid array (BGA) type semiconductor device will be explained with reference to FIGS. 1A through 1I.
- Initially, an
interposer substrate 101 made of polyamide as illustrated in FIG. 2 is prepared. Note that a dotted area PA designates a package area, and CA designates a current supply area. - Next, referring to FIG. 1A, an
adhesive layer 102 is coated on a back surface of theinterposer substrate 101. Then, acopper foil layer 103 is formed on a front surface of theinterposer substrate 101. - Next, referring to FIG. 1B, the
copper foil layer 103 is patterned by a photolithography and etching process to form a pattern layer as illustrated in FIG. 3. Each pattern of the pattern layer is constructed by wiringlayers 103 a,terminals 103 b for mounting solder balls (outer bumps) and platinglayers 103 c. - Next, referring to FIG. 1C, a solder resist
layer 104 is coated on the entire front surface. - Next, referring to FIG. 1D,
openings layer 104. The opening 104 a is used for forming an innerhole INH (see FIG. 1E), and theopening 104 b exposes the terminal 103 b. - Next, referring to FIG. 1E, an innerhole INH is perforated in the
adhesive layer 102 and theinterposer substrate 101 by a laser trimming process or the like. Note that the innerhole INH does not penetrate thewiring layer 103 a. Also, the innerhole INH corresponds to a terminal of a semiconductor chip which will be mounted on the back of theinterposer substrate 101. - Next, referring to FIG. 1F, a
plating mask layer 105 made of insulating material is coated on the entire front surface. Then, an electroplating process is carried out by supplying a current to the pattern layer (103 a, 103 b, 103 c) from the current supply area CA of FIG. 2 while theinterposer substrate 101 is dipped into a plating solution. As a result, a bump (plug layer) 106 is buried in the innerhole INH. - Next, referring to FIG. 1G, the
plating mask layer 105 is removed. - Next, referring to FIG. 1H, an Au electroplating process is carried out by supplying a current to the pattern layer (103 a, 103 b, 103 c) from the current supply area CA of FIG. 2 while the
interposer substrate 101 is dipped into an Au plating solution. As a result, as illustrated in FIG. 4, anAu plating layer 107 a is formed on the terminal 103 b on the front surface of theinterposer substrate 101, and anAu plating layer 107 b is formed on theplug layer 106 on the back surface of theinterposer substrate 101. Then, the current supply area CA of FIG. 2 is electrically separated from the package areas PA of FIG. 2. - Finally, referring to FIG. 1I, a terminal of a flip-chip
type semiconductor chip 2 is mounted on the back surface of theinterposer substrate 101 by using an ultrasonic pushing tool. Then, thesemiconductor chip 2 is molded by resin. Also, asolder ball 3 is provided on the front surface of theinterposer substrate 101. - After that, a plurality of the package areas PA are separated by a cutting apparatus to obtain a plurality of BGA type semiconductor devices as illustrated in FIGS. 5A, 5B and5C, where FIGS. 5B and 5C are side views of FIG. 5A.
- In the BGA type semiconductor device obtained by the method as illustrated in FIGS. 1A through 1I, however, the
plating layer 103 c is left. Therefore, when the operation frequency of this BGA type semiconductor device is higher, the amount of signals reflected by theplating layer 103 c is increased. Also, the parasitic capacitance of theplating layer 103 c adversely affects signals from thesemiconductor chip 2 to thesolder bump 3 and vice versa. - A first embodiment of the method for manufacturing a BGA type semiconductor device will be explained next with reference to FIGS. 6A through 6J.
- Initially, in the same way as in the prior art, an
interposer substrate 11 made of polyimide as illustrated in FIG. 2 is prepared. - Next, referring to FIG. 6A, in the same way as in FIG. 1A, an
adhesive layer 12 is coated on a back surface of theinterposer substrate 11. Then, acopper foil layer 13 is formed on a front surface of theinterposer substrate 11. - Next, referring to FIG. 6B, in a similar way to those of FIG. 1B, the
copper foil layer 13 is patterned by a photolithography and etching process to form a pattern layer as illustrated in FIG. 7. Each pattern of the pattern layer is constructed by wiringlayers 13 a,terminals 13 b for mounting solder balls (outer bumps), plating layers 13 c, and aground plate 13 d. Note that theground plate 13 d is connected to the plating layers 13 c. Also, theterminals 13 b marked by “G” are ground terminals, theterminals 13 b marked by “Vcc” are power supply terminals, and theterminals 13 b marked by “S” are signal input/output terminals. - Next, referring to FIG. 6C, in the same way as in FIG. 1C, a solder resist
layer 14 is coated on the entire front surface. - Next, referring to FIG. 6D, in the same way as in FIG. 1D,
openings layer 14. The opening 14 a is used for forming an innerhole INH (see FIG. 6E), and theopening 14 b exposes the terminal 13 b. - Next, referring to FIG. 6E, in the same way as in FIG. 1E, an innerhole INH is perforated in the
adhesive layer 12 and theinterposer substrate 11 by a laser trimming process or the like. Note that the innerhole INH does not penetrate thewiring layer 13 a. Also, the innerhole INH corresponds to a terminal of a semiconductor chip which will be mounted on the back of theinterposer substrate 11. - Next, referring to FIG. 6F, in the same way as in FIG. 1F, a
plating mask layer 15 made of insulating material is coated on the entire front surface. Then, an electroplating process is carried out by supplying a current to the pattern layer (13 a, 13 b, 13 c, 13 d) from the current supply area CA of FIG. 2 while theinterposer substrate 11 is dipped into a plating solution. As a result, abump 16 is buried in the innerhole INH. - Next, referring to FIG. 6G, in the same way as in FIG. 1G, the
plating mask layer 15 is removed. - Next, referring to FIG. 6H, in the same way as in FIG. 1H, an Au electroplating process is carried out by supplying a current to the pattern layer (13 a, 13 b, 13 c, 13 d) from the current supply area CA of FIG. 2 while the
interposer substrate 11 is dipped into an Au plating solution. As a result, as illustrated in FIG. 8, anAu plating layer 17 a is formed on the terminal 13 b on the front surface of theinterposer substrate 11, and anAu plating layer 17 b is formed on theplug layer 16 on the back surface of theinterposer substrate 11. Then, the current supply area CA of FIG. 2 is electrically separated from the package areas PA of FIG. 2. - Next, referring to FIG. 9 as well as FIG. 6I, throughholes TH are perforated in the
interposer substrate 11, theadhesive layer 12 and the solder resistlayer 14 by using metal molds. As a result, the plating layers 13 c connected to the power supply terminals Vcc and the signal input/output terminals S are terminated at the throughholes TH. In this case, these platinglayers 13 c serve as stubs. On the other hand, the plating layers 13 c connected to the ground terminals G remains and is still connected to theplate ground layer 13 d. - Finally, referring to FIG. 6J, in the same way as in FIG. 1I, a terminal of a flip-chip
type semiconductor chip 2 is mounted on the back surface of theinterposer substrate 11 by using an ultrasonic pushing tool. Then, thesemiconductor chip 2 is molded by resin. Also, asolder ball 3 is provided on the front surface of theinterposer substrate 11. - After that, a plurality of the package areas PA are separated by a cutting apparatus to obtain a plurality of BGA type semiconductor devices as illustrated in FIGS. 10A, 10B and10C, where FIGS. 10B and 10C are side views of FIG. 10A.
- In the BGA type semiconductor device obtained by the method as illustrated in FIGS. 6A through 6J, the plating layers13 c connected to the power supply terminal Vcc and the signal input/output terminals S are terminated at the throughholes TH. Therefore, even when the operation frequency of this BGA type semiconductor device is higher, the amount of signals reflected by the plating layers 13 c is decreased. Also, since the parasitic capacitance of the plating layers 13 c is decreased, signals from the
semiconductor chip 2 to thesolder bump 3 and vice versa are hardly affected thereby. - Also, in the first embodiment, since the
ground plate 13 d covers a large area of the package, the noise at the signal input/output terminals S can be remarkably suppressed. - Further, in the first embodiment, if the
terminals 13 b are signal input/output terminals S, a length L of each of the pattern layers 13 between thebump 16 and the throughhole TH should be as small as possible to decrease the capacitance, thus enabling a high speed operation. Also, a length L1 of each of the remaining plating layers 13 c connected to the signal input/output terminals S should be as small as possible to decrease the amount of reflected signals. Further, the length L of each of the pattern layers 13 connected to the signal input/output terminals S are equalized to homogenize the capacitance thereof, which is helpful in a high speed operation. - The first embodiment can be modified as illustrated in FIGS. 11, 12 and13, which correspond to FIGS. 7, 8 and 9, respectively. That is, the
ground plate 13 d of FIGS. 7, 8 and 9 is replaced by wiringlayers 13 e. Even in this modification, the same effect except for the noise characteristics by theground plate 13 d can be expected. - The first embodiment can be also modified as illustrated in FIGS. 14, 15 and16, which correspond to FIGS. 7, 8 and 9, respectively. That is, the
ground plate 13 d of FIGS. 7, 8 and 9 is replaced by platinglayers 13 f. The plating layers 13 f are used in the Au electroplating process, and the plating layers 13 f as well as the plating layers 13 c are terminated by forming a throughhole TH. In FIGS. 14, 15 and 16, note that each of theterminals 13 b provided in the periphery of the package PA can be any of a ground terminal G, a power supply terminal Vcc and a signal input/output terminal S, while each of theterminals 13 b provided at the center of the package PA can be a signal input/output terminal S or a power supply terminal G. Even in this modification, the same effect except for the noise characteristics by theground plate 13 d can be expected. - A second embodiment of the method for manufacturing a BGA type semiconductor device will be explained next with reference to FIGS. 17A through 17J.
- Initially, in the same way as in the prior art, an
interposer substrate 21 made of polyimide as illustrated in FIG. 2 is prepared. - Next, referring to FIG. 17A, in the same way as in FIG. 1A, an
adhesive layer 22 is coated on a back surface of theinterposer substrate 21. Then, a copper foil layer 23 is formed on a front surface of theinterposer substrate 21. - Next, referring to FIG. 17B, in a similar way to those of FIG. 1B, the copper foil layer23 is patterned by a photolithography and etching process to form a pattern layer as illustrated in FIG. 18. Each pattern of the pattern layer is constructed by wiring
layers 23 a,terminals 23 b for mounting solder balls (outer bumps), plating layers 23 c, and aground plate 23 d. Note that theground plate 23 d is connected to the plating layers 23 c. Also, theterminals 23 b marked by “S” are signal input/output terminals. Further, since theground plate 23 d surrounds the pattern layer (23 a, 23 b, 23 c) so that the pattern layer is shielded by theground plate 23 d, the inductance of the package can be decreased. - Next, referring to FIG. 17C, in the same way as in FIG. 1C, a solder resist
layer 24 is coated on the entire front surface. - Next, referring to FIG. 17D, in the same way as in FIG. 1D,
openings layer 24. The opening 24 a is used for forming an innerhole INH (see FIG. 17E), and theopening 24 b exposes the terminal 23 b. - Next, referring to FIG. 17E, in the same way as in FIG. 1E, an innerhole INH is perforated in the
adhesive layer 22 and theinterposer substrate 21 by a laser trimming process or the like. Note that the innerhole INH does not penetrate thewiring layer 23 a. Also, the innerhole INH corresponds to a terminal of a semiconductor chip which will be mounted on the back of theinterposer substrate 21. - Next, referring to FIG. 17F, in the same way as in FIG. 1F, a
plating mask layer 25 made of insulating material is coated on the entire front surface. Then, an electroplating process is carried out by supplying a current to the pattern layer (23 a, 23 b, 23 c, 23 d) from the current supply area CA of FIG. 2 while theinterposer substrate 21 is dipped into a plating solution. As a result, abump 26 is buried in the innerhole INH. - Next, referring to FIG. 17G, in the same way as in FIG. 1G, the
plating mask layer 25 is removed. - Next, referring to FIG. 17H, in the same way as in FIG. 1H, an Au electroplating process is carried out by supplying a current to the pattern layer (23 a, 23 b, 23 c, 23 d) from the current supply area CA of FIG. 2 while the
interposer substrate 21 is dipped into an Au plating solution. As a result, as illustrated in FIG. 19, anAu plating layer 27 a is formed on the terminal 23 b on the front surface of theinterposer substrate 21, and anAu plating layer 27 b is formed on theplug layer 26 on the back surface of theinterposer substrate 21. Then, the current supply area CA of FIG. 2 is electrically separated from the package areas PA of FIG. 2. - Next, referring to FIG. 20 as well as FIG. 17I, a part of the plating layer27 c on the side of the terminals S is removed by a laser trimming process or a photolithography and etching process. Note that a part of the solder resist
layer 24 is also removed. As a result, theplating layer 23 c connected to the signal input/output terminal S is terminated at a location indicated by X. In this case, theplating layer 23 c serves as a stub. - Finally, referring to FIG. 17J, in the same way as in FIG. 1I, a terminal of a flip-chip
type semiconductor chip 2 is mounted on the back surface of theinterposer substrate 21 by using an ultrasonic pushing tool. Then, thesemiconductor chip 2 is molded by resin. Also, asolder ball 3 is provided on the front surface of theinterposer substrate 21. - After that, a plurality of the package areas PA are separated by a cutting apparatus to obtain a plurality of BGA type semiconductor devices.
- In the BGA type semiconductor device obtained by the method as illustrated in FIGS. 17A through 17J, the plating layers23 c connected to the signal input/output terminal S is terminated at the location X. Therefore, even when the operation frequency of this BGA type semiconductor device is higher, the amount of signals reflected by the plating layers 23 c is decreased. Also, since the parasitic capacitance of the plating layers 23 c is decreased, signals from the
semiconductor chip 2 to thesolder bump 3 and vice versa are hardly affected thereby. - Also, in the second embodiment, since the
ground plate 23 d covers a large area of the package, the noise at the signal input/output terminals S can be remarkably suppressed. - Further, in the second embodiment, a length L of the pattern layers23 between the
bump 26 and the location X should be as small as possible to decrease the capacitance, thus enabling a high speed operation. Also, a length L1 of each of the remaining plating layers 23 c should be as small as possible to decrease the amount of reflected signals. - The second embodiment can be modified as illustrated in FIGS. 21, 22 and23, which correspond to FIGS. 18, 19 and 20, respectively. That is, the
plating layer 23 c is connected between theground plate 23 d and a portion of thewiring layer 23 a where thebump 26 will be provided. - The second embodiment can be also modified as illustrated in FIGS. 24, 25 and26, which correspond to FIGS. 18, 19 and 20, respectively. That is, the
plating layer 23 c is connected between theground plate 23 d and a center portion of thewiring layer 23 a. - Even in the modifications, the same effect can be expected. In addition, the length L of the pattern layers23 are equalized to homogenize the capacitance thereof, which is helpful in a high speed operation.
- In the above-described embodiments, although the interposer substrate is made of single polyamide, the present invention can be applied to an interposer substrate made of other material or multi-structured materials. Additionally, the present invention can be applied to other packages than a BGA type package, such as a land grid array (LGA) type package.
- As explained hereinabove, according to the present invention, since plating layers for supplying currents during an electroplating operation are finally terminated, even when the operation frequency of a semiconductor device is higher, the amount of signals reflected by the plating layers can be decreased. Also, since the parasitic capacitance of the plating layers is decreased, signals from the semiconductor device to its solder bumps and vice versa are hardly affected thereby.
Claims (4)
1. A package for mounting a semiconductor device and a bump, comprising:
an interposer substrate having a first surface for mounting said semiconductor device;
a wiring layer formed on a second surface of said interposer substrate capable of being connected to said semiconductor device;
a terminal, formed on the second surface of said interposer substrate and connected to said wiring layer, for mounting said bump;
a plating layer, formed on the second surface of said interposer substrate and connected to said wiring layer,
said plating layer being terminated within said interposer substrate.
2. The package as set forth in claim 1 , wherein said plating layer is connected to an end of said wiring layer opposite to said terminal.
3. The package as set forth in claim 1 , wherein said plating layer is connected to a center portion of said wiring layer.
4. The package as set forth in claim 1 , further comprising a ground plate terminated at an end of said package, said ground plate surrounding said wiring layer, said terminal and said plating layer.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/226,258 US20020190376A1 (en) | 1999-08-26 | 2002-08-23 | Package having terminated plating layer and its manufacturing method |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11-240607 | 1999-08-16 | ||
JP24060799A JP3339473B2 (en) | 1999-08-26 | 1999-08-26 | Package substrate, semiconductor device including the package substrate, and methods of manufacturing the same |
US09/642,806 US6486052B1 (en) | 1999-08-16 | 2000-08-22 | Package having terminated plating layer and its manufacturing method |
US10/226,258 US20020190376A1 (en) | 1999-08-26 | 2002-08-23 | Package having terminated plating layer and its manufacturing method |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
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US09/642,806 Division US6486052B1 (en) | 1999-08-16 | 2000-08-22 | Package having terminated plating layer and its manufacturing method |
Publications (1)
Publication Number | Publication Date |
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US20020190376A1 true US20020190376A1 (en) | 2002-12-19 |
Family
ID=17062018
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
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US09/642,806 Expired - Fee Related US6486052B1 (en) | 1999-08-16 | 2000-08-22 | Package having terminated plating layer and its manufacturing method |
US10/226,258 Abandoned US20020190376A1 (en) | 1999-08-26 | 2002-08-23 | Package having terminated plating layer and its manufacturing method |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
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US09/642,806 Expired - Fee Related US6486052B1 (en) | 1999-08-16 | 2000-08-22 | Package having terminated plating layer and its manufacturing method |
Country Status (4)
Country | Link |
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US (2) | US6486052B1 (en) |
JP (1) | JP3339473B2 (en) |
KR (1) | KR100351551B1 (en) |
TW (1) | TW463339B (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20100155939A1 (en) * | 2008-12-24 | 2010-06-24 | Via Technologies, Inc. | Circuit board and fabrication method thereof and chip package structure |
Families Citing this family (14)
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JP3339473B2 (en) * | 1999-08-26 | 2002-10-28 | 日本電気株式会社 | Package substrate, semiconductor device including the package substrate, and methods of manufacturing the same |
JP4149377B2 (en) | 2001-06-07 | 2008-09-10 | 株式会社ルネサステクノロジ | Manufacturing method of semiconductor device |
US7425759B1 (en) * | 2003-11-20 | 2008-09-16 | Bridge Semiconductor Corporation | Semiconductor chip assembly with bumped terminal and filler |
US7176716B2 (en) * | 2003-12-24 | 2007-02-13 | Viciciv Technology | Look-up table structure with embedded carry logic |
US7157361B2 (en) * | 2004-06-28 | 2007-01-02 | Agere Systems Inc. | Methods for processing integrated circuit packages formed using electroplating and apparatus made therefrom |
US20060160346A1 (en) * | 2005-01-19 | 2006-07-20 | Intel Corporation | Substrate bump formation |
JP2007335581A (en) * | 2006-06-14 | 2007-12-27 | Renesas Technology Corp | Method for manufacturing semiconductor device |
TWI358079B (en) | 2007-06-08 | 2012-02-11 | Sandisk Corp | Two-sided substrate lead connection for minimizing |
JP2009147270A (en) * | 2007-12-18 | 2009-07-02 | Nec Electronics Corp | Method of manufacturing wiring board, wiring board, and semiconductor device |
JP5188289B2 (en) | 2008-06-26 | 2013-04-24 | ラピスセミコンダクタ株式会社 | Method for manufacturing printed circuit board |
JP4839384B2 (en) * | 2009-02-06 | 2011-12-21 | ルネサスエレクトロニクス株式会社 | Manufacturing method of semiconductor device |
JP5390494B2 (en) * | 2010-09-14 | 2014-01-15 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
JP5533506B2 (en) * | 2010-09-29 | 2014-06-25 | カシオ計算機株式会社 | Method for manufacturing flexible printed circuit board and flexible printed circuit board |
JP2013030712A (en) | 2011-07-29 | 2013-02-07 | Toshiba Corp | Semiconductor module and method of manufacturing semiconductor module |
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- 2000-08-23 KR KR1020000048932A patent/KR100351551B1/en not_active IP Right Cessation
- 2000-08-25 TW TW089117196A patent/TW463339B/en not_active IP Right Cessation
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US6486052B1 (en) * | 1999-08-16 | 2002-11-26 | Nec Corporation | Package having terminated plating layer and its manufacturing method |
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US20100155939A1 (en) * | 2008-12-24 | 2010-06-24 | Via Technologies, Inc. | Circuit board and fabrication method thereof and chip package structure |
US7906377B2 (en) | 2008-12-24 | 2011-03-15 | Via Technologies, Inc. | Fabrication method of circuit board |
Also Published As
Publication number | Publication date |
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JP2001068588A (en) | 2001-03-16 |
KR20010021385A (en) | 2001-03-15 |
KR100351551B1 (en) | 2002-09-05 |
TW463339B (en) | 2001-11-11 |
JP3339473B2 (en) | 2002-10-28 |
US6486052B1 (en) | 2002-11-26 |
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