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Publication numberUS20020192575 A1
Publication typeApplication
Application numberUS 10/188,146
Publication dateDec 19, 2002
Filing dateJul 3, 2002
Priority dateAug 19, 1999
Also published asUS6465138
Publication number10188146, 188146, US 2002/0192575 A1, US 2002/192575 A1, US 20020192575 A1, US 20020192575A1, US 2002192575 A1, US 2002192575A1, US-A1-20020192575, US-A1-2002192575, US2002/0192575A1, US2002/192575A1, US20020192575 A1, US20020192575A1, US2002192575 A1, US2002192575A1
InventorsWilliam Stanton
Original AssigneeWilliam Stanton
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Method for designing and making photolithographic reticle, reticle, and photolithographic process
US 20020192575 A1
Abstract
There are provided methods for making a reticle for use in a photolithography process, comprising forming at least two printable features on a reticle substrate, and forming at least one sub-resolution connecting structure on the reticle substrate, the sub-resolution connecting structure connecting at least two of the printable reticle features, as well as reticles formed according to such methods. In addition, there are provided computer-implemented methods for designing such a reticle, as well as computer readable storage media, computer systems and computer programs for use in making such reticles. In addition, there are provided photolithographic processes using such a reticle. The reticle may be a binary mask, a phase shift mask, or an attenuated phase shift mask.
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Claims(37)
What is claimed is:
1. A method for making a reticle for use in a photolithography process, comprising:
forming at least two printable features on a reticle substrate; and
forming at least one sub-resolution connecting structure on said reticle substrate, said sub-resolution connecting structure connecting at least two of said printable reticle features.
2. A method as recited in claim 1, wherein said reticle is a binary mask.
3. A method as recited in claim 1, wherein said reticle is a phase shift mask.
4. A method as recited in claim 1, wherein said reticle is an attenuated phase shift mask.
5. A method as recited in claim 1, wherein at least one dimension of said at least one sub-resolution connecting structure is less than about one third of the wavelength of exposure used in said photolithography process.
6. A method for designing a reticle, comprising:
generating an initial reticle layout, said initial reticle layout comprising at least two printable reticle features; and
generating a modified reticle layout, said modified reticle layout comprising said printable reticle features and at least one sub-resolution connecting structure, said sub-resolution connecting structure connecting at least two of said printable reticle features.
7. A method as recited in claim 6, further comprising checking said initial reticle layout to analyze differences between a pattern that will be produced by exposing a resist through said initial reticle and a desired circuit feature layout.
8. A method as recited in claim 6, wherein at least one dimension of said at least one sub-resolution connecting structure is less than about one third of the wavelength of exposure used in said photolithography process.
9. A method as recited in claim 6, wherein said modified reticle layout is generated on a computer.
10. A method as recited in claim 7, further comprising altering said modified reticle layout depending on said differences.
11. A method as recited in claim 7, further comprising altering said modified reticle layout according to an optical proximity correction method for reducing said differences.
12. A photolithographic process, comprising:
directing exposure onto a resist through a reticle, said reticle comprising a reticle substrate, at least two printable features on said reticle substrate, and at least one sub-resolution connecting structure on said reticle substrate, said sub-resolution connecting structure connecting at least two of said printable reticle features.
13. A photolithographic process as recited in claim 12, wherein said reticle is a binary mask.
14. A photolithographic process as recited in claim 12, wherein said reticle is a phase shift mask.
15. A photolithographic process as recited in claim 12, wherein said reticle is an attenuated phase shift mask.
16. A photolithographic process as recited in claim 12, wherein at least one dimension of said at least one sub-resolution connecting structure is less than about one third of the wavelength of said exposure.
17. A reticle comprising a reticle substrate, at least two printable features on said reticle substrate, and at least one sub-resolution connecting structure on said reticle substrate, said sub-resolution connecting structure connecting at least two of said printable reticle features.
18. A reticle as recited in claim 17, wherein said reticle is a binary mask.
19. A reticle as recited in claim 17, wherein said reticle is a phase shift mask.
20. A reticle as recited in claim 17, wherein said reticle is an attenuated phase shift mask.
21. A reticle as recited in claim 17, wherein at least one dimension of said at least one sub-resolution connecting structure is less than about one third of the wavelength of exposure light for use with said reticle.
22. A computer readable storage medium containing a computer readable code for operating a computer to perform a method of designing a reticle, said method comprising:
forming at least two printable features on a reticle substrate design; and
forming at least one sub-resolution connecting structure on said reticle substrate design, said sub-resolution connecting structure connecting at least two of said printable reticle features.
23. A computer readable storage medium as recited in claim 22, wherein said reticle is a binary mask.
24. A computer readable storage medium as recited in claim 22, wherein said reticle is a phase shift mask.
25. A computer readable storage medium as recited in claim 22, wherein said reticle is an attenuated phase shift mask.
26. A computer readable storage medium as recited in claim 22, wherein at least one dimension of said at least one sub-resolution connecting structure is less than about one third of the wavelength of exposure used in said photolithography process.
27. A system, comprising:
a computer readable storage medium containing program instructions for execution by a processor to design a reticle; and
a processor in communication with said computer readable storage medium, said processor executing said program instructions stored on said computer readable storage medium to:
form at least two printable features on a reticle substrate design; and
form at least one sub-resolution connecting structure on said reticle substrate design, said sub-resolution connecting structure connecting at least two of said printable reticle features.
28. A system as recited in claim 27, wherein said reticle is a binary mask.
29. A system as recited in claim 27, wherein said reticle is a phase shift mask.
30. A system as recited in claim 27, wherein said reticle is an attenuated phase shift mask.
31. A system as recited in claim 27, wherein at least one dimension of said at least one sub-resolution connecting structure is less than about one third of the wavelength of exposure light for use with said reticle.
32. A computer program transmitted from a server computer to a computer system, said computer system comprising memory and a processor in communication with said memory, said memory containing the computer program, said computer program causing said processor to perform the acts of:
forming at least two printable features on a reticle substrate design; and
forming at least one sub-resolution connecting structure on said reticle substrate design, said sub-resolution connecting structure connecting at least two of said printable reticle features.
33. A computer program as recited in claim 32, wherein said reticle is a binary mask.
34. A computer program as recited in claim 32, wherein said reticle is a phase shift mask.
35. A computer program as recited in claim 32, wherein said reticle is an attenuated phase shift mask.
36. A computer program as recited in claim 32, wherein at least one dimension of said at least one sub-resolution connecting structure is less than about one third of the wavelength of exposure used in said photolithography process.
37. A system for designing a reticle comprising:
a plurality of computer systems, each computer system comprising:
a computer readable storage medium containing program instructions for execution by a processor to design and/or check a reticle; and
a processor in communication with said computer readable storage medium, said processor executing said program instructions stored on said computer readable medium, said plurality of computer systems operating in conjunction with each other to form a reticle having:
at least two printable features on a reticle substrate; and
at least one sub-resolution connecting structure on said reticle
substrate, said sub-resolution connecting structure connecting
at least two of said printable reticle features;
wherein each computer system processes different tasks associated with formation of said reticle.
Description
FIELD OF THE INVENTION

[0001] The present invention relates generally to the field of semiconductor fabrication, more particularly, to a reticle for use in a photolithography process during semiconductor fabrication, and a method for designing such a reticle.

BACKGROUND OF THE INVENTION

[0002] In the manufacture of semiconductor chip devices, photolithographic processes are often used to pattern various layers on a wafer in order to produce circuit features (e.g., transistors or polygates, wing patterns, capacitors, etc.) positioned as specified in a circuit feature layout. In such processes, a layer of resist (also referred to as “photoresist”) is deposited on the layer being patterned, and the resist is then exposed using an exposure tool and a template. These templates are known in the art as reticles or masks. For purposes of the present application, the term reticle includes both reticles and masks. During the exposure process, the reticle is typically placed over the resist, and then a form of radiant energy such as ultraviolet light is directed toward the reticle to selectively expose the resist in a desired pattern. A preferred device for creating such exposure is known as a “stepper.”

[0003] One type of reticle which has been used is referred to as a binary reticle. A binary reticle includes reticle features, namely transparent features (areas through which exposure passes) and opaque features (areas which block exposure). The design of the reticle features is typically shown in a two-dimensional “reticle layout”, although the reticle itself typically includes two or more layers,(e.g., a transparent layer and a patterned opaque layer). In use, radiant energy is directed toward the binary reticle, and the radiant energy is blocked by the opaque areas but passes through the transparent areas to pattern-wise expose the resist. After pattern-wise exposure, the resist is developed to remove either the exposed portions of the resist (a positive resist) or the unexposed portions of the resist (a negative resist), thereby forming a patterned resist on the layer being patterned. The patterned resist is then used to protect a corresponding pattern of underlying areas on the layer during subsequent fabrication processes, such as deposition, etching or ion implantation processes. Thus, the patterned resist prevents or substantially prevents the effects of the fabrication process(es) from being produced in the layer in areas of the layer which lie beneath portions of the resist which have not been removed. The reticle is designed so as to enable exposing the resist in a pattern which corresponds to the feature or features which are desired to be formed.

[0004] There are a number of effects caused by diffraction of exposure which tend to distort the patterns formed in a resist, i.e., which cause the pattern formed in a resist to differ from the pattern formed in the reticle.

[0005] Due to limitations imposed by the wavelength of light used to transfer the pattern, resolution degrades at the edges of the patterns of the reticle. Such degradation is caused by diffraction of the exposure such that it is spread outside the transparent areas. Phase shift masks (PSMs) have been used to counteract these diffraction effects and to improve the resolution and depth of images projected onto a target (i.e., the resist covered wafer). There are a variety of PSMs. One kind of PSM includes a phase shifting layer having areas which allow close to 100% of the exposure to pass through but phase shifted 180 degrees relative to exposure passing through a transparent layer. Attenuated PSMs utilize partially transmissive regions which pass a portion of the exposure, e.g., about three to eight percent, out of phase with exposure through transparent areas. Typically, the shift in phase is 180 degrees, such that the portion of exposure passing through the partially transmissive regions destructively interferes with exposure which is spread outside the transparent areas by diffraction. Phase shift masks can thereby increase image contrast and resolution without reducing wavelength or increasing numerical aperture. These masks can also improve depth of focus and process latitude for a given feature size. Designs of such reticles typically are represented using one or more two-dimensional reticle layouts including appropriate reticle features, e.g., selected from among transparent features, opaque features, phase shifting features and phase shifting attenuating features.

[0006] There has been an ongoing need to increase the density of features contained in semiconductor devices, by making the features smaller and/or reducing the amount of space between features. Advances in feature density have required that reticles include correspondingly smaller and/or more densely packed features. The extent to which features printed by photolithographic methods can be reduced in size is limited by the resolution limit of the exposure device. The resolution limit of an exposure tool is defined as the minimum feature dimension that the exposure tool can repeatedly expose onto the resist, and is a function of the wavelength of exposure emitted by the stepper, the aperture through which exposure is emitted, the depth of focus and other factors. Thus, reticle design is limited in that the gaps between respective features on the reticle (i.e., transparent regions, opaque regions and/or phase shifted regions) must be large enough for the circuit features to be correctly printed.

[0007] The critical dimension (CD) of a circuit pattern is defined as the smallest width of a line in the pattern, or the smallest space between lines in the pattern. The CD thus directly affects the size and density of the design. As the density of features in a pattern is increased, the CD of the design approaches the resolution limit of the stepper. As the CD of a circuit layout approaches the resolution limit of the stepper, the diffraction of exposure causes increasingly significant distortions of the pattern being created.

[0008] These distortions are known as optical proximity effects. The primary optical proximity effects are that corners of features are rounded, isolated features print differently from identically shaped and sized semi-isolated or densely packed features, smaller features are printed relatively smaller than larger features, and relatively thin line features are shortened. Features which are in close proximity to other features tend to be more significantly distorted than features which are relatively isolated from other features. Furthermore, optical proximity effect distortion is compounded by subsequent processing step distortions such as resist processing distortions and etching distortions.

[0009] As a result, many design techniques have been developed, with the goal being to reduce such distortion. Such techniques, referred to in the art as optical proximity correction (OPC) techniques, involve adding and/or subtracting areas to reticle design patterns such that the pattern formed by exposure through the reticle more closely corresponds to the desired pattern. Typically, OPC is performed on a digital representation of a desired pattern, in which the desired pattern is evaluated with software to identify regions where distortion will occur. Areas which are added to the design, sometimes referred to as “serifs”, are typically designed such that their largest dimension is smaller than the resolution of the stepper. As a result, such areas counteract distortion but do not print to the resist.

[0010] U.S. Pat. No. 5,821,014 discloses a method comprising using scattering bars between features for correcting for proximity effects. According to the patent, scattering bars are correction features (typically non-resolvable) that are placed next to isolated edges on a mask in order to adjust the edge intensity at the isolated edge to match the edge intensity at a densely packed edge.

[0011] U.S. Pat. No. 5,707,765 discloses a method of making a photolithography mask that utilizes serifs to increase the correspondence between an actual circuit design and the final circuit pattern on a semiconductor wafer. The mask uses a plurality of serifs having a size determined by a resolution limit of the optical exposure tool used during the fabrication process. The serifs are positioned on the corner regions of the mask such that a portion of surface area for each of the serifs overlaps the corner regions of the mask. The size of the serifs is about one-third the resolution limit of said optical exposure tool.

[0012] However, the addition of serifs according to prior art reticle design techniques limits the extent to which the density of features in a circuit can be increased while still maintaining adequate spacing between the features in reticles used to pattern the resist used to provide such circuit features.

[0013] For example, FIG. 1A is a partial view of an example of a desired repetitive circuit feature layout having densely packed circuit features 10, as well as forbidden regions 13 in which features cannot be present. FIG. 1B is a partial view of an example of a reticle layout for use in producing a device having the circuit feature layout shown in FIG. 1A, in which the reticle layout is formed using prior art techniques. As shown in FIG. 1B, the reticle layout having has densely packed printable reticle features 11 and serifs 12. It is necessary that there be at least a minimum amount of space between each of these features, e.g., in order that the reticle can be properly inspected using existing inspection procedures. If such minimum sized gaps are not present, current inspection procedures cannot identify the presence of the gap. As such inspection procedures are developed which can perform inspection despite smaller gaps, the present invention will still be applicable for the same reasons as described above, but with the tolerances of design being adjusted appropriately. FIG. 1C is a partial view of a computer-generated simulation of the pattern of exposure areas 14 which would be exposed if exposure were directed through a reticle having a reticle layout as shown in FIG. 1B. FIG. 1D is a view showing the pattern of FIG. 1C superimposed on the layout of FIG. 1A, demonstrating the variance of the actual pattern which will be produced relative to the desired pattern. This variance, at any given point on the perimeter of a feature 10, is the distance from the point on the perimeter 16 of a feature 10 to the nearest point on the perimeter 15 of an exposure area 14. For example, at point 17 in FIG. 1D, the variance is shown by the length of the line segment identified with reference number 18. Returning to FIG. 1B, as the gaps 19 become smaller, there reaches a point where there is insufficient space between serifs 12 to increase their size to reduce this variance.

[0014] Accordingly, in such a situation, the prior art reticle design method has reached the point where the variance between the actual exposure pattern and the desired exposure pattern cannot be substantially improved. Therefore, according to the prior art method, the reticle layout of FIG. 1B would be sent to a mask shop or the like, where a reticle would be manufactured which conforms to FIG. 1B. In such a reticle, opaque regions would be formed in all areas other than areas 11 and 12. Thus, for a binary reticle, the completed reticle would include transparent portions in areas 11 and 12, and exposure blocking regions everywhere else. In the case of a phase shift mask, the completed reticle would include transparent portions in areas 11 and 12, and phase shift regions everywhere else.

[0015]FIG. 2A is a partial view of a second example of a desired repetitive circuit feature layout having densely packed circuit features 20, as well as forbidden regions 23 in which features cannot be present. FIG. 2B is a partial view of an example of a reticle layout for use in producing a device having the circuit feature layout shown in FIG. 2A, the reticle layout being formed using prior art techniques. The reticle layout has densely packed printable reticle features 21 and serifs 22. FIG. 2C is a partial view of a computer-generated simulation of the pattern which would be exposed if exposure were directed through a reticle having a reticle layout as shown in FIG. 2A. FIG. 2D is a view showing the pattern of FIG. 2C superimposed on the layout of FIG. 2A, demonstrating the variance of the actual pattern which will be produced relative to the desired pattern. Analogously to FIG. 1D, in FIG. 2D. this variance, at any given point on the perimeter of a feature 20, is the distance from the point on the perimeter 26 of a feature 20 to the nearest point on the perimeter 25 of an exposure area 24. For example, at point 27 in FIG. 2D, the variance is shown by the length of the line segment identified with reference number 28. Returning to FIG. 2B, it is seen that there is insufficient space between serifs 22 to increase their size to reduce this variance. In FIG. 2B, as in FIG. 1B, there is insufficient space between serifs 22 to increase their size to reduce this variance. Accordingly, the prior art reticle design method of FIG. 2B has reached the point where the variance between the actual exposure pattern and the desired exposure pattern cannot be substantially improved.

[0016] There is an ongoing need for methods of designing reticles which can be used to form features which are packed in patterns which are increasingly more dense, while reducing or eliminating printing errors and decreasing the variance between the actual exposure pattern and the desired exposure pattern.

SUMMARY OF THE INVENTION

[0017] The present invention provides a method for designing reticles which can be used to produce circuit designs having densely packed circuit features, in which the occurrence of printing errors is reduced or eliminated, and the variance between the actual exposure pattern and the desired exposure pattern is reduced.

[0018] According to the present invention, there are provided reticle designs which include sub-resolution connecting structures which connect two or more reticle features. By “sub-resolution” is meant a feature on a reticle which, when exposure is directed through the reticle onto a resist, will not print on the resist. For example, a feature on a reticle having at least one dimension which is less than about one third of the wavelength of the exposure used will not print on the resist. The present invention is applicable to all types of reticles, e.g., binary masks and phase shift masks (including attenuated phase shift masks).

[0019] In practicing the method of this invention, an initial reticle layout is generated which includes printable reticle features which are sized, shaped and positioned such that if exposure were directed through a reticle having such an initial reticle layout onto a resist, the resist would be exposed in a pattern which roughly approximates the desired circuit feature layout. Each of the printable reticle features corresponds to a separate circuit feature in the desired circuit feature layout. The initial reticle layout may be based on any known technique, e.g., optical proximity correction (OPC) and/or trial and error. The initial reticle layout may, for instance, be generated completely through experience with particular reticle layouts, or by generating serifs using one of the many known OPC algorithms and modifying the serifs, e.g., shrinking them in size. The generation of the initial reticle layout is not limited by the present invention, which can be applied to any initial reticle layout.

[0020] A modified reticle layout is then generated which includes the reticle features of the initial reticle layout plus one or more sub-resolution connecting structures in accordance with the present invention. The sub-resolution connecting structures connect at least one set of two or more of the reticle features contained in the initial reticle layout. Because the sub-resolution connecting structures connect reticle features, the modified reticle layout will include fewer shapes than the number of features contained in the desired circuit feature layout. Likewise, individual shapes in the modified reticle layout which include, for example, two reticle features connected by a sub-resolution connecting structure will print as two separate features.

[0021] Prior to making a reticle corresponding to the modified reticle layout, the modified reticle layout is preferably checked to analyze differences between the pattern that will be produced on a resist and the desired circuit feature layout. Depending on the differences, additional modifications can be made to the modified reticle layout, which may include changes to one or more of the printable reticle features and/or addition or removal of one or more of the sub-resolution connecting structures.

[0022] The present invention also relates to reticles which include one or more sub-resolution connecting structures which connect two or more printable reticle features, each designed to print separate circuit features in the desired circuit feature layout.

[0023] The present invention is further directed to integrated circuits which incorporate one or more components made using any of the reticles according to the present invention, e.g., the reticles of the present invention can be used in making such components.

[0024] These and other features and advantages of the invention will become more readily apparent from the following detailed description of preferred embodiments of the present invention, which is provided in conjunction with the accompanying drawings. The invention is not limited to the exemplary embodiments described below and it should be recognized that the invention includes all modifications falling within the scope of the attached claims.

BRIEF DESCRIPTION OF THE DRAWINGS

[0025]FIG. 1A is a partial schematic view of a desired repetitive circuit feature layout;

[0026]FIG. 1B is a partial schematic view of a reticle layout for use in producing a device having the circuit feature layout shown in FIG. 1A, in which the reticle layout is formed using prior art techniques;

[0027]FIG. 1C is a partial schematic view of a computer-generated simulation of the pattern which would be produced in a resist if exposure were directed through a reticle having a reticle layout as shown in FIG. 1B;

[0028]FIG. 1D is a view of the pattern of FIG. 1C superimposed on the layout of FIG. 1A;

[0029]FIG. 2A is a partial schematic view of a second desired repetitive circuit feature layout;

[0030]FIG. 2B is a partial schematic view of a second example of a reticle layout for use in producing a device having the circuit feature layout shown in FIG. 2A;

[0031]FIG. 2C is a partial schematic view of a computer-generated simulation of the pattern which would be exposed if exposure were directed through a reticle having a reticle layout as shown in FIG. 2B;

[0032]FIG. 2D is a view of the pattern of FIG. 2C superimposed on the layout of FIG. 2A;

[0033]FIG. 3 is a partial schematic view of a modified reticle layout according to the present invention for use in making a reticle to print features corresponding with FIG. 1A;

[0034]FIG. 4 is a partial schematic view of a computer-generated simulation of the pattern which would be exposed if exposure were directed through a reticle having a reticle layout as shown in FIG. 3;

[0035]FIG. 5 is a view showing the pattern of FIG. 4 superimposed on the layout of FIG. 1A;

[0036]FIG. 6 is a view showing the pattern of FIG. 4 superimposed on the pattern of FIG. 1C;

[0037]FIG. 7 is a partial schematic view of a second modified reticle layout according to the present invention for use in making a reticle to print features corresponding with FIG. 2A;

[0038]FIG. 8 is a partial schematic view of a computer-generated simulation of the pattern which would be exposed if exposure were directed through a reticle having a reticle layout as shown in FIG. 7;

[0039]FIG. 9 is a view showing the pattern of FIG. 8 superimposed on the layout of FIG. 2A;

[0040]FIG. 10 is a view showing the pattern of FIG. 8 superimposed on the pattern of FIG. 2C; and,

[0041]FIG. 11 is a schematic diagram of a computer system in which the process of the present invention can be implemented.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS OF THE INVENTION

[0042] The present invention provides a method for designing reticles which can be used to produce circuit designs having densely packed circuit features, in which the occurrence of printing errors is reduced or eliminated.

[0043] Referring to the drawing figures, FIG. 3 depicts a modified reticle layout 30 according to the present invention for use in making a reticle to print features corresponding with FIG. 1A. The modified reticle layout 30 includes printable reticle features 31, serifs 32 and sub-resolution connecting structures 33. FIG. 4 shows a computer-generated simulation of the pattern which would be exposed if exposure were directed through a reticle having a reticle layout as shown in FIG. 3. FIG. 5 is a view showing the pattern of FIG. 4 superimposed on the layout of FIG. 1A, demonstrating that there is little or no variance between the actual pattern which will be produced relative to the desired pattern. FIG. 6 is a view showing the pattern of FIG. 4 superimposed on the pattern of FIG. 1C, showing the increased feature area produced by the method according to the present invention, relative to that produced by the prior art method depicted in FIG. 1B.

[0044] The sub-resolution connecting structures 33 preferably have at least one dimension which is less than one third the wavelength of the exposure which is used in the photolithographic process.

[0045] When making a binary mask corresponding to the modified reticle layout 30, the printable reticle features 31, serifs 32 and sub-resolution connecting structures 33 would be formed of a transparent material, while the remaining areas would be formed of an opaque material. As mentioned above, the present invention is also directed to phase shift masks, including attenuated phase shift masks, in which case the printable reticle features 31, serifs 32 and sub-resolution connecting structures would be formed of a transparent material, while the remaining areas would be formed of a phase shift material.

[0046] Prior to making a mask, the modified reticle layout 30 is preferably checked to analyze differences between the pattern that will be produced on a resist by exposure through a reticle formed according to the reticle layout 30 and the desired circuit feature layout. Depending on those differences, additional modifications can be made to the modified reticle layout 30, which may include further changes generated by an OPC technique and/or addition or removal of one or more of the sub-resolution connecting structures.

[0047] Examples of simulation software that can be used to determine the pattern which will be produced on a resist by exposure through a reticle formed according to the modified reticle layout 30 include FAIM by Vector Technologies of Boston, Mass., SPLAT by the University of Berkeley, Calif. and PROLITH by Finle Technologies of Plano, Tex. The simulated image data can then be fed to a design rule checker or data integrity verification and correction program where it is compared to the data comprising the desired circuit feature layout. If the simulated image correlates with the desired circuit feature layout within predetermined parameters or design rules, the modified reticle layout 30 is designated as the final reticle layout. However, if the simulated image differs from the desired circuit feature layout by more than the design limits, further modifications may be made to the modified reticle layout 30 to counteract the areas of excessive variance from the desired circuit feature layout. The further modified reticle layout can then be run through the simulation and checking software again to check for excessive variances. These steps can be repeated until the simulated images correlate with the binary mask layout within the design limits.

[0048] Various different types of design rule checker programs can be used to perform the data integrity verification and correction analysis. Examples of suitable software include CATS by Transcription Enterprises Limited of Los Gatos, Calif., iv Verify by Cadence System Inc. of San Jose, Calif., CheckMate by Mentor Graphics, Wilsonville, Oreg. and VeriCheck by Integrated Silicon System of Research Triangle Park, N.C.

[0049]FIG. 7 depicts another modified reticle layout 70 according to the present invention for use in making a reticle to print features corresponding with FIG. 2A. The reticle layout 70 includes printable reticle features 71 and sub-resolution connecting structures 73. FIG. 8 shows a computer-generated simulation of the pattern which would be exposed if exposure were directed through a reticle having a reticle layout as shown in FIG. 7. FIG. 9 is a view showing the pattern of FIG. 8 superimposed on the layout of FIG. 2A, demonstrating that there is little or no variance between the actual pattern which will be produced relative to the desired pattern. FIG. 10 is a view showing the pattern of FIG. 8 superimposed on the pattern of FIG. 2C, showing the increased feature area produced by the method according to the present invention, relative to that produced by the prior art method depicted in FIG. 2B.

[0050] A preferred material for use in making the transparent portions of a reticle is quartz, however, any suitable transparent material, e.g., soda-lime glass, borosilicate glass, or other similar natural or synthetic substances can be used. Those of skill in the art can readily select an appropriate material for use in making the transparent portions of a reticle.

[0051] A preferred material for use in making opaque portions (if present) of a reticle is chrome, however, any suitable opaque material can be used. Those of skill in the art can readily select an appropriate material for use in making the opaque portions of a reticle.

[0052] Similarly, those of skill in the art can readily select appropriate materials for use in making phase shifting portions (if present) and phase shifting attenuating portions (if present) of a reticle. For example, a preferred material for use in making an attenuated phase shifting layer is molybdenum silicide (MoSi), however, any suitable partially light transmissive, phase shifting material can be used. Another material which has been used to form attenuated phase shifting layers is “leaky chrome”, which is a mixture of chrome, nitrogen and oxygen.

[0053] The present invention is further directed to any sequence of process steps which includes performance of any of the processes in accordance with the present invention, in addition to any other process steps, including but not limited to coating or applying one or more additional layers, removing part of all of one or more additional layers, creating a pattern on a surface of a layer by applying, exposing and developing a photoresists and then removing portions of the layer defined by the pattern, forming interconnect holes through two or more layers, creating interconnects, etc.

[0054]FIG. 11 depicts an example of a computer system 650 in which a process according to the present invention can be implemented. The system 650 includes a central processing unit (CPU) 652 that communicates with an input/output (I/O) device 654 over a bus 670. A second I/O device 656 is illustrated, but is not necessary to practice the present invention. The computer system 650 also includes random access memory (RAM), read only memory (ROM) 660 and may include peripheral devices such as a floppy disk drive 664 or a compact disk read only memory (CD-ROM) drive 666 that also communicate with the CPU 652 over the bus 670. The exact architecture of the computer system 650 is not critical, and any suitable combination of computer compatible devices may be incorporated into the system 650. In a preferred embodiment, the computer system 650 is a UNIX based workstation. Moreover, the program implementing the process of the present invention may be stored in ROM 608, a CD-ROM 668, a floppy disk 664, a hard disk drive, or any other medium capable of storing a computer program and data required by the program. In addition, the computer program or programs used in the process of the present invention may be transmitted over a communications network and downloaded, for example, transmitted from a server computer or another computer connected to the computer system 650 which downloads the program or programs. The process of the present invention can be executed in a distributed manner over several computer systems 650, whether connected by a network or not, to process different tasks associated with formation of a reticle, in parallel fashion. One or more of the features contained in the devices shown in FIG. 11 can be made using reticles designed in accordance with the present invention.

[0055] Although the articles and methods in accordance with the present invention have been described in connection with preferred embodiments, it will be appreciated by those skilled in the art that modifications not specifically described may be made without departing from the spirit and scope of the invention. Accordingly, the invention is not limited by the foregoing description, but is only limited by the scope of the appended claims.

Referenced by
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Classifications
U.S. Classification430/5, 430/3, 430/396, 716/53, 716/55
International ClassificationG03F1/14, G03F1/00
Cooperative ClassificationG03F1/144, G03F1/32
European ClassificationG03F1/32, G03F1/14G