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Publication numberUS20030017660 A1
Publication typeApplication
Application numberUS 10/237,596
Publication dateJan 23, 2003
Filing dateSep 10, 2002
Priority dateJun 4, 2001
Also published asUS6458640
Publication number10237596, 237596, US 2003/0017660 A1, US 2003/017660 A1, US 20030017660 A1, US 20030017660A1, US 2003017660 A1, US 2003017660A1, US-A1-20030017660, US-A1-2003017660, US2003/0017660A1, US2003/017660A1, US20030017660 A1, US20030017660A1, US2003017660 A1, US2003017660A1
InventorsWeiqi Li
Original AssigneeAnadigics, Inc.
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
GaAs MESFET having LDD and non-uniform P-well doping profiles
US 20030017660 A1
Abstract
A MESFET has a conduction channel provided with a first doping profile in a first portion which extends between the source and the gate, and a second doping profile in a second portion which extends between the gate and the drain. A background p-type region is provided beneath the first portion, but not necessarily behind the second portion.
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Claims(7)
What is claimed is:
1. A metal-semiconductor field effect transistor (MESFET) comprising:
a substrate;
a source region formed in the substrate and having a source electrode;
a drain region formed in the substrate and having a drain electrode;
a conduction channel formed in the substrate between the source region and the drain region; and
a gate electrode positioned between the source region and the drain region, the gate electrode also being above the conduction channel; wherein
the conduction channel has a first doping profile in a first portion thereof between the source region and the gate electrode, and a second doping profile in a second portion thereof between the gate electrode and the drain region.
2. The MESFET according to claim 1, wherein:
a p-type background region is implanted in the substrate beneath the first portion, but not beneath the second portion.
3. The MESFET according to claim 2, wherein the first portion is doped with n-type ions.
4. The MESFET according to claim 3, wherein the first portion is more heavily doped than the second portion.
5. The MESFET according to claim 1, wherein:
the p-type background region merges with the first portion.
6. The MESFET according to claim 1, wherein the first portion is more heavily doped than the second portion.
7. The MESFET according to claim 1, wherein the substrate is formed from GaAs.
Description
RELATED APPLICATIONS

[0001] This is a Divisional of U.S. patent application Ser. No. 09/871,740, filed Jun. 4, 2001, now U.S. Pat. No. ______.

TECHNICAL FIELD

[0002] The present invention is directed to the general field of forming gallium arsenide (GaAs) semiconductor devices. More particularly, it is directed to forming GaAs Metal-Semiconductor Field Effect Transistors (MESFETs).

BACKGROUND OF THE INVENTION

[0003]FIG. 1 illustrates a simplified structure of a conventional GaAs MESFET 100. The MESFET 100 has a GaAs substrate 102, a source region 104, a drain region 106, an n-type channel 108, and a p-type background region 110 and. A source electrode 112 is formed above the source region 104, a drain electrode 114 is formed above the drain region 106 and a gate electrode 116 is formed between the source and drain electrodes on a surface of the GaAs substrate, and above the n-type channel 108. As seen in FIG. 1, the gate electrode 116 is formed in a depressed area 118 formed in the upper surface of the device. When a voltage is applied to the gate electrode 116, the width of the n-type channel changes, thereby affecting the flow of current between the source electrode 112 and the drain electrode 114.

[0004] In conventional ion implanted, or epitaxially grown, GaAs MESFET devices, such as that depicted in FIG. 1, the channel 108 is doped uniformly between the source 104 and drain 106 regions. The result is that the p-type background forms a p-n junction with the n-type channel doping underneath the channel. When the MESFET 100 is used as an amplifier, it normally operates with high electrical field intensity in the gate-drain region. In high RF power amplifiers, the electrical field in the gate-drain region may be high enough to initiate impact ionization, in which both excessive electrons and holes are generated. In such case, the holes become trapped in the p-n junction, thereby forming a virtual back-gating, which results in a pinch-off the n-channel 108. This phenomenon is termed a power transient in RF amplifiers, which is detrimental to normal operation.

SUMMARY OF THE INVENTION

[0005] The present invention uses selective ion implantation techniques to create a GaAs MESFET device with non-uniform doping profiles in the conduction channel. In the Source-Gate region of the MESFET, a conventional p-type implantation is used as the background, and one or more n-type implantations form the conduction channel. In the Gate-Drain region of the device, there is either no, or a reduced, background p-type implantation, and the n-type implantation dose is also reduced, resulting in lower doping concentration between the gate and the drain.

[0006] The present invention is also directed to a method for forming a GaAs MESFET having non-uniform doping profiles in the conduction channel. This is accomplished by forming a lightly-doped first conduction channel of a first type, forming a moderately doped second conduction channel of the first type along a first portion of the first conduction channel, forming a background region of a second type beneath the second conduction channel, forming source and drain regions at opposite ends of the first conduction channel, forming source and drain contacts over corresponding source and drain regions, and forming a gate contact between the source and drain contacts, the gate contact being positioned approximately over an end of the second conduction channel.

BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The present invention is next described with reference to the following figures, in which:

[0008]FIG. 1 shows a prior art GaAs MESFET with uniform channel doping; and

[0009]FIGS. 2a-2 d show various stages in forming a GaAs MESFET in accordance with the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0010] The process for forming a GaAs MESFET having a non-uniformly doped channel is now described.

[0011] As seen in FIG. 2a, a substrate 202 is first provided. The substrate is preferably formed from GaAs, although it may instead be formed of such materials as AlxGa(1-x)As, InxGa(1-x)As, x˜[0.0-1.0], and InP.

[0012] A first photoresist layer 204 is placed over selected regions of the upper surface 206 of the substrate. The photoresist 204 is deposited using a mask (not shown) and is configured to expose a first, preferably continuous upper surface area of the substrate above what will eventually become the channel.

[0013] Next a lightly doped n-channel 208 having a first length defined between first end 208 a and second end 208 b is formed in the substrate. To do this, n-type ions 206 are implanted into the substrate, as depicted by the arrows. The n-type ions, preferably in form of silicon ions, are implanted at an energy of between approximately 25 KeV and 200 Kev, and so penetrate the substrate to a depth of between approximately 0.5 nm and 1.2 μm. The n-type ions preferably are implanted at a relatively low dosage of between approximately 1E12/cm2 and 5E12/cm2, thereby forming the lightly doped n-channel 208.

[0014] As seen in FIG. 2b, a second photoresist layer 212 is then placed over the resulting structure. The second photoresist layer 212 is configured to expose a first portion 214 of the lightly doped channel 208 while a second portion 216 of the lightly doped channel 208 is covered. Next, a p-type background region 218 having a second length shorter than the first length and extending from proximate to the first end 208 a of the lightly-doped n-channel 208 is formed in first portion 214. The p-type background region 218 is formed at or near the boundary between the first portion 214 of the lightly doped n-channel 208 and the substrate 202 below. To do this, p-type ions 220 are implanted into the substrate, as depicted by the arrows. The p-type ions, preferably in the form of beryllium or magnesium ions, are implanted at an energy of between approximately 30 KeV and 200 KeV, and so penetrate to a depth of between approximately 0.1 nm and 1.5 μm The p-type ions preferably are implanted at a dosage of between approximately 1E11/cm2 and 1E12/cm2, thereby forming the p-type background region 218, a “p-well”, in only the first region 214 of the n-channel 208. As seen in the figures, the p-type background region 218 extends along the first portion 214 in a direction parallel to the upper surface, at one end of the n-channel 208.

[0015] Next, using the same photoresist mask, a moderately doped n-type channel region 222 is formed in the first region 214 of the lightly doped n-channel 208, above the p-type background region 218. The moderately doped n-type channel region 222 has a third length which is substantially similar to the second length and extends from proximate to the first end 208 a of the lightly-doped n-channel 208. To form the channel region 222, n-type ions 224 are implanted into the first portion 214 of the lightly doped n-channel 208, as depicted by the arrows. The n-type ions, preferably in the form of silicon ions, are implanted at the substantially same energy as that used to create the lightly doped n-channel 208 and so penetrate to about the same depth, just above the p-type background region 218. The n-type ions preferably are implanted at a dosage of between approximately 1E12/cm2 and 5E12/cm2, thereby converting the original lightly doped n-channel 208 into a moderately doped n-channel region 222 in only the first region 214 of the n-channel 208. It should be noted here that one can reverse the order in which the p-type background region 218 and the moderately doped n-type channel regions 222 are formed, without substantially impacting the performance of the ultimate device. While FIG. 2b shows the regions 218 and 222 to be distinct and non-overlapping, it should be kept in mind that due to distribution of ion energies, the regions do not always have a crisp boundary, but rather somewhat merge together.

[0016] As seen in FIG. 2c, a third photoresist layer 230 is then placed over the resulting structure. The third photoresist layer substantially covers the first 214 and second 216 regions of the original lightly doped n-channel 208, and leaves exposed a pair of lateral areas 232 a, 232 b of the substrate on either side of the original n-channel 208. The lateral areas are situated over what will eventually become the source region 234 and the drain region 236. To convert the substrate below lateral areas 232 a, 232 b into the source 234 and drain 236 regions, n-type ions 238 are implanted into the regions of the substrate below the lateral areas 232 a, 232 b, as depicted by the arrows. This results in the formation of a source region 234 adjacent to one end of the moderately doped n-channel 222 and the p-type background region, and also results in the formation of a drain region 236 adjacent to an end of the lightly doped n-channel 208. The n-type ions, preferably in the form of silicon ions, are implanted at an energy of between approximately 50 KeV and 100 KeV, and so penetrate to a depth of between approximately 0.5 μm and 1.0 μm. Furthermore, the n-type ions preferably are implanted at a dosage of between approximately 5E12/cm2 and 1E13/cm2, thereby converting the substrate into highly doped n-type regions 234, 236. It should be noted here that while the source 234 and drain 236 regions preferably are formed in a single step, it may also be possible to form them in separate step, especially in the event that the two regions are to be differently doped, or have different depths.

[0017] As seen in FIG. 2d, source 242 and drain contacts 244, preferably made of germanium gold (GeAu), are formed over respective source 234 and 236 drain regions. In addition, a gate contact 246 is formed between the source and drain contacts. As is known to those skilled in the art, the gate contacts are typically formed from Ti/Pt/Au, or other refractory metal, such as Mo, W, TiW, and the like. Preferably, the gate contact 246 is positioned near the second end of the moderately doped n-channel 222 extending between the source and the gate; the gate contact may even straddle the boundary 248 between the channel 222 and the lightly doped n-channel 208 extending between the gate and the drain, or be positioned entirely above the lightly-doped n-channel adjacent to the boundary 248. Also, as seen in FIG. 2d, the gate is formed in a depression 250 created in the upper surface of the device, the depression having the effect of physically limiting the width of the channel below. While the source 242 and drain 244 contacts are preferably formed at the same time using a single photoresist mask, they may be made in separate steps. Furthermore, the gate contact 248 preferably is formed after the source and drain contacts are formed.

[0018] The final device has a conduction channel between the source and the drain which has a first doping profile between the source and the gate, and a second doping profile between the drain and the gate. More particularly, the MESFET of the present invention has p-type background region between the source and the gate, forming a p-well profile. The n-type channel implant dosage is reduced in the gate-drain region to form a lightly doped drain (LDD), as compared to the n-type channel implant dosage in the source-gate region.

[0019] The design of the present invention helps mitigate the p-n junction in the gate-drain region, while the LDD profile helps minimize the peak electric field intensity in the drain region. The LDD profile may also assist in increasing the gate-drain breakdown voltage, and alleviate the initiation of impact ionization, thereby mitigating the power transients caused by excessive hole trapping in the drain region.

[0020] In general, the P-well LDD GaAs MESFET design of the present invention does not severely degrade the device DC and RF performance, as compared to conventionally implanted GaAs MESFETs. This is because the channel current and the transconductance of a GaAs MESFET are mainly determined by the doping profiles in the source-gate region, where it is the same for both the P-well LDD GaAs MESFET of the present invention and the conventional MESFET. Furthermore, in normal amplifier operation, the electrons travel at saturation velocity in the gate-drain region and so the LDD doping profile generally does not negatively affect the channel electron transport process.

[0021] Also, although the final MESFET is an n-channel semiconductor device, this is not intended as a limitation of the present invention and as those skilled in the art will appreciate, a P-channel semiconductor device may be achieved by converting P-type regions to N-type regions, and vice versa.

[0022] Finally, while the above invention has been described with reference to certain preferred embodiments, it should be kept in mind that the scope of the present invention is not limited to these. One skilled in the art may find variations of these preferred embodiments which, nevertheless, fall within the spirit of the present invention, whose scope is defined by the claims set forth below.

Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US6902964Jul 30, 2004Jun 7, 2005Cree, Inc.Methods of fabricating delta doped silicon carbide metal-semiconductor field effect transistors having a gate disposed in a double recess structure
US6906350Oct 24, 2001Jun 14, 2005Cree, Inc.Delta doped silicon carbide metal-semiconductor field effect transistors having a gate disposed in a double recess structure
US6956239 *Nov 26, 2002Oct 18, 2005Cree, Inc.Transistors having buried p-type layers beneath the source region
US7067361Nov 12, 2003Jun 27, 2006Cree, Inc.Methods of fabricating silicon carbide metal-semiconductor field effect transistors
US7265399Oct 29, 2004Sep 4, 2007Cree, Inc.Asymetric layout structures for transistors and methods of fabricating the same
US7297580Jun 1, 2005Nov 20, 2007Cree, Inc.Methods of fabricating transistors having buried p-type layers beneath the source region
US7326962Dec 15, 2004Feb 5, 2008Cree, Inc.Transistors having buried N-type and P-type regions beneath the source region and methods of fabricating the same
US7348612Oct 29, 2004Mar 25, 2008Cree, Inc.Metal-semiconductor field effect transistors (MESFETs) having drains coupled to the substrate and methods of fabricating the same
US7402844Nov 29, 2005Jul 22, 2008Cree, Inc.Metal semiconductor field effect transistors (MESFETS) having channels of varying thicknesses and related methods
US7485514 *Jan 5, 2006Feb 3, 2009Winslow Thomas AMethod for fabricating a MESFET
US7646043Sep 28, 2006Jan 12, 2010Cree, Inc.Transistors having buried p-type layers coupled to the gate
US7943972Nov 30, 2009May 17, 2011Cree, Inc.Methods of fabricating transistors having buried P-type layers coupled to the gate
US8203185Jun 21, 2005Jun 19, 2012Cree, Inc.Semiconductor devices having varying electrode widths to provide non-uniform gate pitches and related methods
WO2006065324A2 *Oct 4, 2005Jun 22, 2006Cree IncTransistors having buried n-type and p-type regions beneath the source region and methods of fabricating the same
Classifications
U.S. Classification438/174, 257/E29.05, 257/E29.321, 438/167, 438/527, 257/E21.453
International ClassificationH01L29/10, H01L21/338, H01L29/812
Cooperative ClassificationH01L29/1029, H01L29/66871, H01L29/8128
European ClassificationH01L29/66M6T6S2L2, H01L29/10D2, H01L29/812E