US 20030025619 A1 Abstract A system for, and method of, increasing sample rate converter filter coefficient derivation and running speed and a digital signal processor incorporating the system or the method. In one embodiment, the system includes: (1) a coefficient table containing a matrix of predefined filter coefficients for each of a plurality of alpha intervals and (2) an intra-range interpolator that adjusts the predefined filter coefficients for a specific alpha within the alpha interval to yield filter coefficients specific to the alpha.
Claims(15) 1. A system for increasing sample rate converter filter coefficient derivation and running speed, comprising:
a coefficient table containing a matrix of predefined filter coefficients for each of a plurality of alpha intervals; and an intra-range interpolator that adjusts said predefined filter coefficients for a specific alpha within said alpha interval to yield filter coefficients specific to said alpha. 2. The system as recited in 3. The system as recited in 4. The system as recited in 5. The system as recited in 6. A method of increasing sample rate converter filter coefficient derivation and running speed, comprising:
pregenerating a coefficient table containing a matrix of predefined filter coefficients for each of a plurality of alpha intervals; and adjusting said predefined filter coefficients for a specific alpha within said alpha interval to yield filter coefficients specific to said alpha. 7. The method as recited in 8. The method as recited in 9. The method as recited in interpolating samples; and
decimating said samples.
10. The method as recited in 11. A digital signal processor, comprising:
a signal processing core; a memory that contains software instructions, said software instructions causing said signal processing core to operate as a sample rate converter that employs filter coefficients to process a stream of input samples; and a system for increasing sample rate converter filter coefficient derivation and running speed, comprising:
a coefficient table containing a matrix of predefined filter coefficients for each of a plurality of alpha intervals, and
an intra-range interpolator that adjusts said predefined filter coefficients for a specific alpha within said alpha interval to yield filter coefficients specific to said alpha.
12. The sample rate converter as recited in 13. The sample rate converter as recited in 14. The sample rate converter as recited in 15. The sample rate converter as recited in Description [0001] The present invention is directed, in general, to digital signal processors and, more specifically, to a system and method for increasing sample rate converter filter coefficient derivation and running speed. [0002] Digital signal processors (DSPs) currently have a plethora of applications, and the importance of these classes of devices will only continue to grow. For example, DSPs may be used as a digital filter in an environment such as digital audio. In the digital audio environment, the DSP may perform analogous functionality similar to a passive or an active analog filter. However, there are certain problems which may arise in the context of using the DSP as a passive or active filter. For instance, issues pertaining to accommodating differing input and output DSP signal data rates may arise. [0003] One proposed solution associated with accommodating differing input and output DSP signal data rates using such techniques as data interpolation. Interpolations of the input data signal to achieve an acceptable output data signal may involve, however, trade-offs in levels of precision or level of accuracy of the output data. For instance, as a tolerance for approximate solutions pertaining to calculated values of the output signal decreases, the computational, architectural or processing complexity of the DSP may disadvantageously increase, and design trade-offs and decisions should be made. The prior art discloses certain attempts at implementing differing approaches to signal interpolations performed by a DSP. [0004] For instance, in one prior-art approach, a digital signal, which may represent an audio signal that has been sampled at a given rate, is first “up-sampled” or “over-sampled”, i.e., between every digital sample at a given frequency there is inserted equidistantly between at least value of zero. Up-sampling effectively increases the sample rate of the input data signal, perhaps for reasons such as helping to avoid aliasing problems and running afoul of the Nyquist sampling theorem. [0005] Next, a Finite Impulse Response (“FIR”) filter is used. The FIR filter is programmed with the various tap values desired for a given characteristic, such as the skirt, dB dropoff rate, attenuation rate, passband, and so on. After the FIR filter has been applied, the prior art teaches re-sampling (“decimating”) the FIR filtered data, and then linear interpolating the now-decimated data to achieve the desired output sample rate. [0006] The over-sampling FIR plus linear interpolator strategy involves heavy real-time computations of multiplication and addition, and requires large memory space to store the FIR tap coefficients, although the reduction of interpolation factor makes its implementation easier than a single-stage FIR implementation. [0007] A second approach, employing a Continuously Variable Digital Delay (“CVDD”) Element, has also been tried. The CVDD has been described in “A Continuously Variable Digital Delay Element” by C. W. Farrow, which is hereby incorporated by reference in its entirety, and shall therefore only be described in a summary fashion. [0008] Briefly, the CVDD Element uses a FIR filter which employs and synchronizes a controllable delay relationship between the input data signal and the output data signal. By changing the delay between the input data signal and the output data signal, the FIR filter of Farrow has the ability to interpolate between samples in the data stream of a band-limited signal. [0009] Advantageously, the CVDD of Farrow does not need large memory space to run since it calculates filter coefficients in real-time with its pre-optimized coefficient taps and a time-varying parameter, a delay “α”. However, employing the CVDD of Farrow involves vector and matrix operation, which can lead to quite heavy online computation. Another disadvantage of the CVDD of Farrow is the online calculation of α [0010] Accordingly, what is needed in the art is a system and method of filtering and interpating digital data of differing sample rates that overcomes the deficiencies of the prior art. [0011] To address the above-discussed deficiencies of the prior art, the present invention provides a system for, and method of, increasing sample rate converter filter coefficient derivation and running speed and a digital signal processor incorporating the system or the method. In one embodiment, the system includes: (1) a coefficient table containing a matrix of predefined filter coefficients for each of a plurality of alpha intervals and (2) an intra-range interpolator that adjusts the predefined filter coefficients for a specific alpha within the alpha interval to yield filter coefficients specific to the alpha. [0012] The present invention introduces the broad concept of deriving filter coefficients by first retrieving coefficients valid over a range of alpha intervals from memory and then interpolating the coefficients to yield coefficients specific to a particular alpha [0013] In one embodiment of the present invention, the intra-range interpolator linearly interpolates the predefined filter coefficients to yield the filter coefficients specific to the alpha. However, those skilled in the art may find nonlinear interpolation useful in a given application. [0014] In one embodiment of the present invention, the sample rate converter comprises a doubler that doubles an input sample rate. Predoubling improves subsequent interpolation, but is not necessary to the present invention. [0015] In one embodiment of the present invention, the sample rate converter comprises a sample interpolator and a sample decimator. The sample interpolator and decimator cooperate to apply the coefficients to a stream of input samples to yield a stream of output samples taken at a desired output rate. [0016] In one embodiment of the present invention, the system the sample interpolator provides samples to the sample decimator. Alternatively, the samples may be decimated before being interpolated, in which case the sample decimator would provide samples to the sample interpolator. [0017] The foregoing has outlined, rather broadly, preferred and alternative features of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiment as a basis for designing or modifying other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form. [0018] For a more complete understanding of the present invention, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which: [0019]FIG. 1 illustrates an environment of a digital signal processor system (“DSP”) data rate converter system (“converter”) within which the present invention may operate; [0020]FIG. 2 illustrates an embodiment of a device for increasing a sample rate converter filter's coefficient derivation speed constructed according to the principles of the present invention; and [0021]FIG. 3 illustrates a method of use of a digital signal processor according to the principles of the present invention. [0022] Referring initially to FIG. 1, illustrated is an environment of a digital signal processor system (“DSP”) data rate converter system (“converter”) [0023] The memory [0024] The DSP converter [0025] The DSP converter [0026] Generally, when converting from the input data rate to the output data rate, a different array of tap coefficients must be employed by the FIR filter for each specific α value, in order for the FIR filter to exhibit the desired filter characteristics. In the prior-art data rate converters, as the interval α value could vary unpredictably as the input and output rates would vary, the specific α values could also be any value in a range of −0.5 to 0.5, to an arbitrary number of decimal places. The extreme variability of the specific a value (as the interval a values were not pre-defined) therefore necessitated a real-time calculation of the tap values of the FIR, as the tap values were derived from the specific α values. [0027] However, this prior-art tap-calculation approach leads to quite heavy online computation. Another disadvantage of the prior art is the calculation of α [0028] Advantageously, according to the principles of the present invention, for a given range of possible interval α values, a specific predefined interval α value will instead be used by the DSP converter [0029] Having discrete sets of pre-defined interval α values in turn enables the pre-generation of a matrix of specific α values. Thereafter, pre-defined tap-values, derived from specific a values, can be also stored in matrix form in the CDS [0030] As elaborate upon the above, Finite Impulse Response (“FIR”) filter of the CDS [0031] As detailed above, these pre-defined tap values are a function of a given, pre-defined a interval value and desired FIR characteristics. Use of pre-defined tap-values enhances the computational efficiency of the DSP [0032] Arrays of tap-values are employed sequentially by the FIR filter, necessary to achieve a given FIR filter response of the CDS [0033] The CDS [0034] Alternatively, the IRI may simply interpolate between two output data values as a function of the relative time between the two intermediate samples. As detailed above, as the ultimate real-world interval α value may be different from the approximate α data value, the derived specific α values may be different. The IRI may interpolate the output data value, proportional to its specific a position between two pre-defined specific α values. [0035] For instance, if the precalculated specific α values are −0.1, 0.1, 0.3, and so on (i. e. these values were the values that were used when calculating the tap-value coefficients), but the desired specific α value is that of 0.15, the final data value of the CDS [0036] Turning now to FIG. 2, illustrated is an embodiment of a system [0037] The system [0038] The doubler [0039] The doubler [0040] Next the table [0041] For instance, if the interval α value=1/64, and use a 12-Tap, 7 [0042] The IRI [0043] Alternatively, as detailed above, the sample interpolator [0044] For instance, if the precalculated specific α values are −0.1, 0.1, 0.3, and so on (i.e. these values were the values that were used when pre-calculating the employed tap-value coefficients), but the calculated specific α value of a data train at the desired output signal rate would be 0.15, a final data value of the IRI [0045] Finally, the sample decimator [0046] Turning now to FIG. 3, illustrated is a method of use of a digital signal processor data rate converter (“converter”) [0047] After executing a start [0048] After pregenerating tables of matrixes in the pregeneration step [0049] After the doubling has occurred in the doubling step [0050] Next, a decimating step [0051] Although the present invention has been described in detail, those skilled in the art should understand that they can make various changes, substitutions and alterations herein without departing from the spirit and scope of the invention in its broadest form. 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