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Publication numberUS20030035400 A1
Publication typeApplication
Application numberUS 10/208,252
Publication dateFeb 20, 2003
Filing dateJul 30, 2002
Priority dateJul 31, 2001
Also published asDE10137345A1, DE10137345B4, US6781398
Publication number10208252, 208252, US 2003/0035400 A1, US 2003/035400 A1, US 20030035400 A1, US 20030035400A1, US 2003035400 A1, US 2003035400A1, US-A1-20030035400, US-A1-2003035400, US2003/0035400A1, US2003/035400A1, US20030035400 A1, US20030035400A1, US2003035400 A1, US2003035400A1
InventorsFrank Adler, Hartmut Berger
Original AssigneeFrank Adler, Hartmut Berger
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Circuit for testing an integrated circuit
US 20030035400 A1
Abstract
A test circuit for testing an integrated circuit, includes a test signal input for receiving a test signal from the integrated circuit and a reference signal input for receiving a reference signal. A comparator is in communication with the test signal input and with the reference signal input. The comparator is configured to provide, at a comparator output, an error signal if a comparison between the reference signal and the test signal indicates an error. The error signal, if present, is stored in an error memory, in communication with the comparator output.
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Claims(18)
1. A test circuit for testing an integrated circuit, the test circuit comprising:
a test signal input for receiving a test signal from the integrated circuit;
a reference signal input for receiving a reference signal;
a comparator in communication with the test signal input and with the reference signal input, the comparator being configured to provide, at a comparator output, an error signal if a comparison between the reference signal and the test signal indicates an error;
an error memory, in communication with the comparator output, for storing the error signal; and
an error signal output in communication with the error memory.
2. The test circuit of claim 1, wherein the comparator is configured to output a binary error signal in response to a comparison of voltages of the test signal and the reference signal.
3. The test circuit of claim 1, wherein the error memory comprises a flip-flop.
4. The test circuit of claim 1, further comprising a reset signal input connected to the error memory for erasing an error state thereof.
5. The test circuit of claim 1, wherein
the comparator is configured to output a first error signal when a test signal voltage of the test signal exceeds a reference signal voltage of a reference signal,
and the circuit further comprises:
an additional reference signal input for receiving an additional reference signal, and
an additional comparator in communication with the test signal input and with the additional reference signal input, the additional comparator being configured to provide, at an additional comparator output, an additional error signal when a reference signal voltage of the additional reference signal exceeds the test signal voltage.
6. The test circuit of claim 5, further comprising an additional error memory in communication with the additional comparator output for storing the additional error signal, the additional error memory being in communication with the error signal output.
7. The test circuit of claim 6, wherein the error memory and the additional error memory are configured to be read separately from each other at the error signal output.
8. A system for testing an integrated circuit, the system comprising:
a test circuit as recited in claim 1,
a programmable driver output for outputting the reference signal to the reference signal input of the test circuit, and
a test result input in communication with the error signal output for receiving the error signal.
9. The system of claim 8, wherein the test circuit comprises an ASIC (“application specific integrated circuit”).
10. The system of claim 8, wherein the test circuit comprises a programmable logic array.
11. The system of claim 8, wherein the programmable driver output comprises an analog high-speed output.
12. The system of claim 11, wherein the test result input is a low speed input.
13. A system for testing an integrated circuit, the system comprising:
a test circuit as recited in claim 5,
a first programmable driver output for outputting the reference signal to the reference signal input of the test circuit,
a second programmable driver output for outputting the additional reference signal to the additional reference signal input, and
a test result input in communication with the error signal output for receiving the error signal.
14. The system of claim 8, further comprising an additional programmable driver output in communication with the test signal input.
15. The system of claim 14, wherein the additional programmable driver output forms an active termination of the test signal input.
16. A method of testing a test signal of a DDR-DIMM, the method comprising:
providing a system as recited in claim 8, and
providing the test signal to the system.
17. A method of testing a test signal generated by an integrated circuit, the method comprising:
providing the test signal to a test signal input of a test circuit;
providing a reference signal into a reference signal input of the test circuit;
comparing the test signal and reference signal with a comparator;
storing an error signal into an error memory when the comparison of the test signal and the reference signal indicates an error; and
reading the error signal from the error memory.
18. The method of claim 17, wherein comparing the test signal comprises providing an external control signal to the comparator for causing the comparator to enter a comparison mode.
Description
FIELD OF INVENTION

[0001] The invention relates to a circuit apparatus for testing at least one test signal output by an integrated circuit.

RELATED APPLICATIONS

[0002] This application claims the benefit of the Jul. 31, 2001 filing date of German application 101 37 345.7-53, the contents of which are herein incorporated by reference.

BACKGROUND

[0003] Integrated circuits undergo a multiplicity of different test methods during and after their fabrication process. With the continually growing complexity of modern integrated circuits—in particular DRAM memories—the required test methods also become more complex and require ever more powerful test systems. Since the typical product lifetime, in particular of modern memory components, often amounts to only a few months, it is impracticable for cost reasons to individually create anew a test system suitable for a specific memory component. Therefore, modern test systems for the functional testing of complex integrated circuits are usually individually programmable within wide limits, in order to be able to be adapted to ever new DUTs (device under test). Therefore, the test systems used in the semiconductor memory industry, some of which have procurement prices of in excess of one million Euros, can typically be used over a plurality of product generations.

[0004] A critical bottleneck of commercial test systems for integrated circuits, for example of the Advantest T 5581 test system for DRAM-DIMMS, is the number of freely programmable and fast input/output terminals (I/O pins). By way of example, the Advantest T 5581 D-type test system, for parallel test purposes, has over n*72 fast, freely programmable I/O pins (n=4, 8 or 16) which suffice for complete functional testing of an SDR-DIMM (single data rate DIMM) with high parallelism and flexibility (in particular owing to the scrambling of the PCB (printed circuit board) that is to be taken into account). DDR-DIMMs (double data rate DIMMs), which are increasingly being used, have a further 18 terminals, however, on account of the DQS signals (data query strobe) arising in this case, so that flexible and highly parallel functional testing of, in particular, the DQS signals during the read operation is problematic with this test system.

[0005] Therefore, performance boards (base boards or HiFix boards) have conventionally had to be used, on which DDR-DIMMs have been able to be tested only 4-fold in parallel with low flexibility.

SUMMARY

[0006] In view of the above disadvantages, it is an object of the invention, therefore, to extend in particular conventional test systems, whose number of freely programmable fast I/O pins (i.e. the number of comparators) does not suffice for a flexible and complete functional test of an integrated circuit, in a simple and cost-effective manner for the new test task.

[0007] According to the invention, a circuit apparatus for testing at least one test signal output by an integrated circuit comprises

[0008] at least one test signal input for the signal inputting of the test signal;

[0009] at least one reference signal input for the signal inputting of a reference signal;

[0010] at least one comparator device, which is designed for a signal comparison of the test signal with the reference signal and for outputting an error signal if the signal comparison yields an error;

[0011] at least one error memory device for storing the error signal; and

[0012] at least one error signal output connected to the error memory device.

[0013] According to the invention, a circuit apparatus is used which has inputs for the signal to be tested (e.g. the DQS signal of DDR-DIMM) and for a reference signal chosen in accordance with the corresponding specification. The test signal is input into the test signal input from the integrated circuit to be tested.

[0014] The reference signal can be output by an external test system. It is advantageous that there is no need to use a “valuable” fast I/O pin of the test system in order to output the reference signal to the circuit apparatus. Instead of this, a so-called driver output of the test system may preferably be used, which driver output, although designed for fast and freely programmable signal outputting, is not designed for signal inputting. Although it is often the case in test systems which are used for highly complex test tasks that all the fast I/O pins which can compare signals output by the integrated circuit to be tested with reference signals are occupied, so that additional signals of the integrated circuit cannot be directly tested at the same time, such test systems nonetheless typically also have a multiplicity of additional driver outputs which are not yet occupied.

[0015] The circuit apparatus according to the invention enables these hitherto unutilized driver outputs of the test system to be preferably used to test the additional (test) signals of the integrated circuit to be tested. The test signal is compared with the reference signal (from the driver output of the test system) in the comparator device of the circuit apparatus. If the signal comparison turns out to be negative, i.e. the test signal does not satisfy the test reference prescribed by the reference signal, the comparator device generates an error signal which is stored in an error memory device. The error memory device can be read externally via the error signal output in particular by the external test system.

[0016] Although a signal input of the test system is required for the read-out operation of the error memory device, this test result input of the test system need not be a “fast” signal input, since the error state stored in the error memory device can also be read out with a read-out rate which is significantly lower than the signal rate of the test and reference signals. Such “slow” programmable signal inputs of the test system are often still available even when all the “fast” inputs are already occupied.

[0017] Consequently, the circuit device enables the functional testing of an additional signal output of the integrated circuit (i.e. of the test signal) without this requiring an additional fast I/O pin of the test system. Instead of this, the circuit apparatus according to the invention makes it possible to use a fast driver output and also a slow signal input of the test system.

[0018] It is particularly advantageous, moreover, that a single driver output of the test system can be connected to a multiplicity of reference signal inputs of the circuit apparatuses in order to test a multiplicity of DQS signals of a DDR-DIMM. In this case, a multiplicity of test signal inputs and comparator devices are correspondingly provided. The error evaluation can in this case be effected separately for each test signal (i.e. DQS-fine error testing) if each comparator device is assigned an error memory device. It is often sufficient, however, for the error evaluation merely to be of DUT-fine design, so that, in particular, a single error memory device per DUT may be sufficient.

[0019] Preferably, the comparator device is designed for a voltage comparison of the test signal with the reference signal and for outputting a binary error signal. The voltage comparison may be performed by the comparator device in particular continuously or only when said comparator device is in a comparison mode which can be activated externally. It is advantageous to provide a binary signal as the error signal. In this case, the test result input of the test system, which input is connected to the error signal output of the circuit apparatus, need be, for example, only a simple (slow) TTL input.

[0020] Preferably, the error memory device comprises at least one flip-flop circuit. Preferably, the error memory device is connected to a reset signal input for erasing an error state of the error memory device. The reset signal can be generated by a programmable signal output of the test system, which output may be, in particular, slow and binary.

[0021] Preferably, the test signal input is connected to at least one first and one second comparator device and at least one first and one second reference signal input are provided, wherein

[0022] the first comparator device is designed for outputting a first error signal if the voltage of the test signal is greater than the voltage of a first reference signal at the first reference signal input, and

[0023] the second comparator device is designed for outputting a second error signal if the voltage of the test signal is less than the voltage of a second reference signal at the second reference signal input.

[0024] The first comparator device is designed for testing the HIGH signal state and the second comparator device is designed for testing the LOW signal state of the test signal.

[0025] Preferably, the first comparator device is connected to a first error memory device and the second comparator device is connected to a second error memory device, and the error memory devices can be read separately from one another via the error signal output.

[0026] If the intention is to carry out separate error evaluation according to HIGH and LOW errors, each comparator device is connected to a separate error memory device. These error memory devices can be connected to a single error signal output if additional error memory selection inputs (output enable) are provided. Otherwise, it is also possible to use a single error memory device for both comparator devices if HIGH error states do not have to be discriminated from LOW error states.

[0027] The invention furthermore proposes an arrangement of a test system for integrated circuits having a circuit apparatus according to the invention, wherein the test system comprises:

[0028] at least one programmable driver output for outputting a voltage signal, which is connected to the reference signal input of the circuit apparatus, and

[0029] at least one test result input, which is connected to the error signal output of the circuit apparatus.

[0030] As already described in detail above, such an arrangement of an, in particular, conventional test system with the circuit arrangement enables functional testing of an output signal of an integrated circuit without a further fast I/O pin of the test system having to be occupied for this purpose. Instead of this, the test signal can be tested by the arrangement if the test system has an as yet unoccupied driver output and also an, in particular, slow signal input (test result input).

[0031] In particular, the test system is an Advantest T 5581 (preferably D-type) and the circuit apparatus is an ASIC or a programmable logic device (PLD). The circuit apparatus is preferably integrated into a performance board (base board, HiFix board) of the test system in the form of an ASIC. The arrangement according to the invention is advantageously suitable for testing DDR-DIMMs with 18 additional DQS signal outputs relative to SDR-DIMMs for complete functioning of all signal outputs with high parallelism and flexibility. This is not possible without the circuit apparatus.

[0032] Preferably, the driver output is an analogue high-speed output and the test result input is a low-speed input of the test system. In this case, a high-speed output is understood to be a signal output which is designed for signal rates of the order of magnitude of the system clock of the integrated circuit. The “speed” of the test result input may be orders of magnitude lower than this.

[0033] Preferably, the test system comprises at least one first and one second programmable driver output for outputting voltage signals, and the first driver output is connected to the first reference signal input and the second driver output is connected to the second reference signal input, a reference voltage vREF also sufficing given a suitable termination.

[0034] Preferably, the test system has at least one further programmable driver output, which is connected to the test signal input. This further driver output which is connected to the test signal input may advantageously be used for functional testing and calibration of the arrangement. In particular, a precisely defined signal can be output by the test system via the further driver output into the test signal input of the circuit apparatus in order to simulate an actual test signal. Since the time and/or voltage behavior of this simulated test signal is known precisely, it is possible to check whether the circuit apparatus is working properly.

[0035] Since, moreover, a possible propagation time difference between the actual test signal from the integrated circuit to the test signal input and the simulated test signal from the test system to the test signal input is known, the further driver output can be used for time calibration of the arrangement. The time behavior of the reference signal output by the test system can be exactly adapted in this way.

[0036] Preferably, the further driver output is connected to the test signal input in such a way that it forms an active termination of the test signal input.

[0037] Particular preference is attached to a use of the arrangement according to the invention for testing at least one DQS signal of a DDR-DIMM, in particular in conjunction with the Advantest T 5581 D-type test system.

[0038] According to the invention, a method for testing at least one test signal output by an integrated circuit, having the following steps:

[0039] inputting of the test signal from the integrated circuit into a test signal input of a circuit apparatus;

[0040] inputting of a reference signal from a test system into a reference signal input of the circuit apparatus;

[0041] comparison of the test signal with the reference signal by a comparator device of the circuit apparatus;

[0042] outputting of an error signal into an error memory device of the circuit apparatus if the signal comparison yields an error; and

[0043] read-out of the error signal from the error memory device by the test system.

[0044] The circuit apparatus is preferably a circuit apparatus according to the invention as described above. It may be provided that the comparator device carries out the signal comparison only in a comparison mode which can be activated externally.

[0045] The invention is described by way of example below with reference to accompanying drawings of a preferred embodiment. In the figures:

BRIEF DESCRIPTION OF THE FIGURES

[0046]FIG. 1 shows a schematic circuit diagram of an embodiment of an arrangement according to the invention; and

[0047]FIG. 2 shows a timing diagram of the test signal (DQS) and of the reference signal (PDy, PDz) in the case of a test method with the arrangement of FIG. 1.

DETAILED DESCRIPTION

[0048]FIG. 1 illustrates a preferred embodiment of an arrangement according to the invention of a test system for integrated circuits with a circuit apparatus. The test system may be, for example, an Advantest T 5581 D which is used for testing DRAM memory modules. Only the driver outputs PDx, PDy and PDz of the test system 10 are illustrated in FIG. 1. The driver output PDy outputs a reference signal into a reference signal input 18 (negative comparator input) of a comparator device 14 of the circuit apparatus 12, which is likewise designated by PDy for simplification. The comparator device 14 is a first comparator device designed for testing the HIGH signal state of a test signal DQS of the integrated circuit 11.

[0049] In a similar manner, the driver output PDz is connected to a reference signal input 20 (positive comparator input) of a second comparator device 16 of the circuit apparatus 12. The comparator device 16 is designed for testing the LOW signal state of the test signal DQS.

[0050] The test signal DQS, which is output by the integrated circuit 11, is input into the test signal inputs 22 and 24 of the comparator devices 14 and 16, respectively. The test signal inputs 22 and 24 are connected to a further driver output PDx of the test system 10, whereby these are actively terminated. Furthermore, the driver output PDx enables a self-calibration of the arrangement (see below) and generates the DQS signal during the writing of data to the DDR-DIMM.

[0051] The method of operation of the embodiment of the arrangement according to the invention is described below with reference to FIG. 1 and the signal profile of the signals DQS, PDy and PDz of FIG. 2. FIG. 2 shows, in the upper region, the time behavior of a DQS signal, which may be, for example, an output signal to be tested of the integrated circuit 11. A task of the arrangement is to test whether, in certain time windows, the test signal DQS is greater or less than a predetermined reference voltage value.

[0052] The reference signal PDy serves for switching the comparator device 14 for testing the HIGH signal state of the test signal DQS in “sharp” or “critical” fashion. For this purpose, in the time window in which the DQS signal must have a high voltage potential, the reference signal PDy is put from a very small potential to a minimum value for the high voltage potential. If the test signal DQS is greater than said minimum value in said time window, the signal comparison is positive and an error signal is not output (cf. FIG. 2, central region). However, if the test signal DQS is less than the minimum value, the signal comparison turns out to be negative and an error signal is output by the comparator device 14 into a first error memory device 26 and stored there. Outside the time window, i.e. when the reference signal PDy has a small potential, the signal present at the test signal input 22 will always be greater than the reference signal PDy, so that the comparator device 14 does not generate and output an error.

[0053] In a similar manner, the reference signal PDz serves for prescribing the maximum value of the voltage potential which the test signal DQS is permitted to have in a time window in which a low voltage potential (LOW) is expected for DQS. The second comparator device 16 is accordingly switched in “critical” fashion by the reference signal PDz being set from a very high voltage potential to the maximum value for the low voltage potential (LOW). If the test signal DQS has an excessively large voltage potential in this time window, then an error state is generated and stored in a second error memory device 28. The error memory devices 26 and 28 can preferably be erased by a slow and binary RESET signal from the test system 10.

[0054] After a predetermined test duration (a predetermined number of DQS pulses), the error memory devices 26 and 28 are read by the test system 10. For this purpose, the circuit apparatus 12 has two error memory selection devices 30, 32 assigned to the error memory devices 26 and 28, respectively. The error memory selection devices 30, 32 respectively have an error memory selection input 34, 36, which can be switched by a preferably slow, binary signal from the test system 10. Consequently, the error state of the error memory devices 26, 28 can be determined by read-out at the error signal output 38, connected to the test result input (not illustrated) of the test system 10.

[0055] The driver output PDx of the test system 10 is used in order to test or to calibrate the arrangement and to generate the DQS signal during writing. The test signal DQS can be simulated by the PDx signal of the test system 10, so that the circuit apparatus can be tested with a test signal whose time and level behavior is known precisely. Calibration is effected by the reference signals PDy and PDz being adapted with regard to level and “timing”.

[0056] The arrangement can advantageously be extended in a simple manner to test a multiplicity of test signals DQS. By way of example, if 18 DQS signals are to be tested by the arrangement, it is possible to provide 18 comparator device pairs in the circuit apparatus. 18 PDx driver outputs of the test system 10 are connected separately to the 18 DQS test signals. The reference signals PDy and PDz may advantageously be identical for all the test signals DQS. As already described above, the error evaluation can be effected separately for each test signal DQS (DQS-fine evaluation) or overall for the DUT (DUT-fine evaluation).

Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US7092836 *Aug 28, 2003Aug 15, 2006Mosel Vitelic, Inc.Method for locating wiring swap in a hi-fix structure of a simultaneous multi-electronic device test system
Classifications
U.S. Classification370/338
International ClassificationG11C29/56
Cooperative ClassificationG11C29/56, G11C2029/5606
European ClassificationG11C29/56
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