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Publication numberUS20030051907 A1
Publication typeApplication
Application numberUS 09/957,373
Publication dateMar 20, 2003
Filing dateSep 20, 2001
Priority dateSep 20, 2001
Also published asUS6573461, US20030051903
Publication number09957373, 957373, US 2003/0051907 A1, US 2003/051907 A1, US 20030051907 A1, US 20030051907A1, US 2003051907 A1, US 2003051907A1, US-A1-20030051907, US-A1-2003051907, US2003/0051907A1, US2003/051907A1, US20030051907 A1, US20030051907A1, US2003051907 A1, US2003051907A1
InventorsGlen Roeters, Frank Mantz
Original AssigneeRoeters Glen E., Mantz Frank E.
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Retaining ring interconnect used for 3-d stacking
US 20030051907 A1
Abstract
A retaining ring interconnect. A retaining ring is formed on a perimeter of a pad on each of two adjoining surfaces of two PCB substrates. A conductive paste is applied between the pads on the two adjoining surfaces. The retaining rings are aligned and facing with each other. By performing a heat compression process, the retaining rings are connected to encompass the conductive paste. A eutectic bond is thus formed to bond the two PCB substrates.
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Claims(16)
What is claimed is:
1. A retaining ring interconnect, comprising:
two pads disposed on two adjoining surfaces of two stacked substrates, each of the two pads including a peripheral retaining ring, the two retaining rings being aligned with and connected to each other; and
a conductive paste disposed between the two pads and contained by the two retaining rings thereof.
2. The retaining ring interconnect according to claim 1, further comprising an adhesive layer bonding the two adjoining surfaces of the two substrates to each other.
3. The retaining ring interconnect according to claim 1, wherein each of the two substrates has a distal surface including a pad formed thereon and electrically connected to the pad on the surface adjoining the other substrate by a conductive via.
4. The retaining ring interconnect according to claim 3, wherein each pad formed on the distal surface has a height of about 0.0007 inches.
5. The retaining ring interconnect according to claim 1, wherein the adhesive layer includes a glass resin pregreg.
6. The retaining ring interconnect according to claim 1, wherein each of the two pads including the retaining ring has a total height of about 0.001 inches.
7. The retaining ring interconnect according to claim 6, wherein each of the retaining rings of the two pads has a height of about 0.0005 inches.
8. The retaining ring interconnect according to claim 1, wherein each of the retaining rings has an inner diameter of about 0.0006 inches and an outer diameter of about 0.0008 inches.
9. The retaining ring interconnect according to claim 1, wherein the retaining rings are formed of copper.
10. The retaining ring interconnect according to claim 2, wherein the adhesive layer has a thickness of about 0.002 inches.
11. A retaining ring interconnect process, comprising the steps of:
(a) providing two substrates, each of the substrates having at least one first pad on one surface thereof;
(b) forming a retaining ring on a peripheral portion of each of the first pads;
(c) aligning and facing the retaining rings of the two substrates with each other;
(d) applying a conductive paste between the facing retaining rings; and
(e) stacking the two substrates such that the conductive paste is compressed between the first pads.
12. The retaining ring interconnect process according to claim 11, wherein step (a) comprises providing a second pad on a distal surface of each of the two substrates.
13. The retaining ring interconnect process according to claim 12, wherein step (a) further comprises electrically connecting the first and the second pads of each of the two substrates by a conductive via therethrough.
14. The retaining ring interconnect process according to claim 11, wherein step (d) comprises applying an adhesive layer between the surfaces of the two substrates to bond the substrates to each other.
15. The retaining ring interconnect process according to claim 14, wherein step (d) comprises applying the conductive paste within the adhesive layer using a lased via technique.
16. The retaining ring interconnect process according to claim 11, wherein step (e) comprises forming an eutectic bond of the conductive paste between the two first pads by controlling pressure and temperature.
Description
    BACKGROUND OF THE INVENTION
  • [0001]
    The present invention relates generally to chip stacks, and more particularly to a 3-D chip stack with a retaining ring interconnect.
  • [0002]
    As is currently known in the art, packaged components are often stacked using a variety of approaches. In all of the approaches to date, the concept has been for the end user to mount the stacks on the surface of a solid board such as a printed circuit board (PCB). More particularly, one of the most commonly used techniques to increase memory capacity is the stacking of memory devices into a vertical chip stack, sometimes referred to as 3D packaging or Z-Stacking. In the Z-Stacking process, from two to as many as eight memory devices or other integrated circuit (IC) chips are interconnected in a single component (i.e., a chip stack) which is mountable to the “footprint” typically used for a single packaged device such as a packaged chip. The Z-Stacking process has been found to be volumetrically efficient, with packaged chips in TSOP (thin small outline package) or LCC (leadless chip carrier) form generally being considered to be the easiest to use in relation thereto. Though bare dies may also be used in the Z-Stacking process, such use tends to make the stacking process more complex and not well suited to automation.
  • [0003]
    In the 3-D stacking process, a solder bridge is typically applied to interconnect neighboring layers or PCB substrates that carry IC devices. However, in the ever changing world of electronics, smaller, faster, and more functionality are always requested. Shrinkage of devices generally results in more I/O's in a smaller package. Design rules are requiring shorter signal paths to accommodate the faster die speeds. With the tighter pitches becoming more prominent in the packages, solder bridging between neighboring interconnects becomes more difficult to control. This forces the issue of eliminating solder paste because of its limitation on density. Another concern relates to environmental issues with the lead content in solder and the concern of the disposal. A method to resolve these problems is required.
  • SUMMARY OF THE INVENTION
  • [0004]
    The invention provides a retaining ring interconnection to replace the solder joints between neighboring substrates or layers for stacking IC devices, such that the limitation in density and environmental problems caused by lead content attendant to the use of solder paste are eliminated.
  • [0005]
    A PCB substrate is provided with conductive pads on two opposing surfaces thereof. The two conductive pads are electrically connected with each other by a via through the PCB substrate. A retaining ring is plated on the peripheral portion of at least one of the conductive pads. When the PCB substrate is stacked with the other PCB substrate with the same structure, the retaining rings of two PCB substrates are aligned and faced with each other. A conductive paste is applied between two aligned retaining rings, and an adhesive is applied between two adjoining surfaces of the two PCB substrates. By a lamination process, a eutectic bond is formed of the conductive paste between the retaining rings of two adjoining pads of the two PCB substrates. Meanwhile, the adhesive tightly bonds the two adjoining surfaces of the two PCB boards.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • [0006]
    These, as well as other features of the present invention, will become more apparent upon reference to the drawings wherein:
  • [0007]
    [0007]FIG. 1 is a side view of two substrates stacked together using the retaining ring interconnect provided in the present invention;
  • [0008]
    [0008]FIG. 2 is an enlarged view of the encircled region A in FIG. 1 showing the retaining ring interconnect before being compressed;
  • [0009]
    [0009]FIG. 3 is an enlarged view of the pad on a distal surface opposed to the adjoining surface of one of the substrates;
  • [0010]
    [0010]FIG. 4 shows a top view of the plated ring on one of the pads;
  • [0011]
    [0011]FIG. 5 shows the stacked substrates after compression;
  • [0012]
    [0012]FIG. 6 shows an enlarged view of the encircled region C in FIG. 5;
  • [0013]
    [0013]FIG. 7 is a top view of a component carrier, on which an IC device is attached;
  • [0014]
    [0014]FIG. 8 is a top view of a frame to over fit the component carrier as shown in FIG. 7; and
  • [0015]
    [0015]FIG. 9 is a side view of the layer to be stacked with the other, on which a retaining ring is formed.
  • DETAILED DESCRIPTION OF THE INVENTION
  • [0016]
    [0016]FIG. 1 shows two substrates 100 and 102 to be stacked with each other. The substrate 100 has a top surface 104 and a bottom surface 106, and the substrate 102 has a top surface 108 and a bottom surface 110. Pads 112 and 114 are formed on the top surface 104 and the bottom surface 106, respectively, of the substrate 100. The pads 112 and 114 on two opposing surfaces 104 and 106 of the substrate 100 are electrically connected to each other by the formation of a conductive via 120. Similarly, pads 116 and 118 are formed on the top surface 108 and the bottom surface 110, respectively, of the substrate 106. The pads 116 and 118 on two opposing surfaces 108 and 110 of the substrate 106 are electrically connected to each other by the formation of a conductive via 122 through the substrate 102. The pads 114 and 116 on the surfaces 106 and 108 are processed with plated retaining rings 114 a and 116 a (FIG. 2), respectively. Between the pads 114 and 116 and retained within plated rings 114 a and 116 a is a conductive ink or conductive paste 126. To facilitate the bonding of the neighboring surfaces 106 and 108 of the substrates 100 and 102, an adhesive 124, preferably a glass resin prepreg, is inserted therebetween. In one embodiment of the invention, the adhesive 124 is applied between adjoining surfaces 106 and 108 of the substrates 100 and 102. Using a lased via technique, the conductive paste 126 is inserted into a via in the lased adhesive 124 in alignment with the retaining rings 114 a and 116 a.
  • [0017]
    [0017]FIG. 2 shows an enlarged side view of the encircled region A as illustrated in FIG. 1. In FIG. 2, plated retaining rings 114 a and 116 a are formed on the pads 114 and 116, respectively. Preferably, the plated retaining rings 114 a and 116 a are made of the same material, for example, copper, as that of the pads 114 and 116. In one embodiment of the invention, the pads 114 and 116 including the retaining rings 114 a and 116 a have a total height of about 0.001 inches. This height may vary in accordance with the dielectric separation needed in the Z-axis. Of the height, about 0.0005 inches is attributable to the retaining ring 114 a, 116 a, i.e., the central portion of the pad 114, 116 also has a height or thickness of about 0.0005 inces. That is, the pads 114 and 116 with the retaining rings 114 a and 116 a each define a recess having a depth of about 0.0005 inches. The recesses allow the conductive paste 124 to be filled and retained therebetween when the substrates 100 and 102 are compressed against each other. Further in this embodiment, the cross sectional width of the conductive vias 120 and 122 is about 0.004 inches.
  • [0018]
    Referring to FIG. 3, an enlarged view of the pad 118 on the distal or bottom surface 110 of the substrate 102 is illustrated. The pad 118 has a height or thickness of about 0.0007 inches in this embodiment. Preferably, the pad 112 on the top surface 104 of the substrate 100 has the same dimension of the pad 118. In FIG. 4, a top view of the plated retaining ring 116 a is given. The inner and outer diameters of the retaining ring 116 a are about 0.0006 inches and 0.0008 inches, respectively. Preferably, the retaining ring 114 a has the same dimension as the retaining ring 116 a. The above parameters are preferred when the substrates 100 and 102 each have a thickness of about 0.38 inches. It is appreciated that these parameters are only given as an example of the invention. These parameters may be altered according to specific requirements.
  • [0019]
    [0019]FIG. 5 shows the stacked structure of the substrates 100 and 102 after compression. Referring to FIG. 1, once the retaining rings 114 a and 116 a of the pads 114 and 116 are aligned with each other and the conductive paste 126 is applied therebetween, a compression step is performed. Tooling pins can be used for the alignment of the retaining rings 114 a and 116 a. The compression step such as a lamination process controls the pressure and temperature. As a result, a eutectic bond is formed between the pads 114 and 116, while the adhesive 124, preferably a glass resin prepreg, with a thickness equal to the total heights of both the pads 114 and 116 (inclusive of the retaining rings 114 a and 116 a) reflows to create a tight bond between the substrates 100 and 102. In the above embodiment, as the height of each of the pads 114 and 116 is about 0.001 inches, the thickness of the adhesive 124 is about 0.002 inches. Again, it is appreciated that the thickness of the adhesive 124 may vary from 0.002 inches according to specific requirements.
  • [0020]
    [0020]FIG. 6 shows an enlarged view of the pads 114 and 116 after compression. After compression, the retaining rings 114 a and 116 a are aligned and adjoined with each other. Therefore, the conductive paste 126 is encompassed within to form a eutectic bond between the substrates 100 and 102.
  • [0021]
    The technique of retaining ring interconnect can be applied between layers in a 3-D stacking approach. The retaining ring is used to greatly enhance the assembly process for achieving higher densities. The stacking approach enables the stacking of IC devices, one on top of the other, with vertical as well as horizontal interconnections. Each device or a plurality of devices is attached to a component carrier, also termed as a base. The I/0's of each component carrier are terminated in pads located around the perimeter thereof. A frame comprising matching perimeter pads with retaining rings and feed through holes connecting top and bottom pads is placed between component carrier layers. The bottom component carrier translates the stack to route the I/O's to the appropriate pattern. The layers (component carrier, frame, and the component carrier I/O) are then interconnected using the retaining ring technique.
  • [0022]
    [0022]FIG. 7 shows an example of the component carrier layer mentioned above. As shown in FIG. 7, an IC device 700 is attached on a component carrier 710. The component carrier 710 has a plurality of perimeter pads 712 formed around the IC device 700. As mentioned above, the I/O's are routed and terminated at the perimeter pads 712.
  • [0023]
    [0023]FIG. 8 shows a frame 800, of which a surface 801 is provided with a plurality of pads 812. Each of the pads 812 on the surface 801 is designed to match a respective one of the perimeter pads 712 on the component carrier 710. On the other surface 802 opposed to the surface 801, a plurality of pads 822 are formed. Each of the pads 822 is electrically connected to a corresponding one of the pads 812 on the surface 801 through a conductive via 820. As shown in FIG. 9, the frame 800 is engageable to the component carrier 710 such that the IC device 700 is accommodated in the opening 810 defined by the frame 800. When a ball grid array (BGA) device is used as the IC device 700, the electrical connections between the IC device 700 and the component carrier 710 are achieved by the ball grid array 702 and a pad array 720. Traces are configured to redirect the pad array 720 to the perimeter pads 712.
  • [0024]
    The IC device 700 carried by the component carrier 710 may include a BGA device, a TSOP (thin, small outline package) device, a flip chip device, a chip scale package (CSP), a microBGA (μBGA) device, or even a bare die. Alternatively, more than one of the above IC devices may be intermixed on the component carrier 700. When the frame 800 overfits the component carrier 710, the pads 812 and 712 are aligned and electrically connected to each other. Preferably, the retaining ring structure is applied on the pads 812 and 712 instead of using conventional solder. Further, retaining rings may also be applied on the pads 822 and 722 on distal surfaces of the frame 800 and the component carrier 710 for further connection or stacking.
  • [0025]
    Further, when panels, for example, the typical 4″6″ panels with multiple stack sites, are processed and stacked in a stacking fixture and cured with heat and pressure such as provided by a vacuum lamination press, the retaining rings can be applied. During the lamination cycle, the conductive paste forms a eutectic bond between the retaining rings. At this time the adhesive also reflows to create a tight bond from layer to layer. Once cured, the conductive paste will not reflow at temperature above 350 C.
  • [0026]
    The retaining ring interconnect replacing the solder bridge makes a finer pitch more possible and practical. A lower process temperature is required compared to the conventional solder process, therefore, less potential damage is caused to the IC components. Using the conductive paste for the eutectic bond, there is no post assembly cleaning required. Further, as it can be easily produced in panel format, producibility is increased.
  • [0027]
    Indeed, each of the features and embodiments described herein can be used by itself, or in combination with one or more of other features and embodiments. Thus, the invention is not limited by the illustrated embodiment but is to be defined by the following claims when read in the broadest reasonable manner to preserve the validity of the claims.
Classifications
U.S. Classification174/260
International ClassificationH01R12/04, H05K3/46, H05K3/32, H05K3/40
Cooperative ClassificationH01L2224/16057, H01L2224/13019, H05K3/321, H05K3/462, H05K2201/09745, H05K3/4069, H05K2201/096, H05K2201/10378, H01L2924/01322
European ClassificationH05K3/46B2D
Legal Events
DateCodeEventDescription
Sep 20, 2001ASAssignment
Owner name: DENSE-PAC MICROSYSTEMS, INC., CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:ROETERS, GLEN E.;MANTZ, FRANK E.;REEL/FRAME:012196/0277;SIGNING DATES FROM 20010913 TO 20010918
Jun 25, 2004ASAssignment
Owner name: STAKTEK GROUP L.P., TEXAS
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:DPAC TECHNOLOGIES CORP. (FORMERLY KNOWN AS DENSE-PAC MICROSYSTEMS, INC.);REEL/FRAME:015521/0622
Effective date: 20040609
Dec 4, 2006FPAYFee payment
Year of fee payment: 4
Jan 26, 2010ASAssignment
Owner name: ENTORIAN TECHNOLOGIES L.P., TEXAS
Free format text: CHANGE OF NAME;ASSIGNOR:STAKTEK GROUP, L.P.;REEL/FRAME:023848/0062
Effective date: 20080229
Jan 10, 2011REMIMaintenance fee reminder mailed
Jun 3, 2011LAPSLapse for failure to pay maintenance fees
Jul 26, 2011FPExpired due to failure to pay maintenance fee
Effective date: 20110603