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Publication numberUS20030054670 A1
Publication typeApplication
Application numberUS 09/954,858
Publication dateMar 20, 2003
Filing dateSep 17, 2001
Priority dateSep 17, 2001
Also published asUS6541370
Publication number09954858, 954858, US 2003/0054670 A1, US 2003/054670 A1, US 20030054670 A1, US 20030054670A1, US 2003054670 A1, US 2003054670A1, US-A1-20030054670, US-A1-2003054670, US2003/0054670A1, US2003/054670A1, US20030054670 A1, US20030054670A1, US2003054670 A1, US2003054670A1
InventorsMing-Tsong Wang, Shi-Wei Wang, Shin-Kai Chen
Original AssigneeTaiwan Semiconductor Manufacturing Co., Ltd.
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Composite microelectronic dielectric layer with inhibited crack susceptibility
US 20030054670 A1
Abstract
Within each of a pair of methods for forming each of a pair of microelectronic fabrications with reduced cracking within each of a pair of silicon oxide dielectric layers there is employed at least one stress reducing layer. The at least one stress reducing layer is formed of a silicon and nitrogen containing dielectric material, such as a silicon nitride dielectric material or a silicon oxynitride dielectric material.
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Claims(12)
What is claimed is:
1. A method for fabricating a microelectronic fabrication comprising:
providing a substrate;
forming upon the substrate a pair of horizontally spaced topographic features;
forming upon exposed portions of the substrate and the pair of horizontally spaced topographic features a conformal silicon oxide liner layer formed employing a chemical vapor deposition method selected from the group consisting of low pressure thermal chemical vapor deposition methods and plasma enhanced chemical vapor deposition methods;
forming over the conformal silicon oxide liner layer a gap filling silicon oxide layer formed employing a method selected from the group consisting of sub-atmospheric chemical vapor deposition methods, atmospheric pressure chemical vapor deposition methods and spin-on methods;
forming over the gap filling silicon oxide layer a capping silicon oxide layer formed employing a chemical vapor deposition method selected from the group consisting of low pressure thermal chemical vapor deposition methods and plasma enhanced chemical vapor deposition methods; and
forming at least either:
(1) interposed between the conformal silicon oxide liner layer and the gap filling silicon oxide layer;
(2) interposed between the gap filling silicon oxide layer and the capping silicon oxide layer; and
(3) upon the capping silicon oxide layer, at least one stress reducing layer, wherein the at least one stress reducing layer is formed of a silicon and nitrogen containing dielectric material.
2. The method of claim 1 wherein the substrate is employed within a microelectronic fabrication selected from the group consisting of integrated circuit microelectronic fabrications, ceramic substrate microelectronic fabrications, solar cell optoelectronic microelectronic fabrications, sensor image array optoelectronic microelectronic fabrications and display image array optoelectronic microelectronic fabrications.
3. The method of claim 1 wherein the pair of horizontally spaced topographic features is selected from the group consisting of conductor structures, semiconductor structures and dielectric structures.
4. The method of claim 1 wherein the silicon and nitrogen containing dielectric material is selected from the group consisting of silicon nitride dielectric materials and silicon oxynitride dielectric materials.
5. The method of claim 1 wherein the at least one stress reducing layer is formed employing a method selected from the group consisting of low pressure thermal chemical vapor deposition (LPCVD) methods and plasma enhanced chemical vapor deposition (PECVD) methods.
6. The method of claim 1 wherein the at least one stress reducing layer is formed to a thickness of from about 200 to about 1000 angstroms.
7. A method for fabricating a microelectronic fabrication comprising:
providing a substrate;
forming upon the substrate a pair of horizontally spaced topographic features;
forming upon exposed portions of the substrate and the pair of horizontally spaced topographic features a silicon oxide passivation layer formed employing a high density plasma chemical vapor deposition method; and
forming upon the silicon oxide passivation layer a stress reducing layer formed of a silicon and nitrogen containing dielectric material.
8. The method of claim 7 wherein the substrate is employed within a microelectronic fabrication selected from the group consisting of integrated circuit microelectronic fabrications, ceramic substrate microelectronic fabrications, solar cell optoelectronic microelectronic fabrications, sensor image array optoelectronic microelectronic fabrications and display image array optoelectronic microelectronic fabrications.
9. The method of claim 7 wherein the pair of horizontally spaced topographic features is selected from the group consisting of conductor structures, semiconductor structures and dielectric structures.
10. The method of claim 7 wherein the silicon and nitrogen containing dielectric material is selected from the group consisting of silicon nitride dielectric materials and silicon oxynitride dielectric materials.
11. The method of claim 7 wherein the at least one stress reducing layer is formed employing a method selected from the group consisting of low pressure thermal chemical vapor deposition (LPCVD) methods and plasma enhanced chemical vapor deposition (PECVD) methods.
12. The method of claim 7 wherein the at least one stress reducing layer is formed to a thickness of from about 200 to about 1000 angstroms.
Description
BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates generally to dielectric layers employed within microelectronic fabrications. More particularly, the present invention relates to crack inhibited dielectric layers employed within microelectronic fabrications.

[0003] 2. Description of the Related Art

[0004] Microelectronic fabrications are formed from microelectronic substrates over which are formed patterned microelectronic conductor layers which are separated by microelectronic dielectric layers.

[0005] As microelectronic fabrication integration levels have increased and patterned microelectronic conductor layer dimensions and separations have decreased, it has become increasingly difficult to fabricate within microelectronic fabrications microelectronic dielectric layers with enhanced integrity, and in particular enhanced physical integrity. Microelectronic dielectric layers with enhanced integrity are desirable in the art of microelectronic fabrication insofar as microelectronic dielectric layers with enhanced integrity typically provide microelectronic fabrications with enhanced performance and enhanced reliability.

[0006] It is thus desirable in the art of microelectronic fabrication to provide within microelectronic fabrications microelectronic dielectric layers with enhanced integrity.

[0007] It is towards the foregoing object that the present invention is directed.

[0008] Various methods have been disclosed in the art of microelectronic fabrication, for forming, with desirable properties, microelectronic dielectric layers within microelectronic fabrications.

[0009] Included among the methods, but not limited among the methods, are methods disclosed within: (1) Ravi et al., in U.S. Pat. No. 5,976,993 (a method for reducing intrinsic stress within a high density plasma chemical vapor deposition (HDP-CVD) deposited dielectric layer within a microelectronic fabrication by cycling within a high density plasma chemical vapor deposition (HDP-CVD) method when forming the high density plasma chemical vapor deposition (HDP-CVD) deposited dielectric layer a bias power ); and (2) Pangrle et al., in U.S. Pat. No. 6,171,947 (a method for inhibiting stress induced patterned conductor layer/dielectric layer voiding within a microelectronic fabrication by employing a silicon oxynitride liner layer formed upon a patterned conductor layer prior to forming thereupon a gap filling silicon oxide layer)

[0010] Desirable in the art of microelectronic fabrication are additional methods for forming within microelectronic fabrications microelectronic dielectric layers with enhanced integrity.

[0011] It is towards the foregoing object that the present invention is directed.

SUMMARY OF THE INVENTION

[0012] A first object of the present invention is to provide a method for forming a dielectric layer within a microelectronic fabrication.

[0013] A second object of the present invention is to provide a method in accord with the first object of the present invention, wherein the dielectric layer is formed with enhanced integrity.

[0014] A third object of the present invention is to provide a method in accord with the first object of the present invention and the second object of the present invention, wherein the method is readily commercially implemented.

[0015] In accord with the objects of the present invention, there is provided by the present invention a pair of methods for forming a pair of dielectric layers within a pair of microelectronic fabrications.

[0016] To practice a first of the methods of the present invention, there is first provided a substrate. There is then formed upon the substrate a pair of horizontally spaced topographic features. There is then formed upon exposed portions of the substrate and the pair of horizontally spaced topographic features a conformal silicon oxide liner layer formed employing a chemical vapor deposition (CVD) method selected from the group consisting of low pressure thermal chemical vapor deposition (LPCVD) methods and plasma enhanced chemical vapor deposition (PECVD) methods. There is also formed over the conformal silicon oxide liner layer a gap filling silicon oxide layer formed employing a method selected from the group consisting of sub-atmospheric chemical vapor deposition (SACVD) methods, atmospheric pressure chemical vapor deposition (APCVD) methods and spin-on methods. There is also formed over the gap filling silicon oxide layer a capping silicon oxide layer formed employing a chemical vapor deposition (CVD) method selected from the group consisting of low pressure thermal chemical vapor deposition (LPCVD) methods and plasma enhanced chemical vapor deposition (PECVD) methods. Finally, there is also formed at least either: (1) interposed between the conformal silicon oxide liner layer and the gap filling silicon oxide layer; (2) interposed between the gap filling silicon oxide layer and the capping silicon oxide layer; or (3) upon the capping silicon oxide layer, at least one stress reducing layer, wherein the at least one stress reducing layer is formed of a silicon and nitrogen containing dielectric material.

[0017] In accord with a second embodiment of the present invention, there is also first provided a substrate having formed thereupon a pair of horizontally spaced topographic features. However, within the second embodiment of the present invention there is formed upon exposed portions of the substrate and the pair of horizontally spaced topographic features a passivation silicon oxide layer formed employing a high density plasma chemical vapor deposition (HDP-CVD) method. Finally, within the second embodiment of the present invention, there is formed upon the passivation silicon oxide layer a stress reducing layer formed of a silicon and nitrogen containing dielectric material.

[0018] The present invention provides a pair of methods for forming a pair of dielectric layers within a pair of microelectronic fabrications, wherein the pair of dielectric layers is formed with enhanced integrity.

[0019] The present invention realizes the foregoing object by forming each of the pair of dielectric layers as composite dielectric layers which are otherwise formed of silicon oxide dielectric materials formed at least in part employing chemical vapor deposition (CVD) methods, but having laminated therein at least one stress reducing layer formed of a silicon and nitrogen containing dielectric material. In accord with the present invention, each of the pair of composite dielectric layers so formed exhibits reduced cracking and thus enhanced integrity, due to presence of the stress reducing layers.

[0020] The methods of the present invention are readily commercially implemented.

[0021] The present invention employs methods and materials as are generally conventional in the art of microelectronic fabrication, but employed within the context of specific structural limitations and specific materials limitations to provide the present invention. Since it is thus at least in part a series of structural limitations and materials limitations which provides at least in part the present invention, rather than the existence of methods and materials which provides the present invention, the methods of the present invention are readily commercially implemented.

BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The objects, features and advantages of the present invention are understood within the context of the Description of the Preferred Embodiments, as set forth below. The Description of the Preferred Embodiments is understood within the context of the accompanying drawings, which form a material part of this disclosure, wherein:

[0023]FIG. 1 and FIG. 2 show a pair of schematic cross-sectional diagrams directed towards a first preferred embodiment of the present invention.

[0024]FIG. 3 and FIG. 4 show a pair of schematic cross-sectional diagrams directed towards a second preferred embodiment of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0025] The present invention provides a pair of methods for forming a pair of dielectric layers within a pair of microelectronic fabrications, wherein the pair of dielectric layers is formed with enhanced integrity. The present invention realizes the foregoing object by forming each of the pair of dielectric layers as a composite dielectric layer, formed primarily of a silicon oxide dielectric material, but laminated with a stress reducing layer formed of a silicon and nitrogen containing dielectric material. Within the present invention, each of the pair of composite dielectric layers exhibits reduced cracking due to the presence of the stress reducing layer.

[0026] As is understood by a person skilled in the art, the preferred embodiments of the present invention provide particular value within the context of forming, with enhanced physical integrity as evidenced by reduced cracking, a dielectric layer interposed between a pair of horizontally spaced patterned conductor layers within a semiconductor integrated circuit microelectronic fabrication. However, the present invention may nonetheless also be employed for forming, with enhanced integrity as evidenced by reduced cracking, analogous dielectric layers within microelectronic fabrications selected from the group including but not limited to integrated circuit microelectronic fabrications, ceramic substrate microelectronic fabrications, solar cell optoelectronic microelectronic fabrications, sensor image array optoelectronic microelectronic fabrications and display image array optoelectronic microelectronic fabrications. Similarly, although the preferred embodiments of the present invention illustrate the present invention within the context of enhanced integrity of a dielectric layer formed interposed between a pair of horizontally spaced patterned conductor layers within a semiconductor integrated circuit microelectronic fabrication, the present invention may also be employed to realize an analogous result with respect within a microelectronic fabrication having formed therein a pair of horizontally spaced topographic features selected from the group including but not limited to conductor features (including gate electrodes), semiconductor features and dielectric features.

First Preferred Embodiment

[0027] Referring now to FIG. 1 and FIG. 2, there is shown a pair of schematic cross-sectional diagrams directed towards a microelectronic fabrication fabricated in accord with a first preferred embodiment of the present invention.

[0028] Shown in FIG. 1 is a schematic cross-sectional diagram illustrating a microelectronic fabrication comprising in a first instance a substrate 10 having formed thereupon a pair of patterned conductor stack layers 11 a and 11 b.

[0029] Within the preferred embodiment of the present invention with respect to the substrate 10, the substrate 10 may be a substrate employed within a microelectronic fabrication selected from the group including but not limited to integrated circuit microelectronic fabrications, ceramic substrate microelectronic fabrications, solar cell optoelectronic microelectronic fabrications, sensor image array optoelectronic microelectronic fabrications and display image array optoelectronic microelectronic fabrications.

[0030] Although not specifically illustrated within the schematic cross-sectional diagram of FIG. 1, the substrate 10 may consist of a substrate alone as employed within the microelectronic fabrication, or in an alternative, the substrate 10 may comprise a substrate as employed within the microelectronic fabrication, wherein the substrate has formed thereupon and/or thereover any of several additional microelectronic layers as are conventionally employed within the microelectronic fabrication within which is employed the substrate. Similarly with the substrate alone as employed within the microelectronic fabrication, such additional microelectronic layers may be formed from microelectronic materials selected from the group including but not limited to microelectronic conductor materials, microelectronic semiconductor materials and microelectronic dielectric materials.

[0031] In addition, and although also not specifically illustrated within the schematic cross-sectional diagram of FIG. 1, the substrate 10, typically and preferably, but not exclusively, when the substrate 10 consists of or comprises a semiconductor substrate as employed within a semiconductor integrated circuit microelectronic fabrication, has formed therein and/or thereupon microelectronic devices as are similarly also conventional within the microelectronic fabrication within which is employed the substrate 10. Such microelectronic devices may be selected from the group including but not limited to resistors, transistors, diodes and capacitors.

[0032] Within the preferred embodiment of the present invention with respect to the pair of patterned conductor stack layers 11 a and 11 b, the pair of conductor stack layers 11 a and 11 b is, as illustrated within the schematic cross-sectional diagram of FIG. 1, formed of a pair of patterned lower barrier layers 12 a and 12 b having formed aligned thereupon a pair of patterned conductor layers 14 a and 14 b having formed thereupon a pair of patterned upper barrier layers 16 a and 16 b.

[0033] Typically and preferably, the pair of patterned lower barrier layers 12 a and 12 b and the pair of patterned upper barrier layers 16 a and 16 b are formed of barrier materials as are conventional in the art of microelectronic fabrication, including but not limited titanium, tantalum and tungsten barrier materials, alloys thereof and nitrides thereof. Typically and preferably, each of the pair of patterned lower barrier layers 12 a and 12 b and the pair of patterned upper barrier layers 16 a and 16 b is formed to a thickness of from about 200 to about 2000 angstroms.

[0034] Typically and preferably, the pair of patterned conductor layers 14 a and 14 b is similarly also formed employing methods and materials as are conventional in the art of microelectronic fabrication, including but not limited to aluminum, aluminum alloy, copper and copper alloy conductor materials. Typically and preferably, each of the pair of patterned conductor layers 14 a and 14 b is formed to a thickness of from about 2000 to about 10000 angstroms.

[0035] There is also shown within the schematic cross-sectional diagram of FIG. 1 formed upon exposed portions of the substrate 10 and the pair of patterned conductor stack layers 11 a and 11 b a blanket tri-layer silicon oxide dielectric stack layer 17 comprising: (1) a blanket conformal silicon oxide liner layer 18 formed upon exposed portions of the substrate 10 and the pair of patterned conductor stack layers 11 a and 11 b; (2) a blanket gap filling silicon oxide layer 20 formed upon the blanket conformal silicon oxide liner layer 18; and (3) a blanket capping silicon oxide dielectric layer 22 formed upon the blanket gap filling silicon oxide dielectric layer 20.

[0036] Within the microelectronic fabrication whose schematic cross-sectional diagram is illustrated in FIG. 1, each of the blanket conformal silicon oxide liner layer 18 and the blanket capping silicon oxide layer 22 is formed employing a chemical vapor deposition (CVD) method selected from the group consisting low pressure thermal chemical vapor deposition (LPCVD) methods and plasma enhanced chemical vapor deposition (PECVD) methods. The foregoing two chemical vapor deposition (CVD) methods will typically and preferably employ a reactor chamber pressure of from about 2 to about 5 torr, along with a silicon source material such as but not limited to silane or tetraethylorthosilicate (TEOS), in conjunction with an appropriate oxidant. Typically and preferably, the blanket conformal silicon oxide liner layer 18 is formed to a thickness of from about 200 to about 800 angstroms and the blanket capping silicon oxide layer 22 is formed to a thickness of from about 1000 to about 4000 angstroms.

[0037] Similarly, within the microelectronic fabrication whose schematic cross-sectional diagram is illustrated in FIG. 1, the blanket gap filling silicon oxide layer 20 is formed employing a method selected from the group consisting of sub-atmospheric chemical vapor deposition (SACVD) methods, atmospheric pressure chemical vapor deposition (APCVD) methods and spin-on methods. The foregoing two chemical vapor deposition (CVD) methods employ reactor chamber pressures of at least about 450 torr, typically with an ozone oxidant and a tetraethylorthosilicate (TEOS) silicon source material, in order to provide gap filling characteristics. When formed employing spin-on materials, the blanket gap filling silicon oxide layer 20 may be formed of silicate precursor spin-on materials or organo-siloxane precursor spin-on materials.

[0038] Within the first preferred embodiment of the present invention as illustrated within the schematic cross-sectional diagram of FIG. 1, none of the layers within the blanket tri-layer silicon oxide stack layer 17 is formed of a silicon and nitrogen containing dielectric material, and in particular a silicon nitride or a silicon oxynitride dielectric material.

[0039] Finally, as is also illustrated within the schematic cross-sectional diagram of FIG. 1, and as an unfortunate consequence as a spacing between the pair of patterned conductor stack layers 11 a and 11 b is generally reduced to less than about 0.4 microns, there is shown a crack 24 which extends through the blanket capping silicon oxide layer 22 and into the blanket gap filling silicon oxide layer 20.

[0040] It is towards the reduction and elimination of such cracks that the present invention is directed.

[0041] In order to effectuate that result, the present invention provides for forming at least: (1) interposed between the blanket conformal silicon oxide liner layer 18 and the blanket gap filling silicon oxide layer 20; (2) interposed between the blanket gap filling silicon oxide layer 20 and the blanket capping silicon oxide layer 22; or (3) upon the blanket capping silicon oxide layer 22, a stress reducing layer. Within the present invention, the stress reducing layer is formed of a silicon and nitrogen containing dielectric material. Typically and preferably the silicon and nitrogen containing dielectric material is selected from the group consisting of silicon nitride dielectric materials and silicon oxynitride dielectric materials. Similarly, typically and preferably, the stress reducing layer is formed as a conformal layer (i.e., single thickness layer) formed employing a chemical vapor deposition (CVD) method selected from the group including but not limited to, but more preferably consisting of, low pressure thermal chemical vapor deposition (LPCVD) methods and plasma enhanced chemical vapor deposition (PECVD) methods. Typically and preferably the stress reducing layer is formed to a thickness of from about 200 to about 1000 angstroms.

[0042] Thus, there is illustrated in FIG. 2 a schematic cross-sectional diagram of a microelectronic fabrication in accord with the first preferred embodiment of the present invention. The microelectronic fabrication whose schematic cross-sectional diagram is illustrated in FIG. 2 derives directly from the microelectronic fabrication whose schematic cross-sectional diagram is illustrated in FIG. 1.

[0043] As is illustrated within the microelectronic fabrication whose schematic cross-sectional diagram is illustrated in FIG. 2, there is formed at least one of: (1) a first stress reducing layer 26 a interposed between the blanket conformal silicon oxide liner layer 18 and the blanket gap filling silicon oxide layer 20; (2) a second stress reducing layer 26 b interposed between the blanket gap filling silicon oxide layer 20 and the blanket capping silicon oxide layer 22; and (3) a third stress reducing layer 26 c formed upon the blanket capping silicon oxide layer 22.

[0044] In accord with the present invention, by employing at least one, or alternatively two or three, of the foregoing three stress reducing layers within the positions designated within the schematic cross-sectional diagram of FIG. 2, there is reduced or eliminated crack formation within the microelectronic fabrication whose schematic cross-sectional diagram is illustrated in FIG. 2, in comparison with the microelectronic fabrication whose schematic cross-sectional diagram is illustrated in FIG. 1.

[0045] As is further understood by a person skilled in the art, the first stress reducing layer 26 a or the third stress reducing layer 26 c may be formed in-situ upon the corresponding blanket conformal silicon oxide liner layer 18 or the corresponding blanket capping silicon oxide layer 22, within a continuous chemical vapor deposition (CVD) method, incident to initiating a nitrogen containing source material flow rate, as an adjunct with or in the alternative of an oxidant source material flow rate, further in conjunction with a silicon source material flow rate. The nitrogen containing source material may be selected from the group consisting of nitrogen and ammonia.

Second Preferred Embodiment

[0046] Referring now to FIG. 3 and FIG. 4, there is shown a pair of schematic cross-sectional diagrams directed towards a second preferred embodiment of the present invention.

[0047] Shown within the schematic cross-sectional diagram of FIG. 3, in a first instance, is a microelectronic fabrication analogous or equivalent to the microelectronic fabrication whose schematic cross-sectional diagram is illustrated in FIG. 1 and FIG. 2 with respect to the substrate 10 having formed thereupon the pair of patterned conductor stack layers 11 a and 11 b. However, within the second preferred embodiment of the present invention, rather than having formed upon the substrate 10 and the pair of patterned metal stack layers 11 a and 11 b the tri-layer dielectric stack layer 17 comprising the blanket conformal silicon oxide liner layer 18, having formed thereupon the blanket gap filling silicon oxide layer 20 in turn having formed thereupon the blanket capping silicon oxide layer 22 as illustrated within the schematic cross-sectional diagram of FIG. 1, there is instead formed a single blanket silicon oxide dielectric layer 28 as illustrated within the schematic cross-sectional diagram of FIG. 3. Within the second preferred embodiment of the present invention, the single blanket silicon oxide dielectric layer is a blanket passivation silicon oxide layer 28 formed employing a high density plasma chemical vapor deposition (HDP-CVD) method. As is understood by a person skilled in the art, and in accord with the schematic cross-sectional diagram of FIG. 3 in comparison with the schematic cross-sectional diagram of FIG. 1, the blanket passivation silicon oxide layer 28 is formed with gap filling characteristics rather than conformal (i.e., single thickness layer) characteristics.

[0048] As is understood by a person skilled in the art, a high density plasma chemical vapor deposition (HDP-CVD) method is a plasma enhanced chemical vapor deposition (PECVD) method which is further enhanced with a bias sputtering. Such methods are disclosed in greater detail within Ravi et al., in U.S. Pat. No. 5,976,993, as cited within the Description of the Related Art, all of which related art is incorporated herein fully by reference. In accord with the Description of the Related Art, and as is further understood by a person skilled in the art, such high density plasma chemical vapor deposition (HDP-CVD) methods provide particularly dense silicon oxide or low k dielectric layers, but, as illustrated within the schematic cross-sectional diagram of FIG. 3, they similarly also suffer from cracking, as illustrated by the crack 30 within blanket passivation silicon oxide layer 28 within the schematic cross-sectional diagram of FIG. 3.

[0049] Thus, within the context of the schematic cross-sectional diagram of FIG. 3, the second preferred embodiment of the present invention also provides a method for reducing or eliminating crack formation within a silicon oxide dielectric layer within a microelectronic fabrication. However, although the nature and location of the crack 30 are analogous with the nature and location of the crack 24 within the first preferred embodiment of the present invention, the physical structure of the silicon oxide layer is different insofar as the silicon oxide layer is formed employing a different method.

[0050] Analogously with the first preferred embodiment of the present invention, the second preferred embodiment of the present invention also employs for reducing or eliminating cracks within a silicon oxide dielectric layer a stress reducing layer of composition and thickness analogous or equivalent to the composition and thicknesses of the stress reducing layers 26 a, 26 b and 26 c as illustrated within the schematic cross-sectional diagram of FIG. 2. However, within the second preferred embodiment of the present invention as is illustrated within the context of the schematic cross-sectional diagram of FIG. 4, a stress reducing layer 26 d is formed upon the high density plasma chemical vapor deposition (HDP-CVD) deposited blanket passivation silicon oxide or low k layer 28.

[0051] As is further understood by a person skilled in the art, the blanket stress reducing layer 26 d as illustrated within the schematic cross-sectional diagram of FIG. 4 may be formed in-situ upon the blanket passivation dielectric layer 28 while employing chemical vapor deposition methods including but not limited to low pressure thermal chemical vapor deposition (LPCVD) methods, plasma enhanced chemical vapor deposition (PECVD) methods and high density plasma chemical vapor deposition (HDP-CVD) methods, by appropriate introduction of a nitrogen source material flow.

[0052] As is understood by a person skilled in the art, the preferred embodiments of the present invention are illustrative of the present invention rather than limiting of the present invention. Revisions and modifications may be made to methods, materials, structures and dimensions through which is provided a microelectronic fabrication in accord with the preferred embodiments of the present invention, while still providing a method for fabricating a microelectronic fabrication in accord with the present invention, further in accord with the accompanying claims.

Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US7141483 *Jan 14, 2004Nov 28, 2006Applied Materials, Inc.Nitrous oxide anneal of TEOS/ozone CVD for improved gapfill
US8669619 *Nov 4, 2010Mar 11, 2014Mediatek Inc.Semiconductor structure with multi-layer contact etch stop layer structure
US9018093 *Jan 25, 2013Apr 28, 2015Asm Ip Holding B.V.Method for forming layer constituted by repeated stacked layers
US20120112289 *Nov 4, 2010May 10, 2012Tien-Chang ChangSemiconductor structure with multi-layer contact etch stop layer structure
Classifications
U.S. Classification438/787, 438/791, 257/E21.576, 257/E21.293, 257/E21.268
International ClassificationH01L21/318, H01L21/314, H01L21/768, H01L23/532
Cooperative ClassificationH01L21/76837, H01L21/76829, H01L21/3144, H01L23/53295, H01L21/76834, H01L21/76832, H01L21/3185
European ClassificationH01L21/768B10M, H01L21/768B14, H01L21/768B10, H01L21/768B10S, H01L23/532N4
Legal Events
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Sep 3, 2014FPAYFee payment
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Sep 17, 2001ASAssignment
Owner name: TAIWAN SEMICONDUCTOR MANUFACTURING CO. LTD., TAIWA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:WANG, MING-TSONG;WANG, SHI-WEI;CHEN, SHIN-KAI;REEL/FRAME:012184/0542
Effective date: 20010718
Owner name: TAIWAN SEMICONDUCTOR MANUFACTURING CO. LTD. SCIENC
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:WANG, MING-TSONG /AR;REEL/FRAME:012184/0542
Owner name: TAIWAN SEMICONDUCTOR MANUFACTURING CO. LTD. SCIENC
Owner name: TAIWAN SEMICONDUCTOR MANUFACTURING CO. LTD. SCIENC
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:WANG, MING-TSONG /AR;REEL/FRAME:012184/0542
Effective date: 20010718
Owner name: TAIWAN SEMICONDUCTOR MANUFACTURING CO. LTD. SCIENC
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:WANG, MING-TSONG;WANG, SHI-WEI;CHEN, SHIN-KAI;REEL/FRAME:012184/0542
Effective date: 20010718