Search Images Maps Play YouTube News Gmail Drive More »
Sign in
Screen reader users: click this link for accessible mode. Accessible mode has the same essential features but works better with your reader.

Patents

  1. Advanced Patent Search
Publication numberUS20030061592 A1
Publication typeApplication
Application numberUS 10/194,703
Publication dateMar 27, 2003
Filing dateJul 12, 2002
Priority dateAug 2, 2000
Also published asUS6523162
Publication number10194703, 194703, US 2003/0061592 A1, US 2003/061592 A1, US 20030061592 A1, US 20030061592A1, US 2003061592 A1, US 2003061592A1, US-A1-20030061592, US-A1-2003061592, US2003/0061592A1, US2003/061592A1, US20030061592 A1, US20030061592A1, US2003061592 A1, US2003061592A1
InventorsDeepak Agrawal, Fang-Cheng Chang, Hyungjip Kim, Yao-Ting Wang, Myunghoon Yoon
Original AssigneeNumerical Technologies, Inc.
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
General purpose shape-based layout processing scheme for IC layout modifications
US 20030061592 A1
Abstract
Layout processing can be applied to an integrated circuit (IC) layout using a shape-based system. A shape can be defined by a set of associated edges in a specified configuration. A catalog of shapes is defined and layout processing actions are associated with the various shapes. Each layout processing action applies a specified layout modification to its associated shape. A shape-based rule system advantageously enables efficient formulation and precise application of layout modifications. Shapes/actions can be provided as defaults, can be retrieved from a remote source, or can be defined by the user. The layout processing actions can be compiled in a bias table.
Images(16)
Previous page
Next page
Claims(12)
We claim:
1. A method for creating a photomask layout by applying optical proximity correction (OPC) to an integrated circuit (IC) layout, the method comprising the steps of:
defining a first OPC action, the first OPC action being associated with a first shape, the first shape comprising a plurality of coupled edges;
scanning the IC layout for a first set of features matching the first shape; and
applying the first OPC action to the first set of features to generate a first portion of the photomask layout.
2. The method of claim 1, further comprising the steps of:
defining a second OPC action, the second OPC action being associated with a second shape, the second shape comprising a plurality of coupled edges distinguishable from the first shape;
scanning the IC layout for a second set of features matching the second shape; and
applying the second OPC action to the second set of features to generate a second portion of the photomask layout.
3. The method of claim 1, further comprising the steps of:
defining a second OPC action, the second OPC action being associated with a single edge;
scanning the IC layout for a second set of features matching the single edge, the third set of features being distinct from the first set of features;
applying the second OPC rule to the second set of features to generate a second portion of the photomask layout; and
combining the first and second portions of the IC layout with the portion of the IC layout not included in the first and second sets of features.
4. The method of claim 2, wherein the step of applying the first OPC action is performed before the step of applying the second OPC action, the first shape having a greater complexity than the second shape, the second set of features being selected from the portions of the IC layout not including the first set of features.
5. The method of claim 2, wherein the step of applying the first OPC action is performed before the step of applying the second OPC action, the second shape having a greater complexity than the first shape.
6. A system for applying optical proximity correction (OPC) to an integrated circuit (IC) layout, the system comprising:
a catalog of shapes, each of the shapes comprising at least two edges coupled in a prespecified manner; and
means for comparing the catalog of shapes with the IC layout.
7. The system of claim 6, further comprising:
a library of actions, wherein each of the actions is associated with one of the shapes; and
means for applying the actions to the IC layout.
8. The system of claim 7, wherein at least some of the actions controls application of a layout modification.
9. The system of claim 7, further comprising means for resolving shape conflicts.
10. The system of claim 7, further comprising means for resolving action conflicts.
11. A photomask created from an integrated circuit (IC) layout, wherein the IC layout comprises a plurality of layout features, the photomask comprising:
a substantially transparent substrate; and
a substantially opaque layer forming a photomask pattern on the substantially transparent substrate,
wherein the photomask pattern includes at least one layout modification formed by an optical proximity correction (OPC) action associated with a shape matching one of the plurality of layout features, the shape comprising at least two edges coupled in a specified manner.
12. An integrated circuit (IC) created using a photomask, the photomask comprising at least one layout modification formed using an optical proximity correction (OPC) action associated with a shape, the shape comprising at least two edges coupled in a specified manner.
Description
    RELATED APPLICATIONS
  • [0001]
    The present application is a divisional of commonly owned co-pending U.S. patent application Ser. No. 09/632,080, “GENERAL PURPOSE SHAPE-BASED LAYOUT PROCESSING SCHEME FOR IC LAYOUT MODIFICATIONS” filed Aug. 2, 2000 by Deepak Agrawal, Fang-Cheng Chang, Hyungjip Kim, Yao-Ting Wang and Myunghoon Yoon.
  • FIELD OF THE INVENTION
  • [0002]
    The invention relates to the field of photolithography, and more particularly to a system for applying modifications to an IC layout.
  • BACKGROUND OF THE INVENTION
  • [0003]
    Photomasks are used in the production of integrated circuits (ICs) to transfer a circuit layout (“IC layout”) onto a receiving substrate, such as a silicon wafer. A photomask is typically a glass plate covered by a thin chrome layer, in which a portion of the IC layout is etched. A source of light or radiation is used to expose this photomask pattern (“photomask layout”) onto a layer of photosensitive resist on the surface of the wafer. The top surface of the wafer is then chemically etched away in the areas not covered by the photoresist, thereby completing the transfer of the original IC layout onto the wafer. This transference process is known as photolithography.
  • [0004]
    Photolithography is a critical step in the IC manufacturing process. The accuracy of the pattern formed on the wafer (“printed image”) significantly affects both process yield and IC performance. However, reliably resolving modern IC geometries in the 0.25-μm range and smaller using existing photolithography equipment is difficult. At such reduced feature sizes, optical distortion impedes exact transfer of the photomask pattern onto the wafer.
  • [0005]
    To counteract any unwanted deviations, a technique known as optical proximity correction (OPC) has been developed. OPC involves modification of the original IC layout to compensate for distortions introduced by the exposure process. The modification involves changing the dimensions of affected features or incorporating corrective features into the photomask pattern. For example, diffractive effects around small features in a photomask pattern can cause corner rounding in the printed image. FIG. 1a shows a sharp corner 100 that would typically be present in an original photomask pattern, and a rounded corner 110 that would appear in the actual printed image without OPC. FIG. 1b shows a corner 120 in a photomask pattern that has been modified using OPC to include an extra feature called a serif. The serif is sized such that the printed image corner 130 produced by photomask corner 120 has the desired form. Other OPC features (hammerheads, scattering bars, assist features, etc.) are well known in the art. These modifications to the original IC layout may sometimes be referred to generically as “biases” or “bias features”.
  • [0006]
    There are two methods for determining the appropriate biases to add to an IC layout: model-based OPC and rule-based OPC. Model-based OPC applies corrections to the IC layout and uses models of the photolithography processes to determine the most effective biases. By essentially simulating an actual photolithography step and converging on a solution, model-based OPC can provide a thorough and detailed set of biases to apply to the original layout. However, this technique is extremely computation-intensive due to the iterative nature of the process. Also, the accuracy of the final output is only as good as the models used in the calculations.
  • [0007]
    In contrast, rule-based OPC applies a set of geometry-based rules to the original IC layout. The rules are specified by the user, and define the biases to be incorporated in the photomask layout. Conventional rule-based OPC systems base the application of OPC biases on the geometries of edges within the original IC layout.
  • [0008]
    Although the complex patterns of an IC layout may seem to be made up of fine lines, even the thinnest of lines are actually 2-dimensional elements. As such, they can be represented by a series of contiguous edges, joined to other edges at distinct vertices. Conventional rule-based OPC systems evaluate each edge of the original IC layout and apply biases to those edges according to pre-specified rules. The rules are typically based upon the length of an edge and its spacing from other edges.
  • [0009]
    [0009]FIG. 2a shows a layout feature 200 a, sometimes referred to as a “finger”, which is common in IC layouts. OPC modifications must often be applied to finger features to create photomask layouts that properly transfer the original feature during photolithography. Feature 200 a comprises edges 221, 222, 223, 224, and 225. The directions of edges 221-225 are as shown, and the inner sides of edges 221-225 are on the left.
  • [0010]
    [0010]FIG. 2b shows a printed image 200 b that represents the printed image produced by a photolithography step using unmodified feature 200 a in a photomask pattern. Printed image 200 b shows undesirable corner rounding and shortening in region 230. To compensate for such distortion, various OPC modifications can be incorporated into the photomask layout, depending on the specific dimensions of feature 200 a and its relationship to the rest of the IC layout. FIG. 2c shows a modified feature 200 c, which includes a hammerhead 240 to correct for the distortions shown in FIG. 2b. FIG. 2d shows an alternative modified feature 200 d, which includes serifs 250 as a corrective mechanism.
  • [0011]
    Determination of the appropriate OPC correction is made through the use of a bias table. Created prior to performing the OPC operation, the bias table defines the rules to be applied, each of which is a function of the edge properties. The bias table is typically structured as a look-up table, such as shown in Table 1.
    TABLE 1
    Edge-Based Bias Table
    L d
    (μm) (μm) BIAS
    <0.25 >1.5 Hammerhead
    0.5 ± .05 1.0 ± 0.5 Serifs
  • [0012]
    Table 1 includes sample values for rules that would be applied to edge 223 of FIG. 2a to create OPC features 240 and 250, shown in FIGS. 2c and 2 d, respectively. In Table 1, “L” represents the length of edge 223, and d represents the minimum spacing between edges (i.e., the distance between edge 223 and edges 221 and 225). As indicated by the values in Table 1, if feature 200 a is tall and thin (i.e., less than 0.25 μm wide and greater than 1.5 μm tall), then a hammerhead feature will be applied. However, if feature 200 a is more squat (i.e., 0.5 μm wide and 1.0 μm tall), serifs will be added. Of course, the bias table would contain additional sizing and placement information for the various biases.
  • [0013]
    Because a simple lookup table can be used, rule-based OPC is much more computationally efficient than model-based OPC. However, the current edge-based systems may be too limited to effectively provide corrections for complex layouts. For example, it may be desirable to apply (or not apply) different OPC modifications to edges that have similar properties. FIG. 2e shows a feature 200 e that includes an edge 263. Edge 263 may have the same length and spacing as edge 223 in FIG. 2a, but it may be desirable to apply OPC correction to only one of the two features. For example, feature 200 a may be a non-critical feature that can tolerate substantial distortion, while feature 200 e must be accurately transferred for proper IC function. If feature 200 a was prevalent throughout the IC layout, it would be preferable to avoid complicating the final photomask layout by adding unnecessary OPC modifications. However, an edge-based system using a single edge is not able to readily make a distinction between edges 223 and 263, and therefore would not be able to apply different OPC modifications to features 200 a and 200 e.
  • [0014]
    Accordingly, it would be desirable to provide a system that enables greater flexibility and control in applying layout modifications.
  • SUMMARY OF THE INVENTION
  • [0015]
    Embodiments of the invention provide a system for applying layout processing to an IC layout (a portion of the layout or the entire layout) using a shape-based identification system. A shape can be defined as a set of associated edges. Therefore, a shape can provide much greater specificity than a single edge in identifying layout features of interest. A catalog of shapes can be defined and layout processing actions can be formulated based on the properties of the various shapes. Shapes can include various contiguous edge profiles, such as fingers, hammerheads, diamond hammerheads, fuzzy hammerheads, and tombstones, among others. Shapes can also include non-contiguous edge combinations, edges from multiple layers of an IC layout, and edges with specific properties. Properties inherent in a particular edge can include length, inner color, and outer color, among others. Other properties associated with an edge can include spacing, beginning angle, and ending angle, among others.
  • [0016]
    While length and spacing are relatively self-explanatory, other edge properties such as inner/outer color and beginning/ending angle cannot be easily defined without understanding the concept of direction. Direction is a convention used to define the inner and outer sides of an edge. Because all edges are part of a closed form, one side of the edge will always be within the form (inner side), while the other side will always be outside the form (outer side). Therefore, direction can be defined by stating that when travelling from the beginning to the end of the edge, the inner side will always be to the left. Of course, the inner side could just as well be defined to be always to the right. The closed nature of the forms also means that each edge is joined to another edge at its beginning and its end. These junctions are defined as vertices, or corners. Each vertex represents a meeting of two edges at a specific angle. The beginning angle is the angle between the inner sides of the edges meeting at the vertex at the beginning of the edge. Similarly, the ending angle is the angle between the inner sides of the edges meeting at the vertex at the end of the edge. Finally, color is simply another convention used to identify the nature of the shape on the inner or outer side of the edge. Colors can be specified for various device or interconnect components, to enable more appropriate OPC rule application (e.g., edges forming a gate may be blue, while edges forming a diffusion region may be red).
  • [0017]
    The library of layout processing actions associated with the shapes can be rule-based, model-based, or can provide any other response a user would like implemented (i.e., “layout processing” can include OPC, phase shift mask (PSM), design rule checking (DRC), “fracturing” of layout features for e-beam mask making machines, etc.). Specific features can be much more simply, efficiently, and flexibly identified by a single multi-edge structure than by a single edge with multiple relational variables. Therefore, a shape-based feature identification system advantageously enables efficient application of layout processing actions having a high degree of specificity.
  • [0018]
    In some embodiments of the invention, the library of layout processing actions can be compiled in a bias table in an accessible format, such as a look up table. The IC layout is scanned, and whenever a shape match is detected, the associated action(s) are applied to the matching portion of the IC layout to form the corrected photomask layout. This action application process can be performed serially (i.e., after each match, the corresponding action is performed) in batch mode (i.e., all shapes are matched, after which all actions are applied), or in any desired combination of the two.
  • [0019]
    The shape matching, or “scanning”, operation can be performed in any number of sequences. In an embodiment of the invention, the scanning operation can be performed in order of decreasing shape complexity, where no feature in the IC layout can be modified more than once. In another embodiment of the invention, scanning can be performed in order of increasing complexity, where the most complex shape matching/layout modification is performed last. In an alternative embodiment of the invention, the order of scanning can be set by the user as desired.
  • [0020]
    According to an aspect of the invention, resolution logic may be provided to resolve shape and action conflicts. In an embodiment of the invention, the resolution logic comprises a first-shape/action-controls methodology, which can be implemented through an edge-marking technique. According to another aspect of the invention, the resolution logic comprises a set of resolution rules that mandate a desired outcome when any conflict arises.
  • [0021]
    According to an aspect of the invention, the catalog of shapes and the library of layout processing actions may be provided by the system as a default. In another embodiment of the invention, the library of shape-based rules can be modified in part or created in whole by the user. According to another aspect of the invention, the shapes and actions may be received from a remote source such as a remote server.
  • [0022]
    In an embodiment of the invention, the bias table can also include single-edge “filler shapes” that provide default layout modification for portions of the IC layout not covered by the multi-edge shapes. In another embodiment of the invention, the bias table can include both rule-based OPC actions and model-based OPC actions.
  • [0023]
    The invention will be more fully understood in view of the following description and drawings.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • [0024]
    [0024]FIG. 1a illustrates a portion of a photomask pattern and the resulting printed image without OPC;
  • [0025]
    [0025]FIG. 1b illustrates a portion of a photomask pattern with OPC and the resulting printed image;
  • [0026]
    [0026]FIG. 2a illustrates an IC layout feature, showing edge directions and vertices;
  • [0027]
    [0027]FIG. 2b illustrates a printed image of the IC layout feature of FIG. 2a without OPC;
  • [0028]
    [0028]FIG. 2c illustrates a photomask layout feature of the IC layout feature of FIG. 2a after OPC modification;
  • [0029]
    [0029]FIG. 2d illustrates a photomask layout feature of the IC layout feature of FIG. 2a after an alternative OPC modification;
  • [0030]
    [0030]FIG. 2e illustrates an IC layout feature similar to the IC layout feature of FIG. 2a;
  • [0031]
    [0031]FIG. 3a illustrates a portion of an IC layout including two distinct features;
  • [0032]
    [0032]FIG. 3b illustrates a portion of a photomask layout of the IC layout of FIG. 3a after selective OPC application;
  • [0033]
    [0033]FIGS. 4a, 4 b, and 4 c illustrate sample shapes in a shape-based rule library of the invention;
  • [0034]
    [0034]FIGS. 5a, 5 b, and 5 c illustrate sample IC layout features including prior OPC modifications;
  • [0035]
    [0035]FIG. 5d illustrates a desired mask layout feature to be created from the features in FIGS. 5a, 5 b, and 5 c;
  • [0036]
    [0036]FIG. 6a illustrates an example of a shape comprising non-contiguous edges;
  • [0037]
    [0037]FIG. 6b illustrates an example of multi-layer IC layout features;
  • [0038]
    [0038]FIG. 6c illustrates an example of a shape-based modification for PSM;
  • [0039]
    [0039]FIG. 6d illustrates an example of a branching IC layout feature;
  • [0040]
    [0040]FIG. 6e illustrates an example of nesting IC layout features;
  • [0041]
    [0041]FIGS. 7a-7 c illustrate IC layout features that differ from each other only in certain regions;
  • [0042]
    [0042]FIG. 7d illustrates a shape having an indeterminate section that provides wildcard functionality;
  • [0043]
    [0043]FIG. 8 shows a flow diagram of a basic shape match/action application process;
  • [0044]
    [0044]FIGS. 9a and 9 b illustrate sample shapes and their associated actions;
  • [0045]
    [0045]FIG. 9c illustrates a shape and action conflict;
  • [0046]
    [0046]FIG. 10a illustrates a schematic diagram of a shape-based OPC system;
  • [0047]
    [0047]FIG. 10b illustrates a schematic diagram of an OPC engine;
  • [0048]
    [0048]FIG. 11 illustrates an embodiment of a shape-based OPC system including access to remote action and shape databases; and
  • [0049]
    [0049]FIG. 12 shows a sample graphical user interface for defining shapes and actions.
  • DETAILED DESCRIPTION
  • [0050]
    An embodiment of the invention provides a system and method for applying layout processing to an IC layout using a shape-based approach. The shape-based approach advantageously enables accurate and efficient application of layout modifications.
  • [0051]
    [0051]FIG. 3a shows a sample IC layout element 300 a from a larger IC layout (not shown). The outline of element 300 a has been selected for explanatory purposes only. The invention may be applied to any configuration of edges in an IC layout. Element 300 a comprises a series of contiguous edges 321-334. Element 300 a includes a feature 320 a, comprising edges 323-325, and a feature 340 a, comprising edges 328-332. Edges 329-331 in feature 340 a form a grouping substantially similar in size and configuration to feature 320 a. In a conventional rule-based OPC system, the same biases would probably be applied to both features 320 a and 330 a. This would be problematic if different biases were desired for the two features. In contrast, a shape-based OPC system in accordance with an embodiment of the invention could apply different bias features to the photomask layout for features 320 a and 340 a.
  • [0052]
    [0052]FIG. 3b shows an example of a photomask layout element 300 b that could correspond to IC layout element 300 a shown in FIG. 3a. Photomask layout element 300 b includes features 320 b and 340 b that correspond to features 320 a and 340 a, respectively, in FIG. 3a. As shown in FIG. 3b, feature 320 b includes no OPC modifications, but feature 340 b includes a bias feature 350 (hammerhead). As described previously, such differentiation may be desirable depending on the requirements of the final printed layout. The invention enables this type of discrimination between IC layout features by employing a “shape-based” rule set to create the final photomask layout.
  • [0053]
    Shape Definition
  • [0054]
    In accordance with embodiments of the invention, a catalog of “shapes” can be established, based on groupings of associated edges. Each shape represents a type of feature (or range of features) that may be present in an IC layout. Each individual shape within the catalog can be defined by the properties associated with its grouping of edges. Table 2 lists a number of sample properties in accordance with an embodiment of the invention. The listing in Table 2 is intended to be explanatory rather than comprehensive. Other properties will become readily apparent to those of ordinary skill in the art.
    TABLE 2
    Partial Listing of Shape Properties
    Spacing Min. Spacing Length
    Inner Color Outer Color Height
    Width Neighbor Width Min. Width
    Inner Distance Min. Inner Distance Continuity
    Outer Distance Min. Outer Distance Min. Continuity
    Radial Spacing Min. Radial Spacing Angle
  • [0055]
    [0055]FIGS. 4a-4 c provide examples of basic shapes according to aspects of the invention. FIG. 4a shows a shape 410 comprising an edge E411 and an edge E412 forming a corner at a vertex V413. FIG. 4b shows a shape 420 comprising an edge E421 joined at a vertex V424 to an edge E422, which in turn is joined at a vertex V425 to an edge E423. Finally, FIG. 4c shows a shape 430 that comprises contiguous edges E431-E435, which are joined at vertices V436-V439, respectively.
  • [0056]
    Although geometrically simple, shapes 410, 420, and 430 can present problems for conventional OPC systems. Edge-based systems can have difficulty differentiating edges E412, E422, and E433 in FIGS. 4a, 4 b, and 4 c, respectively, since the edges “look” similar in each configuration. In contrast, the shape-based approach of the invention allows each different implementation to be selected without confusion.
  • [0057]
    In addition to enabling more effective differentiation between simple yet similar features, a shape-based approach in accordance with an aspect of the invention also enables efficient identification of complex features. For example, an IC layout may have existing (inadequate) OPC modifications that can be replaced with more accurate/appropriate corrections. IC layout features 510 (including a hammerhead bias feature 511), 520 (including a “fuzzy hammerhead” bias feature 521), and 530 (including a “diamond hammerhead” bias feature 531), shown in FIGS. 5a, 5 b, and 5 c, respectively, could represent unsuccessful OPC modifications to a finger feature. A photomask feature 540 having a hammerhead feature 541 shown in FIG. 5d might represent the desired configuration after proper OPC modification. If the original IC layout is no longer available, it would be desirable to perform OPC on the existing (modified) feature. A conventional edge-based OPC system would have difficulty identifying features 510, 520, or 530 as having been previously modified, and so might try to apply corrections on top of original bias features 511, 521, and 531, respectively, rather than replacing them with hammerhead feature 541. In contrast, a shape-based system in accordance with the invention could define a shape having the same configuration as feature 510, 520, or 530, thereby enabling straightforward detection of the prior OPC modifications.
  • [0058]
    According to another aspect of the invention, a shape may include non-contiguous edges. For example, FIG. 6a shows a shape 600 comprising edges E01-E09. Edges E01-E05 are contiguous, forming a “tombstone” feature that is physically disconnected from contiguous edges E06-E09. The use of only contiguous edges E01-E05 to define a shape, would require the formulation of additional rules to detect the presence of a feature like that formed by edges E06-E09 within the shape. In addition to the difficulties associated with this rule generation, the additional rules would also consume greater processing resources, since each feature matching a shape formed by edges E01-E05 would have to be checked for the presence of an interior feature. These problems could be avoided through the use of shape 600, which already includes the proper interior elements, thereby enabling direct identification of only the desired features.
  • [0059]
    According to another aspect of the invention, a shape may include edges from different layers of an IC layout, where each layer represents a different process step in the manufacture of the IC. FIG. 6b shows IC layout features 610, 620, and 630, which are part of a single layer in a larger IC layout (not shown). Feature 610 comprises contiguous edges E11, E12, and E13, feature 620 comprises contiguous edges E21, E22, and E23, and feature 630 comprises contiguous edges E31, E32, and E33. Features 610, 620, and 630 are all similarly sized. However, only feature 610 is positioned over a feature L2, which is part of a different layer (not shown) of the IC layout.
  • [0060]
    Feature L2 might, for example, represent a diffusion region, thereby indicating that feature 610 is to be used to form a transistor gate. As a critical device component, the printed image corresponding to feature 610 probably demands much greater accuracy than the printed images corresponding to features 620 and 630. Therefore, a shape may be defined that includes edges E11-E13 of feature 610, and also includes edges (or all) of feature L2. By defining a shape in this manner, critical features such as feature 610 can be readily distinguished from less critical features such as features 620 and 630.
  • [0061]
    [0061]FIG. 6c shows a layout transistor feature 650 comprising a source region 651(a), a drain region 651(b), a gate region 652, and an interconnect region 653. Source region 651(a) comprises edges 654-659. PSM techniques may be used to provide accurate resolution of transistor feature 650. For example, by assigning different phases to regions 651(a) and 651(b), the accuracy of gate region 652 can be enhanced. However, an OPC feature such as a gate serif 660 may be required to maintain the accuracy of region 651(a) where it is not bounded by region 651(b). By defining a shape that includes edges 656-658, gate serifs can be added to all IC layout features similar to region 651(a).
  • [0062]
    [0062]FIG. 6d shows a branching shape 660 comprising edges 661-673 comprising multiple extremities. This type of branching arrangement would be difficult to identify using conventional edge-based identification, due to the angular relationships of the edges and the multiple arms. However, by defining the entire collection of edges as a single shape, matching IC layout features can be readily identified. IC layout features with any number of branches can be identified in a similar fashion.
  • [0063]
    [0063]FIG. 6e shows a shape 680 comprising contiguous edges 681-683 and contiguous edges 684-688. Edges 681-683 form a finger feature that is “nested” in a pocket formation created by edges 684-688. Edges 681-683 and edges 684-688 may be portions of two different features, but by defining a shape using edges 681-688, all portions of an IC layout matching the configuration shown in FIG. 6e can be quickly identified.
  • [0064]
    [0064]FIGS. 7a, 7 b, and 7 c show layout features 710, 720, and 730, respectively. Features 710, 720, and 730 significantly differ only in indicated regions R10, R20, and R30, respectively. Therefore, one shape with a “wildcard” functionality could be used to identify all of features 710, 720, and 730. Specifically, in accordance with another aspect of the invention, portions of the group of edges making up a shape may be left indeterminate. This provides a “wildcard” functionality that allows the shape to identify a range of actual layout features. For example, FIG. 7d shows a shape 740 comprising edges E41, E43-E45, and E47, and indeterminate regions R42 and R46. Edges E43-E45 are contiguous, while edges E41 and E43 are coupled by indeterminate region R42, and edges E45 and E47 are coupled by indeterminate region R46. Indeterminate region R42 may be defined as any linkage between edges E41 and E43. Similarly, region R46 may be defined as any linkage between edges E45 and E47. Indeterminate regions R42 and R46 therefore allow shape 740 to match any layout feature having edges E41, E43-E45, and E47, regardless of how those edges are coupled. Additional limitations on the regions as a whole (length, width, number of included edges, etc.) and on individual edges within the regions (length, color, orientation, etc.) may be imposed to restrict the potential coverage of shape 740.
  • [0065]
    Shape Matching and Action Application
  • [0066]
    Once the catalog of shapes is specified, “actions” may be formulated as functions of the property variables of those shapes, such as those listed in Table 2. Actions may consist of instructions to perform a modification (such as in rule-based OPC), instructions to perform a simulation (such as in model-based OPC), or any other response (e.g., checking for design rule violations, generating phase shifted regions, fracturing polygons for e-beam patterning, etc.) to a particular set of parameters. Therefore, a shape-based system in accordance with an aspect of the invention may be used in any situation requiring improved identification of layout features.
  • [0067]
    In an embodiment of the invention, a layout modification system includes a bias table capturing a set of actions based on a catalog of shapes. The shapes/actions may be provided as defaults by the system, or the user may add or modify shapes/actions as desired. In an embodiment of the invention, a graphical user interface (GUI) can be provided to allow the user to input custom shapes and define actions. A sample GUI 1200 in accordance with an aspect of the invention is shown in FIG. 12. GUI 1200 allows a user to define PSM and OPC actions to be applied upon detection of particular shapes. The particular menu displayed in GUI 1200 allows the user to apply different phases to features in various layers of the IC layout. In another embodiment of the invention, a predetermined shape/action file may be loaded from an external source to provide the desired shape/action definitions.
  • [0068]
    Table 3 is a bias table that includes sample actions for shapes 420 and 430, from FIGS. 4b and 4 c, respectively. Additional information related to proper placement and sizing of the resultant bias features is not shown for simplicity. Such information could also be included in the bias table or be made accessible to the bias table.
    TABLE 3
    Shape-Based Bias Table
    Beg/
    E3 E2, E4 E1, E5 V2, V3 V1, V4 End
    SHAPE (μm) (μm) (μm) (deg.) (deg.) (deg.) BIAS
    430 <0.25 >1.5 <1.0 90 ± 5 270 ± 5 90 ± 5 Ham-
    mer
    head
    420 <0.5 <3.0 90 ± 5 270 ± 5 None
  • [0069]
    Table 3 includes rules that could be applied to IC layout element 300 a (FIG. 3a) to produce photomask element 300 b (FIG. 3b). For example, if feature 340 a shown in FIG. 3a matched the dimensional and angular orientations of the rule listed for shape 430 (FIG. 4c) in Table 3, a hammerhead (350) would be added to that feature (340 b) in the photomask layout (element 300 b). Similarly, feature 320 a (FIG. 3a) might be governed by the rule for shape 420 (FIG. 4b) listed in Table 3, thereby resulting in no modification to its corresponding photomask layout feature (320 b). In this manner, OPC modifications may be applied to IC layout features on a selective basis, under the control of the user.
  • [0070]
    The sample bias table shown in Table 3 includes a single action for each of shapes 420 and 430. Often, a single action will be sufficient to define the universe of required OPC modifications for a particular shape. For example, a user may decide that a hammerhead feature is to be added to any finger structure narrower than 0.25 μm and longer than 0.75 μm, and that all other finger structures are to be left unmodified. In such a case, a single action associated with 0.25 μm×0.75 μm fingers effectively defines the OPC for all fingers, since any not covered by the action are properly unmodified.
  • [0071]
    However, it may also be desirable to break the action associated with a particular shape into a plurality of actions, each of the plurality of actions being applicable to IC layout features falling within a certain range of that shape's characteristic property values (e.g., edge lengths, vertex angles, etc.). Table 4 is another bias table that is similar to the bias table of Table 3, but includes two actions for shape 420. Also note that the bias output for the second action for shape 420 is “Model”. This bias output represents a situation in which a model-based determination of the OPC modification would be applied. Table 4 therefore represents a “hybrid” OPC system, in which a portion of the OPC bias application is rule-based, and a portion is model-based. Such a system allows rule-based OPC to be applied to common, simple features to minimize computation time, and allows model-based OPC to be applied to critical, complex features for enhanced performance (for example, appropriate rules may not be known for unique shapes/configurations).
    TABLE 4
    Hybrid OPC Bias Table
    BEG/
    E3 E2, E4 E1, E5 V2, V3 V1, V4 END
    SHAPE (μm) (μm) (μm) (deg.) (deg.) (deg.) BIAS
    430 <0.25 >1.5 <1.0 90 ± 5 270 ± 5 90 ± 5 Ham-
    mer
    head
    420 <0.5 <3.0 90 ± 5 270 ± 5 None
    420 <.5 >3.0 90 ± 5 270 ± 5 Model
  • [0072]
    Once the actions have been defined, they may be applied to a layout in a variety of ways. For example, the application of actions to layout features may be performed in a sequential operation. Alternatively, the action application process may be performed in a batch operation. FIG. 8 shows a flow diagram of a basic action application, describing both the sequential and batch operations. Other options for action application include parallel processing (i.e., multiple actions applied simultaneously), user control (i.e., operator controls the application of actions through such methods as defining a preset process, interactively selecting actions, selecting a region of the layout to process, etc.), and any combination of the aforementioned techniques.
  • [0073]
    In the flow diagram of FIG. 8, a layout geometry to be scanned enters at block 801. A first shape from a shape catalog is then selected at block 802. Next, the first shape is compared to the layout geometry in block 803. At this point, if a batch action operation is being performed, loop B is followed and a second shape from the shape catalog is selected in block 802. The second shape is compared to the layout geometry at block 803. The process continues looping until the catalog of shapes has been completely processed, at which point the layout geometry is passed to block 804, and appropriate actions are applied to all the matched layout features. The actions are thus applied in an all-at-once (i.e., batch) manner to the layout geometry.
  • [0074]
    However, if a sequential action operation is being performed, after the first shape is compared at block 803, the layout geometry is passed to block 804, where the action associated with the first shape is applied to the matching layout features. Loop A is then followed and a second shape is selected from the shape catalog at block 802. After a second match operation in block 803, the action associated with the second shape is applied to the layout-geometry in block 804. This looping continues until every shape has been compared to the layout geometry and each action has been applied.
  • [0075]
    Regardless of whether a batch or sequential action application process is used, some mechanism may be provided to deal with conflicts that occur during the process. In lithography-related applications, there are two main types of conflicts—shape conflicts and action conflicts. A shape conflict occurs when different shapes match overlapping portions of features in an IC layout. An action conflict occurs when inconsistent or conflicting actions are to be applied an IC layout. Action conflicts may arise as a result of shape conflicts (e.g., the actions associated with overlapping shapes themselves interact) but can also arise from features that are in close proximity with one another.
  • [0076]
    [0076]FIGS. 9a-9 c provide an example to illustrate the two types of conflicts. FIG. 9a shows a shape S1 and a modified feature F1′ that could result from application of an action A associated with shape S1, i.e., action A applies a serif to corners matching shape S1. FIG. 9b shows a shape S2 and a modified feature F2′ that could result from application of an action B associated with shape S2, i.e., action B narrows and lengthens finger structures matching shape S2.
  • [0077]
    Because both shapes S1 and S2 can match the same feature, shape conflicts between the two shapes are likely. For example, FIG. 9c depicts an original layout feature F3 that might cause a shape conflict between shapes S1 and S2. Shape S1 could match the corners of feature F3, while shape S2 could match the entire feature. This overlap of shapes is not inherently problematic, but because OPC actions are typically intended to be applied in isolation from other actions, this type of shape overlap can cause unexpected and undesirable action interactions (i.e., action conflicts).
  • [0078]
    Modified layout feature F3′, shown in FIG. 9c, indicates a possible outcome of an action conflict originating in a shape conflict. The cross-like shape of feature F3′ is produced as the serifs from action A physically overlap with the extended region generated by action B. Feature F3′ is unlikely to produce the results expected from action A or action B. Further incompatibility of actions A and B is also evidenced at underlap regions C1 and C2, where the narrowing caused by action B “pulls” the body of the feature away from the serifs of action A.
  • [0079]
    Therefore, conflict resolution logic can be included to deal with both shape and action conflicts in some embodiments. In an embodiment of the invention, potential rule conflicts (or redundant rules, rules that could be combined, etc.) can be identified to the user during the rule definition stage for resolution prior to shape scanning. In another embodiment, shape and action conflicts could be avoided through the use of “exclusion IDs”. For example, at each shape match detection, the edges and/or corners of the matching layout feature could be marked with exclusion IDs. Then, match operations could perform an initial check of edges/corners marked for exclusion IDs and simply skip layout features including such marked edges. Similarly, bias features added by an OPC action could be marked with exclusion IDs, thereby selectively preventing or allowing bias application in those regions.
  • [0080]
    In accordance with another embodiment of the invention, shape and action conflicts could be avoided through the use of resolution rules. Resolution rules could determine which, if any, of the conflicting shapes/actions take priority and how such shapes/actions would be applied. The rules could perform any manner of conflict resolution desired by a user. For example, a resolution rule may simply provide that the first action always takes priority, and subsequent actions can be simply ignored (essentially the same effect as the exclusion ID method). Or, conflicting actions could be ignored but flagged for subsequent review. Alternatively, the rules could apply a completely different third action when a particular action conflict is encountered. Of course, the user could manually define which shapes/actions are to be implemented over others. The manner of operation of the resolution rules may therefore take almost any form.
  • [0081]
    The order of shape comparison may also have a significant effect on the ultimate resolution of action conflicts. For example, if the resolution rules specify that the first shape/action takes priority, it is clear that the earlier in the process a particular shape/action is applied, the greater the effect of that shape/action.
  • [0082]
    In an embodiment of the invention, shape complexity provides an ordering basis. “Complexity” refers both to the number of edges included in a shape and the precision with which the properties of that shape have been specified. A more complex shape provides greater specificity in the application of the action(s) associated with that shape. In applying the set of actions to an IC layout, one computationally efficient process could be to scan for shapes in order of decreasing complexity. This process could require that once a feature within the IC layout is matched with a shape to produce an OPC-corrected photomask layout feature, no further changes to that specific IC layout feature are allowed. Thus, this process could prevent the less complex shapes (which are theoretically capable of matching more features within the IC layout) from causing unwanted “re-modification” of features to which corrections have already been applied.
  • [0083]
    Alternatively, the IC layout could be scanned for shapes in order of increasing complexity. In such a method, “re-modification” could be allowed, so that the more complex shapes could provide the final modifications to the IC layout, essentially “overruling” any prior modifications by less complex shapes. However, this method could involve more computation (action applications) than the previous method.
  • [0084]
    Shape-Based OPC System
  • [0085]
    [0085]FIG. 10a shows a diagram of a shape-based OPC system 1000 in accordance with an embodiment of the invention. OPC system 1000 comprises an input data manager 1010, a hierarchy manager 1020, an OPC engine 1030, and an output data manager 1040. Input data manger 1010 is coupled to receive an input data file DFin for a particular IC layout. According to an aspect of the invention, data file DFin may be a standard layout database file exchange format such as GDS, GDSTI, DXF, CIF, IGES, a flat file, or even a proprietary database file format. However, any data file format that defines the geometry of a layout could be used.
  • [0086]
    Input data manager 1010 converts data file DFin to a form that may be manipulated and processed by the OPC system. In an embodiment of the invention, input data manager 1010 divides data file DFin into its various layers and discrete sets of geometries within each layer. For example, a single set of geometries may include an entire layer of the IC layout. Alternatively, a single set of geometries might only include a single polygon from a particular layer of the IC layout. In an aspect of the invention, a user may configure the conversion preferences of input data manager 1010. The converted data is then passed to hierarchy manager 1020. In an alternative embodiment, input data manger 1010 can be incorporated in hierarchy manager 1020.
  • [0087]
    Hierarchy manager 1020 organizes and categorizes the sets of geometries according to a predefined ordering basis (for example to minimize the amount of data required to be processed or to minimize the time required for processing). An example of a hierarchy manager is included in the CATS™ software package, from Numerical Technologies, Inc. Hierarchy manager 1020 then feeds the sets of geometries to OPC engine 1030 according to its priority structure.
  • [0088]
    OPC engine 1030 receives a set of geometries, and performs shape matching and action application to the set. An embodiment of OPC engine 1030, comprising a data controller 1032, a shape scanner 1034, and an action manager 1036, is shown in FIG. 10b. Data controller 1032 accepts a set of geometries from hierarchy manager 1020 and further segregates the data into “primitives”; i.e., elements appropriate for shape scanner 1034. In an embodiment of the invention, primitives can be polygon data. Alternatively, data controller 1032 could output trapezoid data, or any other representational format used by shape scanner 1034.
  • [0089]
    Data controller 1032 then supplies the primitives to shape scanner 1034. In an embodiment of the invention, this supply operation can be a batch operation, in which all the primitives can be provided to shape scanner 1034 in a single batch. In such an operation, after the match and action operations of shape scanner 1034 and action manager 1036, respectively, data controller 1032 receives a new set of geometries from hierarchy manager 1020 (loop A). However, in another embodiment of the invention, data controller 1032 performs a sequential supply operation, sending primitives one at a time to shape scanner 1034. After processing of each primitive by shape scanner 1034 and action manager 1036, data controller 1032 supplies a new primitive to shape scanner 1034 (loop B). This looping continues until all the elements in data controller 1032 have been processed.
  • [0090]
    Shape scanner 1034 compares the shapes within its own shape catalog to features of the primitives provided by data controller 1032, identifying any matches. Shape scanner 1034 also includes logic to resolve shape conflicts, using any of the methods described previously. Action manager 1036 then applies the appropriate actions where indicated by the matching operation of shape scanner 1034. Action manager 1036 also includes logic to resolve any action conflicts that arise. As noted with respect to the action application flow diagram of FIG. 8, the match/action operations may be performed in batch mode or sequential mode. Thus, in an embodiment of the invention, shape scanner 1034 compares its entire shape catalog to the geometry elements, identifying any matching features. The fully match-processed data is then passed to action manager 1036. In another embodiment of the invention, shape scanner 1034 passes the data to action manager 1036 after each shape comparison operation. In this manner, after each shape match is performed, the action(s) associated with that shape can be applied before performing the next shape match (loop C).
  • [0091]
    After all the sets of geometries have been processed by OPC engine 1030, they are fed by hierarchy manager 1020 to output data manager 1040, as shown in FIG. 10a. The processed data can be converted by output data manager 1040 into an output data file DFout. In an embodiment of the invention, output data file DFout can be converted to the same layout database file format as input data file DFin. In another embodiment of the invention, a user may select a file format for data file DFout.
  • [0092]
    [0092]FIG. 11 provides a physical representation of shape-based OPC system 1000 shown in FIG. 10a, according to an embodiment of the invention. FIG. 11 shows a computer system 1110 comprising a processor 1112 and a graphical display 1114. Alternatively, computer system 1110 could include multiple processors. Computer system 1110 includes software to perform the operations described with reference to OPC system 1000 in FIG. 10a. Computer system 1110 could include a personal computer (PC) running Microsoft™ software and/or a workstation. Display 1114 allows a user to monitor and control the OPC process being performed by computer system 1110.
  • [0093]
    [0093]FIG. 11 also shows a GDS database 1160 and an action/shape database 1180, both of which may be located in a network storage location 1190 (apart from computer system 1110). GDS database 1160 stores IC layout data files, while action/shape database 1180 houses shape libraries and bias tables for use in OPC operations. Alternatively, the data files, shape libraries, and bias tables could be stored locally in computer system 1110. Computer system 1110 may access GDS database 1160 for files on which to perform OPC, and may access action/shape database 1180 for appropriate settings information for the OPC operation. In an embodiment of the invention, databases 1160 and 1180 may be accessed through a local area network (LAN). In another embodiment of the invention, databases 1160 and 1180 may be accessed though a wide area network (WAN), such as the Internet.
  • [0094]
    Thus, an efficient and powerful technique for performing IC layout processing is described. By using a shape-based identification system, seemingly similar layout features can be readily distinguished, and layout processing actions can be precisely applied. The above disclosure is not intended to be limiting. Numerous modifications and variations of the invention will be apparent to one of ordinary skill in the art. For example, a shape catalog may include default, or “filler”, shapes. These filler shapes can be single edge elements used to account for any portions of the IC layout not covered by the rules associated with the multi-edge shapes. Also, the exclusion ID marking technique described as a conflict resolution technique could be used to identify problematic configurations in violation of basic design rules—in effect enabling the filtering system to perform DRC. Therefore, the invention is limited only by the following claims.
Patent Citations
Cited PatentFiling datePublication dateApplicantTitle
US5159201 *Jul 26, 1991Oct 27, 1992International Business Machines CorporationShape decompositon system and method
US5900338 *Aug 15, 1997May 4, 1999Lsi Logic CorporationPerforming optical proximity correction with the aid of design rule checkers
US6416907 *Apr 27, 2000Jul 9, 2002Micron Technology, Inc.Method for designing photolithographic reticle layout, reticle, and photolithographic process
US6425113 *Jun 13, 2000Jul 23, 2002Leigh C. AndersonIntegrated verification and manufacturability tool
US6430737 *Jul 10, 2000Aug 6, 2002Mentor Graphics Corp.Convergence technique for model-based optical and process correction
US6516459 *Jul 10, 2000Feb 4, 2003Mentor Graphics CorporationIntegrated circuit design correction using fragment correspondence
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US6799313 *Jun 4, 2003Sep 28, 2004Lacour Patrick JosephSpace classification for resolution enhancement techniques
US6842889 *Aug 6, 2002Jan 11, 2005Micron Technology, Inc.Methods of forming patterned reticles
US6964031 *Sep 27, 2002Nov 8, 2005Kabushiki Kaisha ToshibaMask pattern generating method and manufacturing method of semiconductor apparatus
US7069535 *Jun 3, 2003Jun 27, 2006Lsi Logic CorporationOptical proximity correction method using weighted priorities
US7073161Aug 4, 2004Jul 4, 2006Micron Technology, Inc.Methods of forming patterned reticles
US7086031Aug 4, 2004Aug 1, 2006Micron Technology, Inc.Methods of forming patterned reticles
US7093227Aug 4, 2004Aug 15, 2006Micron Technology, Inc.Methods of forming patterned reticles
US7107572Aug 4, 2004Sep 12, 2006Micron Technology, Inc.Methods of forming patterned reticles
US7313769 *Mar 1, 2004Dec 25, 2007Advanced Micro Devices, Inc.Optimizing an integrated circuit layout by taking into consideration layout interactions as well as extra manufacturability margin
US7337424 *Mar 24, 2005Feb 26, 2008Aprio Technologies, Inc.Flexible shape identification for optical proximity correction in semiconductor fabrication
US7350182Aug 4, 2004Mar 25, 2008Micron Technology, Inc.Methods of forming patterned reticles
US7562337 *Dec 11, 2006Jul 14, 2009International Business Machines CorporationOPC verification using auto-windowed regions
US7653892 *Aug 18, 2005Jan 26, 2010Cadence Design Systems, Inc.System and method for implementing image-based design rules
US7661087Dec 12, 2006Feb 9, 2010Cadence Design Systems, Inc.Yield analysis with situations
US7707542Dec 12, 2006Apr 27, 2010Cadence Design Systems, Inc.Creating a situation repository
US7752577Jul 6, 2010Cadence Design Systems, Inc.Constraint plus pattern
US7818707Oct 19, 2010Cadence Design Systems, Inc.Fast pattern matching
US7831942Nov 9, 2010Cadence Design Systems, Inc.Design check database
US7842975Sep 17, 2008Nov 30, 2010Tela Innovations, Inc.Dynamic array architecture
US7888705Feb 15, 2011Tela Innovations, Inc.Methods for defining dynamic array section with manufacturing assurance halo and apparatus implementing the same
US7906801Sep 16, 2009Mar 15, 2011Tela Innovations, Inc.Semiconductor device and associated layouts having transistors formed from six linear conductive segments with intervening diffusion contact restrictions
US7908578Mar 15, 2011Tela Innovations, Inc.Methods for designing semiconductor device with dynamic array section
US7910958Sep 18, 2009Mar 22, 2011Tela Innovations, Inc.Semiconductor device and associated layouts having transistors formed from linear conductive segment with non-active neighboring linear conductive segment
US7910959Mar 22, 2011Tela Innovations, Inc.Semiconductor device and associated layouts having transistors formed from six linear conductive segments with gate electrode connection through single interconnect level
US7917879Mar 29, 2011Tela Innovations, Inc.Semiconductor device with dynamic array section
US7923757Sep 18, 2009Apr 12, 2011Tela Innovations, Inc.Semiconductor device and associated layouts having linear shaped gate electrodes defined along at least five adjacent gate electrode tracks of equal pitch with gate electrode connection through single interconnect level
US7932544Sep 16, 2009Apr 26, 2011Tela Innovations, Inc.Semiconductor device and associated layouts including linear conductive segments having non-gate extension portions
US7932545Sep 18, 2009Apr 26, 2011Tela Innovations, Inc.Semiconductor device and associated layouts including gate electrode level region having arrangement of six linear conductive segments with side-to-side spacing less than 360 nanometers
US7939443May 10, 2011Tela Innovations, Inc.Methods for multi-wire routing and apparatus implementing same
US7943966Sep 16, 2009May 17, 2011Tela Innovations, Inc.Integrated circuit and associated layout with gate electrode level portion including at least two complimentary transistor forming linear conductive segments and at least one non-gate linear conductive segment
US7943967Sep 16, 2009May 17, 2011Tela Innovations, Inc.Semiconductor device and associated layouts including diffusion contact placement restriction based on relation to linear conductive segments
US7948012Sep 16, 2009May 24, 2011Tela Innovations, Inc.Semiconductor device having 1965 nm gate electrode level region including at least four active linear conductive segments and at least one non-gate linear conductive segment
US7948013Sep 25, 2009May 24, 2011Tela Innovations, Inc.Semiconductor device and associated layouts having linear shaped gate electrodes defined along at least five adjacent gate electrode tracks of equal pitch
US7952119May 31, 2011Tela Innovations, Inc.Semiconductor device and associated layout having three or more linear-shaped gate electrode level conductive segments of both equal length and equal pitch
US7956421Mar 11, 2009Jun 7, 2011Tela Innovations, Inc.Cross-coupled transistor layouts in restricted gate level layout architecture
US7979829Jul 12, 2011Tela Innovations, Inc.Integrated circuit cell library with cell-level process compensation technique (PCT) application and associated methods
US7989847Sep 16, 2009Aug 2, 2011Tela Innovations, Inc.Semiconductor device having linear-shaped gate electrodes of different transistor types with uniformity extending portions of different lengths
US7989848Sep 16, 2009Aug 2, 2011Tela Innovations, Inc.Semiconductor device having at least four side-by-side electrodes of equal length and equal pitch with at least two transistor connections to power or ground
US7994545Aug 9, 2011Tela Innovations, Inc.Methods, structures, and designs for self-aligning local interconnects used in integrated circuits
US8022441Sep 16, 2009Sep 20, 2011Tela Innovations, Inc.Semiconductor device and associated layouts having transistors formed from six linear conductive segments with gate electrode-to-gate electrode connection through single interconnect level and common node connection through different interconnect level
US8030689Oct 4, 2011Tela Innovations, Inc.Integrated circuit device and associated layout including separated diffusion regions of different type each having four gate electrodes with each of two complementary gate electrode pairs formed from respective linear conductive segment
US8035133Oct 11, 2011Tela Innovations, Inc.Semiconductor device having two pairs of transistors of different types formed from shared linear-shaped conductive features with intervening transistors of common type on equal pitch
US8058671Sep 18, 2009Nov 15, 2011Tela Innovations, Inc.Semiconductor device having at least three linear-shaped electrode level conductive features of equal length positioned side-by-side at equal pitch
US8058691Apr 2, 2010Nov 15, 2011Tela Innovations, Inc.Semiconductor device including cross-coupled transistors formed from linear-shaped gate level features
US8072003Dec 6, 2011Tela Innovations, Inc.Integrated circuit device and associated layout including two pairs of co-aligned complementary gate electrodes with offset gate contact structures
US8088679Jan 3, 2012Tela Innovations, Inc.Method for fabricating integrated circuit with gate electrode level portion including at least two complementary transistor forming linear conductive segments and at least one non-gate linear conductive segment
US8088680Oct 1, 2009Jan 3, 2012Tela Innovations, Inc.Method for fabricating integrated circuit having at least three linear-shaped gate electrode level conductive features of equal length positioned side-by-side at equal pitch
US8088681Jan 3, 2012Tela Innovations, Inc.Method for fabricating integrated circuit including separated diffusion regions of different type each having four gate electrodes with each of two complementary gate electrode pairs formed from respective linear condcutive segment
US8088682Oct 1, 2009Jan 3, 2012Tela Innovations, Inc.Method for fabricating integrated circuit with gate electrode level region including two side-by-side ones of at least three linear-shaped conductive structures electrically connected to each other through non-gate level
US8089098Sep 18, 2009Jan 3, 2012Tela Innovations, Inc.Integrated circuit device and associated layout including linear gate electrodes of different transistor types next to linear-shaped non-gate conductive segment
US8089099Sep 18, 2009Jan 3, 2012Tela Innovations, Inc,Integrated circuit device and associated layout including gate electrode level region of 965 NM radius with linear-shaped conductive segments on fixed pitch
US8089100Sep 25, 2009Jan 3, 2012Tela Innovations, Inc.Integrated circuit with gate electrode level region including at least four linear-shaped conductive structures forming gate electrodes of transistors and including extending portions of at least two different sizes
US8089101Jan 3, 2012Tela Innovations, Inc.Integrated circuit device with gate electrode level region including two side-by-side ones of at least three linear-shaped conductive structures electrically connected to each other through non-gate level
US8089102Sep 25, 2009Jan 3, 2012Tela Innovations, Inc.Method for fabricating integrated circuit having three or more linear-shaped gate electrode level conductive segments of both equal length and equal pitch
US8089103Sep 25, 2009Jan 3, 2012Tela Innovations, Inc.Integrated circuit device with gate level region including at least three linear-shaped conductive segments having offset line ends and forming three transistors of first type and one transistor of second type
US8089104Jan 3, 2012Tela Innovations, Inc.Integrated circuit with gate electrode level region including multiple linear-shaped conductive structures forming gate electrodes of transistors and including uniformity extending portions of different size
US8101975Sep 25, 2009Jan 24, 2012Tela Innovations, Inc.Integrated circuit device with gate level region including non-gate linear conductive segment positioned within 965 nanometers of four transistors of first type and four transistors of second type
US8110854Sep 25, 2009Feb 7, 2012Tela Innovations, Inc.Integrated circuit device with linearly defined gate electrode level region and shared diffusion region of first type connected to shared diffusion region of second type through at least two interconnect levels
US8129750Sep 25, 2009Mar 6, 2012Tela Innovations, Inc.Integrated circuit including at least six linear-shaped conductive structures forming gate electrodes of transistors with at least two linear-shaped conductive structures of different length
US8129751Sep 25, 2009Mar 6, 2012Tela Innovations, Inc.Integrated circuit including at least six linear-shaped conductive structures forming gate electrodes and including four conductive contacting structures having at least two different connection distances
US8129752Sep 25, 2009Mar 6, 2012Tela Innovations, Inc.Integrated circuit including a linear-shaped conductive structure forming one gate electrode and having length greater than or equal to one-half the length of linear-shaped conductive structure forming two gate electrodes
US8129753Sep 25, 2009Mar 6, 2012Tela Innovations, Inc.Integrated circuit including gate electrode level region including at least seven linear-shaped conductive structures of equal length positioned at equal pitch with at least two linear-shaped conductive structures each forming one transistor and having extending portion sized greater than gate portion
US8129754Sep 30, 2009Mar 6, 2012Tela Innovations, Inc.Integrated circuit with gate electrode level including at least six linear-shaped conductive structures forming gate electrodes of transisters with at least one pair of linear-shaped conductive structures having offset ends
US8129755Oct 1, 2009Mar 6, 2012Tela Innovations, Inc.Integrated circuit with gate electrode level including at least four linear-shaped conductive structures of equal length and equal pitch with linear-shaped conductive structure forming one transistor
US8129756Oct 1, 2009Mar 6, 2012Tela Innovations, Inc.Integrated circuit including at least six linear-shaped conductive structures forming gate electrodes of transistors with at least two different extension distances beyond conductive contacting structures
US8129757Oct 1, 2009Mar 6, 2012Tela Innovations, Inc.Integrated circuit including at least six linear-shaped conductive structive structures at equal pitch including at least two linear-shaped conductive structures having non-gate portions of different length
US8129819Sep 25, 2009Mar 6, 2012Tela Innovations, Inc.Method of fabricating integrated circuit including at least six linear-shaped conductive structures at equal pitch including at least two linear-shaped conductive structures having non-gate portions of different length
US8134183Sep 25, 2009Mar 13, 2012Tela Innovations, Inc.Integrated circuit including linear-shaped conductive structures that have gate portions and extending portions of different size
US8134184Sep 25, 2009Mar 13, 2012Tela Innovations, Inc.Integrated circuit having gate electrode level region including at least four linear-shaped conductive structures with some outer-contacted linear-shaped conductive structures having larger outer extending portion than inner extending portion
US8134185Sep 25, 2009Mar 13, 2012Tela Innovations, Inc.Integrated circuit having gate electrode level region including at least seven linear-shaped conductive structures at equal pitch including linear-shaped conductive structure forming transistors of two different types and at least three linear-shaped conductive structures having aligned ends
US8134186Oct 1, 2009Mar 13, 2012Tela Innovations, Inc.Integrated circuit including at least three linear-shaped conductive structures at equal pitch including linear-shaped conductive structure having non-gate portion length greater than gate portion length
US8138525Oct 1, 2009Mar 20, 2012Tela Innovations, Inc.Integrated circuit including at least three linear-shaped conductive structures of different length each forming gate of different transistor
US8198656Jun 12, 2012Tela Innovations, Inc.Integrated circuit including gate electrode level region including at least four linear-shaped conductive structures of equal length having aligned ends and positioned at equal pitch and forming multiple gate electrodes of transistors of different type
US8207053Sep 25, 2009Jun 26, 2012Tela Innovations, Inc.Electrodes of transistors with at least two linear-shaped conductive structures of different length
US8214778Jul 3, 2012Tela Innovations, Inc.Methods for cell phasing and placement in dynamic array architecture and implementation of the same
US8217428Jul 10, 2012Tela Innovations, Inc.Integrated circuit including gate electrode level region including at least three linear-shaped conductive structures of equal length having aligned ends and positioned at equal pitch and forming multiple gate electrodes of transistors of different type
US8225239Jul 17, 2012Tela Innovations, Inc.Methods for defining and utilizing sub-resolution features in linear topology
US8225261Mar 7, 2009Jul 17, 2012Tela Innovations, Inc.Methods for defining contact grid in dynamic array architecture
US8245180Jun 12, 2009Aug 14, 2012Tela Innovations, Inc.Methods for defining and using co-optimized nanopatterns for integrated circuit design and apparatus implementing same
US8247846Aug 21, 2012Tela Innovations, Inc.Oversized contacts and vias in semiconductor chip defined by linearly constrained topology
US8253172Aug 28, 2012Tela Innovations, Inc.Semiconductor device with linearly restricted gate level region including four serially connected transistors of first type and four serially connected transistors of second type separated by non-diffusion region
US8253173Aug 28, 2012Tela Innovations, Inc.Semiconductor device with gate level including four transistors of first type and four transistors of second type separated by non-diffusion region and having at least two gate contacts positioned outside separating non-diffusion region
US8258547Sep 18, 2009Sep 4, 2012Tela Innovations, Inc.Semiconductor device with linearly restricted gate level region including two transistors of first type and two transistors of second type with offset gate contacts
US8258548Oct 1, 2009Sep 4, 2012Tela Innovations, Inc.Semiconductor device with gate level including four transistors of first type and four transistors of second type separated by non-diffusion region with restricted gate contact placement over separating non-diffusion region
US8258549Oct 1, 2009Sep 4, 2012Tela Innovations, Inc.Semiconductor device including two transistors of first type having gates formed by conductors of different length respectively aligned with two transistors of second type having gates formed by conductors of different length
US8258550Oct 1, 2009Sep 4, 2012Tela Innovations, Inc.Semiconductor device including at least six transistor forming linear shapes including at least two transistor forming linear shapes having different extension distances beyond gate contact
US8258551Sep 4, 2012Tela Innovations, Inc.Semiconductor device with gate level including transistors of first type and transistors of second type with corresponding gate contact placement restriction
US8258552Oct 1, 2009Sep 4, 2012Tela Innovations, Inc.Semiconductor device including at least six transistor forming linear shapes with at least two transistor forming linear shapes having offset ends
US8258581Apr 2, 2010Sep 4, 2012Tela Innovations, Inc.Integrated circuit including cross-coupled transistors with two transistors of different type formed by same gate level structure and two transistors of different type formed by separate gate level structures
US8264007Oct 1, 2009Sep 11, 2012Tela Innovations, Inc.Semiconductor device including at least six transistor forming linear shapes including at least two different gate contact connection distances
US8264008Sep 11, 2012Tela Innovations, Inc.Semiconductor device including transistor forming linear shapes including gate portions and extending portions of different size
US8264009Oct 1, 2009Sep 11, 2012Tela Innovations, Inc.Semiconductor device with linearly restricted gate level region including four transistors of first type and four transistors of second type with gate defining shapes of different length
US8264044Sep 11, 2012Tela Innovations, Inc.Integrated circuit including cross-coupled transistors having two complementary pairs of co-aligned gate electrodes with offset contacting structures positioned between transistors of different type
US8264049Sep 11, 2012Tela Innovations, Inc.Integrated circuit including cross-coupled transistors with two transistors of different type having gate electrodes formed by common gate level feature with shared diffusion regions on opposite sides of common gate level feature
US8274099Apr 5, 2010Sep 25, 2012Tela Innovations, Inc.Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with gate contact position and offset specifications
US8283701Jan 14, 2011Oct 9, 2012Tela Innovations, Inc.Semiconductor device with dynamic array sections defined and placed according to manufacturing assurance halos
US8286107Dec 19, 2008Oct 9, 2012Tela Innovations, Inc.Methods and systems for process compensation technique acceleration
US8327299Dec 4, 2012Cadence Design Systems, Inc.System and method for implementing image-based design rules
US8356268Mar 28, 2011Jan 15, 2013Tela Innovations, Inc.Integrated circuit device including dynamic array section with gate level having linear conductive features on at least three side-by-side lines and uniform line end spacings
US8365103Jan 29, 2013Cadence Design Systems, Inc.System and method for implementing image-based design rules
US8381152Jun 5, 2008Feb 19, 2013Cadence Design Systems, Inc.Method and system for model-based design and layout of an integrated circuit
US8395224Apr 2, 2010Mar 12, 2013Tela Innovations, Inc.Linear gate level cross-coupled transistor device with non-overlapping PMOS transistors and non-overlapping NMOS transistors relative to directions of gate electrodes
US8405162Apr 2, 2010Mar 26, 2013Tela Innovations, Inc.Integrated circuit including gate electrode level region including cross-coupled transistors having at least one gate contact located over outer portion of gate electrode level region
US8405163Mar 26, 2013Tela Innovations, Inc.Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with shared diffusion regions on opposite sides of two-transistor-forming gate level feature
US8429582 *Dec 30, 2010Apr 23, 2013Cadence Design Systems, Inc.Methods, systems, and articles of manufacture for smart pattern capturing and layout fixing
US8436400May 7, 2013Tela Innovations, Inc.Semiconductor device with gate level including gate electrode conductors for transistors of first type and transistors of second type with some gate electrode conductors of different length
US8448102May 21, 2013Tela Innovations, Inc.Optimizing layout of irregular structures in regular layout context
US8453094May 28, 2013Tela Innovations, Inc.Enforcement of semiconductor structure regularity for localized transistors and interconnect
US8471391Apr 12, 2011Jun 25, 2013Tela Innovations, Inc.Methods for multi-wire routing and apparatus implementing same
US8516406Dec 30, 2010Aug 20, 2013Cadence Design Systems, Inc.Methods, systems, and articles of manufacture for smart pattern capturing and layout fixing
US8541879Dec 13, 2007Sep 24, 2013Tela Innovations, Inc.Super-self-aligned contacts and method for making the same
US8543965Dec 30, 2010Sep 24, 2013Cadence Design Systems, Inc.Methods, systems, and articles of manufacture for smart pattern capturing and layout fixing
US8549455Jul 2, 2012Oct 1, 2013Tela Innovations, Inc.Methods for cell phasing and placement in dynamic array architecture and implementation of the same
US8552508Apr 5, 2010Oct 8, 2013Tela Innovations, Inc.Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with shared diffusion regions on opposite sides of two-transistor-forming gate level feature and electrical connection of transistor gates through linear interconnect conductors in single interconnect layer
US8552509Apr 5, 2010Oct 8, 2013Tela Innovations, Inc.Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with other transistors positioned between cross-coupled transistors
US8558322Apr 5, 2010Oct 15, 2013Tela Innovations, Inc.Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with at least two gate electrodes electrically connected to each other through gate level feature
US8564071Apr 5, 2010Oct 22, 2013Tela Innovations, Inc.Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with at least two different gate level feature extensions beyond contact
US8566754 *Nov 21, 2008Oct 22, 2013Synopsys, Inc.Dual-purpose perturbation engine for automatically processing pattern-clip-based manufacturing hotspots
US8569841Apr 5, 2010Oct 29, 2013Tela Innovations, Inc.Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with at least one gate level feature extending into adjacent gate level feature layout channel
US8575706Apr 5, 2010Nov 5, 2013Tela Innovations, Inc.Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with at least two different gate level features inner extensions beyond gate electrode
US8581303Apr 2, 2010Nov 12, 2013Tela Innovations, Inc.Integrated circuit including cross-coupled trasistors having gate electrodes formed within gate level feature layout channels with four inside positioned gate contacts having offset relationships and electrical connection of cross-coupled transistors through same interconnect layer
US8581304Apr 2, 2010Nov 12, 2013Tela Innovations, Inc.Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with four inside positioned gate contacts having offset and aligned relationships
US8587034Apr 2, 2010Nov 19, 2013Tela Innovations, Inc.Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with four inside positioned gate contacts and electrical connection of transistor gates through linear interconnect conductors in single interconnect layer
US8592872Aug 17, 2012Nov 26, 2013Tela Innovations, Inc.Integrated circuit including cross-coupled transistors with two transistors of different type having gate electrodes formed by common gate level feature with shared diffusion regions on opposite sides of common gate level feature
US8631373Dec 22, 2009Jan 14, 2014Cadence Design Systems, Inc.Yield analysis with situations
US8645887Jun 27, 2012Feb 4, 2014Cadence Design Systems, Inc.Method and system for model-based design and layout of an integrated circuit
US8653857May 5, 2009Feb 18, 2014Tela Innovations, Inc.Circuitry and layouts for XOR and XNOR logic
US8658542May 16, 2012Feb 25, 2014Tela Innovations, Inc.Coarse grid design methods and structures
US8661392Oct 13, 2010Feb 25, 2014Tela Innovations, Inc.Methods for cell boundary encroachment and layouts implementing the Same
US8667443Mar 3, 2008Mar 4, 2014Tela Innovations, Inc.Integrated circuit cell library for multiple patterning
US8669594Apr 2, 2010Mar 11, 2014Tela Innovations, Inc.Integrated circuit including cross-coupled transistors having gate electrodes formed within at least twelve gate level feature layout channels
US8669595Apr 5, 2010Mar 11, 2014Tela Innovations, Inc.Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with gate contact position, alignment, and offset specifications
US8677301Jun 27, 2012Mar 18, 2014Cadence Design Systems, Inc.Method and system for model-based design and layout of an integrated circuit
US8680583Apr 2, 2010Mar 25, 2014Tela Innovations, Inc.Integrated circuit including cross-coupled transistors having gate electrodes formed within at least nine gate level feature layout channels
US8680626Jul 22, 2011Mar 25, 2014Tela Innovations, Inc.Methods, structures, and designs for self-aligning local interconnects used in integrated circuits
US8701071May 17, 2013Apr 15, 2014Tela Innovations, Inc.Enforcement of semiconductor structure regularity for localized transistors and interconnect
US8713507May 4, 2012Apr 29, 2014Cadence Design Systems, Inc.Method and apparatus for efficiently inserting fills in an integrated circuit layout
US8729606Apr 5, 2010May 20, 2014Tela Innovations, Inc.Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels
US8729643Mar 15, 2013May 20, 2014Tela Innovations, Inc.Cross-coupled transistor circuit including offset inner gate contacts
US8735944Apr 5, 2010May 27, 2014Tela Innovations, Inc.Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with serially connected transistors
US8735995Mar 15, 2013May 27, 2014Tela Innovations, Inc.Cross-coupled transistor circuit defined on three gate electrode tracks with diffusion regions of common node on opposing sides of same gate electrode track
US8742462Apr 5, 2010Jun 3, 2014Tela Innovations, Inc.Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with gate contact position specifications
US8742463Apr 5, 2010Jun 3, 2014Tela Innovations, Inc.Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with outer positioned gate contacts
US8756551Mar 14, 2011Jun 17, 2014Tela Innovations, Inc.Methods for designing semiconductor device with dynamic array section
US8759882Jan 14, 2011Jun 24, 2014Tela Innovations, Inc.Semiconductor device with dynamic array sections defined and placed according to manufacturing assurance halos
US8759985Jun 14, 2013Jun 24, 2014Tela Innovations, Inc.Methods for multi-wire routing and apparatus implementing same
US8769474Oct 18, 2010Jul 1, 2014Cadence Design Systems, Inc.Fast pattern matching
US8772839Apr 2, 2010Jul 8, 2014Tela Innovations, Inc.Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with four inside positioned gate contacts having offset and aligned relationships and electrical connection of transistor gates through linear interconnect conductors in single interconnect layer
US8782574 *Feb 2, 2009Jul 15, 2014Youping ZhangSystem for simplifying layout processing
US8785978Apr 2, 2010Jul 22, 2014Tela Innovations, Inc.Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with electrical connection of cross-coupled transistors through same interconnect layer
US8785979Apr 2, 2010Jul 22, 2014Tela Innovations, Inc.Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with two inside positioned gate contacts and two outside positioned gate contacts and electrical connection of cross-coupled transistors through same interconnect layer
US8789005 *May 4, 2012Jul 22, 2014Cadence Design Systems, Inc.Method and apparatus for efficiently processing an integrated circuit layout
US8816402Apr 5, 2010Aug 26, 2014Tela Innovations, Inc.Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with gate level feature layout channel including single transistor
US8823062Mar 14, 2013Sep 2, 2014Tela Innovations, Inc.Integrated circuit with offset line end spacings in linear gate electrode level
US8835989Apr 5, 2010Sep 16, 2014Tela Innovations, Inc.Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with gate electrode placement specifications
US8836045Mar 15, 2013Sep 16, 2014Tela Innovations, Inc.Cross-coupled transistor circuit having diffusion regions of common node on opposing sides of same gate electrode track
US8839175Dec 6, 2011Sep 16, 2014Tela Innovations, Inc.Scalable meta-data objects
US8847329Mar 15, 2013Sep 30, 2014Tela Innovations, Inc.Cross-coupled transistor circuit defined having diffusion regions of common node on opposing sides of same gate electrode track with at least two non-inner positioned gate contacts
US8847331May 8, 2014Sep 30, 2014Tela Innovations, Inc.Semiconductor chip including region having cross-coupled transistor configuration with offset electrical connection areas on gate electrode forming conductive structures and at least two different inner extension distances of gate electrode forming conductive structures
US8853793Jan 14, 2013Oct 7, 2014Tela Innovations, Inc.Integrated circuit including gate electrode level region including cross-coupled transistors having gate contacts located over inner portion of gate electrode level region and offset gate level feature line ends
US8853794Apr 1, 2014Oct 7, 2014Tela Innovations, Inc.Integrated circuit within semiconductor chip including cross-coupled transistor configuration
US8863045 *Nov 21, 2013Oct 14, 2014Shanghai Huali Microelectronics CorporationOptical proximity correction method based on hybrid simulation model
US8863063Mar 15, 2013Oct 14, 2014Tela Innovations, Inc.Finfet transistor circuit
US8866197Apr 5, 2010Oct 21, 2014Tela Innovations, Inc.Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with at least two gate electrodes electrically connected to each other through another transistor forming gate level feature
US8872283Jan 14, 2013Oct 28, 2014Tela Innovations, Inc.Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with shared diffusion regions on opposite sides of two-transistor-forming gate level feature
US8921896Mar 14, 2013Dec 30, 2014Tela Innovations, Inc.Integrated circuit including linear gate electrode structures having different extension distances beyond contact
US8921897Mar 15, 2013Dec 30, 2014Tela Innovations, Inc.Integrated circuit with gate electrode conductive structures having offset ends
US8942464 *Mar 28, 2011Jan 27, 2015Hitachi High-Technologies CorporationPattern measuring apparatus, and pattern measuring method and program
US8943453 *Jun 11, 2010Jan 27, 2015Taiwan Semiconductor Manufacturing Company, Ltd.Automatic application-rule checker
US8946781Mar 15, 2013Feb 3, 2015Tela Innovations, Inc.Integrated circuit including gate electrode conductive structures with different extension distances beyond contact
US8951916Sep 23, 2013Feb 10, 2015Tela Innovations, Inc.Super-self-aligned contacts and method for making the same
US8952425Feb 22, 2013Feb 10, 2015Tela Innovations, Inc.Integrated circuit including at least four linear-shaped conductive structures having extending portions of different length
US8966424Sep 27, 2013Feb 24, 2015Tela Innovations, Inc.Methods for cell phasing and placement in dynamic array architecture and implementation of the same
US9009641Jan 12, 2013Apr 14, 2015Tela Innovations, Inc.Circuits with linear finfet structures
US9035359Jun 13, 2014May 19, 2015Tela Innovations, Inc.Semiconductor chip including region including linear-shaped conductive structures forming gate electrodes and having electrical connection areas arranged relative to inner region between transistors of different types and associated methods
US9081931Mar 15, 2013Jul 14, 2015Tela Innovations, Inc.Cross-coupled transistor circuit having diffusion regions of common node on opposing sides of same gate electrode track and gate node connection through single interconnect layer
US9117050Aug 21, 2012Aug 25, 2015Tela Innovations, Inc.Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with gate contact position and offset specifications
US9122832Jul 30, 2009Sep 1, 2015Tela Innovations, Inc.Methods for controlling microloading variation in semiconductor wafer layout and fabrication
US9159627Nov 14, 2011Oct 13, 2015Tela Innovations, Inc.Methods for linewidth modification and apparatus implementing the same
US9202779Mar 17, 2014Dec 1, 2015Tela Innovations, Inc.Enforcement of semiconductor structure regularity for localized transistors and interconnect
US9208279Jun 12, 2014Dec 8, 2015Tela Innovations, Inc.Semiconductor chip including digital logic circuit including linear-shaped conductive structures having electrical connection areas located within inner region between transistors of different type and associated methods
US9213792Mar 9, 2015Dec 15, 2015Tela Innovations, Inc.Semiconductor chip including digital logic circuit including at least six transistors with some transistors forming cross-coupled transistor configuration and associated methods
US9230910May 14, 2009Jan 5, 2016Tela Innovations, Inc.Oversized contacts and vias in layout defined by linearly constrained topology
US9240413Feb 24, 2014Jan 19, 2016Tela Innovations, Inc.Methods, structures, and designs for self-aligning local interconnects used in integrated circuits
US9245081Sep 3, 2014Jan 26, 2016Tela Innovations, Inc.Semiconductor chip including digital logic circuit including at least nine linear-shaped conductive structures collectively forming gate electrodes of at least six transistors with some transistors forming cross-coupled transistor configuration and associated methods
US20030074646 *Sep 27, 2002Apr 17, 2003Toshiya KotaniMask pattern generating method and manufacturing method of semiconductor apparatus
US20030208742 *Jun 4, 2003Nov 6, 2003Lacour Patrick JosephSpace classification for resolution enhancement techniques
US20040031013 *Aug 6, 2002Feb 12, 2004Dulman H. DanielMethods of forming patterned reticles
US20040250232 *Jun 3, 2003Dec 9, 2004Kobozeva Olga A.Optical proximity correction method using weighted priorities
US20050008949 *Aug 4, 2004Jan 13, 2005Dulman H. DanielMethods of forming patterned reticles
US20050008950 *Aug 4, 2004Jan 13, 2005Dulman H. DanielMethods of forming patterned reticles
US20050008951 *Aug 4, 2004Jan 13, 2005Dulman H. DanielMethods of forming patterned reticles
US20050008952 *Aug 4, 2004Jan 13, 2005Dulman H. DanielMethods of forming patterned reticles
US20050008953 *Aug 4, 2004Jan 13, 2005Dulman H. DanielMethods of forming patterned reticles
US20050125763 *Jun 30, 2004Jun 9, 2005Taiwan Semiconductor Manufacturing Company, Ltd.System and method for the online design of a reticle field layout
US20050202326 *Mar 9, 2004Sep 15, 2005International Business Machines CorporationOptimized placement of sub-resolution assist features within two-dimensional environments
US20060236287 *Mar 24, 2005Oct 19, 2006Shao-Po WuFlexible shape identification for optical proximity correction in semiconductor fabrication
US20070086481 *Dec 30, 2005Apr 19, 2007Microsoft CorporationRTP Payload Format For VC-1
US20080141211 *Dec 11, 2006Jun 12, 2008International Business Machines CorporationOpc verification using auto-windowed regions
US20090014811 *Sep 17, 2008Jan 15, 2009Tela Innovations, Inc.Dynamic Array Architecture
US20090032898 *Jan 11, 2008Feb 5, 2009Tela Innovations, Inc.Methods for Defining Dynamic Array Section with Manufacturing Assurance Halo and Apparatus Implementing the Same
US20090224317 *Mar 11, 2009Sep 10, 2009Tela Innovations, Inc.Cross-Coupled Transistor Layouts in Restricted Gate Level Layout Architecture
US20090224408 *Mar 25, 2009Sep 10, 2009Tela Innovations, Inc.Methods for Multi-Wire Routing and Apparatus Implementing Same
US20090241087 *Feb 2, 2009Sep 24, 2009Youping ZhangSystem for simplifying layout processing
US20090268958 *Nov 21, 2008Oct 29, 2009Synopsys, Inc.dual-purpose perturbation engine for automatically processing pattern-clip-based manufacturing hotspots
US20100001321 *Sep 16, 2009Jan 7, 2010Tela Innovations, Inc.Semiconductor Device Layout Having Restricted Layout Region Including Rectangular Shaped Gate Electrode Layout Features Defined Along At Least Four Gate Electrode Tracks with Corresponding Non-Symmetric Diffusion Regions
US20100006897 *Jan 14, 2010Tela Innovations. Inc.Semiconductor Device Layout Having Restricted Layout Region Including Rectangular Shaped Gate Electrode Layout Features and Equal Number of PMOS and NMOS Transistors
US20100006901 *Jan 14, 2010Tela Innovations, Inc.Semiconductor Device Portion Having Gate Electrode Conductive Structures Formed from Rectangular Shaped Gate Electrode Layout Features Defined Along At Least Four Gate Electrode Tracks and Having Corresponding Non-Symmetric Diffusion Regions
US20100006903 *Jan 14, 2010Tela Innovations, Inc.Semiconductor Device Portion Having Sub-193 Nanometers-Sized Gate Electrode Conductive Structures Formed from Rectangular Shaped Gate Electrode Layout Features Defined Along At Least Four Gate Electrode Tracks and Having Corresponding Non-Symmetric Diffusion Regions
US20100006947 *Jan 14, 2010Tela Innovations, Inc.Semiconductor Device Portion Having Sub-Wavelength-Sized Gate Electrode Conductive Structures Formed from Rectangular Shaped Gate Electrode Layout Features and Having At Least Eight Transistors
US20100006948 *Jan 14, 2010Tela Innovations, Inc.Semiconductor Device Portion Having Sub-193 Nanometers -Sized Gate Electrode Conductive Structures Formed from Rectangular Shaped Gate Electrode Layout Features and Having At Least Eight Transistors
US20100006950 *Sep 18, 2009Jan 14, 2010Tela Innovations, Inc.Semiconductor Device Portion Having Gate Electrode Conductive Structures Formed from Rectangular Shaped Gate Electrode Layout Features and Having At Least Eight Transistors
US20100011329 *Sep 16, 2009Jan 14, 2010Tela Innovations, Inc.Semiconductor Device Layout Including Cell Layout Having Restricted Gate Electrode Level Layout with Rectangular Shaped Gate Electrode Layout Features and Equal Number of PMOS and NMOS Transistors
US20100011331 *Sep 18, 2009Jan 14, 2010Tela Innovations, Inc.Semiconductor Device Layout Including Cell Layout Having Restricted Gate Electrode Level Layout with Linear Shaped Gate Electrode Layout Features Defined Along At Least Four Gate Electrode Tracks with Minimum End-to-End Spacing with Corresponding Non-Symmetric Diffusion Regions
US20100012981 *Jan 21, 2010Tela Innovations, Inc.Semiconductor Device Portion Having Gate Electrode Conductive Structures Formed from Linear Shaped Gate Electrode Layout Features Defined Along At Least Four Gate Electrode Tracks with Minimum End-to-End Spacing and Having Corresponding Non-Symmetric Diffusion Regions
US20100012982 *Sep 25, 2009Jan 21, 2010Tela Innovations, Inc.Semiconductor Device Portion Having Sub-Wavelength-Sized Gate Electrode Conductive Structures Formed from Linear Shaped Gate Electrode Layout Features Defined Along At Least Four Gate Electrode Tracks with Minimum End-to-End Spacing and Having Corresponding Non-Symmetric Diffusion Regions
US20100012985 *Sep 25, 2009Jan 21, 2010Tela Innovations, Inc.Semiconductor Device Portion Having Sub-193 Nanometers -Sized Gate Electrode Conductive Structures Formed from Linear Shaped Gate Electrode Layout Features Defined with Minimum End-to-End Spacing and Having At Least Eight Transistors
US20100017768 *Sep 25, 2009Jan 21, 2010Tela Innovations, Inc.Layout of Cell of Semiconductor Device Having Rectangular Shaped Gate Electrode Layout Features Defined Along At Least Four Gate Electrode Tracks with Corresponding p-type and n-type Diffusion Regions Separated by Central Inactive Region
US20100017772 *Jan 21, 2010Tela Innovations, Inc.Layout of Cell of Semiconductor Device Having Rectangular Shaped Gate Electrode Layout Features and At Least Eight Transistors with Corresponding p-type and n-type Diffusion Regions Separated by Central Inactive Region
US20100019280 *Jan 28, 2010Tela Innovations, Inc.Cell of Semiconductor Device Having Gate Electrode Conductive Structures Formed from Rectangular Shaped Gate Electrode Layout Features Defined Along At Least Four Gate Electrode Tracks
US20100019284 *Oct 1, 2009Jan 28, 2010Tela Innovations, Inc.Cell of Semiconductor Device Having Sub-Wavelength-Sized Gate Electrode Conductive Structures Formed from Rectangular Shaped Gate Electrode Layout Features and At Least Eight Transistors
US20100019285 *Jan 28, 2010Tela Innovations, Inc.Cell of Semiconductor Device Having Sub-193 Nanometers-Sized Gate Electrode Conductive Structures Formed from Rectangular Shaped Gate Electrode Layout Features and At Least Eight Transistors
US20100023907 *Jan 28, 2010Tela Innovations, Inc.Layout of Cell of Semiconductor Device Having Linear Shaped Gate Electrode Layout Features Defined Along At Least Four Gate Electrode Tracks with Minimum End-to-End Spacing and Having Corresponding p-type and n-type Diffusion Regions Separated by Central Inactive Region
US20100025734 *Oct 1, 2009Feb 4, 2010Tela Innovations, Inc.Cell of Semiconductor Device Having Sub-Wavelength-Sized Gate Electrode Conductive Structures Formed from Linear Shaped Gate Electrode Layout Features Defined with Minimum End-to-End Spacing and Equal Number of PMOS and NMOS Transistors
US20100025736 *Feb 4, 2010Tela Innovations, Inc.Cell of Semiconductor Device Having Gate Electrode Conductive Structures Formed from Linear Shaped Gate Electrode Layout Features Defined with Minimum End-to-End Spacing and At Least Eight Transistors
US20100096671 *Oct 1, 2009Apr 22, 2010Tela Innovations, Inc.Cell of Semiconductor Device Having Gate Electrode Conductive Structures Formed from Rectangular Shaped Gate Electrode Layout Features and At Least Eight Transistors
US20100187616 *Apr 2, 2010Jul 29, 2010Tela Innovations, Inc.Linear Gate Level Cross-Coupled Transistor Device with Overlapping PMOS Transistors and Overlapping NMOS Transistors Relative to Direction of Gate Electrodes
US20100187618 *Apr 2, 2010Jul 29, 2010Tela Innovations, Inc.Linear Gate Level Cross-Coupled Transistor Device with Overlapping PMOS Transistors and Non-Overlapping NMOS Transistors Relative to Direction of Gate Electrodes
US20100187627 *Apr 5, 2010Jul 29, 2010Tela Innovations, Inc.Channelized Gate Level Cross-Coupled Transistor Device with Overlapping PMOS Transistors and Overlapping NMOS Transistors Relative to Direction of Gate Electrodes
US20100187634 *Apr 5, 2010Jul 29, 2010Tela Innovations, Inc.Channelized Gate Level Cross-Coupled Transistor Device with Cross-Coupled Transistors Defined on Four Gate Electrode Tracks with Crossing Gate Electrode Connections
US20100237427 *Apr 5, 2010Sep 23, 2010Tela Innovations, Inc.Channelized Gate Level Cross-Coupled Transistor Device with Contiguous p-type Diffusion Regions and Contiguous n-type Diffusion Regions
US20100237429 *Sep 23, 2010Tela Innovations, Inc.Channelized Gate Level Cross-Coupled Transistor Device with Non-Overlapping PMOS Transistors and Non-Overlapping NMOS Transistors Relative to Direction of Gate Electrodes
US20100252893 *Apr 5, 2010Oct 7, 2010Tela Innovations, Inc.Channelized Gate Level Cross-Coupled Transistor Device with Cross-Coupled Transistors Defined on Three Gate Electrode Tracks with Crossing Gate Electrode Connections
US20100252896 *Jun 11, 2010Oct 7, 2010Tela Innovations, Inc.Methods, Structures, and Designs for Self-Aligning Local Interconnects used in Integrated Circuits
US20110055778 *Mar 3, 2011Taiwan Semiconductor Manufacturing Company, Ltd.Automatic Application-Rule Checker
US20110175144 *Jul 21, 2011Tela Innovations, Inc.Integrated Circuit Device Including Dynamic Array Section with Gate Level Having Linear Conductive Features on at Least Three Side-by-Side Lines and Uniform Line End Spacings
US20130223723 *Mar 28, 2011Aug 29, 2013Hitachi High-Technologies CorporationPattern measuring apparatus, and pattern measuring method and program
DE102004008378B4 *Feb 20, 2004Aug 28, 2014Nanya Technology CorporationOptisches Nähenkorrekturverfahren
Classifications
U.S. Classification716/52, 174/250, 430/5, 716/53
International ClassificationG03F1/36, G03F1/00, G06F17/50
Cooperative ClassificationG03F1/36, G06F17/5081, G03F1/144
European ClassificationG03F1/36, G03F1/14G, G06F17/50L3
Legal Events
DateCodeEventDescription
Feb 4, 2005ASAssignment
Owner name: SYNOPSYS, INC., CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:SYNOPSYS MERGER HOLDINGS LLC;REEL/FRAME:015653/0738
Effective date: 20041223
Dec 22, 2009ASAssignment
Owner name: SYNOPSYS MERGER HOLDINGS LLC, CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:NUMERICAL TECHNOLOGIES, INC.;REEL/FRAME:023688/0923
Effective date: 20091216