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Publication numberUS20030062614 A1
Publication typeApplication
Application numberUS 10/291,025
Publication dateApr 3, 2003
Filing dateNov 7, 2002
Priority dateMar 21, 2001
Also published asUS6884653, US6982869, US20020137252, US20030069654, US20060242477
Publication number10291025, 291025, US 2003/0062614 A1, US 2003/062614 A1, US 20030062614 A1, US 20030062614A1, US 2003062614 A1, US 2003062614A1, US-A1-20030062614, US-A1-2003062614, US2003/0062614A1, US2003/062614A1, US20030062614 A1, US20030062614A1, US2003062614 A1, US2003062614A1
InventorsCharles Larson
Original AssigneeLarson Charles E.
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Folded interposer
US 20030062614 A1
Abstract
A folded interposer used to achieve a high density semiconductor package is disclosed. The folded interposer is comprised of a thin, flexible material that can be folded around one or multiple semiconductor die in a serpentine fashion. The semiconductor die are then attached to a substrate through electrical contacts on the interposer. The folded interposer allows multiple semiconductor die to be efficiently stacked in a high density semiconductor package by reducing the unused or wasted space between stacked semiconductor die. Vias extending through the folded interposer provide electrical communication between the semiconductor die and the substrate. The present invention also relates to a method of packaging semiconductor die in a high density arrangement and a method of forming the high density semiconductor package.
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Claims(30)
What is claimed is:
1. A folded interposer comprising:
a thin, flexible material comprised of a first surface and a second surface, said material for folding around at least one semiconductor die having substantially the same width as said at least one semiconductor die;
a plurality of vias extending from said first surface to said second surface; and
a plurality of electrical contacts on said first surface of said material.
2. The interposer of claim 1, wherein said material comprises an insulative polymer.
3. The interposer of claim 2, wherein said material further comprises a thermally conductive material.
4. The interposer of claim 1, wherein said second surface surrounds at least three sides of one semiconductor die around which said interposer is folded.
5. The interposer of claim 1, wherein said second surface surrounds at least two sides of said at least one semiconductor die around when said interposer is folded.
6. The interposer of claim 1, wherein said electrical contacts are applied to said second surface of said interposer.
7. A high density semiconductor package having at least two semiconductor die comprising:
a substrate having at least one contact pad on a surface thereof; and
a flexible interposer folded around a first semiconductor die of said at least two semiconductor die, said interposer including a first surface having a plurality of electrical contacts for electrically connecting the first semiconductor die to a substrate, a second surface, and a plurality of vias extending through said interposer from said first surface to said second surface, the first semiconductor die having a plurality of bond pads on a surface thereof and a back surface, the first semiconductor die positioned in a back-to-back configuration with another semiconductor die of said at least two semiconductor die and attached to said interposer to form an intermediate packaging structure; at least one contact of said plurality of contacts of said flexible interposer connected to the at least one contact pad of said substrate.
8. The package of claim 7, wherein said vias are filled with conductive metal.
9. The package of claim 7, wherein said second surface surrounds at least three sides of the first semiconductor die around which said interposer is folded.
10. The package of claim 7, wherein said second surface surrounds at least two sides of the first semiconductor die around which said interposer is folded.
11. The package of claim 7, wherein at least one bond pad of said bond pads of said first semiconductor die is in electrical communication with at least one electrical contact of said electrical contacts of said flexible interposer through said vias therein.
12. The package of claim 7, wherein said interposer folds around more than two semiconductor die by weaving in a serpentine fashion around groups of semiconductor die including two semiconductor die.
13. The package of claim 7, wherein said substrate comprises a semiconductor device.
14. The package of claim 7, wherein said substrate further comprises a printed circuit board.
15. The package of claim 7, further comprising electrical contacts applied to a top surface of said package.
16. An interposer comprising:
a thin, flexible material comprised of a first surface and a second surface, said material for folding around at least one semiconductor die having substantially the same width as said at least one semiconductor die;
a plurality of vias extending from said first surface to said second surface; and
a plurality of electrical contacts on said first surface of said material.
17. The interposer of claim 16, wherein said material comprises an insulative polymer.
18 The interposer of claim 17, wherein said material further comprises a thermally conductive material.
19. The interposer of claim 16, wherein said second surface surrounds at least three sides of one semiconductor die around which said interposer is folded.
20. The interposer of claim 16, wherein said second surface surrounds at least two sides of said at least one semiconductor die around when said interposer is folded.
21. The interposer of claim 16, wherein said electrical contacts are applied to said second surface of said interposer.
22. A high density semiconductor package having a plurality of semiconductor die comprising:
a substrate having at least one contact pad on a surface thereof; and
a flexible interposer folded around a first semiconductor die of said at least two semiconductor die, said interposer including a first surface having a plurality of electrical contacts for electrically connecting the first semiconductor die to a substrate, a second surface, and a plurality of vias extending through said interposer from said first surface to said second surface, the first semiconductor die having a plurality of bond pads on a surface thereof and a back surface, the first semiconductor die positioned in a back-to-back configuration with another semiconductor die of said at least two semiconductor die and attached to said interposer to form an intermediate packaging structure; at least one contact of said plurality of contacts of said flexible interposer connected to the at least one contact pad of said substrate.
23. The package of claim 22, wherein said vias are filled with conductive metal.
24. The package of claim 22, wherein said second surface surrounds at least three sides of the first semiconductor die around which said interposer is folded.
25. The package of claim 22, wherein said second surface surrounds at least two sides of the first semiconductor die around which said interposer is folded.
26. The package of claim 22, wherein at least one bond pad of said bond pads of said first semiconductor die is in electrical communication with at least one electrical contact of said electrical contacts of said flexible interposer through said vias therein.
27. The package of claim 22, wherein said interposer folds around more than two semiconductor die by weaving in a serpentine fashion around groups of semiconductor die including two semiconductor die.
28. The package of claim 22, wherein said substrate comprises a semiconductor device.
29. The package of claim 22, wherein said substrate further comprises a printed circuit board.
30. The package of claim 22, further comprising electrical contacts applied to a top surface of said package.
Description
    CROSS-REFERENCE TO RELATED APPLICATION
  • [0001]
    This application is a divisional of application Ser. No. 09/813,724, filed Mar. 21, 2001, pending.
  • BACKGROUND OF THE INVENTION
  • [0002]
    1. Field of the Invention
  • [0003]
    The present invention relates to a semiconductor die package. More particularly, the present invention relates to a folded interposer used to increase the semiconductor die density of a high density semiconductor package.
  • [0004]
    2. Background of Related Art
  • [0005]
    As electronic devices, such as cell phones and personal digital assistants (“PDAs”), become smaller, more portable, and more technologically advanced, there is an increasing need for high density semiconductor die packages that can provide the necessary memory for these devices. New, high density semiconductor packages must be easily and cheaply manufactured with existing equipment. In addition, the package must maintain the reliability and quality of the semiconductor die. A semiconductor die package contains many electrical circuit components that must be interconnected to form functional, integrated circuits.
  • [0006]
    Consumers want their portable devices to perform the same functions as their desktop computers, therefore requiring large amounts of memory in a much smaller electronic device. One way of accomplishing this is to increase the density of a semiconductor die package by using the package's real estate more efficiently. One advantage of high density packaging is that it decreases the length of the connections between the semiconductor die and the package, allowing the semiconductor die to respond faster. Also, reducing the length of the connections reduces the signal propagation time and makes the signal paths less vulnerable to the affects of noise.
  • [0007]
    Numerous high density semiconductor packages exist in the art. However, these packages are ill-suited for use in small, portable electronic devices because they inefficiently use their real estate, which unnecessarily adds to the overall size of the package. For instance, U.S. Pat. No. 5,128,831 issued to Fox, III et al. teaches a high density package composed of multiple submodules, each of which contains a chip bonded to a substrate. A spacer, which is at least as thick as the chip, is adhesively bonded to the peripheral upper surface of each submodule before the submodules are stacked to form the high density package. The thickness of the spacer causes a gap between each submodule. When multiple submodules are needed, the cumulative effect of these gaps makes the package significantly larger than the size of the components used in the package.
  • [0008]
    A multichip module comprised of stacked semiconductor dice is disclosed in U.S. Pat. No. 5,323,060, issued to Fogal et al. The semiconductor dice are electrically connected to a substrate by extending long bond wires from bond pads on each semiconductor die to the substrate. In order to accommodate the loop height of the bond wires, a thick adhesive layer is applied between the semiconductor dice. The adhesive layer must be thick enough that the bond wires of the lower semiconductor die do not contact the upper semiconductor die. This multichip module is not suited for small electronic devices because the adhesive layer between the dice increases the overall thickness of the semiconductor package.
  • [0009]
    U.S. Pat. No. 5,604,377 issued to Palagonia teaches a stack of semiconductor chips designed to be lightweight and to provide better cooling, mechanical shock, and vibration protection. The chips are separated by rigid, insulating interposers formed from a rack structure that contains shelves. The shelves provide electrical insulation and mechanical protection to the chips. The rigid shelves also prevent undue movement of the chips, while the spacing between shelves allows for adequate heat dissipation. Since the shelves are rigid and provide space between the chips, the packaging scheme is not suited for use in small electronic devices.
  • [0010]
    U.S. Pat. No. 5,818,197 issued to Pierson et al. teaches an integrated circuit package that utilizes metallization features, located at opposite edges of each chip, to attach a stack of chips to a substrate. The chips are bonded together through their metallization features to form a chip stack, which is then bonded to the substrate. The thickness of the metallization features, in addition to the bonding material used, provides a “stand off” or separation between chips. This separation adds to the overall thickness of the integrated circuit package, making it incompatible for use in electronic devices that require small semiconductor packages.
  • [0011]
    In U.S. Pat. No. 5,994,166 issued to Akram et al. a dense semiconductor package comprising multiple substrates with attached flip-chips is disclosed. The substrates are stacked on top of one another. Column-like connections positioned between the stacked substrates provide electrical communication. The electrical connections must be of sufficient height to provide enough clearance between substrates to mount components and also must be of sufficient strength to provide support between the substrates. Since the column-like connections cause unused space between the substrates, this semiconductor package is incompatible with electronic devices that require small semiconductor packages.
  • [0012]
    While numerous high density semiconductor packages exist, they share a common disadvantage in that they inefficiently use the space of the semiconductor package. The unused or wasted space may be the result of thick adhesive layers between semiconductor dice or may be caused by rigid interposers or other spacers. Small electronic devices, such as cell phones and PDAs, have very limited space and cannot afford to waste any of this space. Reducing the wasted or unused space in a semiconductor die package is essential because large packages occupy too much of this limited space. It would be preferable to reduce the unused or wasted space in a stack of semiconductor dice by more closely spacing the semiconductor dice. It would be more preferable for the semiconductor dice to be spaced substantially one on top of another. It would be most preferable for the overall size of a high density semiconductor package to be caused only by the thickness of the semiconductor die and a substrate, without substantial thickness coming from additional packaging or unused space.
  • [0013]
    Methods for connecting die to a substrate are well known in the art. For example, wire bonding, tape automated bonding (“TAB”), and controlled collapse chip connection (“C4”) are commonly used to physically and electrically connect semiconductor dice to a substrate. Wire bonding utilizes fine wire conductors bonded on one end to the substrate and on the other end to electrical contacts on the semiconductor die. Because wire bonding requires wires to be welded to the die, there must be adequate space to accommodate the wires. TAB utilizes patterned metal on a polymeric tape to join dice together. The joined semiconductor dice are attached to a substrate by outer lead bonding. C4, or flip-chip, bonding uses solder balls on the surface of a semiconductor die to bond the semiconductor die to a substrate.
  • [0014]
    In addition to the above-mentioned methods, the prior art also discloses using vias to attach a semiconductor die to a substrate and to provide electrical communication between the semiconductor die and substrate. The vias may be filled with conductive metal or flexible leads may be run through the vias to provide electrical communication. As mentioned above, U.S. Pat. No. 5,128,831 issued to Fox, III et al. teaches a high density package composed of multiple submodules, each of which contain a chip bonded to a substrate. Each substrate has a metallization pattern, which comprises multiple conductive traces. A spacer is adhesively bonded to the peripheral upper surface of each submodule before the submodules are stacked. Both the substrate and spacer contain vias that are coincident and substantially coaxial to each other when the package is assembled. The vias are filled with solder to electrically connect the traces of all the submodules. Similarly, U.S. Pat. No. 5,148,266 issued to Kane et al., mentioned in more detail below, uses solid vias to electrically interconnect two chips on opposite sides of a flexible carrier.
  • [0015]
    U.S. Pat. Nos. 5,252,857 and 5,682,061 issued to Khandros et al. disclose a semiconductor chip assembly containing a semiconductor chip and a substrate that are separated by an interposer. The interposer contains multiple apertures that extend from the first surface to the second surface of the interposer. Flexible leads extending through the apertures are used to connect the chip to terminals on the interposer. The interposer terminals are then connected to contact pads on the substrate. The flexible leads allow for movement of the contacts on the chip relative to the contacts on the substrate, thereby reducing the stresses caused by thermal cycling.
  • [0016]
    The semiconductor die industry has commonly used flexible components to ameliorate the problems associated with differential thermal expansion of a semiconductor die and substrate. If a die and substrate have different coefficients of expansion, the heat generated by operating an electronic device causes the die and substrate to expand at different rates. When the electronic device is turned off, the semiconductor die and substrate contract at different rates. Over time, these heat cycles place a large amount of mechanical stress on the electrical contacts and solder connections between the semiconductor die and substrate. After repeated cycles, the contacts and connections may fail. The semiconductor die industry has recognized two ways around this problem. First, the mechanical stress on the electrical contacts and solder connections can be minimized by using components that have similar coefficients of expansion. However, this severely limits the types of components that can be used together. A second way around this problem is to incorporate flexible components into the die package. Flexible components known in the art include interposers, circuits, circuit boards, and leads. For example, U.S. Pat. No. 4,851,613 issued to Jacques teaches a flexible circuit board that can be bent, rolled, or folded into a desired shape. The circuit board comprises a substrate, a layer of conductive material in which a circuit is formed, and an insulating layer. Surface mount devices, such as resistors, capacitors, and integrated circuits, can be mounted to the flexible circuit board. Use of the flexible circuit board allows for thermal expansion between the surface mount devices and circuit board without cracking solder joints or breaking electrical and physical connections.
  • [0017]
    In U.S. Pat. Nos. 5,148,266 and 5,682,061 issued to Khandros et al., a semiconductor chip assembly containing an interposer and flexible leads is disclosed. The interposer separates a semiconductor chip and a substrate. The chip and substrate electrically communicate through flexible leads that run through apertures in the interposer. The leads connect the chip to terminals on the interposer, which are then connected to contact pads on the substrate. The flexible leads allow for movement of the contacts on the chip and, therefore, reduce the stresses caused by thermal cycling.
  • [0018]
    U.S. Pat. No. 5,889,652 issued to Turturro teaches an integrated circuit package comprising an integrated circuit attached to a substrate. The substrate includes two portions, a bond portion and a contact portion, separated by a flexible portion. The integrated circuit is attached to the bond portion of the substrate, while the contact portion is attached to a printed circuit board. The flexible portion of the substrate allows for relative movement between the package and the circuit board, minimizing thermal expansion stress on the solder joints.
  • [0019]
    U.S. Pat. No. 6,002,590 issued to Famworth et al. teaches a printed circuit board that contains traces attached to a flexible trace surface. Components, such as ball grid array (“BGA”) components, are attached to the traces. The flexible trace surface may be created by the top surfaces of flexible protuberances, which are formed by etching away substrate not covered by the traces. Alternatively, the flexible trace surface may be formed by depositing a flexible layer onto the printed circuit board. The flexible trace surface allows the traces to be displaced in a direction of thermal expansion of the attached components, thus preventing cracking of solder joints between the trace and component.
  • [0020]
    U.S. Pat. No. 6,014,320 issued to Mahon et al. teaches a high density circuit module that is comprised of a flex circuit attached to a substrate. The flex circuit is attached to one side of the substrate and folded over to the other side of the substrate. The resulting module includes integrated circuits on one side of the substrate and input/output pads on the opposite side.
  • [0021]
    While the above-mentioned inventions disclose flexible components in semiconductor die packages, they only disclose attaching one semiconductor die to a substrate. Since high density semiconductor packages are necessary for new generations of electronic devices, it would be preferable to combine flexible components with semiconductor die packages that can accommodate multiple semiconductor dice.
  • [0022]
    U.S. Pat. No. 5,252,857 issued to Kane et al., discloses both of these features. A dense memory package is disclosed where two memory chips are mounted face-to-face on opposite sides of a flexible carrier or interposer. The two chips contain solder bumps that align when the chips are placed face to face. In addition, the interposer contains pads that are coated with low melting point solder. The bumps on the chips contact the pads on the interposer and are soldered together. Kane also discloses a plurality of pairs of chips mounted on opposite sides of a flexible carrier. The flexible carrier with the attached chips can be folded to connect with substrates, such as printed circuit boards. While Kane discloses a flexible carrier that can be used to connect multiple die to a printed circuit board or backplane, Kane discloses that the pairs of dice are mounted face-to-face on opposite sides of the flexible carrier.
  • [0023]
    The present invention solves the above-mentioned problems. The present invention discloses a high density semiconductor package that has reduced or eliminated the unused space between stacked semiconductor die. The resulting high density semiconductor package of the present invention is small, and is, therefore, useful in portable electronic devices such as cell phones and PDAs.
  • SUMMARY OF THE INVENTION
  • [0024]
    The present invention relates to a folded interposer and a high density semiconductor package that utilizes the folded interposer. The folded interposer is comprised of a thin, flexible material that can be folded around one or multiple semiconductor dice. The folded interposer allows multiple semiconductor dice to be efficiently stacked in a high density semiconductor package by reducing the unused or wasted space between stacked semiconductor dice. The present invention also relates to a method of packaging semiconductor dice in a high density arrangement and a method of forming the high density semiconductor die package. Finally, the present invention relates to a computer system that incorporates the folded interposer in a high density semiconductor die package.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • [0025]
    While the specification concludes with claims particularly pointing out and distinctly claiming the present invention, the advantages of the invention can be more readily ascertained from the following detailed description of the invention when read in conjunction with the accompanying drawings in which:
  • [0026]
    [0026]FIG. 1 is a side view of an interposer of the present invention;
  • [0027]
    [0027]FIG. 2 is a side view of an interposer of the present invention folded around one semiconductor die;
  • [0028]
    [0028]FIG. 3 is a side view of an interposer of the present invention folded around two semiconductor dice;
  • [0029]
    [0029]FIG. 4 is a side view of an interposer of the present invention folded around two semiconductor dice and attached to a substrate;
  • [0030]
    [0030]FIG. 5 is a side view of an interposer of the present invention folded in a serpentine fashion around more than two semiconductor dice; and
  • [0031]
    [0031]FIG. 6 is a side view of an interposer of the present invention showing electrical contacts on the top surface of the structure.
  • DETAILED DESCRIPTION OF THE INVENTION
  • [0032]
    Illustrated in drawing FIG. 1 is an interposer 10, which includes a first surface 16 and a second surface 18. The first surface 16 includes electrical contacts 20 for attaching the interposer 10 to a substrate (not shown), such as a printed circuit board. Vias 24 extend through the interposer 10 from the first surface 16 to the second surface 18 and are in communication with the electrical contacts 20. The folded interposer 10 is comprised of a thin, flexible material, such as an insulative polymer. The material has substantially the same width as a semiconductor die so that the material covers the surface of the semiconductor die. Preferably, the material should also be thermally conductive to allow for adequate dissipation of heat generated by the electrical circuitry.
  • [0033]
    As illustrated in drawing FIGS. 2 and 3, the interposer 10 is flexible enough to fold around one or multiple semiconductor dice 12. Preferably, the semiconductor dice 12 are bare, unpackaged die. As is illustrated in drawing FIG. 2 (vias not shown), the interposer 10 surrounds at least three sides of one semiconductor die 12, to form an intermediate packaging structure 28. Illustrated in drawing FIG. 3 (vias not shown) is an intermediate packaging structure 28 containing multiple semiconductor dice 12, wherein the interposer 10 surrounds at least two sides of each semiconductor die.
  • [0034]
    Methods of attaching a semiconductor die to a substrate are well known in the art. Any means known in the art for attaching the semiconductor die to the interposer may be used in the present invention. Intermediate packaging structure 28, which includes the interposer 10 and attached semiconductor die 12, is attached to a substrate to form a high density semiconductor package 14 (see FIG. 4).
  • [0035]
    The present invention also relates to a high density semiconductor die package 14 utilizing the folded interposer 10. As is best illustrated in drawing FIGS. 4 through 6, the folded interposer 10 is used to attach one or multiple semiconductor dice 12 to a substrate 22, thus forming the high density semiconductor package 14. The interposer 10, which has two surfaces, is folded around the semiconductor die 12 to form intermediate packaging structure 28. As is best illustrated in drawing FIG. 2 (vias not shown), the interposer 10 surrounds at least three sides of one semiconductor die 12 in intermediate packaging structure 28. Illustrated in drawing FIG. 3 (vias not shown) is an intermediate packaging structure 28 containing two semiconductor dice 12, wherein the interposer 10 surrounds at least two sides of each semiconductor die. Since the bond pads 26 of each semiconductor die must be in contact with vias 24, multiple semiconductor die 12 must be positioned in groups of two in a back-to-back configuration so that all semiconductor die 12 are in electrical communication with substrate 22. Intermediate packaging structure 28 is then attached to the substrate 22 through the electrical contacts 20 on the first surface 16 of the interposer. The substrate 22 may be any type of semiconductor substrate known in the art, such as a printed circuit board. The semiconductor die 12 and substrate 22 are in electrical communication through the bond pads 26 and the electrical contacts 20, which are in contact with the vias 24. The vias 24 may be filled with a conductive material to provide electrical communication between the semiconductor die 12 and substrate 22.
  • [0036]
    The high density semiconductor die package 14 accommodates more than two semiconductor die by weaving the flexible interposer 10 around groups of two semiconductor dice. Since the bond pads 26 of each die must be in contact with vias 24, the two semiconductor dice 12 must be positioned in a back-to-back configuration so that all semiconductor dice 12 are in electrical communication with substrate 22. As is illustrated in drawing FIG. 5 (bond pads and vias not shown), the interposer weaves in a serpentine fashion between groups of two semiconductor dice.
  • [0037]
    As is illustrated in drawing FIG. 5 (bond pads, vias, and substrate not shown), the present invention also relates to a method of packaging semiconductor dice in a high density arrangement. The semiconductor dice are packaged by providing at least one semiconductor die 12, a flexible interposer 10, and a substrate 22. The interposer 10 is folded around and attached to the semiconductor dice 12. The interposer 10 has a first surface 16, a second surface 18, and vias 24 that extend through the interposer 10 from the first surface 16 to the second surface 18. The first surface 16 includes electrical contacts 20. The semiconductor dice 12 are attached to the interposer 10 through bond pads 26 on the active surface of the semiconductor die 12 to form intermediate packaging structure 28. Intermediate packaging structure 28 is then attached to substrate 22 through the electrical contacts 20 to form a high density semiconductor package 14. This attachment also results in electrical communication between the semiconductor die 12 and the substrate 22. In a high density semiconductor package 14 containing one semiconductor die 12, the interposer 10 is folded around the semiconductor die 12 so that at least three sides of the semiconductor die are surrounded, as is illustrated in drawing FIG. 2 (vias and substrate not shown). In a high density semiconductor package 14 containing two semiconductor dice 12, the interposer 10 surrounds at least two sides of each semiconductor die 12, as is illustrated in drawing FIG. 3 (vias and substrate not shown). Illustrated in drawing FIG. 5 (bond pads, vias, and substrate not shown) is that the interposer 10 weaves in a serpentine fashion between semiconductor die 12 stacked in groups of two when a high density semiconductor package 14 containing more than two semiconductor dice 12 is desired. Additionally, electrical contacts 20 may be applied to a top surface 30 of the package 14, as is shown in drawing FIG. 6 (bond pads, vias, and substrate not shown), so that the package 14 can be attached to other semiconductor devices, depending on the desired application.
  • [0038]
    The present invention also relates to a method of forming a high density semiconductor die package 14. The high density semiconductor die package 14 is formed by providing the interposer 10 and at least one semiconductor die 12. The semiconductor die 12 are attached to the interposer 10 to form intermediate packaging structure 28. The intermediate packaging structure 28 is attached to substrate 22 through methods well known in the art, such as wire bonding, C4, TAB, and bonding through vias. In applications where more than two semiconductor dice are desired, the semiconductor die 12 are attached to the interposer 10 in groups of two in a back-to-back configuration. Electrical connection between the substrate 22 and semiconductor die 12 is established through the electrical contacts 20 and vias 24 on the interposer 10. Additionally, electrical contacts 20 may be applied to a top surface 30 of the package 14, as is shown in drawing FIG. 6 (bond pads and vias not shown), so that the package 14 can be attached to other semiconductor devices, depending on the desired application.
  • [0039]
    The present invention also relates to a computer system using the folded interposer 10 and high density semiconductor die package 14. The computer system is comprised of an input device, an output device, a processor, and a memory module. The processor is coupled to the input and output devices. The memory module is coupled to the processor. The memory module includes a module board and the high density semiconductor package 14, which are in electrical contact with each other. The high density semiconductor package 14 utilizes the folded interposer 10 as has been described above.
  • [0040]
    Although specific examples demonstrating the present invention have been described, it is to be understood that the invention defined by the appended claims is not to be limited by the particular details set forth in the above description. One of ordinary skill in the art would understand that many apparent variations are possible without departing from the scope of the appended claims. For example, varying the number of semiconductor die in the high density semiconductor die package would be understood to be within the scope of the appended claims. In addition, varying the methods of attaching the die to the interposer and/or the substrate and the methods of achieving electrical communication between the semiconductor die and substrate would be understood to be within the scope of the appended claims.
Patent Citations
Cited PatentFiling datePublication dateApplicantTitle
US4851613 *Jun 8, 1988Jul 25, 1989Flex Technology, Inc.Flexible circuit laminate for surface mount devices
US5128831 *Oct 31, 1991Jul 7, 1992Micron Technology, Inc.High-density electronic package comprising stacked sub-modules which are electrically interconnected by solder-filled vias
US5148266 *Sep 24, 1990Sep 15, 1992Ist Associates, Inc.Semiconductor chip assemblies having interposer and flexible lead
US5252857 *Aug 5, 1991Oct 12, 1993International Business Machines CorporationStacked DCA memory chips
US5266912 *Aug 19, 1992Nov 30, 1993Micron Technology, Inc.Inherently impedance matched multiple integrated circuit module
US5323060 *Jun 2, 1993Jun 21, 1994Micron Semiconductor, Inc.Multichip module having a stacked chip arrangement
US5585675 *May 11, 1994Dec 17, 1996Harris CorporationSemiconductor die packaging tub having angularly offset pad-to-pad via structure configured to allow three-dimensional stacking and electrical interconnections among multiple identical tubs
US5600183 *Nov 15, 1994Feb 4, 1997Hughes ElectronicsMulti-layer film adhesive for electrically isolating and grounding an integrated circuit chip to a printed circuit substrate
US5604377 *Oct 10, 1995Feb 18, 1997International Business Machines Corp.Semiconductor chip high density packaging
US5682061 *Jun 5, 1995Oct 28, 1997Tessera, Inc.Component for connecting a semiconductor chip to a substrate
US5818107 *Jan 17, 1997Oct 6, 1998International Business Machines CorporationChip stacking by edge metallization
US5889652 *Apr 21, 1997Mar 30, 1999Intel CorporationC4-GT stand off rigid flex interposer
US5900738 *Oct 21, 1996May 4, 1999Formfactor, Inc.Contact structure device for interconnections, interposer, semiconductor assembly and package using the same and method
US5994166 *Mar 10, 1997Nov 30, 1999Micron Technology, Inc.Method of constructing stacked packages
US6002590 *Mar 24, 1998Dec 14, 1999Micron Technology, Inc.Flexible trace surface circuit board and method for making flexible trace surface circuit board
US6014320 *Mar 30, 1998Jan 11, 2000Hei, Inc.High density stacked circuit module
US6020749 *Nov 12, 1996Feb 1, 2000Hewlett-Packard CompanyMethod and apparatus for performing testing of double-sided ball grid array devices
US6097611 *Sep 17, 1999Aug 1, 2000Intel CorporationMulti-chip land grid array carrier
US6121676 *Dec 11, 1997Sep 19, 2000Tessera, Inc.Stacked microelectronic assembly and method therefor
US6225688 *Feb 4, 1999May 1, 2001Tessera, Inc.Stacked microelectronic assembly and method therefor
US6281577 *Apr 22, 1997Aug 28, 2001Pac Tech-Packaging Technologies GmbhChips arranged in plurality of planes and electrically connected to one another
US6300679 *Jun 1, 1998Oct 9, 2001Semiconductor Components Industries, LlcFlexible substrate for packaging a semiconductor component
US6444921 *Feb 3, 2000Sep 3, 2002Fujitsu LimitedReduced stress and zero stress interposers for integrated-circuit chips, multichip substrates, and the like
US6473308 *Apr 19, 2001Oct 29, 2002John A. ForthunStackable chip package with flex carrier
US6552910 *Jun 28, 2000Apr 22, 2003Micron Technology, Inc.Stacked-die assemblies with a plurality of microelectronic devices and methods of manufacture
US6699730 *Feb 2, 2001Mar 2, 2004Tessers, Inc.Stacked microelectronic assembly and method therefor
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US6724090 *Jan 8, 2003Apr 20, 2004Hynix Semiconductor Inc.Multi-chip package and method for manufacturing the same
US6927497 *Aug 22, 2002Aug 9, 2005Intel CorporationMulti-die semiconductor package
US6969906 *Feb 26, 2004Nov 29, 2005Hynix Semiconductor Inc.Multi-chip package and method for manufacturing the same
US6982869 *Nov 7, 2002Jan 3, 2006Micron Technology, Inc.Folded interposer
US7145249Mar 29, 2004Dec 5, 2006Intel CorporationSemiconducting device with folded interposer
US7288433 *Jun 20, 2005Oct 30, 2007Tessera, Inc.Method of making assemblies having stacked semiconductor chips
US7378725Mar 31, 2004May 27, 2008Intel CorporationSemiconducting device with stacked dice
US7456048Sep 22, 2006Nov 25, 2008Intel CorporationSemiconducting device with folded interposer
US7482698Sep 22, 2006Jan 27, 2009Intel CorporationSemiconducting device with folded interposer
US7498201Jun 27, 2005Mar 3, 2009Intel CorporationMethod of forming a multi-die semiconductor package
US8058145 *Nov 15, 2011Semiconductor Energy Laboratory Co., Ltd.Micro-electro-mechanical device and manufacturing method for the same
US8552473Nov 2, 2011Oct 8, 2013Semiconductor Energy Laboratory Co., Ltd.Micro-electro-mechanical device and manufacturing method for the same
US9086874 *Jun 7, 2012Jul 21, 2015Morgan/Weiss Technologies Inc.Above motherboard interposer with quarter wavelength electrical paths
US9357648Jul 2, 2015May 31, 2016Morgan/Weiss Technologies Inc.Above motherboard interposer with quarter wavelength electrical paths
US20030197283 *Jan 8, 2003Oct 23, 2003Shin ChoiMulti-chip package and method for manufacturing the same
US20040036163 *Aug 22, 2002Feb 26, 2004Intel CorporationMulti-die semiconductor package
US20040164394 *Feb 26, 2004Aug 26, 2004Shin ChoiMulti-chip package and method for manufacturing the same
US20050212112 *Mar 29, 2004Sep 29, 2005Intel CorporationSemiconducting device with folded interposer
US20050224943 *Mar 31, 2004Oct 13, 2005Sahaida Scott RSemiconducting device with stacked dice
US20050233496 *Jun 20, 2005Oct 20, 2005Tessera, Inc.Method of making assemblies having stacked semiconductor chips
US20050233497 *Jun 27, 2005Oct 20, 2005Intel CorporationMethod of forming a multi-die semiconductor package
US20050285254 *Jun 23, 2004Dec 29, 2005Buot Joan R VSemiconducting device having stacked dice
US20070023905 *Sep 22, 2006Feb 1, 2007Intel CorporationSemiconducting device with folded interposer
US20070026569 *Sep 22, 2006Feb 1, 2007Intel CorporationSemiconducting device with folded interposer
US20100285627 *Jul 23, 2010Nov 11, 2010Semiconductor Energy Laboratory Co., Ltd.Micro-electro-mechanical device and manufacturing method for the same
US20120262862 *Jun 7, 2012Oct 18, 2012Morgan JohnsonAbove motherboard interposer with quarter wavelength electical paths
Classifications
U.S. Classification257/688, 257/691, 438/109, 257/E25.013, 257/737, 257/E23.177, 257/723, 257/693, 257/780
International ClassificationH01L23/538, H01L25/065
Cooperative ClassificationH05K1/147, H05K2201/10378, H01L25/0657, H01L23/5387, H01L2225/06579, H01L23/4985, H01L2225/06517, H01L2224/16
European ClassificationH01L23/498J, H01L25/065S, H01L23/538J