US 20030062922 A1 Abstract Interconnecting logic provides connectivity of an embedded fixed logic circuit, or circuits, with programmable logic fabric of a programmable gate array such that the fixed logic circuit functions as an extension of the programmable logic fabric. The interconnecting logic includes interconnecting tiles and may further include interfacing logic. The interconnecting tiles provide selective connectivity between inputs and/or outputs of the fixed logic circuit and the interconnects of the programmable logic fabric. The interfacing logic, when included, provides logic circuitry that conditions data transfers between the fixed logic circuit and the programmable logic fabric.
Claims(1) 1. A programmable gate array comprising: programmable logic fabric;
fixed logic circuit having at least one input and at least one output, wherein the fixed logic circuit is physically located within the programmable logic fabric; and interconnecting logic operable to couple the at least one input and the at least one output of the fixed logic circuit to the programmable logic fabric. Description [0001] This invention relates generally to programmable gate arrays and in particular to embedding fixed logic circuits within such programmable gate arrays. [0002] Programmable devices are a class of general-purpose integrated circuits that can be configured for a wide variety of applications. Such programmable devices have two basic versions, mask programmable devices, which are programmed only by a manufacture, and field programmable devices, which are programmable by the end user. In addition, programmable devices can be further categorized as programmable memory devices or programmable logic devices. Programmable memory devices include programmable read only memory (PROM), erasable programmable read only memory (EPROM) and electronically erasable programmable read only memory (EEPROM). Programmable logic devices include programmable logic array (PLA) devices, programmable array logic (PAL) devices, erasable programmable logic devices (EPLD) devices, and programmable gate arrays (PGA). [0003] Field programmable gate arrays (FPGA) have become very popular for telecommunication applications, Internet applications, switching applications, routing applications, and a variety of other end user applications. FIG. 1 illustrates a generic schematic block diagram of a field programmable gate array (FPGA) [0004]FIG. 2 illustrates the programmable logic fabric [0005] The programmable interconnections [0006]FIG. 3 illustrates a schematic block diagram of the programmable logic fabric [0007]FIG. 4 illustrates a schematic block diagram of the programmable logic fabric [0008]FIG. 5 illustrates the programmable logic fabric [0009] As is known, field programmable gate arrays allow end users the flexibility of implementing custom integrated circuits while avoiding the initial cost, time delay and inherent risk of application specific integrated circuits (ASIC). While FPGAs have these advantages, there are some disadvantages. For instance, an FPGA programmed to perform a similar function as implemented in an ASIC can require more die area than the ASIC. Further, the performance of a design using a FPGA may in some cases be lower than that of a design implemented using an ASIC. [0010] One way to mitigate these disadvantages is to embed into an FPGA certain commonly used complex functions as fixed logic circuits. Therefore, a need exists for a programmable gate array that includes embedded fixed logic circuits yet retains programmable components. [0011]FIG. 1 illustrates a schematic block diagram of a prior art field programmable gate array; [0012]FIG. 2 illustrates a schematic block diagram of the programmable logic fabric of the programmable gate array of FIG. 1 being implemented in a symmetrical array configuration; [0013]FIG. 3 illustrates a schematic block diagram of the programmable logic fabric of the programmable gate array of FIG. 1 being implemented as a row based configuration; [0014]FIG. 4 illustrates a schematic block diagram of a programmable logic fabric of the programmable gate array of FIG. 1 being implemented as a column based configuration; [0015]FIG. 5 illustrates a schematic block diagram of the programmable logic fabric of the programmable gate array of FIG. 1 being implemented as a hierarchical programmable logic device configuration; [0016]FIG. 6 illustrates a graphical diagram of a programmable gate array in accordance with the present invention; [0017]FIG. 7 illustrates a graphical diagram of an alternate programmable gate array in accordance with the present invention; [0018]FIG. 8 illustrates a graphical diagram of another programmable gate array in accordance with the present invention; [0019]FIG. 9 illustrates a more detailed graphical diagram of the programmable gate array of FIG. 3; [0020]FIG. 10A illustrates a schematic block diagram of the interconnecting tiles and interfacing logic in accordance with the present invention; [0021]FIG. 10B illustrates a schematic block diagram of the interconnecting tiles and an embodiment of the interfacing logic in accordance with the present invention; [0022]FIG. 11 illustrates a schematic block diagram of the interconnecting tiles interfacing with the programmable logic fabric in accordance with the present invention; [0023]FIG. 12 illustrates a graphical diagram of yet another programmable gate array in accordance with the present invention; [0024]FIG. 13 illustrates a graphical diagram of a variation of the programmable gate array of FIG. 12; and [0025]FIG. 14 illustrates a graphical diagram of a further variation of the programmable gate array of FIG. 12. [0026] Generally, the present invention provides interconnecting logic that interfaces an embedded fixed logic circuit, or circuits, with programmable logic fabric of a programmable gate array. The interconnecting logic enables any fixed logic circuit (e.g., a digital signal processor, microprocessor, physical layer interface, link layer interface, network layer interface, audio processor, video graphics processor, and/or applications specific integrated circuit) to be embedded within the programmable logic fabric of a programmable gate array. In addition, the interconnecting logic provides connectivity between the fixed logic circuit and the programmable logic fabric such that the fixed logic circuit can be connected to any other blocks in the programmable logic fabric. [0027] The interconnecting logic includes interconnecting tiles and may further include interfacing logic. The interconnecting tiles provide programmable connectivity between inputs and/or outputs of the fixed logic circuit and the interconnects of the programmable logic fabric. The interfacing logic, when included, conditions signals between the fixed logic circuit and the programmable logic fabric. The signal conditioning can include data format changes, parallel-to-serial conversion, serial-to-parallel conversion, multiplexing, demultiplexing, performing logic functions and/or control signal generation, etc. With such interconnecting logic, any fixed logic circuit may be readily embedded within a programmable gate array to provide additional functionality to the end users of FPGAs. [0028] The present invention can be more fully described with reference to FIGS. 6 through 18. FIG. 6 illustrates a block diagram of a programmable gate array [0029] The fixed logic circuit [0030] The programmable logic fabric [0031] The programmable gate array [0032] In operation, the interconnecting logic [0033]FIG. 7 illustrates a graphical diagram of an alternate programmable gate array [0034] The 2 [0035]FIG. 8 illustrates a graphical diagram of another programmable gate array [0036] The construct of interconnecting logic [0037]FIG. 9 illustrates a more detailed graphical diagram of a portion of the programmable gate array [0038] As shown in FIG. 9, the programmable logic fabric [0039] As shown, the configurable logic blocks [0040] In the FPGA [0041] With the insertion of the fixed logic circuit [0042] The interfacing logic [0043]FIG. 10A illustrates a schematic block diagram of a microprocessor [0044] The interface logic [0045] The microprocessor [0046] The block RAM [0047] It should be noted that the block RAM [0048] A specific implementation of an interface logic is shown in FIG. 10B. To efficiently input and output signals from microprocessor [0049] As shown, demultiplexor [0050] Multiplexor [0051] It should be noted that memory [0052] Multiplexors [0053] As further shown in FIG. 10B, Multiplexor [0054] Demultiplexor [0055] The interfacing logic [0056] The interfacing logic [0057] The interfacing logic [0058] In this illustration, the control module [0059] The interfacing logic [0060] As one of average skill in the art will further appreciate, the interfacing logic [0061] As one of average skill in the art will still further appreciate, the circuitry embodying the interfacing logic [0062] As one of average skill in the art will also further appreciate, while FIG. 10B illustrates a microprocessor [0063]FIG. 11 illustrates a schematic block diagram of a few of the interconnecting tiles [0064] Each interconnecting tile contains a programmable switch matrix that is programmably connected to (a) a programmable switch matrix in the programmable logic fabric, (b) a termination tile (called herein “term tile”), and (c) adjacent interconnecting tiles. FIG. 11 shows six matrices labeled [0065] The structure of switch matrices [0066] The function of the term tiles is to terminate the interconnect lines and/or provide connectivity to the lines that are interrupted by the microprocessor [0067]FIG. 12 illustrates a schematic block diagram of an alternate programmable gate array [0068]FIG. 13 illustrates a variation of the gate array [0069]FIG. 14 illustrates a further variation of a programmable gate array [0070] From FIGS. [0071] The preceding discussion has presented a programmable gate array that includes interconnecting logic such that any fixed logic circuit may be embedded within the programmable logic fabric. Accordingly, the applications and versatility of such a programmable gate array is dramatically enhanced via the use of the present invention. As one of average skill in the art will appreciate, other embodiments may be derived from the teaching of the present invention without deviating from the scope of the claims. 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