US 20030071745 A1 Abstract One embodiment of the present invention provides a system for encoding a dataword into a current codeword within a stream of codewords, wherein each codeword in the stream has a substantially equal number of ones and zeros, and wherein each transition between codewords involves a substantially equal number of rising and falling transitions. The system creates the current codeword from the dataword and a preceding codeword in the stream by inverting substantially half of the zero bits of the preceding codeword and inverting substantially half of the one bits of the preceding codeword. This is accomplished by using the dataword to select one bits and the zero bits to invert; determining locations of the one bits and zero bits in the preceding codeword; and then inverting the selected one bits and zero bits in the preceding codeword to form the current codeword. Note that because the present invention balances rising and falling transitions without significantly increasing pin requirements, it achieves most of the electrical advantages of differential signaling along with most of the pin-efficiency of single-ended signaling. Moreover, by having substantially half the bits change at each transition, it is possible to determine timing information from transitions in the codeword, without the need for a separate clock signal.
Claims(24) 1. A method for encoding a dataword into a current codeword in a stream of codewords, wherein each codeword in the stream has a substantially equal number of ones and zeros, and wherein each transition between codewords involves a substantially equal number of rising and falling transitions, the method comprising:
receiving the dataword; and creating the current codeword from the dataword and a preceding codeword in the stream by inverting substantially half of the zero bits of the preceding codeword and inverting substantially half of the one bits of the preceding codeword; wherein inverting substantially half of the zero bits and substantially half of the one bits involves,
using the dataword to select one bits and the zero bits to invert,
determining locations of the one bits and zero bits in the preceding codeword, and
inverting the selected one bits and zero bits in the preceding codeword to form the current codeword.
2. The method of wherein there exists a predefined mapping between possible bit patterns for the dataword and corresponding inversion patterns for zero bits in the preceding codeword; and wherein there exists a predefined mapping between possible bit patterns for the dataword and corresponding inversion patterns for one bits in the preceding codeword. 3. The method of dividing the dataword into a first index and a second index; wherein selecting zero bits to invert involves using the first index to identify zero bits of the preceding codeword to invert; and wherein selecting one bits to invert involves using the second index to identify one bits of the preceding codeword to invert. 4. The method of wherein using the first index to identify zero bits of the preceding codeword to invert involves using the first index to calculate an inversion pattern for zero bits of the preceding codeword; and wherein using the second index to identify one bits of the preceding codeword to invert involves using the second index to calculate an inversion pattern for one bits of the preceding codeword. 5. The method of wherein using the first index to calculate an inversion pattern for zero bits of the preceding codeword involves using the first index to perform a lookup into a first table containing inversion patterns for zero bits of the preceding codeword; and wherein using the second index to calculate an inversion pattern for one bits of the preceding codeword involves using the second index to perform a lookup into a second table containing inversion patterns for one bits of the preceding codeword. 6. The method of 7. The method of 8. An apparatus that encodes a dataword into a current codeword in a stream of codewords, wherein each codeword in the stream has a substantially equal number of ones and zeros, and wherein each transition between codewords involves a substantially equal number of rising and falling transitions, the method comprising:
an input that is configured to receive the dataword and a preceding codeword in the stream of codewords; and an inverting circuit that is configured to create the current codeword from the dataword and the preceding codeword inverting substantially half of the zero bits of the preceding codeword and inverting substantially half of the one bits of the preceding codeword; wherein the inverting circuit is configured to,
use the dataword to select one bits and the zero bits to invert,
determine locations of the one bits and zero bits in the preceding codeword, and to
invert the selected one bits and zero bits in the preceding codeword to form the current codeword.
9. The apparatus of wherein there exists a predefined mapping between possible bit patterns for the dataword and corresponding inversion patterns for zero bits in the preceding codeword; and wherein there exists a predefined mapping between possible bit patterns for the dataword and corresponding inversion patterns for one bits in the preceding codeword. 10. The apparatus of a partitioning mechanism that is configured to partition the dataword into a first index and a second index; wherein the inverting circuit is configured to use the first index to identify zero bits of the preceding codeword to invert; and wherein the inverting circuit is configured to use the second index to identify one bits of the preceding codeword to invert. 11. The apparatus of wherein the inverting circuit is configured to use the first index to calculate an inversion pattern for zero bits of the preceding codeword; and wherein the inverting circuit is configured to use the second index to calculate an inversion pattern for one bits of the preceding codeword. 12. The apparatus of wherein the inverting circuit is configured to calculate the inversion pattern for zero bits by using the first index to perform a lookup into a first table containing inversion patterns for zero bits of the preceding codeword; and wherein the inverting circuit is configured to calculate the inversion pattern for one bits by using the second index to perform a lookup into a second table containing inversion patterns for one bits of the preceding codeword. 13. The apparatus of 14. The apparatus of 15. A method for decoding a current codeword into a dataword, the method comprising:
receiving a stream of codewords, including a preceding codeword and the current codeword, wherein each codeword in the stream has a substantially equal number of ones and zeros, and wherein each transition between codewords involves a substantially equal number of rising and falling transitions; identifying a pattern of bits that have been inverted in the preceding codeword to produce the current codeword; and translating the pattern of bits that have been inverted into the dataword, wherein the translation uses a predefined mapping between inversion patterns for bits in the preceding codeword and bit patterns for the dataword. 16. The method of wherein identifying the pattern of bits that have been inverted involves,
identifying a pattern of zero bits that have been inverted in the preceding codeword to produce the current codeword, and
identifying a pattern of one bits that have been inverted in the preceding codeword to produce the current codeword; and
wherein translating the pattern of bits into the dataword involves,
translating the pattern of zero bits into a first part of the dataword, wherein the translation uses a predefined mapping between inversion patterns for zero bits in the preceding codeword and bit patterns for the first part of the dataword, and
translating the pattern of one bits into a second part of the dataword,
wherein the translation uses a predefined mapping between inversion patterns for one bits in the preceding codeword and bit patterns for the second part of the dataword.
17. The method of producing a permutation that sorts the preceding codeword so that,
zeros and ones are separated,
relative ordering is maintained between ones, and
relative ordering is maintained between zeros; and
permuting the current codeword using the permutation to produce a permuted codeword,
wherein a first part of the permuted codeword contains the pattern of zero bits in the preceding codeword have been inverted, and
wherein a second part of the permuted codeword contains the pattern of one bits in the preceding codeword have been inverted. 18. The method of 19. The method of wherein translating the pattern of zero bits into the first part of the dataword involves using the pattern of zero bits to perform a lookup into a first table containing corresponding bit patterns for the first part of the dataword; and wherein translating the pattern of one bits into the second part of the dataword involves using the pattern of one bits to perform a lookup into a second table containing corresponding bit patterns for the second part of the dataword. 20. An apparatus for decoding a current codeword into a dataword, comprising:
an input that is configured to receive a stream of codewords, including a preceding codeword and the current codeword, wherein each codeword in the stream has a substantially equal number of ones and zeros, and wherein each transition between codewords involves a substantially equal number of rising and falling transitions; an identification circuit that is configured to identify a pattern of bits that have been inverted in the preceding codeword to produce the current codeword; and a translation circuit that is configured to translate the pattern of bits that have been inverted into the dataword based on a predefined mapping between inversion patterns for bits in the preceding codeword and bit patterns for the dataword. 21. The apparatus of wherein the identification circuit is configured to,
identify a pattern of zero bits that have been inverted in the preceding codeword to produce the current codeword, and to
identify a pattern of one bits that have been inverted in the preceding codeword to produce the current codeword; and
wherein the translation circuit is configured to,
translate the pattern of zero bits into a first part of the dataword based on a predefined mapping between inversion patterns for zero bits in the preceding codeword and bit patterns for the first part of the dataword, and to
translate the pattern of one bits into a second part of the dataword based on a predefined mapping between inversion patterns for one bits in the preceding codeword and bit patterns for the second part of the dataword.
22. The apparatus of wherein the identification circuit includes a permutation circuit;
wherein the permutation circuit is configured to produce a permutation that sorts the preceding codeword so that,
zeros and ones are separated,
relative ordering is maintained between ones, and
relative ordering is maintained between zeros; and
wherein the permutation circuit is configured to permute the current codeword using the permutation to produce a permuted codeword,
wherein a first part of the permuted codeword contains the pattern of zero bits in the preceding codeword have been inverted, and
wherein a second part of the permuted codeword contains the pattern of one bits in the preceding codeword have been inverted.
22. The apparatus of 24. The apparatus of wherein the translation circuit is configured to use the pattern of zero bits to perform a lookup into a first table containing corresponding bit patterns for the first part of the dataword; and wherein the translation circuit is configured to use the pattern of one bits to perform a lookup into a second table containing corresponding bit patterns for the second part of the dataword. Description [0001] This application hereby claims priority under 35 U.S.C. §119 to U.S. Provisional Patent Application No. 60/328,546 by inventor Mark R. Greenstreet, filed on Oct. 11, 2001. [0002] 1. Field of the Invention [0003] The present invention relates to techniques for transmitting data through electrical signals. More specifically, the present invention relates to a method and an apparatus for implementing a doubly balanced code, wherein each codeword has a substantially equal number of ones and zeros, and wherein each transition between codewords involves a substantially equal number of rising and falling transitions. [0004] 2. Related Art [0005] As processor clock speeds continue to increase at an exponential rate, data must be transferred at correspondingly faster rates between computer system components. Computer systems typically use large parallel busses for this purpose. [0006] These large parallel busses typically use either single-ended signaling or differential signaling. Single-ended signaling makes use of a single signal line to carry each bit, along with one or more clock lines to latch the signals. [0007] In contrast, differential signaling uses two signal lines to carry each bit, wherein the value of the bit is indicated by a voltage difference between the two signal lines. Because currents are balanced between power and ground rails, differential signaling reduces power supply noise and solves the problem of where return currents come from. Moreover, differential signaling is less sensitive to ground shifts between sender and receiver because differential signaling relies on voltage differences between pairs of signal lines, instead of relying on an absolute voltage level of a single signal line. [0008] Unfortunately, differential signaling uses twice as many wires as single-ended signaling, which can greatly exacerbate pin limitation problems. [0009] What is needed is a method and apparatus for transferring data between computer system components without the large number of signal lines required by differential signaling, and without the current balance and ground noise problems of single-ended signaling. [0010] One embodiment of the present invention provides a system for encoding a dataword into a current codeword within a stream of codewords, wherein each codeword in the stream has a substantially equal number of ones and zeros, and wherein each transition between codewords involves a substantially equal number of rising and falling transitions. The system creates the current codeword from the dataword and a preceding codeword in the stream by inverting substantially half of the zero bits of the preceding codeword and inverting substantially half of the one bits of the preceding codeword. This is accomplished by using the dataword to select one bits and the zero bits to invert; determining locations of the one bits and zero bits in the preceding codeword; and then inverting the selected one bits and zero bits in the preceding codeword to form the current codeword. Note that because the present invention balances rising and falling transitions without significantly increasing pin requirements, it achieves most of the electrical advantages of differential signaling along with most of the pin-efficiency of single-ended signaling. Moreover, by having substantially half the bits change at each transition, it is possible to determine timing information from transitions in the codeword, without the need for a separate clock signal. [0011] In a variation on this embodiment, there exists a predefined mapping between possible bit patterns for the dataword and corresponding inversion patterns for zero bits in the preceding codeword. There also exists a predefined mapping between possible bit patterns for the dataword and corresponding inversion patterns for one bits in the preceding codeword. [0012] In a variation on this embodiment, the system divides the dataword into a first index and a second index. The system uses the first index to identify zero bits of the preceding codeword to invert, and uses the second index to identify one bits of the preceding codeword to invert. [0013] In a variation on this embodiment, using the first index to identify zero bits of the preceding codeword to invert involves using the first index to perform a lookup into a first table containing inversion patterns for zero bits of the preceding Moreover, using the second index to identify one bits of the preceding codeword to invert involves using the second index to perform a lookup into a second table containing inversion patterns for one bits of the preceding codeword. [0014] In a variation on this embodiment, determining locations of the one bits and zero bits in the preceding codeword involves using a prefix sum calculation circuit to identify locations of zero bits and one bits in the preceding codeword. [0015] In a variation on this embodiment, inverting the selected one bits and zero bits in the preceding codeword involves using a selection circuit for each bit in the preceding codeword to select a corresponding inversion bit based on an index for the bit generated by the prefix sum calculation circuit. [0016] One embodiment of the present invention provides a system for decoding a codeword into a data word. During operation, the system receives a stream of codewords, including a preceding codeword and the current codeword, wherein each codeword in the stream has a substantially equal number of ones and zeros, and wherein each transition between codewords involves a substantially equal number of rising and falling transitions. Next, the system identifies a pattern of bits that have been inverted in the preceding codeword to produce the current codeword, and translates this pattern into the data word, wherein the translation uses a predefined mapping between inversion patterns for bits in the preceding codeword and bit patterns for the data word. [0017] In a variation on this embodiment, the system identifies a pattern of zero bits that have been inverted in the preceding codeword to produce the current codeword, and also identifies a pattern of one bits that have been inverted in the preceding codeword to produce the current codeword. In this embodiment, the system translates the pattern of zero bits into a first part of the data word by using a predefined mapping between inversion patterns for zero bits in the preceding codeword and bit patterns for the first part of the data word. The system also translates the pattern of one bits into a second part of the data word by using a predefined mapping between inversion patterns for one bits in the preceding codeword and bit patterns for the second part of the data word. [0018] In a variation on this embodiment, the system identifies the pattern of one bits and the pattern of zero bits by producing a permutation that sorts the preceding codeword so that: zeros and ones are separated; relative ordering is maintained between ones; and relative ordering is maintained between zeros. Next, the system permutes the current codeword using the permutation, so that a first part of the permuted codeword contains the pattern of zero bits in the preceding codeword have been inverted, and a second part of the permuted codeword contains the pattern of one bits in the preceding codeword have been inverted. In a variation on this embodiment, this permutation is produced by using a sorting network. [0019] In a variation on this embodiment, the system uses the pattern of zero bits to perform a lookup into a first table containing corresponding bit patterns for the first part of the data word. The system also uses the pattern of one bits to perform a lookup into a second table containing corresponding bit patterns for the second part of the data word. [0020]FIG. 1 illustrates a transmitter and a receiver for a doubly balanced code in accordance with an embodiment of the present invention. [0021]FIG. 2 illustrates the structure of a decoder for a doubly balanced code in accordance with an embodiment of the present invention. [0022]FIG. 3 illustrates the structure of an encoder for a doubly balanced code in accordance with an embodiment of the present invention. [0023]FIG. 4 is a flow chart illustrating the encoding process in accordance with an embodiment of the present invention. [0024]FIG. 5 is a flow chart illustrating the decoding process in accordance with an embodiment of the present invention. [0025] The following description is presented to enable any person skilled in the art to make and use the invention, and is provided in the context of a particular application and its requirements. Various modifications to the disclosed embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the present invention. Thus, the present invention is not limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed herein. [0026] Transmitter and Receiver [0027]FIG. 1 illustrates a transmitter [0028] Receiver [0029] Also note that the present invention can generally be applied to any context in which a plurality of signal lines are used to transfer data. In one embodiment, transmitter [0030] Decoder [0031]FIG. 2 illustrates the structure of a decoder [0032] Next, a current codeword [0033] Index [0034] Assume that preceding codeword [0035] possible patterns of bit inversions for index [0036] bits of dataword [0037] For example, if n=16 bits, there are
[0038] possible patterns of bit inversions for index [0039] Note that ROM [0040] Encoder [0041]FIG. 3 illustrates the structure of an encoder [0042] At the same time, preceding codeword [0043] The identification lines for a given bit of preceding codeword [0044] Note that the bus widths indicated in FIGS. 2 and 3 are specified for purposes of illustration only. Other embodiments may use other codeword sizes and therefore other widths for intermediate quantities. [0045] Process of Encoding [0046]FIG. 4 is a flow chart illustrating the encoding process in accordance with an embodiment of the present invention. The system starts by receiving a dataword [0047] As bit inversion pattern [0048] Next, the system uses each identifier to select an inversion bit from bit inversion pattern [0049] Process of Decoding [0050]FIG. 5 is a flow chart illustrating the decoding process in accordance with an embodiment of the present invention. During operation, the system receives a stream of codewords, including a preceding codeword [0051] The system then permutes current codeword [0052] Next, the system uses the pattern of zero bit inversions in index [0053] The foregoing descriptions of embodiments of the present invention have been presented only for purposes of illustration and description. They are not intended to be exhaustive or to limit the present invention to the forms disclosed. Accordingly, many modifications and variations will be apparent to practitioners skilled in the art. Additionally, the above disclosure is not intended to limit the present invention. The scope of the present invention is defined by the appended claims. Referenced by
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