US 20030076129 A1 Abstract An impedance controller comprises impedance control logic outputting an adjustable impedance and a comparator comparing the adjustable impedance with a reference voltage. The impedance control logic recalibrates said adjustable impedance only when said comparator indicates a change in impedance.
Claims(20) 1. An impedance controller comprising:
impedance control logic outputting an adjustable impedance; and a comparator comparing said adjustable impedance with a reference voltage, wherein said impedance control logic recalibrates said adjustable impedance only when said comparator indicates a change in impedance. 2. The impedance controller in 3. The impedance controller in 4. The impedance controller in 5. The impedance controller in 6. The impedance controller in a counter adapted to generate said adjustable impedance; an inverter adapted to generate said inverted adjustable impedance; a plurality of latches adapted to temporarily hold said adjustable impedance and said inverted adjustable impedance; and multiplexors that select between increment values of said adjustable impedance and said inverted adjustable impedance until one of said adjustable impedance and said inverted adjustable impedance is substantially equivalent to said reference voltage. 7. The impedance controller in 8. An impedance controller comprising:
impedance control logic outputting an adjustable impedance; and at least one set of dual comparators comparing a high value of said adjustable impedance with a reference voltage and a low value of said adjustable impedance with said reference voltage, wherein said impedance control logic recalibrates said adjustable impedance only when said comparator indicates that said reference voltage is above said high value or below said low value. 9. The impedance controller in 10. The impedance controller in 11. The impedance controller in 12. The impedance controller in 13. The impedance controller in a counter adapted to generate said adjustable impedance; an inverter adapted to generate said inverted adjustable impedance; a plurality of latches adapted to temporarily hold said adjustable impedance and said inverted adjustable impedance; and multiplexors that select between increment values of said adjustable impedance and said inverted adjustable impedance until one of said adjustable impedance and said inverted adjustable impedance value is substantially equivalent to said reference voltage. 14. The impedance controller in 15. An impedance controller connected to a circuit controlled by a system clock, said impedance controller comprising:
impedance control logic outputting an adjustable impedance; and a comparator comparing said adjustable impedance with a reference voltage, wherein said impedance control logic recalibrates said adjustable impedance only when said comparator indicates a change in impedance and independently of said system clock signal. 16. The impedance controller in 17. The impedance controller in 18. The impedance controller in 19. The impedance controller in a counter adapted to generate said adjustable impedance; an inverter adapted to generate said inverted adjustable impedance; a plurality of latches adapted to temporarily hold said adjustable impedance and said inverted adjustable impedance; and multiplexors that select between increment values of said adjustable impedance and said inverted adjustable impedance until one of said adjustable impedance and said inverted adjustable impedance value is substantially equivalent to said reference voltage. 20. The impedance controller in Description [0001] With the ever-increasing speed of digital circuits comes the problem of running sub-circuits at speeds in excess of their minimum requirements (e.g., not at their maximum performance capabilities), thus wasting system resources for power. Impedance controllers in particular, can perform functionally at or below 1 MHz. However, they are often incorporated into a system running at 500 MHz plus. Due to the nature of digital circuits, the impedance controller is forced to run off of the system clock or some division thereof. The clock speed is generally well above the speed needed by the controller. By running at higher speeds than is necessary, the power consuming portions of the circuit operate more frequently than is necessary, thereby wasting power. The main system clock can be slowed by dividing the system clock. However, dividing system clocks creates more system clocking issues and requires more power for the system. Additionally, analog impedance control circuits can take up areas hundreds of times larger than those of their digital counterparts. [0002] Therefore, there is a need for an impedance controller that operates digitally and that runs independently of the system clock. The invention described below provides such a controller that does not use the system clock, but instead updates as the impedance of the I/O drivers to match that of the off-chip circuit. [0003] The present invention generally relates to impedance controllers and more particularly to an improved impedance controller that does not utilize a clock signal and, by being free of the clock signal, the invention can operate at its optimum speed independently of the clock signal of the device in which it is embodied. [0004] In view of the foregoing and other problems, disadvantages, and drawbacks of the conventional impedance controller, the present invention has been devised, and it is an object of the present invention to provide a structure for an impedance controller that does not rely upon any external clock signal and is free to operate at its optimum speed. [0005] In order to attain the object(s) suggested above, there is provided, according to one aspect of the invention, an impedance controller that has an impedance control logic outputting an adjustable impedance and a comparator comparing the adjustable impedance with a reference voltage. The impedance control logic recalibrates the adjustable impedance only when the comparator indicates a change in impedance. The impedance control logic recalibrates the adjustable impedance independently of a system clock signal. The comparator comprises a dual differential amplifier comparator. The dual differential amplifier comparator includes a first differential amplifier comparator adapted to identify a high impedance and a second differential amplifier comparator adapted to identify a low impedance. The impedance controller has an alternating incremental impedance adjustment circuit adapted to converge the adjustable impedance and an inverse adjustable impedance to an amount less than the high impedance and greater than the low impedance, as controlled by the first differential amplifier and the second differential amplifier. The alternating incremental impedance adjustment circuit has a counter adapted to generate the adjustable impedance and an inverter adapted to generate the inverted adjustable impedance. The invention also has a plurality of latches adapted to temporarily hold the adjustable impedance. The inverted adjustable impedance and multiplexors select between increment values of the adjustable impedance and the inverted adjustable impedance until one of the adjustable impedance and the inverted adjustable impedance is substantially equivalent to the reference voltage. The impedance controller includes an enable signal that controls the multiplexors in incrementing values of the adjustable impedance and the inverted adjustable impedance. [0006] Implementing the ideas contained in this invention could save power resources in systems using standard impedance controllers which run off system clocks or some division thereof. Secondly, this impedance controller circuit runs on demand when there is a change in impedance. Thus, it is idle a large percentage of the time. Finally, it saves designers from dealing with clock synchronization issues because the controller works off its own generated recalibration signal which does not need to be synchronous with a system clock. Systems that implement the design described within will also benefit from area savings. Since there are no clock tree circuits within the design, the area normally consumed by these circuits is available for additional system logic and added functionality. In systems with many impedance controllers on a system on a chip (SoC), the area savings become greater the more these improved impedance controllers replace traditional system clock driven controllers. In fact, any system that currently implements an impedance controller design could benefit from the use of this improved controller. Older designs could be reworked to implement the new impedance controllers and future designs could make these controllers the new standard. [0007] The foregoing and other objects, aspects and advantages will be better understood from the following detailed description of a preferred embodiment(s) of the invention with reference to the drawings, in which: [0008]FIG. 1 is a schematic diagram of an impedance controller; [0009]FIG. 2 is a schematic diagram of an impedance controller; [0010]FIG. 3 is a schematic diagram of an impedance controller; and [0011]FIG. 4 is a timing diagram of the signals within the impedance controller shown in FIG. 3. [0012] As mentioned above, there is a need for an impedance controller that operates digitally and that runs independently of the system clock. The invention addresses this need and provides a “clockless” impedance controller that runs on-demand. With the inventive impedance controller, only when there is a change in impedance of the system does the controller respond (rather than at regular cycles of a system clock). The change in impedance is detected by a set of dual differential amplifiers. The change in impedance acts as a “clock” for the impedance controller sub-circuit. The circuit also ensures that there will be a continuous change in the outputs of the two comparators during each impedance control phase until the reference impedance is matched. The inventive impedance controller is thus independent of the system clock and can be utilized in any electronic system regardless of the system's speed. The impedance control on-demand device saves much needed power resources for other functions within a given system. [0013] As shown in FIG. 1, an impedance controller that relies upon an external clock signal normally take a reference voltage ( [0014] The invention makes a range out of the calculated impedance from the impedance control logic ( [0015] This changing output generates the edges necessary to create an “impedance change signal” ( [0016] In order to generate an impedance change signal for the impedance control logic to function, the invention uses dual differential amplifier ( [0017] An example embodiment for a linear count-type impedance control circuit (e.g., ping pong circuit ( [0018] The counter ( [0019] The waveforms of the signals processed by the circuit shown in FIG. 3 are shown in FIG. 4. In this example, a 4 bit impedance signal is used, the reference voltage is 4.5 and the system is reset to 0 on power up. As discussed above and as shown in FIG. 4, the enable signal ( [0020] Thus, the invention provides an impedance controller that can operate at its own pace and that is free of the system clock of the device to which it is connected. This allows the inventive impedance controller to perform many less operations per time period than does a conventional impedance controller, thereby saving substantial power. Because the inventive impedance controller does not receive a regular clock signal, it utilizes dual circuits (the dual differential amplifiers), one of which continues to recalibrate the impedance level so long as the impedance is to low, while the other circuit continues to recalibrate the impedance level so long as the impedance is to high. Therefore, the inventive circuit will only stop the recalibration process when the value is stabilized above the “low” value and below the “high” value. Such dual circuits allow the impedance level to be stabilized (through successive recalibration cycles) without having to rely upon a cyclical clock cycle. This substantially reduces the power consumed by the impedance controller by operating the impedance controller's power consuming calibration process only when necessary. [0021] Any system that implements an impedance controller could benefit from this invention. Firstly, implementing the ideas contained in this invention could save power resources in systems using standard impedance controllers which run off system clocks or some division thereof. Secondly, this impedance controller circuit runs on demand when there is a change in impedance. Thus, it is idle a large percentage of the time. Finally, it saves designers from dealing with clock synchronization issues because the controller works off its own generated recalibration signal which does not need to be synchronous with a system clock. Systems that implement the design described within will also benefit from area savings. Since there are no clock tree circuits within the design, the area normally consumed by these circuits is available for additional system logic and added functionality. In systems with many impedance controllers on a system on a chip (SoC), the area savings become greater the more these improved impedance controllers replace traditional system clock driven controllers. In fact, any system that currently implements an impedance controller design could benefit from the use of this improved controller. Older designs could be reworked to implement the new impedance controllers and future designs could make these controllers the new standard. [0022] While the invention has been described in terms of preferred embodiments, those skilled in the art will recognize that the invention can be practiced with modification within the spirit and scope of the appended claims. Classifications
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