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Publication numberUS20030076431 A1
Publication typeApplication
Application numberUS 10/038,546
Publication dateApr 24, 2003
Filing dateOct 24, 2001
Priority dateOct 24, 2001
Also published asUS7697051, US20060244854
Publication number038546, 10038546, US 2003/0076431 A1, US 2003/076431 A1, US 20030076431 A1, US 20030076431A1, US 2003076431 A1, US 2003076431A1, US-A1-20030076431, US-A1-2003076431, US2003/0076431A1, US2003/076431A1, US20030076431 A1, US20030076431A1, US2003076431 A1, US2003076431A1
InventorsAlexander Krymski
Original AssigneeKrymski Alexander I.
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Image sensor with pixels having multiple capacitive storage elements
US 20030076431 A1
Abstract
An apparatus has a pixel that includes (i) a buffer transistor having an input, (ii) first and second capacitive storage elements each of which selectively can be coupled to the input of the buffer transistor, and (iii) a photosensitive element having an output which selectively can be coupled to the input of the buffer transistor. A readout circuit selectively can be coupled to an output of the buffer transistor. A first signal level, sensed by the photosensitive element, can be stored by the first capacitive storage element, and a second signal level, sensed by the photosensitive element, can be stored by the second capacitive storage element. The first and second signal levels can be read out from the pixel.
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Claims(30)
What is claimed is:
1. An apparatus comprising:
a pixel including (i) a buffer transistor having an input, (ii) first and second capacitive storage elements each of which selectively can be coupled to the input of the buffer transistor, and (iii) a photosensitive element having an output which selectively can be coupled to the input of the buffer transistor; and
a readout circuit that selectively can be coupled to an output of the buffer transistor.
2. The apparatus of claim 1 including:
a first switch coupled between the output of the photosensitive element and the input of the buffer transistor;
a second switch coupled between the first capacitive storage element and the input of the buffer transistor; and
a third switch coupled between the second capacitive storage element and the input of the buffer transistor,
each of the switches being selectively operable in an open or closed state.
3. The apparatus of claim 2 including a fourth switch coupled between a power supply node and the input of the buffer transistor, the fourth switch being selectively operable in an open or closed state.
4. The apparatus of claim 3 including a controller for providing signals to control the respective states of the first, second, third and fourth switches.
5. The apparatus of claim 4 wherein the controller is configured for providing signals to cause the first capacitive storage element to store a first signal level sensed by the photosensitive element during a first integration time and to cause the second capacitive element to store a second signal level sensed by the photosensitive element during a second integration time.
6. The apparatus of claim 5 wherein the controller is configured for providing signals to cause (i) the first and second switches to be closed during the first integration time, (ii) the third and fourth switches to be open during the first integration time, (iii) the first and third switches to be closed during the second integration time, and (iv) the second and fourth switches to be open during the second integration time.
7. The apparatus of claim 6 wherein the controller is configured for providing signals to cause (i) the first, second and fourth switches to be closed just prior to the first integration period, and (ii) the first, third and fourth switches to be closed just prior to the second integration period.
8. The apparatus of claim 6 wherein the controller is configured for providing signals to reset the photosensitive element and the first capacitive storage element prior to the first integration period and to reset the photosensitive element and the second capacitive storage element prior to the second integration period.
9. The apparatus of claim 5 wherein the controller is configured for providing signals to selectively transfer the first signal level from the first capacitive storage element to the readout circuit and to transfer the second signal level from the second capacitive element to the readout circuit.
10. The apparatus of claim 9 wherein the controller is configured for providing signals to reset the input of the buffer transistor prior to transferring the first signal level from the first capacitive storage element to the readout circuit and to reset the input of the buffer transistor prior to transferring the second signal level from the second capacitive storage element to the readout circuit.
11. The apparatus of claim 9 wherein the controller is configured for providing signals to cause the fourth switch to be closed prior to transferring the first signal level from the first capacitive storage element to the readout circuit and to cause the fourth switch to be closed just prior to transferring the second signal level from the second capacitive storage element to the readout circuit.
12. The apparatus of claim 3 wherein the fourth switch is configured for operation in a sub-threshold reset mode.
13. An integrated circuit comprising:
an array of pixels each of which is associated with a respective row and column in the array, each pixel including (i) a buffer transistor having an input, (ii) first and second capacitive storage elements each of which selectively can be coupled to the input of the buffer transistor, and (iii) a photosensitive element having an output which selectively can be coupled to the input of the buffer transistor;
readout circuitry which selectively can be coupled to outputs of buffer transistors of selected pixels in the array; and
a controller for providing signals to control the selective coupling of the first and second capacitive storage elements and the photosensitive element to the input of the buffer and to control the selective coupling of the readout circuitry to the outputs of the buffer transistors.
14. The integrated circuit of claim 13, each pixel including:
a first switch coupled between the output of the photosensitive element and the input of the buffer transistor;
a second switch coupled between the first capacitive storage element and the input of the buffer transistor; and
a third switch coupled between the second capacitive storage element and the input of the buffer transistor,
each of the switches being selectively operable in an open or closed state.
15. The integrated circuit of claim 14, each pixel including a fourth switch coupled between a power supply node and the input of the buffer transistor, the fourth switch being selectively operable in an open or closed state.
16. The integrated circuit of claim 15 wherein the controller is configured for providing signals to control the respective states of the first, second, third and fourth switches.
17. The integrated circuit of claim 16 wherein the controller is configured for providing signals to cause the first capacitive storage element to store a first signal level sensed by the photosensitive element during a first integration time and to cause the second capacitive element to store a second signal level sensed by the photosensitive element during a second integration time.
18. The integrated circuit of claim 17 wherein the controller is configured for providing signals to cause (i) the first and second switches to be closed during the first integration time, (ii) the third and fourth switches to be open during the first integration time, (iii) the first and third switches to be closed during the second integration time, and (iv) the second and fourth switches to be open during the second integration time.
19. The integrated circuit of claim 18 wherein the controller is configured for providing signals to cause (i) the first, second and fourth switches to be closed just prior to the first integration period, and (ii) the first, third and fourth switches to be closed just prior to the second integration period.
20. The integrated circuit of claim 18 wherein the controller is configured for providing signals to reset the photosensitive element and the first capacitive storage element prior to the first integration period and to reset the photosensitive element and the second capacitive storage element prior to the second integration period.
21. The integrated circuit of claim 17 wherein the controller is configured for providing signals to selectively transfer the first signal level from the first capacitive storage element to the readout circuitry and to transfer the second signal level from the second capacitive element to the readout circuitry.
22. The integrated circuit of claim 21 wherein the controller is configured for providing signals to reset the input of the buffer transistor prior to transferring the first signal level from the first capacitive storage element to the readout circuitry and to reset the input of the buffer transistor prior to transferring the second signal level from the second capacitive storage element to the readout circuitry.
23. The integrated circuit of claim 21 wherein the controller is configured for providing signals to cause the fourth switch to be closed prior to transferring the first signal level from the first capacitive storage element to the readout circuitry and to cause the fourth switch to be closed just prior to transferring the second signal level from the second capacitive storage element to the readout circuitry.
24. The integrated circuit of claim 15 wherein the fourth switch is configured for operation in a sub-threshold reset mode.
25. A method comprising:
storing a first signal level, sensed by a photosensitive element, in a first capacitive storage element in a pixel;
storing a second signal level, sensed by the photosensitive element, in a second capacitive storage element in the pixel; and
reading out the first and second signal levels from the pixel.
26. The method of claim 25 including obtaining a signal representing the difference between the first and second signal levels read from the pixel.
27. The method of claim 25 wherein the first signal level is stored during a first integration period and the second signal level is stored during a second integration period.
28. The method of claim 27 including:
resetting the photosensitive element and the first capacitive storage element prior to the first integration period; and
resetting the photosensitive element and the second capacitive storage element prior to the second integration period.
29. The method of claim 28 including reading out the first and second signal levels from the pixel through a buffer transistor, the method further including:
resetting an input of the buffer transistor prior to reading out the first signal level from the first capacitive storage element; and
resetting the input of the buffer transistor prior to reading out the second signal level from the second capacitive storage element.
30. The method of claim 28 including operating a pixel reset switch in a sub-threshold reset mode.
Description
DETAILED DESCRIPTION

[0018] As shown in FIG. 1, a monolithic integrated imaging circuit chip 10 includes an array of active pixel sensors 30 and a controller 32 that provides timing and control signals to control operation of the pixels and enable reading out of signals stored in the pixels. The array 30 may have dimensions of 128 by 128 pixels or 256 by 256 pixels, although, in general, the size of the array will depend on the particular implementation. The imager can be read out a row at a time using a parallel column readout architecture. The controller 32 selects a particular row of pixels in the array 30 by controlling the operation of a vertical addressing circuit 34 and row drivers 40. Charge signals stored in the selected row of pixels are transferred to a readout circuit 42. The pixels read from each of the columns then can be read out sequentially using a horizontal addressing circuit 44. A differential signal for each pixel can be provided at an output of the readout circuit 42.

[0019] As shown in FIG. 2, the array 30 includes multiple columns 49 of active pixel sensors 50. Each column includes multiple rows of sensors 50. Signals from the active pixel sensors 50 in a particular column can be read out to a readout circuit 52 associated with that column. For example, pixel signal levels corresponding to different exposure times may be stored by the readout circuit 52 and then transferred to a common output stage 54 over lines 70, 72. The output stage 54 can provide a differential signal corresponding to the difference between the pixel signals obtained during the different exposure times.

[0020] As shown in FIG. 3, a single CMOS active pixel sensor 50 includes a photosensitive element 60 buffered by a source-follower transistor M1. The source-follower transistor M1 is coupled to a power supply voltage (vdd) and to a row selection switch which can be implemented by a transistor M2. A signal (ROW) is applied to the gate of the row selection transistor M2 to enable reading out of signals from a pixel in the selected row. The row selection signal (ROW) is common to an entire row of pixels. In one implementation, the photosensitive element 60 includes a photogate. A floating diffusion node 62 that serves as a sense node is coupled to the gate of the source-follower M1 and is separated from the photosensitive element 60 by a transfer gate S1. The pixel 50 includes a reset switch S4 that can be implemented as a transistor. When the reset switch S4 is closed, it is coupled to a power supply voltage (Vrst).

[0021] The pixel includes storage capacitors C1, C2 for storing charge or voltage signals corresponding to optical signals sensed by the photosensitive element 60. Respective switches S2, S3, which can be implemented as transistors, are coupled between the floating diffusion node 62 and the capacitors C1, C2. The values of the capacitors C1, C2 should be substantially the same.

[0022] As illustrated by FIG. 3, output signals from a pixel 50 can be provided to the readout circuit 52 through a bus 64 that is common to an entire column 49 of pixels. The readout includes a load transistor M5 and two sample and hold switches M3, M4, which can be implemented as transistors. The switch M3 is controlled by a signal (SHS) applied to its gate, whereas the switch M4 is controlled by a signal (SHR). When a sample and hold switch is closed, a voltage signal that is present on the common pixel output bus 64 is stored by the corresponding capacitor. For example, when the switch M3 is closed, a voltage signal that is present on the bus 64 is stored by the capacitor C3. Similarly, when the switch M4 is closed, a voltage signal that is present on the bus 64 is stored by the capacitor C4.

[0023] Signals for controlling the state of the various switches are provided by the controller 32. For purposes of the following discussion, it is assumed that each switch is implemented as an n-type metal oxide semiconductor (NMOS) transistor switch such that the switch is open when its control signal is high and is closed when its control signal is low. The reverse is applicable to p-type MOS (PMOS) switches.

[0024] In operation, the photosensitive element 60 and the first storage capacitor C1 are reset by closing and subsequently opening the reset switch S4 while the switches S1 and S2 are closed. As shown, for example, in FIG. 4, the reset switch S4 is closed at time t1 and subsequently opened at time t2. Switches S1 and S2 remain closed to integrate photocharge on the first capacitor C1 during a first integration period. The first integration period ends at time t3 when the switches S1 and S2 are closed. Next, the photosensitive element 60 and the second storage capacitor C2 are reset by closing and subsequently opening the reset switch S4 while the switches S1 and S3 are opened. As shown in FIG. 4, the reset switch S4 is closed at time t4 and subsequently opened at time t5. Switches S1 and S3 remain closed to integrate photocharge on the first capacitor C2 during a second integration period. The second integration period ends at time t6 when the switches S1 and S3 are opened. The first and second integration periods correspond to first and second exposure periods, respectively. The imager can be operated in shutter mode with common integration periods for the entire array of pixels.

[0025] After completion of the two exposure periods, the row selection signal (ROW) enables (at time t7) a pixel in the selected row to be coupled electrically to the column bus 64. The pixel's floating node 62 is reset by closing reset switch S4 at time t8. After re-opening switch S4 (at time t9), the signal stored by the first capacitor C1 is transferred to the source follower M1 by closing the switch S2 (at time t10). The pixel signal corresponding to the first exposure time passes through the row selection switch M2 to the bus 64. The sample and hold switch M3 also is enabled at time t10, thereby allowing the pixel signal for the first exposure time to be sampled and stored by the capacitor C3. At time t11, the switch S2 and the switch M3 are opened.

[0026] The pixel's floating node 62 again is rest by closing reset switch S4 at time t12. After re-opening switch S4 (at time t13), the signal stored by the first capacitor C2 is transferred to the source follower M1 by closing the switch S3 (at time t14). The pixel signal corresponding to the second exposure time passes through the row selection switch M2 to the bus 64. The sample and hold switch M4 also is enabled at time t14, thereby allowing the pixel signal for the second exposure time to be sampled and stored by the capacitor C4. At time t15, the switch S3 and the switch M4 are opened.

[0027] The signals stored by the capacitors C3 and C4 can be read out, respectively, through lines 70, 72 to the output stage 54 which includes circuitry for determining the difference between the input signals. Thus, the output signals from stage 54 represent the difference between the images sensed and stored by the pixel during the two exposure times. The output signals can be converted to corresponding digital signals using an analog-to-digital converter (ADC). The signals from the other pixels in the selected row can be read out sequentially. Alternatively, a separate output stage 54 and ADC can be provided for each column or block of columns to provide parallel readout.

[0028] After processing the signals from the pixels in the selected row, another row of pixels can be selected to allow the stored signal levels to be read out and processed.

[0029] One advantage that may be achieved through the foregoing technique is the ability to obtain differential values representing the difference between two exposures without measuring pixel reset values. Eliminating measurement of pixel reset levels can help reduce the noise that is inherent in such measurements. Nevertheless, the pixel design described above also can be used to obtain differential values representing the difference between the pixel signal level and pixel reset level.

[0030] Additional reductions in thermal or “kTC” noise can be achieved by operating the reset switch S4 in soft, or sub-threshold, reset mode. In that case, as illustrated in FIG. 5, the switch S4 should be implemented as an NMOS transistor, whereas the switches S1, S2 and S3 should be implemented as PMOS transistors operating in linear triode mode to ensure complete transfer of signals between the photosensitive element 60, the capacitive storage memories C1 and C2, and the source follower M1.

[0031] Other implementations are within the scope of the claims.

BRIEF DESCRIPTION OF THE DRAWINGS

[0013]FIG. 1 is a system block diagram of an integrated circuit chip.

[0014]FIG. 2 illustrates further details of the integrated circuit chip.

[0015]FIG. 3 is a schematic diagram of a pixel and an associated column readout circuit.

[0016]FIG. 4 is a timing diagram of signals associated with FIG. 3.

[0017]FIG. 5 is a schematic diagram of a pixel.

BACKGROUND

[0001] The present invention relates to image sensors with pixels having multiple capacitive storage elements.

[0002] Image sensors can be used in a wide variety of fields, including machine vision, robotics, guidance and navigation, automotive applications, and consumer products. They can include on-chip circuitry that controls image sensor operation, signal read-out and image processing functions. Image sensors can utilize, for example, active pixel sensor (APS) technology with each active pixel sensor including one or more active transistors. Each pixel sensor element can provide an output value that represents a particular portion of an image.

SUMMARY

[0003] An apparatus, such as an imager, includes a pixel that has (i) a buffer transistor having an input, (ii) first and second capacitive storage elements each of which selectively can be coupled to the input of the buffer transistor, and (iii) a photosensitive element having an output which selectively can be coupled to the input of the buffer transistor. The apparatus also includes a readout circuit that selectively can be coupled to an output of the buffer transistor.

[0004] A first signal level, sensed by the photosensitive element, can be stored by the first capacitive storage element, and a second signal level, sensed by the photosensitive element, can be stored by the second capacitive storage element. The first and second signal levels can be read out from the pixel.

[0005] In various implementations, the apparatus may include one or more of the following features. A first switch can be coupled between the output of the photosensitive element and the input of the buffer transistor. A second switch can be coupled between the first capacitive storage element and the input of the buffer transistor, and a third switch can be coupled between the second capacitive storage element and the input of the buffer transistor. A fourth switch can be coupled between a power supply node and the input of the buffer transistor. Each of the switches can be selectively operable in an open or closed state.

[0006] A controller can provide signals to control the respective states of the first, second, third and fourth switches. The controller can be configured to provide signals to cause the first capacitive storage element to store a first signal level sensed by the photosensitive element during a first integration time and to cause the second capacitive element to store a second signal level sensed by the photosensitive element during a second integration time. For example, the controller can be configured to provide signals to cause (i) the first and second switches to be closed during the first integration time, (ii) the third and fourth switches to be open during the first integration time, (iii) the first and third switches to be closed during the second integration time, and (iv) the second and fourth switches to be open during the second integration time.

[0007] The controller also can be configured to provide signals to reset the photosensitive element and the first capacitive storage element prior to the first integration period and to reset the photosensitive element and the second capacitive storage element prior to the second integration period. For example, the controller can be configured to provide signals to cause (i) the first, second and fourth switches to be closed just prior to the first integration period, and (ii) the first, third and fourth switches to be closed just prior to the second integration period.

[0008] The controller can be configured for providing signals to selectively transfer the first signal level from the first capacitive storage element to the readout circuit and to transfer the second signal level from the second capacitive element to the readout circuit. Furthermore, the controller can be configured to provide signals to reset the input of the buffer transistor prior to transferring the first signal level from the first capacitive storage element to the readout circuit and to reset the input of the buffer transistor prior to transferring the second signal level from the second capacitive storage element to the readout circuit. Thus, the controller can be configured to provide signals to cause the fourth switch to be closed prior to transferring the first signal level from the first capacitive storage element to the readout circuit and to cause the fourth switch to be closed just prior to transferring the second signal level from the second capacitive storage element to the readout circuit.

[0009] In some implementations, the reset switch is configured for operation in a sub-threshold reset mode.

[0010] An integrated circuit can include an array of pixels each of which includes multiple capacitive storage elements. Readout circuitry selectively can be coupled to outputs of buffer transistors of selected pixels in the array. The pixels, as well as the controller and the readout circuitry, can be formed as part of a monolithic integrated circuit.

[0011] One or more of the following advantages may be present in some implementations. Signals representing the difference between two exposures can be obtained without measuring pixel reset values. Eliminating measurement of pixel reset levels can help reduce the noise that is inherent in such measurements. Additional reductions in thermal or “kTC” noise can be achieved by operating the reset switch in sub-threshold mode.

[0012] Other features and advantages will be readily apparent from the following detailed description, the accompanying drawings and the claims.

Referenced by
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Classifications
U.S. Classification348/308, 348/E03.021, 348/E05.079, 257/E27.132
International ClassificationH04N5/378, H01L27/146, H04N5/217, H04N3/15
Cooperative ClassificationH04N5/3741, H04N5/35572, H04N5/363, H01L27/14609, H04N5/37452, H04N5/374
European ClassificationH01L27/146A4, H04N5/355B2, H04N5/363, H04N5/3745A, H04N5/374A
Legal Events
DateCodeEventDescription
Mar 29, 2002ASAssignment
Owner name: MICRON TECHNOLOGY, INC., IDAHO
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:PHOTOBIT CORPORATION;REEL/FRAME:014007/0590
Effective date: 20011121
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:PHOTOBIT CORPORATION;REEL/FRAME:012745/0385