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Publication numberUS20030080372 A1
Publication typeApplication
Application numberUS 10/283,856
Publication dateMay 1, 2003
Filing dateOct 30, 2002
Priority dateOct 30, 2001
Also published asDE10153384A1, DE10153384B4, US7273786, US20050141271
Publication number10283856, 283856, US 2003/0080372 A1, US 2003/080372 A1, US 20030080372 A1, US 20030080372A1, US 2003080372 A1, US 2003080372A1, US-A1-20030080372, US-A1-2003080372, US2003/0080372A1, US2003/080372A1, US20030080372 A1, US20030080372A1, US2003080372 A1, US2003080372A1
InventorsThomas Mikolajick
Original AssigneeThomas Mikolajick
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Semiconductor memory cell, method for fabricating the memory cell, and semiconductor memory device
US 20030080372 A1
Abstract
In order to be able to store information in a non-volatile fashion as compactly and as flexibly as possible in a semiconductor memory cell, the original gate region of a conventional memory transistor is removed, and a memory gate configuration having a plurality of memory gates that are spatially separate from one another and that are electrically insulated with respect to one another is formed.
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Claims(71)
I claim:
1. A semiconductor memory cell for non-volatile information storage, comprising:
a memory gate configuration designed for non-volatile information storage;
a source/drain configuration designed for accessing said memory gate configuration; and
a control gate configuration designed for controlling access to said memory gate configuration;
said memory gate configuration having a plurality of memory gate regions; and
each of said plurality of said memory gate regions being designed for essentially independent information storage such that a corresponding plurality of information units can be stored independently of one another.
2. The semiconductor memory cell according to claim 1, wherein the plurality of the information units are binary bits.
3. The semiconductor memory cell according to claim 1, wherein said plurality of said memory gate regions are pairwise, spatially separate from one another.
4. The semiconductor memory cell according to claim 3, wherein said plurality of said memory gate regions are electrically insulated from one another.
5. The semiconductor memory cell according to claim 1, wherein said plurality of said memory-gate regions are electrically insulated from one another.
6. The semiconductor memory cell according to claim 1, wherein:
said control gate configuration has a common control gate; and
access to said plurality of said memory gate regions is jointly controllable by said common control gate.
7. The semiconductor memory cell according to claim 1, wherein:
said source/drain configuration includes a plurality of source/drain regions present in a number corresponding to a number of said plurality of said memory gate regions; and
a respective one of said plurality of said source/drain regions is assigned to a respective one of said plurality of said memory gate regions such that said respective one of said plurality of said memory gate regions can be accessed using said control gate configuration and said respective one of said plurality of said source/drain regions.
8. The semiconductor memory cell according to claim 1, wherein said plurality of said memory gate regions have essentially identical geometrical properties.
9. The semiconductor memory cell according to claim 8, wherein said plurality of said memory gate regions have essentially identical material properties.
10. The semiconductor memory cell according to claim 1, wherein said plurality of said memory gate regions have essentially identical material properties.
11. The semiconductor memory cell according to claim 1, wherein:
said control gate configuration has a control gate and said source/drain configuration has a plurality of source/drain regions; and
said plurality of said memory gate regions are configured and designed to be essentially electrically insulated from one another, from said control gate and from said plurality of said source/drain regions.
12. The semiconductor memory cell according to claim 1, wherein said plurality of said memory gate regions are designed as floating gate regions so that the semiconductor memory cell functions as a floating gate memory cell.
13. The semiconductor memory cell according to claim 1, wherein said plurality of said memory gate regions are designed and configured as essentially capacitively coupled floating gates.
14. The semiconductor memory cell according to claim 13, wherein said floating gates are made of a material selected from a group consisting of a polysilicon material, a polycide, and a metal.
15. The semiconductor memory cell according to claim 1, wherein said plurality of said memory gate regions are floating gates made of a material selected from a group consisting of a polysilicon material, a polycide, and a metal.
16. The semiconductor memory cell according to claim 1, wherein: said plurality of said memory gate regions are designed as charge trapping gates so that the semiconductor memory cell functions as a charge trapping memory cell.
17. The semiconductor memory cell according to claim 16, wherein said charge trapping gates include a material in which charge trapping states can be formed.
18. The semiconductor memory cell according to claim 17, wherein said material of said charge trapping gates is an insulator having a sufficient number of defects capable of being occupied by electrons and/or holes.
19. The semiconductor memory cell according to claim 17, wherein: said material of said charge trapping gates is an insulator in which a sufficient number of defects can be formed; and said defects can be occupied by electrons and/or holes.
20. The semiconductor memory cell according to claim 17, comprising:
a channel region; and
an insulation region made of silicon dioxide;
said source/drain configuration having a plurality of source/drain regions;
said control gate configuration having a control gate;
said insulating region configured for insulating said charge trapping gates from said control gate, said plurality of said source/drain regions and said channel region;
said charge trapping gates being composed of silicon nitride;
said charge trapping gates having a structure selected from a group consisting of an ONO structure and an NO structure; and
said charge trapping gates including a material selected from a group consisting of ZrO2, Al2O3, Ta2O5, HfO2.
21. The semiconductor memory cell according to claim 1, wherein each one of said plurality of said memory gate regions can assume a plurality of charge or potential states corresponding to information states assigned to said plurality of said memory gate regions.
22. The semiconductor memory cell according to claim 1, wherein:
said source/drain configuration includes a plurality of source/drain regions;
said control gate configuration includes a control gate configured and designed to be essentially electrically insulated from said plurality of said memory gate regions and from said plurality of said source/drain regions.
23. The semiconductor memory cell according to claim 1, wherein said control gate configuration includes a control gate composed of a material selected from a group consisting of a polysilicon material, a polycide, and a metal.
24. The semiconductor memory cell according to claim 1, comprising:
an intermediate insulation region;
said control gate configuration including a control gate;
said plurality of said memory gate regions being pairwise, spatially separate from one another;
said plurality of said memory gate regions and said control gate being configured in direct spatial proximity to one another; and
said intermediate insulation region located between said control gate and said plurality of said memory gate regions.
25. The semiconductor memory cell according to claim 24, wherein said intermediate insulation region is an intermediate dielectric.
26. The semiconductor memory cell according to claim 1, comprising:
an insulation region;
said source/drain configuration including a plurality of source/drain regions;
each one of said plurality of said memory gate regions being designed and configured in direct spatial proximity to a respective one of said plurality of said source/drain regions such that a spatial overlap is formed between said one plurality of said memory gate regions and said respective one of said plurality of said source/drain regions; and
said insulation region provided between said one plurality of said memory gate regions and said respective one of said plurality of said source/drain regions.
27. The semiconductor memory cell according to claim 26, wherein said insulation region is formed from a silicon dioxide material.
28. The semiconductor memory cell according to claim 1, comprising:
an insulation region formed with a recess;
said plurality of said memory gate regions designed as spacer, elements embedded in said recess of said insulation region.
29. The semiconductor memory cell according to claim 1, wherein said plurality of said memory gate regions are designed as exchange elements for at least a part of an original gate of a conventional MOSFET.
30. The semiconductor memory cell according to claim 29, comprising:
an additional insulator, said plurality of said memory gate regions defining a level; and
an intermediate region located between said plurality of said memory gate regions being filled with said additional insulator to at most the level of said plurality of said memory gate regions to form an insulator thickness greater than a thickness of an original gate oxide or tunnel oxide.
31. A semiconductor memory device, comprising:
a plurality of memory cells designed for non-volatile information storage;
each one of said plurality of said memory cells including:
a memory gate configuration designed for non-volatile information storage;
a source/drain configuration designed for accessing said memory gate configuration; and
a control gate configuration designed for controlling access to said memory gate configuration;
said memory gate configuration having a plurality of memory gate regions; and
each of said plurality of said memory gate regions being designed for essentially independent information storage such that a corresponding plurality of information units can be stored independently of one another.
32. The semiconductor memory device according to claim 31, wherein:
said control gate configuration of each one of said plurality of said memory cells includes a control gate; and
said control gate of adjacent ones of at least some of said plurality of said memory cells are designed as a common control gate.
33. A method for fabricating a semiconductor memory cell for non-volatile information storage, the method which comprises:
providing a memory gate configuration having a plurality of memory gate regions in which each one of the plurality of the memory gate regions is designed for essentially independently storing information such that a corresponding plurality of information units can be stored independently of one another;
providing a source/drain configuration designed for accessing the memory gate configuration; and
providing a control gate configuration for controlling access to the memory gate configuration.
34. The method according to claim 33, wherein the information units are binary bits.
35. The method according to claim 33, which comprises designing the plurality of the memory gate regions to be pairwise, spatially separate from one another.
36. The method according to claim 33, which comprises designing the plurality of the memory gate regions to be electrically insulated from one another.
37. The method according to claim 33, which comprises providing the control gate configuration with a common control gate for jointly controlling access to the plurality of the memory gate regions.
38. The method according to claim 33, which comprises:
providing the source/drain configuration with a plurality of source/drain regions present in a number corresponding to a number of the plurality of the memory gate regions; and
assigning each one of the plurality of the source/drain regions to a respective one of the plurality of the memory gate regions such that the one of the plurality of the memory gate regions can be accessed using the control gate configuration and the one of the plurality of the source/drain regions.
39. The method according to claim 33, which comprises designing the plurality of the memory gate regions to have essentially identical geometrical properties.
40. The method according to claim 33, which comprises designing the plurality of the memory gate regions to have essentially identical material properties.
41. The method according to claim 33, which comprises
providing the control gate configuration with a control gate and providing the source/drain configuration with a plurality of source/drain regions; and
configuring and designing the plurality of the memory gate regions to be essentially electrically insulated from one another, from the control gate and from the plurality of the source/drain regions.
42. The method according to claim 33, which comprises designing the plurality of the memory gate regions as floating gate regions or floating gates so that the semiconductor memory cell functions as a floating gate memory cell.
43. The method according to claim 42, which comprises designing and configuring the plurality of the memory gate regions as floating gates being essentially capacitively coupled.
44. The method according to claim 33, which comprises designing the plurality of the memory gate regions as floating gates made of a material selected from a group consisting of a polysilicon material, a polycide, and a metal.
45. The method according to claim 33, which comprises designing the plurality of the memory gate regions as charge trapping gate regions or charge trapping gates so that the semiconductor memory cell functions as a charge trapping memory cell.
46. The method according to claim 45, which comprises: designing the plurality of the memory gate regions as charge trapping gates formed with silicon nitride;
providing the plurality of the memory gate regions with an ONO structure or an NO structure;
providing the plurality of the memory gate regions with a material selected from a group consisting of ZrO2, Al2O3, Ta2O5, and HfO2; and
providing an insulation region between the charge trapping gates and a control gate of the control gate configuration.
47. The method according to claim 46, which comprises also providing the insulation region between the charge trapping gates and source/drain regions of the source/drain configuration and between the charge trapping gates and a channel region.
48. The method according to claim 33, which comprises: designing the plurality of the memory gate regions as charge trapping gates so that the semiconductor memory cell functions as a charge trapping memory cell; and
forming the charge trapping gates using a material in which charge trapping states can be formed.
49. The method according to claim 48, which comprises: providing the material of the charge trapping gates as an insulator that has or that can form a sufficient number of defects that can be occupied by electrons and/or holes.
50. The method according to claim 33, which comprises designing the plurality of the memory gate regions such that a plurality of charge and/or potential states can be assumed which correspond to information states assigned to the plurality of the memory gate regions.
51. The method according to claim 50, wherein the plurality of the charge and/or potential states is exactly two states.
52. The method according to claim 33, which comprises providing the control gate configuration with a control gate that is electrically insulated from the plurality of the memory gate regions and from source/drain regions of the source/drain configuration.
53. The method according to claim 33, which comprises providing the control gate configuration with a control gate formed from a material selected from a group consisting of a polysilicon material, a polycide, and a metal.
54. The method according to claim 33, which comprises:
providing the control gate configuration with a control gate;
configuring the plurality of the memory gate regions and the control gate in direct spatial proximity to one another; and
providing an intermediate insulation region between the control gate and the plurality of the memory gate regions.
55. The method according to claim 54, which comprises providing the intermediate insulation region as an intermediate dielectric.
56. The method according to claim 33, which comprises:
configuring each one of said plurality of said memory gate regions in direct spatial proximity to an assigned source/drain region such that a spatial overlap is formed between the one of said plurality of said memory gate regions and the assigned source/drain region; and
providing an insulation region between one of said plurality of said memory gate regions and the assigned source/drain region.
57. The method according to claim 56, which comprises forming the insulation region from silicon dioxide.
58. The method according to claim 33, which comprises designing the plurality of the memory gate regions as spacer elements embedded in a recess of an insulation region.
59. The method according to claim 33, which comprises designing the plurality of the memory gate regions to replace at least a part of an original gate of a conventional MOSFET.
60. The method according to claim 33, which comprises:
first, using self-aligning polysilicon technology to form a conventional MOSFET having an original gate embedded in an insulation region;
second, removing the original gate of the MOSFET to create a recess in the insulation region embedding the original gate; and
third, forming the plurality of the memory gate regions in the recess, embedding the plurality of the memory gate regions in an insulating manner, and providing the control gate configuration.
61. The method according to claim 33, which comprises: first embedding an original gate of a conventional MOSFET in an insulation region, the original gate having a surface region defining a level; and second, performing a planarization step and stopping on the level of the surface region of the original gate.
62. The method according to claim 61, which comprises providing the insulation region as SiO2.
63. The method according to claim 61, which comprises using a masked etching to remove the original gate of the conventional MOSFET and to thereby form a recess in the insulation region in a region above and between source/drain regions of the source/drain configuration.
64. The method according to claim 63, which comprises conformally depositing a spacer layer such that the recess is lined.
65. The method according to claim 64, which comprises providing the spacer layer as silicon nitride, an ONO structure, or an NO structure.
66. The method according to claim 63, which comprises conformally depositing at least one material layer for producing the plurality of the memory gate regions such that edge regions of the recess are lined.
67. The method according to claim 66, which comprises:
in order to form floating gates, using an electrically conductive material for the material layer for producing the plurality of the memory gate regions;
for forming charge trapping gates, using an electrically insulating material for the material layer for producing the plurality of the memory gate regions; and
for the electrically insulating material, using a material that has or that can form a high density of traps.
68. The method according to claim 66, which comprises patterning the material layer by anisotropically etching the material layer such that the plurality of the memory gate regions remain as spatially separate parts of the material layer in edge regions of the recess.
69. The method according to claim 68, which comprises performing a thermal oxidation or a deposition and subsequently etching back to make an original gate insulator or an original gate oxide located between the plurality of the memory gate regions thicker than a gate insulator or a gate oxide located below the plurality of the memory gate regions.
70. The method according to claim 68, which comprises conformally depositing at least one insulation layer to embed the plurality of the memory gate-regions in the insulation layer.
71. The method according to claim 70, which comprises depositing and patterning at least one material layer for the control gate configuration such that the recess is filled.
Description
BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The invention relates to a semiconductor memory cell a semiconductor memory device, and a method for fabricating a semiconductor memory cell.

[0003] In further developing semiconductor memory devices that are based on non-volatile memory mechanisms, the principles of the so-called non-volatile floating gate memory cell and of the charge trapping cell have also been developed. Such semiconductor memory cells for storing non-volatile information have a memory gate configuration, a source/drain configuration, and a control gate configuration. The memory gate configuration serves for storing the actual information, while the source/drain configuration is designed for accessing the memory gate configuration and thus for accessing the respective information. The control gate configuration is designed for controlling this access to the memory gate configuration and to the information. What is disadvantageous about known semiconductor memory devices is that from a structural and production engineering standpoint, the fundamental concept on which the memory cells contained in the memory devices and the corresponding fabrication methods for producing semiconductor memory devices or memory cells is based on providing a single binary information unit in each individual memory cell. Each memory cell and thus each memory location are thus occupied only singularly with information and is designed accordingly.

SUMMARY OF THE INVENTION

[0004] It is accordingly an object of the invention to provide a semiconductor memory cell, a method for fabricating the memory cell, and a semiconductor memory device that overcome the above-mentioned disadvantages of the prior art apparatus and methods of this general type.

[0005] In particular, it is an object of the invention to provide a semiconductor memory cell, a method for fabricating the memory cell, and a semiconductor memory device, that in a particularly simple manner, enable a particularly high information density to be obtained and enable the information to be modified and retrieved in a particularly reliable manner.

[0006] With the foregoing and other objects in view there is provided, in accordance with the invention, a semiconductor memory cell for non-volatile information storage. The semiconductor memory cell includes: a memory gate configuration designed for non-volatile information storage; a source/drain configuration designed for accessing the memory gate configuration; and a control gate configuration designed for controlling access to the memory gate configuration. The memory gate configuration has a plurality of memory gate regions. Each of the plurality of the memory gate regions is designed for essentially independent information storage such that a corresponding plurality of information units can be stored independently of one another.

[0007] The inventive semiconductor memory cell for non-volatile information storage is characterized by providing the memory gate configuration with a plurality of memory gates, and by designing each of the memory gates for essentially independent information storage. As a result, a corresponding plurality of information units, in particular binary bits, can be stored independently in the memory cell. The terms memory gate and memory gate region are used synonymously hereinafter.

[0008] Thus, in contrast to the prior art, the invention departs from the one-bit concept, and consequently, the inventive semiconductor memory cell is designed for storing a plurality of information units, in particular binary bits or the like. This is realized by virtue of the fact that, in contrast to the prior art semiconductor memory cell, the inventive memory gate configuration is designed with a plurality of memory gates. In this case, it is provided that each of the memory gates is designed for separate and independent information storage independently of the other memory gates. Consequently, by way of example, a respective bit can be written and retrieved, in accordance with an impressed charge or potential state, in each of the memory gates.

[0009] Each memory gate can also be designed for taking up more than two charge and/or potential states, so that the information density per semiconductor memory cell is increased further in that e.g. each memory gate is designed for storing more than one bit.

[0010] It is particularly advantageous if the memory gate regions are designed such that they are, pairwise, spatially separate from one another and/or electrically insulated from one another. This is because, at locations that are spatially separate from one another, different information contents can then be read out, written in, or influenced in some other way, in a particularly simple manner, independently, in a manner isolated from one another.

[0011] The structure of the inventive semiconductor gate memory cell is configured particularly simply if, in accordance with a particularly preferred embodiment, the control gate configuration has a common control gate and access to the memory gates and the information state contained therein can be jointly controlled by the one common control gate. The initial organizational combination to a common control gate results in a particularly simple control of the access to the information that will be stored in the memory gate. The initially organizational and sequence-technical assignment of the memory gates to a common control gate will advantageously also be represented in a structural or spatial assignment, in particular, in a particular spatial proximity of the assigned floating gates with respect to the control gate.

[0012] A further simplification of the inventive semiconductor memory cell results if the source/drain configuration has a plurality of source/drain regions, the number of source/drain regions of the source/drain configuration corresponds to the number of memory gates or memory gate regions of the memory gate configuration, and a respective memory gate or a respective memory gate region is assigned precisely one respective source/drain region in such a way that all of the memory gates or memory gate regions can be accessed independently of one another.

[0013] With regard to a particularly simple fabrication procedure and also with regard to a corresponding functional reliability, the geometrical and/or material properties of the memory gates are designed essential identically.

[0014] For the reliability of the inventive semiconductor memory cell, on the other hand, the memory gates are arranged and designed in a manner essentially electrically insulated from one another, from the control gate and from the source/drain regions.

[0015] In accordance with another embodiment of the inventive semiconductor memory cell, the memory gate regions are designed as floating gate regions or floating gates, so that the semiconductor memory cell functions as a floating gate memory cell.

[0016] In this case, the memory gate regions are designed and arranged as floating gates in an essentially capacitively coupled manner in the memory cell.

[0017] Furthermore, the memory gate regions are designed as floating gates made of a polysilicon material, polycide, metal and/or the like.

[0018] In another embodiment of the inventive semiconductor memory cell, the memory gate regions are designed as charge trapping regions, charge trapping layers, charge trapping gate regions or charge trapping gates, so that the inventive semiconductor memory cell functions as a charge trapping memory cell.

[0019] In this case, the charge trapping gates are composed of a material or have such a material in which charge trapping states can be formed. In particular, the material is an insulator which has or which can form a sufficient number of defects which, for their part, can be occupied by electrons and/or by holes or the like.

[0020] Moreover, it is provided that the charge trapping gates are composed of silicon nitride, ZrO2, Al2O3, Ta2O5, HfO2 and/or the like or have such a material. In this case, it is possible in addition to provide an insulation layer toward the control gate, toward the source/drain and/or channel region, given the use of nitride, e.g. in the form of an ONO structure, NO structure.

[0021] In another embodiment of the inventive semiconductor memory cell, each memory gate region or each memory gate can assume a plurality of charge and/or potential states, in particular two, which correspond to information states assigned to the memory gate regions or memory gates.

[0022] It is further preferred that the control gate is arranged and designed in a manner essentially electrically insulated from the memory gates and from the source/drain regions.

[0023] In accordance with another embodiment of the inventive semiconductor memory cell, the control gate is composed of a polysilicon material, polycide, metal and/or the like.

[0024] In order to realize the assignment between the memory gates and with respect to the common control gate, in accordance with a preferred embodiment of the inventive semiconductor memory cell, the memory gates and the control gate are in each case designed in direct spatial proximity to one another. Respective intermediate insulation regions are provided, in particular, in each case an intermediate dielectric is provided between the memory gates and the control gate.

[0025] The intermediate dielectric is also referred to, if appropriate, as an interpoly dielectric and may be e.g. an NO or ONO structure, i.e. a structure with a configuration including nitride/oxide or oxide/nitride/oxide, respectively. However, pure silicon dioxide is also possible.

[0026] It is furthermore preferred that each memory gate is designed and arranged in direct spatial proximity to a respectively assigned source/drain region. As a result, in particular, a spatial or areal overlap is formed between the memory gates and the source/drain regions.

[0027] In accordance with another embodiment of the inventive semiconductor memory cell, an insulation region, in particular in the form of a silicon-dioxide material, is provided between the respective memory gate and the source/drain regions.

[0028] With the foregoing and other objects in view there is provided, in accordance with the invention, an inventive semiconductor memory device having a plurality of the inventive memory cells for non-volatile information storage.

[0029] In a particularly preferred embodiment, adjacent memory cells use at least some of the control gates as common control gates.

[0030] The inventive method for fabricating a semiconductor memory cell for non-volatile information storage is presented below. A fabrication method of the generic type is used as a basis in this case. In the case of this method of the generic type, a memory gate configuration, a source/drain configuration and a control gate configuration are provided. The memory gate configuration is designed for the actual information storage. The source/drain configuration is designed for access to the memory gate configuration. The control gate configuration is designed for controlling the access to the memory gate configuration and to the information contained therein.

[0031] The inventive method for fabricating a semiconductor memory cell is characterized in that the memory gate configuration is designed with a plurality of memory gates or memory gate regions, in that each of the memory gates is designed for essentially independent information storage, and in that, as a result, a corresponding plurality of information units, in particular binary bits or the like, can be stored independently of one another in the memory cell.

[0032] Preferably, the memory gate regions or memory gates are designed such that they are, pairwise, spatially separate from one another and/or electrically insulated from one another.

[0033] In a particularly preferred embodiment of the fabrication method, the control gate configuration has a common control gate, and access to the memory gates is jointly controllable by the common control gate.

[0034] On the other hand, the source/drain configuration is formed with a number of source/drain regions. The number of the source/drain regions formed corresponds to the plurality of memory gate regions provided, and a respective memory gate region is assigned to precisely one respective source/drain region, so that, as a result, all of the memory gates or memory gate regions can be accessed independently of one another via the plurality of source/drain regions.

[0035] In a particularly preferred embodiment of the fabrication method, in each case the memory gates are designed essentially identically with regard to their geometrical and/or material properties.

[0036] In another embodiment of the method, the memory gate regions are designed as floating gate regions or floating gates, so that the semiconductor memory device functions as a floating gate memory cell.

[0037] Furthermore, in this case the memory gate regions are designed and arranged as floating gates in an essentially capacitively coupled manner in the inventive semiconductor memory cell.

[0038] Furthermore, it is advantageous in this case if the memory gate regions are designed as floating gates made of a polysilicon material, polycide, metal and/or the like.

[0039] On the other hand, in accordance with another advantageous embodiment of the method, the memory gate regions can be designed as charge trapping gate regions or charge trapping gates, so that the inventive semiconductor memory cell functions as a charge trapping memory cell.

[0040] In this case, it is then advantageous if the charge trapping gates are composed of a material or have such a material in which charge trapping states can be formed, in particular an insulator which has or can form a sufficient number of defects which can be occupied by electrons and/or by holes.

[0041] In this case, it is furthermore advantageous if the charge trapping gates are formed with silicon nitride, e.g. with an ONO structure, NO structure, including ZrO2, Al2O3, Ta2O5, HfO2 and/or the like.

[0042] In a further advantageous embodiment of the method, the memory gate regions or memory gates are designed in such a way that each of the memory gate regions can assume a plurality of charge and/or potential states, in particular two, which correspond to information states assigned to the memory gate regions.

[0043] It is furthermore preferred that the memory gates and/or the control gate are arranged and designed in a manner essentially electrically insulated from one another, from the control gate and/or from the memory gates and from the source/drain regions.

[0044] The control gate is preferably formed from a polysilicon material, polycide, metal and/or the like. It is advantageous to design the control gate in each case with low impedance. By contrast, the memory gates can also have high impedance.

[0045] In order to realize the assignment between the respective floating gates and the control gate, the memory gates and the control gate are formed in direct spatial proximity to one another, and in this case, in particular, an intermediate .insulation region is provided in each case, in particular an intermediate dielectric.

[0046] Preferably, each memory gate is designed or arranged in direct spatial proximity to the first source/drain region. As a result, in particular, a spatial or areal overlap is formed between the memory gates and the source/drain regions. Preferably, an insulation region, in particular in the form of a silicon dioxide material, is furthermore formed between the respective memory gates and the respective source/drain region.

[0047] The previous characterizing features of the fabrication method represent, in part the structural features of the inventive semiconductor memory cell that will be formed. However, different configurations are furthermore conceivable during the fabrication.

[0048] In a particularly advantageous embodiment of the inventive fabrication method, it is provided that first a conventional MOSFET is formed, in particular using self-aligning or self-aligned polysilicon gate technology. In this case, the original gate of the conventional MOSFET is then subsequently removed to create a recess in an insulation region embedding the original gate. Afterward, in the recess the memory gate configuration with the plurality of memory gate regions or memory gates is then formed, and is embedded in an insulated manner and provided with a control gate configuration.

[0049] In a further advantageous embodiment of the method, it is provided that, for that purpose, first the original gate of the conventional MOSFET is embedded in an insulation region, preferably made of SiO2, and then a planarization step with a stop on the level of the surface region of the original gate of the conventional MOSFET subsequently takes place.

[0050] For more concrete implementation of the method, it is advantageously provided that the original gate of the conventional MOSFET is removed, to be precise preferably by masked etching back. In this case, in particular, a recess is formed in the insulation region, preferably in a region above and between the source/drain regions of the original MOSFET.

[0051] Then, a spacer layer is optionally deposited conformally in such a way that the recess is filled—silicon nitride, an NO structure and/or the like being used.

[0052] In a further-preferred embodiment of the fabrication method, at least one material layer for the memory gates or memory gate regions of the memory gate configuration is deposited conformally in-such a way that the recess is lined, in particular in edge regions thereof.

[0053] Furthermore, it is advantageous if for forming floating gates, an electrically conductive material is used for the material layer of the memory gates or memory gate regions. On the other hand, in an advantageous manner, for forming charge trapping gates or charge trapping gate regions, an electrically insulating material is used for the material layer of the memory gates or memory gate regions, to be precise a material which, in particular, has a high density of so-called traps or can form such traps.

[0054] In a further preferred embodiment of the fabrication method, it is provided that in order to form the memory gates, the material region for the memory gates is patterned by anisotropic etching back, and that in this case, in particular, the memory gates remain as spatially separate parts of the material layer for the memory gates in the edge region of the recess.

[0055] When an electrically conductive floating gate is used, a masked etching is provided for isolating-the initially contiguous floating gate regions.

[0056] Furthermore, it is advantageous if at least one insulation layer is then deposited, in particular conformally, such that the memory gate regions or memory gates are embedded by the insulation layer.

[0057] Afterward, a material layer for the control gate configuration is then advantageously deposited and patterned, in particular, the recess in the insulation region is filled.

[0058] The above-described and further aspects of the present invention are also explained on the basis of the remarks below:

[0059] In flash or EEPROM memory cells, it is usually possible to store a plurality of bits per cell by storing different charge states. Recent developments also utilize cells in which a respective bit is stored at spatially separate locations. A new method for fabricating an EEPROM or flash cell, in which two bits are stored at locations that are spatially separate from one another, is presented in the context of this explanation of the invention.

[0060] Storing two bits in one flash cell has been realized heretofore either by using a continuous Si3N4 layer (NROM concept) or by storing a plurality of charge states in one cell. In production, floating gate cells have heretofore exclusively stored a plurality of charge states in a floating gate for storing a plurality of bits in one cell. It is also known to form a floating gate memory cell for storing two bits at different locations of the memory cell.

[0061] The inventive fabrication of spacers makes it possible to form two bits at different locations of a floating gate or charge trapping memory cell. In contrast to the known cells in which charge is stored either in a continuous layer through localized introduction of charge carriers in traps or in floating gate spacer regions lying next to the control gate, here spacers are provided below the control gate. This is achieved by after fabricating a conventional n-channel MOS transistor, removing the polysilicon gate and then fabricating floating gate or charge trapping spacers, and after the applying an insulation dielectric, applying the control gate.

[0062] Advantages appertaining to the realization with a floating gate reside in the better coupling of the control gate to the floating gate regions in comparison with the known method.

[0063] The advantage appertaining to the charge trapping embodiment resides in the structure of the charge trapping layer. Programming of regions that are far away from the locations to be programmed is thus not possible, and this allows one to expect that an improved cycle stability will be obtained.

[0064] One inventive idea lies in first fabricating a conventional n-channel transistor (if appropriate with additional implantation steps) and then removing the gate. This enables the active memory regions to be fabricated in a structured manner in the region of the transistor.

[0065] The inventive semiconductor memory cell is also called a replacement gate memory cell or an exchange gate memory cell. This cell includes a source region and a drain region, two memory regions and also a control gate. This memory cell is suitable for being incorporated into a virtual ground NOR array, but the cell can be used—with a slight modification in—any NOR-like array architecture. 2-Bit replacement gate memory cell architectures:

[0066] In principle, the memory cell can be integrated into all known NOR-like architectures. Preference is given to the virtual ground NOR architecture (as in the case of the NROM) since this is particularly space-saving. In this architecture, the diffusion tracks are used as bit lines. The latter may, if appropriate, be short-circuited by metal interconnects in an upper plane in order to reduce the resistance. In this case, contacts have to be present only for every n-th cell (n>=1). A NOR architecture with metal bit lines is also possible as an alternative, but a source line must then be available for each bit line in order to utilize the 2-bit capability of the cell.

[0067] Charge can be stored in each of the two memory layer regions. The charge can be introduced either by:

[0068] the injection of hot electrons (preferred method as in the case of NROM) or by

[0069] tunneling from the respective adjoining drain or source region into the memory layer.

[0070] The last-mentioned method cannot, however, be realized in conjunction with a virtual ground architecture (preferred embodiment) since then two bits would be programmed in parallel in each case.

[0071] The charge can be removed from the memory layer either by:

[0072] the injection of hot holes (preferred method as in the case of NROM) or by

[0073] tunneling to the channel region.

[0074] During reading, the end of the memory cell that is to be read forms the source, since the threshold voltage of the cell reacts very much more greatly to a charge in the vicinity of the source given sufficiently high drain voltage.

[0075] For fabricating a 2-bit replacement gate memory cell the following sequences are conceivable:

[0076] Fabricating a conventional NMOS transistor using self-aligning poly-gate technology (prior art); the source and drain implantations and also the well doping were adapted to the requirements, if appropriate, by using additional implantation masks.

[0077] An insulation oxide is subsequently deposited.

[0078] The planarization of the insulation oxide with a stop on the polysilicon gate.

[0079] Masked etching-back of the polysilicon; the polysilicon remains in the case of the CMOS transistors in the periphery. Optionally, the gate oxide can also be etched and then a new tunnel oxide can be grown.

[0080] Optionally, first a spacer made of silicon nitride or a nitride/oxide double layer can also be introduced (fabrication-analogous to the next two steps, which can later be used for fabricating self-aligned contacts). If appropriate, this necessitates the adaptation of the doping by using an additional heat treatment.

[0081] The deposition of the memory layer. Two embodiments are conceivable here:

[0082] 1. The deposition of a conductive layer. Polysilicon is used in the preferred embodiment of this variant of the invention,

[0083] or

[0084] 2. The deposition of an insulating layer with a high density of traps. Silicon nitride is used in the preferred embodiment of this variant.

[0085] Anisotropic etching back and masked isotropic etching of the memory layer. The masked etching serves for isolating the memory regions of different cells, for removing the memory material from the transistors in the periphery, and in the case of floating gates, for isolating the two memory gates of a cell.

[0086] The deposition of a thin insulation oxide. This may also involve a multilayer including a plurality of dielectrics (preferably ONO) which can also be fabricated from a combination of deposition and thermal oxidation.

[0087] ONO is preferably used in the variant of the invention with a polysilicon memory layer, and silicon dioxide is preferably used in the variant with a silicon nitride memory layer.

[0088] The masked removal of the insulation dielectric in the periphery (not illustrated).

[0089] The deposition of the gate layer (polysilicon, polycide, metal or a layer sequence including polysilicon and silicide or metal).

[0090] In the periphery, this layer or layer sequence can be used together with the poysilicon that is initially present as a gate electrode. As an alternative, the layer in the periphery can also be removed.

[0091] Patterning the polysilicon.

[0092] In the preferred embodiment (virtual ground architecture), the polysilicon is patterned in tracks running parallel to the plane of-the drawing. Patterning in tracks perpendicular to the plane of the drawing is also possible in other architectures. This can be effected particularly advantageously by CMP (Chemical Mechanical Polishing) polishing of the gate material with a stop on the insulation oxide (illustrated case). In the last-mentioned case, the optional nitride spacer between steps 3 and 4 may enable the fabrication of self-aligned contacts. The last-mentioned variant of CMP planarization is also suitable, in particular, for integrating a metal control gate electrode.

[0093] Other features which are considered as characteristic for the invention are set forth in the appended claims.

[0094] Although the invention is illustrated and described herein as embodied in a semiconductor memory cell, method for fabricating it and semiconductor memory device, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.

[0095] The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0096] FIGS. 1-8 are diagrammatic lateral cross-sectional views of intermediate states of a semiconductor memory cell that are reached in an exemplary embodiment of an inventive fabrication method.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0097] In the figures described below, identical reference symbols always designate identical elements, and therefore, a detailed description is not given for every occurrence.

[0098]FIG. 1 shows a diagrammatic and lateral cross-sectional view of the starting point for performing an embodiment of the inventive method for fabricating an inventive semiconductor memory cell. This starting point consists essentially of fabricating a standard MOSFET in a semiconductor substrate 20 or the like. First and second source/drain regions SD1 and SD2 are formed in the semiconductor substrate 20, and in particular, in the surface region 20 a thereof. An intermediate region 22 is provided in the semiconductor substrate between the source/drain regions SD1 and SD2. This intermediate region 22 functions as channel region K. A so-called gate oxide GOX is formed on the surface region 22 a of the semiconductor substrate 20. This gate oxide GOX terminates to directly touch the free surface region 20 a of the semiconductor substrate 20 and also the source/drain regions SD1 and SD2 that are embedded there and that terminate at the surface 22 a. On the side of the gate oxide GOX that is remote from the intermediate region 22 or the channel region K, the so-called gate or original gate U of the original MOSFET M is formed, which, for its part, is embedded in an insulation layer or an insulation region I. This starting state is illustrated in FIG. 1.

[0099] In the transition to the intermediate state shown in the lateral cross-sectional view of FIG. 2, the insulation layer I embedding the original gate U is then planarized to the level of the surface region Ua of the original gate U, so that the insulation layer or the insulation region I (oxide, for example) terminates flush with the level of the surface region Ua of the original polysilicon gate U.

[0100] In the transition to the intermediate state shown in FIG. 3, the original gate U (a polysilicon gate) is then selectively removed, thereby forming a recess A in the insulation region I. This recess A has side wall regions or edge regions Ab and also a bottom region Aa.

[0101] In the transition to the intermediate state shown in FIG. 4, a material layer 100 for producing the memory gate regions F1 and F2 (See FIG. 5) of the memory gate configuration F that will be formed is deposited in a conformal manner in such a way that at least the wall regions or edge regions Ab of the recess A in the insulation region I are covered. In this case, conductive materials, in particular polysilicon, polycide, metal or the like, are used for forming floating gates. When forming so-called charge trapping gate regions, by contrast, use is made essentially of an electrically insulating material that has a high density of defects or that can form such defects, which are then occupied by electrons or by holes or the like. In this case, silicon nitride or the like is preferred.

[0102] In the transition to the intermediate state shown in FIG. 5, the essentially contiguous region of the material region 100 for the memory gate regions F1 and F2 is then etched back anisotropically in order to form separate memory gate regions F1 and F2 in a form spatially separate from one another and essentially electrically insulated from one another. These memory gate regions F1 and F2, as an ensemble, form the memory gate configuration F of the inventive semiconductor memory cell 10. As is clearly revealed in FIG. 5, the memory gate regions F1 and F2 formed are spatially separated from one another by an intermediate region and are each situated at the junction between an edge region Ab and the bottom region Aa of the recess' A that was formerly occupied by the original gate U of the conventional MOSFET M.

[0103] When using floating gates, it is additionally necessary to carry out a masked etching in order to isolate the floating gate regions in the planes parallel to the plane of the drawing.

[0104] This etching can be obviated in the case of charge trapping layers.

[0105] It is then optionally possible (not illustrated) to deposit an insulation region, preferably made of silicon dioxide, in the region between the memory regions either by thermal oxidation or by deposition and subsequent etching back to the level of the memory regions. This insulation region serves for preventing a charge exchange between channel and control gate during Fowler-Nordheim programming.

[0106] Afterward, as is illustrated in FIG. 6, a material layer 110 for a further insulation region is then formed. This insulation region 110 serves for electrically insulating the memory gate regions F1 and F2 from one another and for electrically insulating the memory gate regions F1 and F2 from the control gate G that will be formed later. FIG. 6 also reveals that part of the recess A of the original insulation region I still remains free after forming the memory gate regions F1 and F2 and after the essentially conformal deposition of the further insulation region 110.

[0107] In the transition to the intermediate state shown in FIG. 7, this remaining recess A in the insulation region I is then filled with a material layer 120 for the control gate G that will be formed. The material layer 120 is then patterned, in the transition to the intermediate state shown in FIG. 8, by removing the material layer 120 for the control gate G and stopping on the surface level 110A of the further insulation region 110. As an alternative, etching back or masked etching is also conceivable, during which the remaining control gate regions are formed with wiring in the same step. FIG. 8 also shows that the recess A for the original gate U of the conventional MOSFET M is now filled by the memory gate regions F1 and F2, a corresponding insulation region 110 and the control gate G. Consequently, the original gate U has been replaced by a spatially separate plurality of memory gate regions F1 and F2 and the control gate G—a circumstance which, with regard to the inventive memory cell 10, also leads to the term replacement gate memory cell or exchange gate memory cell.

Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US6897522Oct 31, 2001May 24, 2005Sandisk CorporationMulti-state non-volatile integrated circuit memory systems that employ dielectric storage elements
US6925007Oct 25, 2002Aug 2, 2005Sandisk CorporationMulti-state non-volatile integrated circuit memory systems that employ dielectric storage elements
US6987297 *Feb 2, 2004Jan 17, 2006Fujitsu LimitedSemiconductor memory device and manufacturing method thereof
US7064030Oct 8, 2004Jun 20, 2006Freescale Semiconductor, Inc.Method for forming a multi-bit non-volatile memory device
US7132332Oct 12, 2005Nov 7, 2006Fujitsu LimitedSemiconductor memory device and manufacturing method thereof
US7132337Dec 20, 2004Nov 7, 2006Infineon Technologies AgCharge-trapping memory device and method of production
US7135737 *Dec 29, 2004Nov 14, 2006Dongbu Electronics Co., Ltd.Non-volatile flash memory device
US7157345 *Jun 29, 2005Jan 2, 2007Freescale Semiconductor, Inc.Source side injection storage device and method therefor
US7177185 *Dec 29, 2004Feb 13, 2007Dongbu Electronics Co., Ltd.Non-volatile flash memory device having dual-bit floating gate
US7235823Sep 28, 2006Jun 26, 2007Freescale Semiconductor, Inc.Source side injection storage device with spacer gates and method therefor
US7272040Apr 29, 2005Sep 18, 2007Infineon Technologies AgMulti-bit virtual-ground NAND memory device
US7402490Oct 19, 2005Jul 22, 2008Infineon Technologies AgCharge-trapping memory device and methods for operating and manufacturing the cell
US7511334 *Dec 8, 2005Mar 31, 2009Samsung Electronics Co., Ltd.Twin-ONO-type SONOS memory
US7518179Oct 8, 2004Apr 14, 2009Freescale Semiconductor, Inc.Virtual ground memory array and method therefor
US7550348Sep 28, 2006Jun 23, 2009Freescale Semiconductor, Inc.Source side injection storage device with spacer gates and method therefor
US7842573Mar 4, 2009Nov 30, 2010Freescale Semiconductor, Inc.Virtual ground memory array and method therefor
US8551858Feb 3, 2010Oct 8, 2013Spansion LlcSelf-aligned SI rich nitride charge trap layer isolation for charge trap flash memory
US8642441 *Dec 15, 2006Feb 4, 2014Spansion LlcSelf-aligned STI with single poly for manufacturing a flash memory device
DE102005025167B3 *Jun 1, 2005Jul 13, 2006Infineon Technologies AgMulti-bit virtual ground NAND-memory unit, has memory cells of two adjacent groups of rows connected in common
WO2005050734A1 *Oct 26, 2004Jun 2, 2005Infineon Technologies AgCharge-trapping memory device, operating and manufacturing
Classifications
U.S. Classification257/315, 257/E29.308, 257/E21.209
International ClassificationH01L29/788, H01L29/792, H01L21/28, G11C16/04
Cooperative ClassificationH01L21/28273, H01L29/7923, H01L29/7887, G11C16/0475
European ClassificationH01L29/788C, G11C16/04M2, H01L29/792B, H01L21/28F