Search Images Maps Play YouTube News Gmail Drive More »
Sign in
Screen reader users: click this link for accessible mode. Accessible mode has the same essential features but works better with your reader.

Patents

  1. Advanced Patent Search
Publication numberUS20030082307 A1
Publication typeApplication
Application numberUS 10/193,333
Publication dateMay 1, 2003
Filing dateJul 10, 2002
Priority dateOct 26, 2001
Also published asCN1774525A, CN1774525B, CN100524692C, CN101174577A, US6916398, US7780788, US8293328, US8318266, US8668776, US20030079686, US20030082301, US20030124262, US20050173068, US20070003698, US20070026147, US20070099415, US20080038463, US20100247767
Publication number10193333, 193333, US 2003/0082307 A1, US 2003/082307 A1, US 20030082307 A1, US 20030082307A1, US 2003082307 A1, US 2003082307A1, US-A1-20030082307, US-A1-2003082307, US2003/0082307A1, US2003/082307A1, US20030082307 A1, US20030082307A1, US2003082307 A1, US2003082307A1
InventorsHua Chung, Ling Chen
Original AssigneeApplied Materials, Inc.
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Integration of ALD tantalum nitride and alpha-phase tantalum for copper metallization application
US 20030082307 A1
Abstract
A method for forming a metal interconnect on a substrate is provided. The method includes depositing a refractory metal-containing barrier layer having a thickness less than about 20 angstroms on at least a portion of a metal layer by alternately introducing one or more pulses of a metal-containing compound and one or more pulses of a nitrogen-containing compound. The method also includes depositing a seed layer on at least a portion of the barrier layer, and depositing a second metal layer on at least a portion of the seed layer. The barrier layer provides adequate barrier properties and allows the grain growth of the metal layer to continue across the barrier layer into the second metal layer thereby enhancing the electrical performance of the interconnect.
Images(5)
Previous page
Next page
Claims(33)
1. A method for forming a metal interconnect on a substrate, comprising:
depositing a refractory metal containing barrier layer having a thickness that exhibits a crystalline like structure and is sufficient to inhibit atomic migration on at least a portion of a metal layer by alternately introducing one or more pulses of a metal-containing compound and one or more pulses of a nitrogen-containing compound;
depositing a seed layer on at least a portion of the barrier layer; and
depositing a second metal layer on at least a portion of the seed layer.
2. The method of claim 1, wherein the refractory metal containing barrier comprises tantalum nitride.
3. The method of claim 1, wherein a grain growth of the metal layer continues across the barrier layer into the second metal layer.
4. The method of claim 1, wherein each pulse is repeated until the refractory metal containing barrier layer has a thickness less than about 20 angstroms.
5. The method of claim 1, wherein each pulse is repeated until the refractory metal containing barrier layer has a thickness of about 10 angstroms.
6. The method of claim 1, wherein the refractory metal containing barrier layer has a thickness of about 10 angstroms.
7. The method of claim 1, wherein the alternate pulsing is repeated between about 10 and about 70 times to form the refractory metal nitride layer.
8. The method of claim 1, further comprising flowing a purge gas continuously during each pulse of the metal-containing compound and each pulse of the nitrogen-containing compound.
9. The method of claim 8, wherein the purge gas comprises argon, nitrogen, helium, or combinations thereof.
10. The method of claim 8, wherein the purge gas has a flowrate of about 200 sccm to about 1,000 sccm.
11. The method of claim 1, wherein each pulse of the metal-containing compound has a flow rate of about 100 sccm to about 400 sccm.
12. The method of claim 1, wherein each pulse of the nitrogen-containing compound has a flow rate of about 200 sccm to about 600 sccm.
13. The method of claim 1, wherein each pulse of the metal-containing compound and the nitrogen-containing is separated by a time delay.
14. The method of claim 13, wherein each time delay is long enough for a volume of the metal-containing compound or a volume of the nitrogen-containing compound to adsorb onto the substrate surface.
15 The method of claim 14, wherein the time delay is long enough to remove non-adsorbed molecules from the substrate surface.
16. The method of claim 1, wherein the nitrogen-containing compound is selected from a group consisting of ammonia; hydrazine; methylhydrazine; dimethylhydrazine; t-butylhydrazine; phenylhydrazine; azoisobutane; ethylazide; derivatives thereof; and combinations thereof.
17. The method of claim 1, wherein the metal-containing compound is selected from a group consisting of: tetrakis (dimethylamino) titanium (TDMAT); tetrakis (ethylmethylamino) titanium (TEMAT); tetrakis (diethylamino) titanium (TDEAT); titanium tetrachloride (TiCl4); titanium iodide (Til4); titanium bromide (TiBr4); t-butylimino tris(diethylamino) tantalum (TBTDET); pentakis (ethylmethylamino); tantalum (PEMAT); pentakis (dimethylamino) tantalum (PDMAT); pentakis (diethylamino) tantalum (PDEAT); t-butylimino tris(diethyl methylamino) tantalum(TBTMET); t-butylimino tris(dimethyl amino) tantalum (TBTDMT); bis(cyclopentadienyl) tantalum trihydride ((Cp)2TaH3); bis(methylcyclopentadienyl) tantalum trihydride ((CpMe)2TaH3); derivatives thereof; and combinations thereof.
18. The method of claim 1, wherein the first and second metal layers each comprise tungsten, copper, or a combination thereof.
19. The method of claim 1, wherein the seed layer comprises copper and a metal selected from the group consisting of aluminum, magnesium, titanium, zirconium, tin, and combinations thereof.
20. The method of claim 1, wherein the seed layer is a dual alloy seed layer comprising copper and aluminum.
21. The method of claim 1, wherein the seed layer comprises a first seed layer deposited over the barrier layer and a second seed layer deposited over the first seed layer.
22. The method of claim 21, wherein the first seed layer comprises a copper alloy seed layer of the copper and a metal selected from the group consisting of aluminum, magnesium, titanium, zirconium, tin, and combinations thereof.
23. The method of claim 21, wherein the second seed layer comprises undoped copper.
24. The method of claim 21, wherein the first seed layer comprises a metal selected from the group consisting of aluminum, magnesium, titanium, zirconium, tin, and combinations thereof.
25. The method of claim 24, wherein the second seed layer comprises undoped copper.
26. A method for forming a metal interconnect on a substrate, comprising:
depositing a tantalum nitride barrier layer having a thickness less than about 20 angstroms on at least a portion of a metal layer by alternately introducing one or more pulses of a tantalum-containing compound and one or more pulses of a nitrogen-containing compound;
depositing a dual alloy seed layer; and
depositing a second metal layer on at least a portion of the dual alloy seed layer.
27. A method for forming a metal interconnect on a substrate, comprising:
depositing a first metal layer on a substrate surface;
depositing a titanium silicon nitride layer having a thickness less than about 20 angstroms over at least a portion of the first metal layer by alternately introducing one or more pulses of a titanium-containing compound, one or more pulses of a silicon-containing compound, and one or more pulses of a nitrogen-containing compound;
depositing a dual alloy seed layer; and
depositing a second metal layer on at least a portion of the dual alloy seed layer.
28. A method for forming a metal interconnect on a substrate, comprising:
depositing a tantalum silicon nitride layer having a thickness less than about 20 angstroms on at least a portion of a metal layer by alternately introducing one or more pulses of a tantalum-containing compound, one or more pulses of a silicon-containing compound, and one or more pulses of a nitrogen-containing compound;
depositing a dual alloy seed layer; and
depositing a second metal layer on at least a portion of the dual alloy seed layer.
29. A method for forming a metal interconnect on a substrate, comprising:
depositing a bilayer barrier having a thickness less than about 20 angstroms on at least a portion of a metal layer, the bilayer barrier comprising:
a first layer of tantalum nitride deposited by alternately introducing one or more pulses of a tantalum-containing compound and one or more pulses of a nitrogen-containing compound; and
a second layer of alpha phase tantalum;
depositing a dual alloy seed layer; and
depositing a second metal layer on at least a portion of the dual alloy seed layer.
30. A method for forming a metal interconnect on a substrate, comprising:
depositing a first metal layer on a substrate surface;
depositing a tantalum nitride barrier layer having a thickness less than about 20 angstroms on at least a portion of the first metal layer by alternately introducing one or more pulses of a tantalum-containing compound and one or more pulses of a nitrogen-containing compound;
depositing a dual alloy seed layer comprising copper and a metal selected from the group consisting of aluminum, magnesium, titanium, zirconium, tin, and combinations thereof; and
depositing a second metal layer on at least a portion of the dual alloy seed layer.
31. The method of claim 30, wherein the dual alloy seed layer comprises a first seed layer deposited over the barrier layer and a second seed layer deposited over the first seed layer.
32. The method of claim 31, wherein the first seed layer comprises a copper alloy seed layer of the copper and the metal.
33. The method of claim 31, wherein the second seed layer comprises undoped copper.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims benefit of U.S. Provisional Patent Application Serial No. 60/346,086, filed on Oct. 26, 2001, and entitled “Method and Apparatus for ALD Deposition”, which is incorporated by reference herein. This application also claims benefit of U.S. patent application Ser. No. 09/965,370, filed on Sep. 26, 2001, and entitled “Integration of Barrier Layer and Seed Layer”, which is incorporated by reference herein. This application also claims benefit of U.S. patent application Ser. No. 09/965,373, filed on Sep. 26, 2001, and entitled “Integration of Barrier Layer and Seed Layer”, which is incorporated by reference herein. This application also claims benefit of U.S. patent application Ser. No. 09/965,369, filed on Sep. 26, 2001, and entitled “Integration of Barrier Layer and Seed Layer”, which is incorporated by reference herein.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] Embodiments of the present invention relate to a method for manufacturing integrated circuit devices. More particularly, embodiments of the invention relate to forming metal interconnect structures using one or more cyclical deposition processes.

[0004] 2. Description of the Related Art

[0005] As the structure size of integrated circuit (IC) devices is scaled down to sub-quarter micron dimensions, electrical resistance and current densities have become an area for concern and improvement. Multilevel interconnect technology provides the conductive paths throughout an IC device, and are formed in high aspect ratio features, including contacts, plugs, vias, lines, wires, and other features. A typical process for forming an interconnect on a substrate includes depositing one or more layers, etching at least one of the layer(s) to form one or more features, depositing a barrier layer in the feature(s) and depositing one or more layers to fill the feature. Typically, a feature is formed within a dielectric material disposed between a lower conductive layer and an upper conductive layer. The interconnect is formed within the feature to link the upper and lower conductive layers. Reliable formation of these interconnect features is important to the production of the circuits and continued effort to increase circuit density and quality on individual substrates and die.

[0006] Copper has recently become a choice metal for filling sub-micron high aspect ratio, interconnect features because copper and its alloys have lower resistivities than aluminum. However, copper diffuses more readily into surrounding materials and can alter the electronic device characteristics of the adjacent layers and, for example, form a conductive path between layers, thereby reducing the reliability of the overall circuit and may even result in device failure.

[0007] Barrier layers therefore, are deposited prior to copper metallization to prevent or impede the diffusion of copper atoms. Barrier layers typically contain of a refractory metal such as tungsten, titanium, tantalum, and nitrides thereof, which all have a greater resistivity than copper. To deposit a barrier layer within a feature, the barrier layer must be deposited on the bottom of the feature as well as the sidewalls thereof. Therefore, the additional amount of the barrier layer on the bottom of the feature not only increases the overall resistance of the feature, but also forms an obstruction between higher and lower metal interconnects of a multi-layered interconnect structure.

[0008] There is a need, therefore, for an improved method for forming metal interconnect structures which minimizes the electrical resistance of the interconnect.

SUMMARY OF THE INVENTION

[0009] A method for forming a metal interconnect on a substrate is provided. In one aspect, the method includes a refractory metal containing a barrier layer having a thickness that exhibits a crystalline like structure and is sufficient to inhibit atomic migration over at least a portion of a metal layer by alternately introducing one or more pulses of a metal-containing compound and one or more pulses of a nitrogen-containing compound; depositing a seed layer on at least a portion of the barrier layer; and depositing a second metal layer on at least a portion of the seed layer.

[0010] In another aspect, the method includes depositing a tantalum nitride barrier layer having a thickness less than about 20 angstroms over at least a portion of a metal layer by alternately introducing one or more pulses of a tantalum-containing compound and one or more pulses of a nitrogen-containing compound; depositing an alloy seed layer on the barrier layer; and depositing a second metal layer. The alloy seed layer may contain a dual alloy such as copper and a metal selected from the group consisting of aluminum, magnesium, titanium, zirconium, tin, and combinations thereof. The second metal layer may be formed using physical vapor deposition (CVD), physical vapor deposition (PVD), electroplating, or electroless techniques.

[0011] In still another aspect, the method includes depositing a titanium silicon nitride layer having a thickness less than about 20 angstroms over at least a portion of a metal layer by alternately introducing one or more pulses of a titanium-containing compound, one or more pulses of a silicon-containing compound, and one or more pulses of a nitrogen-containing compound; depositing a dual alloy seed layer; and depositing a second metal layer on the seed layer.

[0012] In still another aspect, the method includes depositing a tantalum silicon nitride layer having a thickness less than about 20 angstroms over at least a portion of the first metal layer by alternately introducing one or more pulses of a tantalum-containing compound, one or more pulses of a silicon-containing compound, and one or more pulses of a nitrogen-containing compound; depositing a dual alloy seed layer; and depositing a second metal layer on the seed layer.

[0013] In yet another aspect, the method includes depositing a bilayer barrier having a thickness less than about 20 angstroms over at least a portion of the first metal layer. The bilayer barrier includes a first layer of tantalum nitride deposited by alternately introducing one or more pulses of a tantalum-containing compound and one or more pulses of a nitrogen-containing compound; and a second layer of alpha phase tantalum. The method further includes depositing a dual alloy seed layer and a second metal layer on the seed layer.

[0014] In another aspect, the method includes depositing a tantalum nitride barrier layer having a thickness less than about 20 angstroms over at least a portion of the first metal layer by alternately introducing one or more pulses of a tantalum-containing compound and one or more pulses of a nitrogen-containing compound; depositing a dual alloy seed layer comprising copper and a metal selected from the group consisting of aluminum, magnesium, titanium, zirconium, tin, and combinations thereof; and depositing a second metal layer on the seed layer by physical vapor deposition (CVD), physical vapor deposition (PVD), electroplating, or electroless techniques.

BRIEF DESCRIPTION OF THE DRAWINGS

[0015] So that the manner in which the above recited features of the present invention are attained and can be understood in detail, a more particular description of the invention, briefly summarized above, may be had by reference to the embodiments thereof which are illustrated in the appended drawings.

[0016] It is to be noted, however, that the appended drawings illustrate only typical embodiments of this invention and are therefore not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments.

[0017]FIG. 1 illustrates processing sequences according to various embodiments of the invention described herein.

[0018] FIGS. 2A-2D are schematic cross section views of an exemplary wafer at different stages of an interconnect fabrication sequence according to embodiments described herein.

[0019]FIG. 3 illustrates a schematic, partial cross section of an exemplary processing chamber 200 for forming a thin barrier layer according to a cyclical deposition technique described herein.

[0020]FIG. 4 illustrates a schematic plan view of an exemplary integrated cluster tool adaptable to perform the interconnect fabrication sequence described herein.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

[0021] A process sequence for forming one or more interconnect structures is provided. Interconnect structures formed according to embodiments described herein have an overall lower resistivity and better electrical properties than interconnects of the prior art, and are particularly useful for making memory and logic structures for use with the fabrication of integrated circuits. The formation of the interconnect structures includes the formation of a thin barrier layer at least partially deposited on an underlying metal layer, a seed layer at least partially deposited on the barrier layer, and a bulk metal layer at least partially deposited on the seed layer. The term “interconnect” as used herein refers to any conductive path formed within an integrated circuit. The term “bulk” as used herein refers to a greater amount of material deposited in relation to other materials deposited to form the interconnect structure.

[0022]FIG. 1 illustrates the process sequence according to embodiments of the invention. A thin barrier layer is first deposited at least partially on an underlying substrate surface, such as a lower level metal interconnect or a metal gate, for example, as shown at step 480. The barrier layer is deposited according to a cyclical layer deposition technique described herein to provide excellent barrier properties and permit the continuous growth of the underlying metal layer across the barrier layer, into an upper level metal interconnect or subsequently deposited metal layer. In one aspect, the barrier layer is a refractory metal-containing layer, such as tantalum, titanium, and tungsten, for example, and may include a refractory metal nitride material, such as tantalum nitride (TaN). In another aspect, the barrier layer is a thin bi-layer of TaN and alpha-phase tantalum. In yet another aspect, the barrier layer may be a ternary material formed from a refractory metal containing compound, a silicon-containing compound and a nitrogen-containing compound. The barrier layer may also act as a wetting layer, adhesion layer, or glue layer for subsequent metallization.

[0023] A “thin layer” as used herein refers to a layer of material deposited on a substrate surface having a thickness of about 20 angstroms (Å) or less, such as about 10 Å. The thickness of the barrier layer is so small/thin that electrons of the adjacent metal interconnects can tunnel through the barrier layer. Accordingly, the barrier layer significantly enhances the metal interconnect electrical performance by lowering the overall electrical resistance and providing good device reliability.

[0024] The thin barrier layer deposited according to the cyclical deposition methods described herein shows evidence of an epitaxial growth phenomenon. In other words, the barrier layer takes on the same or substantially the same crystallographic characteristics as the underlying layer. As a result, a substantially single crystal is grown such that there is no void formation at an interface between the barrier layer and the underlying layer. Likewise, subsequent metal layers deposited over the barrier layer exhibit the same or substantially the same epitaxial growth characteristics that continue the formation of the single crystal. Accordingly, no void formation is produced at this interface. The resulting structure resembling a single crystal eliminates voids formation, thereby substantially increasing device reliability. The single crystal structure also reduces the overall resistance of the interconnect feature while still providing excellent barrier properties. Furthermore, it is believed that the single crystalline growth reduces the susceptibility of electromigration and stress migration due to the conformal and uniform crystalline orientation across the interconnect material interfaces.

[0025] “Cyclical deposition” as used herein refers to the sequential introduction of two or more compounds to deposit a thin layer on a substrate surface. The two or more compounds are sequentially introduced into a reaction zone of a processing chamber. Each compound is separated by a time delay/pause to allow each compound to adhere and/or react on the substrate surface. In one aspect, a first compound or compound A is dosed/pulsed into the reaction zone followed by a first time delay/pause. Next, a second compound or compound B is dosed/pulsed into the reaction zone followed by a second time delay. When a ternary material is desired, such as titanium silicon nitride, for example, a third compound (C), is dosed/pulsed into the reaction zone followed by a third time delay. These sequential tandems of a pulse of reactive compound followed by a time delay may be repeated indefinitely until a desired film or film thickness is formed on the substrate surface.

[0026] A “pulse/dose” as used herein is intended to refer to a quantity of a particular compound that is intermittently or non-continuously introduced into a reaction zone of a processing chamber. The quantity of a particular compound within each pulse may vary over time, depending on the duration of the pulse. A particular compound may include a single compound or a mixture/combination of two or more compounds.

[0027] A “compound” is intended to include one or more precursors, reductants, reactants, and catalysts. Each compound may be a single compound or a mixture/combination of two or more compounds.

[0028] Still referring to FIG. 1, a seed layer is at least partially deposited on the barrier layer, as shown at step 485. The seed layer may be deposited using any conventional deposition technique, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), electroplating, or electroless plating. Preferably, the seed layer is deposited conformally on the underlying barrier layer to have a thickness between about 100 Å and about 500 Å. In one aspect, the seed layer is a conventional copper seed layer. In another aspect, the seed layer is a dual alloy seed layer. Exemplary dual alloy seed layers include: 1) undoped copper deposited utilizing a target containing undoped copper, 2) a copper alloy containing aluminum in a concentration of about 2.0 atomic percent deposited utilizing a copper-aluminum target comprising aluminum in a concentration of about 2.0 atomic percent, 3) a copper alloy containing tin in a concentration of about 2.0 atomic percent deposited utilizing a copper-tin target comprising tin in a concentration of about 2.0 atomic percent, and 4) a copper alloy containing zirconium in a concentration of about 2.0 atomic percent deposited utilizing a copper-zirconium target comprising zirconium in a concentration of about 2.0 atomic percent.

[0029] The bulk metal layer is at least partially deposited on the seed layer, as shown at step 487. The metal layer may also be deposited using any conventional deposition technique, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), electroplating, or electroless plating. The metal layer preferably includes any conductive material such as aluminum, copper, tungsten, or combinations thereof, for example.

[0030] FIGS. 2A-2D are schematic representations of an exemplary interconnect structure at different stages of fabrication. FIG. 2A shows an underlying metal layer 110 having a dielectric layer 112 formed thereon. FIG. 2B shows a barrier layer 130 at least partially deposited on the underlying metal layer 110. The underlying metal layer 110 may contain any conductive metal such as aluminum, copper, tungsten, or combinations thereof, for example, and may form part of an interconnect feature such as a plug, via, contact, line, wire, and may also be part of a metal gate electrode. FIG. 2C shows a seed layer 140 at least partially deposited on the barrier layer 130, and FIG. 2D shows a bulk metal layer 142 at least partially deposited on the seed layer 140.

[0031] Referring to FIG. 2A, the dielectric layer 112 may be any dielectric material including a low k dielectric material (k≦4.0), whether presently known or yet to be discovered. For example, the dielectric layer 112 may be a silicon oxide or a carbon doped silicon oxide, for example. The dielectric layer 112 has been etched to form a feature 114 therein using conventional and well-known techniques. The feature 114 may be a plug, via, contact, line, wire, or any other interconnect component. Typically, the feature 114 has vertical sidewalls 116 and a floor 118, having an aspect ratio of about 4:1 or greater, such as about 6:1. The floor 118 exposes at least a portion of the lower level metal interconnect 110.

[0032] Referring to FIG. 2B, the barrier layer 130 is conformally deposited on the floor 118 as well as the side walls 116 of the feature 114. Preferably, the barrier layer contains tantalum nitride deposited to a thickness of about 20 Å or less, preferably about 10 Å, by providing one or more pulses of a tantalum-containing compound at a flow rate between about 100 sccm and about 1,000 sccm for a time period of about 1.0 second or less and one or more pulses of a nitrogen-containing compound at a flow rate between about 100 sccm and about 1,000 sccm for a time period of about 1.0 second or less to a reaction zone having a substrate disposed therein. Exemplary tantalum-containing compounds include: t-butylimino tris(diethylamino) tantalum (TBTDET); pentakis (ethylmethylamino); tantalum (PEMAT); pentakis (dimethylamino) tantalum (PDMAT); pentakis (diethylamino) tantalum (PDEAT); t-butylimino tris(diethyl methylamino) tantalum(TBTMET); t-butylimino tris(dimethyl amino) tantalum (TBTDMT); bis(cyclopentadienyl) tantalum trihydride ((Cp)2TaH3); bis(methylcyclopentadienyl) tantalum trihydride ((CpMe)2TaH3); derivatives thereof; and combinations thereof. Exemplary nitrogen-containing compounds include: ammonia; hydrazine; methylhydrazine; dimethylhydrazine; t-butylhydrazine; phenylhydrazine; azoisobutane; ethylazide; derivatives thereof; and combinations thereof.

[0033] It is to be understood that these compounds or any other compound not listed above may be a solid, liquid, or gas at room temperature. For example, PDMAT is a solid at room temperature and TBTDET is a liquid at room temperature. Accordingly, the non-gas phase precursors are subjected to a sublimation or vaporization step, which are both well known in the art, prior to introduction into the processing chamber. A carrier gas, such as argon, helium, nitrogen, hydrogen, or a mixture thereof, may also be used to help deliver the compound into the processing chamber, as is commonly known in the art.

[0034] Each pulse is performed sequentially, and is accompanied by a separate flow of non-reactive gas at a rate between about 200 sccm and about 1,000 sccm. The separate flow of non-reactive gas may be pulsed between each pulse of the reactive compounds or the separate flow of non-reactive gas may be introduced continuously throughout the deposition process. The separate flow of non-reactive gas, whether pulsed or continuous, serves to remove any excess reactants from the reaction zone to prevent unwanted gas phase reactions of the reactive compounds, and also serves to remove any reaction by-products from the processing chamber, similar to a purge gas. In addition to these services, the continuous separate flow of non-reactive gas helps deliver the pulses of reactive compounds to the substrate surface similar to a carrier gas. The term “non-reactive gas” as used herein refers to a single gas or a mixture of gases that does not participate in the metal layer formation. Exemplary non-reactive gases include argon, helium, nitrogen, hydrogen, and combinations thereof.

[0035] A “reaction zone” is intended to include any volume that is in fluid communication with a substrate surface being processed. The reaction zone may include any volume within a processing chamber that is between a gas source and the substrate surface. For example, the reaction zone includes any volume downstream of a dosing valve in which a substrate is disposed.

[0036] The durations for each pulse/dose are variable and may be adjusted to accommodate, for example, the volume capacity of the processing chamber as well as the capabilities of a vacuum system coupled thereto. Additionally, the dose time of a compound may vary according to the flow rate of the compound, the pressure of the compound, the temperature of the compound, the type of dosing valve, the type of control system employed, as well as the ability of the compound to adsorb onto the substrate surface. Dose times may also vary based upon the type of layer being formed and the geometry of the device being formed.

[0037] Typically, the duration for each pulse/dose or “dose time” is typically about 1.0 second or less. However, a dose time can range from microseconds to milliseconds to seconds, and even to minutes. In general, a dose time should be long enough to provide a volume of compound sufficient to adsorb/chemisorb onto the entire surface of the substrate and form a layer of the compound thereon.

[0038]FIG. 3 illustrates a schematic, partial cross section of an exemplary processing chamber 200 for forming a barrier layer according to embodiments of the present invention. Such a processing chamber 200 is available from Applied Materials, Inc. located in Santa Clara, Calif., and a brief description thereof follows. A more detailed description may be found in commonly assigned U.S. patent application Ser. No. 10/032,284, entitled “Gas Delivery Apparatus and Method For Atomic Layer Deposition”, filed on Dec. 21, 2001, which is incorporated herein by reference.

[0039] The processing chamber 200 may be integrated into an integrated processing platform, such as an Endura™ platform also available from Applied Materials, Inc. Details of the Endura™ platform are described in commonly assigned U.S. patent application Ser. No. 09/451,628, entitled “Integrated Modular Processing Platform”, filed on Nov. 30, 1999, which is incorporated by reference herein.

[0040] Referring to FIG. 3, the chamber 200 includes a chamber body 202 having a slit valve 208 formed in a sidewall 204 thereof and a substrate support 212 disposed therein. The substrate support 212 is mounted to a lift motor 214 to raise and lower the substrate support 212 and a substrate 210 disposed thereon. The substrate support 212 may also include a vacuum chuck, an electrostatic chuck, or a clamp ring for securing the substrate 212 to the substrate support 212 during processing. Further, the substrate support 212 may be heated using an embedded heating element, such as a resistive heater, or may be heated using radiant heat, such as heating lamps disposed above the substrate support 212. A purge ring 222 may be disposed on the substrate support 212 to define a purge channel 224 that provides a purge gas to prevent deposition on a peripheral portion of the substrate 210.

[0041] A gas delivery apparatus 230 is disposed at an upper portion of the chamber body 202 to provide a gas, such as a process gas and/or a purge gas, to the chamber 200. A vacuum system 278 is in communication with a pumping channel 279 to evacuate gases from the chamber 200 and to help maintain a desired pressure or a desired pressure range inside a pumping zone 266 of the chamber 200.

[0042] The gas delivery apparatus 230 includes a chamber lid 232 having an expanding channel 234 formed within a central portion thereof. The chamber lid 232 also includes a bottom surface 260 extending from the expanding channel 234 to a peripheral portion of the chamber lid 232. The bottom surface 260 is sized and shaped to substantially cover the substrate 210 disposed on the substrate support 212. The expanding channel 234 has an inner diameter that gradually increases from an upper portion 237 to a lower portion 235 adjacent the bottom surface 260 of the chamber lid 232. The velocity of a gas flowing therethrough decreases as the gas flows through the expanding channel 234 due to the expansion of the gas. The decreased gas velocity reduces the likelihood of blowing off reactants adsorbed on the surface of the substrate 210.

[0043] The gas delivery apparatus 230 also includes at least two high speed actuating valves 242 having one or more ports. At least one valve 242 is dedicated to each reactive compound. For example, a first valve is dedicated to a refractory metal-containing compound, such as tantalum and titanium, and a second valve is dedicated to a nitrogen-containing compound. When a ternary material is desired, a third valve is dedicated to an additional compound. For example, if a silicide is desired, the additional compound may be a silicon-containing compound.

[0044] The valves 242 may be any valve capable of precisely and repeatedly delivering short pulses of compounds into the chamber body 202. In some cases, the on/off cycles or pulses of the valves 242 may be as fast as about 100 msec or less. The valves 242 can be directly controlled by a system computer, such as a mainframe for example, or controlled by a chamber/application specific controller, such as a programmable logic computer (PLC) which is described in more detail in the co-pending U.S. patent application Ser. No. 09/800,881, entitled “Valve Control System For ALD Chamber”, filed on Mar. 7, 2001, which is incorporated by reference herein. For example, the valves 242 may be electronically controlled (EC) valves, which are commercially available from Fujikin of Japan as part number FR-21-6.35 UGF-APD.

[0045] To facilitate the control and automation of the overall system, the integrated processing system may include a controller 140 comprising a central processing unit (CPU) 142, memory 144, and support circuits 146. The CPU 142 may be one of any form of computer processors that are used in industrial settings for controlling various drives and pressures. The memory 144 is connected to the CPU 142, and may be one or more of a readily available memory such as random access memory (RAM), read only memory (ROM), floppy disk, hard disk, or any other form of digital storage, local or remote. Software instructions and data can be coded and stored within the memory 144 for instructing the CPU 142. The support circuits 146 are also connected to the CPU 142 for supporting the processor 142 in a conventional manner. The support circuits 146 may include cache, power supplies, clock circuits, input/output circuitry, subsystems, and the like.

[0046] In a particular embodiment, a TaN barrier layer is formed by cyclically introducing PDMAT and ammonia to the substrate surface. To initiate the cyclical deposition of the TaN layer, a carrier/inert gas such as argon is introduced into the processing chamber 200 to stabilize the pressure and temperature therein. The carrier gas is allowed to flow continuously during the deposition process such that only the argon flows between pulses of each compound. A first pulse of PDMAT is provided from the gas source 238 at a flow rate between about between about 100 sccm and about 400 sccm, with a pulse time of about 0.6 seconds or less after the chamber temperature and pressure have been stabilized at about 200° C. to about 300° C. and about 1 Torr to about 5 Torr. A pulse of ammonia is then provided from the gas source 239 at a flow rate between about 200 sccm and about 600 sccm, with a pulse time of about 0.6 seconds or less.

[0047] A pause between pulses of PDMAT and ammonia is about 1.0 second or less, preferably about 0.5 seconds or less, more preferably about 0.1 seconds or less. In various aspects, a reduction in time between pulses at least provides higher throughput. As a result, a pause after the pulse of ammonia is also about 1.0 second or less, about 0.5 seconds or less, or about 0.1 seconds or less. Argon gas flowing between about 100 sccm and about 1000 sccm, such as between about 100 sccm and about 400 sccm, is continuously provided from the gas source 240 through each valve 242. In one aspect, a pulse of PDMAT may still be in the chamber when a pulse of ammonia enters. In general, the duration of the carrier gas and/or pump evacuation should be long enough to prevent the pulses of PDMAT and ammonia from mixing together in the reaction zone.

[0048] The heater temperature is maintained between about 100° C. and about 300° C. at a chamber pressure between about 1.0 and about 5.0 Torr. Each cycle consisting of a pulse of PDMAT, pause, pulse of ammonia, and pause provides a tantalum nitride layer having a thickness between about 0.3 Å and about 1.0 Å per cycle. The alternating sequence may be repeated until the desired thickness is achieved, which is less than about 20 Å, such as about 10 Å. Accordingly, the deposition method requires between 10 and 70 cycles, more typically between 20 and 30 cycles.

[0049] In another aspect, a ternary barrier layer having a thickness less than about 20 Å, such as 10 Å, is deposited by providing one or more pulses of a refractory metal-containing compound, one or more pulses of a nitrogen-containing compound, and one or more pulses of a silicon-containing compound. Each pulse is adjusted to provide a desirable composition, silicon incorporation level, thickness, density, and step coverage of the refractory metal silicon nitride layer. A “ternary barrier layer” as used herein refers to a material having a composition comprising three major elements, such as titanium, nitrogen and silicon. An exemplary “ternary barrier layer” may also include tantalum, nitrogen and silicon.

[0050] Each pulse is performed sequentially, and is accompanied by a separate flow of carrier/inert gas at the same process conditions described above. The separate flow of carrier/inert gas may be pulsed between each pulse of reactive compound or the separate flow of carrier/inert gas may be introduced continuously throughout the deposition process.

[0051] Preferably, the ternary barrier layer contains titanium silicon nitride. In this embodiment, each cycle consists of a pulse of a titanium-containing compound, a pause, a pulse of a silicon-containing compound, a pause, a pulse of a nitrogen-containing compound, and a pause. Exemplary titanium-containing compound include tetrakis (dimethylamino) titanium (TDMAT), tetrakis (ethylmethylamino) titanium (TEMAT), tetrakis (diethylamino) titanium (TDEAT), titanium tetrachloride (TiCl4), titanium iodide (TiI4), titanium bromide (TiBr4), and other titanium halides. Exemplary silicon-containing compounds include silane, disilane, methylsilane, dimethylsilane, chlorosilane (SiH3Cl), dichlorosilane (SiH2Cl2), and trichlorosilane (SiHCl3). Exemplary nitrogen-containing compounds include: ammonia; hydrazine; methylhydrazine; dimethylhydrazine; t-butylhydrazine; phenylhydrazine; azoisobutane; ethylazide; derivatives thereof; and combinations thereof.

[0052] To initiate the cyclical deposition of a TixSiyN layer, argon is introduced into the processing chamber 200 to stabilize the pressure and temperature therein. This separate flow of argon flows continuously during the deposition process such that only the argon flows between pulses of each compound. The separate flow of argon flows between about 100 sccm and about 1000 sccm, such as between about 100 sccm and about 400 sccm. In one aspect, a pulse of TDMAT is provided at a flow rate between about between about 10 sccm and about 1000 sccm, with a pulse time of about 0.6 seconds or less after the chamber pressure and temperature have been stabilized at about 250° C. and 2 Torr. A pulse of silane is then provided at a flow rate between about 5 sccm and about 500 sccm, with a pulse time of 1 second or less. A pulse of ammonia is then provided at a flow rate between about 100 sccm and about 5,000 sccm, with a pulse time of about 0.6 seconds or less.

[0053] A pause between pulses of TDMAT and silane is about 1.0 second or less, preferably about 0.5 seconds or less, more preferably about 0.1 seconds or less. A pause between pulses of silane and ammonia is about 1.0 second or less, about 0.5 seconds or less, or about 0.1 seconds or less. A pause after the pulse of ammonia is also about 1.0 second or less, about 0.5 seconds or less, or about 0.1 seconds or less. In one aspect, a pulse of TDMAT may still be in the chamber when a pulse of silane enters, and a pulse of silane may still be in the chamber when a pulse of ammonia enters.

[0054] The heater temperature is maintained between about 100° C. and about 300° C. at a chamber pressure between about 1.0 and about 5.0 Torr. Each cycle consisting of a pulse of TDMAT, pause, pulse of silane, pause, pulse of ammonia, and pause provides a titanium silicon nitride layer having a thickness between about 0.3 Å and about 1.0 Å per cycle. The alternating sequence may be repeated until the desired thickness is achieved, which is less than about 20 Å, such as about 10 Å. Accordingly, the deposition method requires between 10 and 70 cycles.

[0055] In yet another aspect, an alpha phase tantalum (α-Ta) layer having a thickness of about 20 Å or less, such as about 10 Å, may be deposited over at least a portion of the previously deposited binary (TaN) or ternary (TiSiN) layers. The α-Ta layer may be deposited using conventional techniques, such as PVD and CVD for example, to form a bilayer stack. For example, the bilayer stack may include a TaN portion deposited by cyclical layer deposition described above and an α-Ta portion deposited by high density plasma physical vapor deposition (HDP-PVD).

[0056] To further illustrate, the α-Ta portion of the stack may be deposited using an ionized metal plasma (IMP) chamber, such as a Vectra™ chamber, available from Applied Materials, Inc. of Santa Clara, Calif. The IMP chamber includes a target, coil, and biased substrate support member, and may also be integrated into an Endura™ platform, also available from Applied Materials, Inc. A power between about 0.5 kW and about 5 kW is applied to the target, and a power between about 0.5 kW and 3 kW is applied to the coil. A power between about 200 W and about 500 W at a frequency of about 13.56 MHz is also applied to the substrate support member to bias the substrate. Argon is flowed into the chamber at a rate of about 35 sccm to about 85 sccm, and nitrogen may be added to the chamber at a rate of about 5 sccm to about 100 sccm. The pressure of the chamber is typically between about 5 mTorr to about 100 mTorr, while the temperature of the chamber is between about 20° C. and about 300° C.

[0057] Prior to depositing the barrier layer 130, the patterned or etched substrate dielectric layer 112 may be cleaned to remove native oxides or other contaminants from the surface thereof. For example, reactive gases are excited into a plasma within a remote plasma source chamber such as a Reactive Pre-clean chamber available from Applied Materials, Inc., located in Santa Clara, Calif. Pre-cleaning may also be done within a metal CVD or PVD chamber by connecting the remote plasma source thereto. Alternatively, metal deposition chambers having gas delivery systems could be modified to deliver the pre-cleaning gas plasma through existing gas inlets such as a gas distribution showerhead positioned above the substrate.

[0058] In one aspect, the reactive pre-clean process forms radicals from a plasma of one or more reactive gases such as argon, helium, hydrogen, nitrogen, fluorine-containing compounds, and combinations thereof. For example, a reactive gas may include a mixture of tetrafluorocarbon (CF4) and oxygen (O2), or a mixture of helium (He) and nitrogen trifluoride (NF3). More preferably, the reactive gas is a mixture of helium and nitrogen trifluoride.

[0059] Following the argon plasma, the chamber pressure is increased to about 140 mTorr, and a processing gas consisting essentially of hydrogen and helium is introduced into the processing region. Preferably, the processing gas comprises about 5% hydrogen and about 95% helium. The hydrogen plasma is generated by applying between about 50 watts and about 500 watts power. The hydrogen plasma is maintained for about 10 seconds to about 300 seconds.

[0060] Referring again to FIG. 2C, the seed layer 140 may be deposited using high density plasma physical vapor deposition (HDP-PVD) to enable good conformal coverage. One example of a HDP-PVD chamber is the Self-Ionized Plasma SIP™ chamber, available from Applied Materials, Inc. of Santa Clara, Calif., which may be integrated into an Endura™ platform, available from Applied Materials, Inc. Of course, other techniques, such as physical vapor deposition, chemical vapor deposition, electroless plating, and electroplating, may be used.

[0061] A typical SIP™ chamber includes a target, coil, and biased substrate support member. To form the copper seed layer, a power between about 0.5 kW and about 5 kW is applied to the target, and a power between about 0.5 kW and 3 kW is applied to the coil. A power between about 200 and about 500 W at a frequency of about 13.56 MHz is applied to bias the substrate. Argon is flowed into the chamber at a rate of about 35 sccm to about 85 sccm, and nitrogen may be added to the chamber at a rate of about 5 sccm to about 100 sccm. The pressure of the chamber is typically between about 5 mTorr to about 100 mTorr.

[0062] Alternatively, a seed layer 140 containing a copper alloy may be deposited by any suitable technique such as physical vapor deposition, chemical vapor deposition, electroless deposition, or a combination of techniques. Preferably, the copper alloy seed layer 140 contains aluminum and is deposited using a PVD technique described above. During deposition, the process chamber is maintained at a pressure between about 0.1 mtorr and about 10 mtorr. The target includes copper and between about 2 and about 10 atomic weight percent of aluminum. The target may be DC-biased at a power between about 5 kW and about 100 kW. The pedestal may be RF-biased at a power between about 10 W and about 1000 W. The copper alloy seed layer 140 is deposited to a thickness of at least about 5 Å, and between about 5 Å and about 500 Å.

[0063] Referring to FIG. 2D, the metal layer 142 is preferably copper and deposited using 140 using CVD, PVD, electroplating, or electroless techniques. Preferably, the copper layer 142 is formed within an electroplating cell, such as the Electra™ Cu ECP system, available from Applied Materials, Inc., of Santa Clara, Calif. The Electra™ Cu ECP system may also be integrated into an Endura™ platform also available from Applied Materials, Inc.

[0064] A copper electrolyte solution and copper electroplating technique is described in commonly assigned U.S. Pat. No. 6,113,771, entitled “Electro-deposition Chemistry”, which is incorporated by reference herein. Typically, the electroplating bath has a copper concentration greater than about 0.7M, a copper sulfate concentration of about 0.85, and a pH of about 1.75. The electroplating bath may also contain various additives as is well known in the art. The temperature of the bath is between about 15° C. and about 25° C. The bias is between about −15 volts to about 15 volts. In one aspect, the positive bias ranges from about 0.1 volts to about 10 volts and the negatives bias ranges from about −0.1 to about −10 volts.

[0065] Optionally, an anneal treatment may be performed following the metal layer 142 deposition whereby the wafer is subjected to a temperature between about 100° C. and about 400° C. for about 10 minutes to about 1 hour, preferably about 30 minutes. A carrier/purge gas such as helium, hydrogen, nitrogen, or a mixture thereof is introduced at a rate of about 100 sccm to about 10,000 sccm. The chamber pressure is maintained between about 2 Torr and about 10 Torr. The RF power is about 200 W to about 1,000 W at a frequency of about 13.56 MHz, and the preferable substrate spacing is between about 300 mils and about 800 mils.

[0066] Following deposition, the top portion of the resulting structure may be planarized. A chemical mechanical polishing (CMP) apparatus may be used, such as the Mirra™ System available from Applied Materials, Santa Clara, Calif., for example. Optionally, the intermediate surfaces of the structure may be planarized between the deposition of the subsequent layers described above.

[0067]FIG. 4 is a schematic top-view diagram of an exemplary multi-chamber processing system 600 that may be adapted to perform processes as disclosed herein. Such a processing system 600 may be an Endura™ system, commercially available from Applied Materials, Inc., of Santa Clara, Calif. A similar multi-chamber processing system is disclosed in U.S. Pat. No. 5,186,718, entitled “Stage Vacuum Wafer Processing System and Method,” issued on Feb. 16, 1993, which is incorporated by reference herein.

[0068] The system 600 generally includes load lock chambers 602, 604 for the transfer of substrates into and out from the system 600. Typically, since the system 600 is under vacuum, the load lock chambers 602, 604 may “pump down” the substrates introduced into the system 600. A first robot 610 may transfer the substrates between the load lock chambers 602, 604, and a first set of one or more substrate processing chambers 612, 614, 616, 618 (four are shown). Each processing chamber 612, 614, 616, 618, can be outfitted to perform a number of substrate processing operations such as cyclical layer deposition, chemical vapor deposition (CVD), physical vapor deposition (PVD), etch, pre-clean, degas, orientation and other substrate processes. The first robot 610 also transfers substrates to/from one or more transfer chambers 622, 624.

[0069] The transfer chambers 622, 624, are used to maintain ultrahigh vacuum conditions while allowing substrates to be transferred within the system 600. A second robot 630 may transfer the substrates between the transfer chambers 622, 624 and a second set of one or more processing chambers 632, 634, 636, 638. Similar to processing chambers 612, 614, 616, 618, the processing chambers 632, 634, 636, 638 can be outfitted to perform a variety of substrate processing operations, such as cyclical layer deposition, chemical vapor deposition (CVD), physical vapor deposition (PVD), etch, pre-clean, degas, and orientation, for example. Any of the substrate processing chambers 612, 614, 616, 618, 632, 634, 636, 638 may be removed from the system 600 if not necessary for a particular process to be performed by the system 600.

[0070] In one arrangement, each processing chamber 632 and 638 may be a physical vapor deposition chamber, a chemical vapor deposition chamber, or a cyclical deposition chamber adapted to deposit a seed layer; each processing chamber 634 and 636 may be a cyclical deposition chamber, a chemical vapor deposition chamber, or a physical vapor deposition chamber adapted to deposit a barrier layer; each processing chamber 612 and 614 may be a physical vapor deposition chamber, a chemical vapor deposition chamber, or a cyclical deposition chamber adapted to deposit a dielectric layer; and each processing chamber 616 and 618 may be an etch chamber outfitted to etch apertures or openings for interconnect features. This one particular arrangement of the system 600 is provided to illustrate the invention and should not be used to limit the scope of the invention.

[0071] The following example is intended to provide a non-limiting illustration of one embodiment of the present invention.

EXAMPLE

[0072] A TaN layer was deposited over a lower level copper layer using cyclical deposition to a thickness of about 20 Å. A copper alloy seed layer was deposited over the TaN layer by physical vapor deposition to a thickness of about 100 Å. The copper alloy seed layer contained aluminum in a concentration of about 2.0 atomic percent, and was deposited by PVD using a copper-aluminum target consisting of aluminum in a concentration of about 2.0 atomic percent. A bulk copper layer was then deposited using ECP to fill the feature. The substrate was then annealed at a temperature of about 380° C. for a time period of about 15 minutes in a nitrogen (N2) and hydrogen (H2) ambient.

[0073] The overall feature resistance was significantly reduced and the upper level copper layer surprisingly exhibited a grain growth similar to that of the lower level copper layer. The barrier performance of the TaN layer exhibited longer TTF compared with 50 Å PVD Ta. Further, the TaN layer showed low contact resistance and tight spread distribution. The TaN layer also exhibited excellent topography, having a smooth and pinhole free surface. Finally, the copper alloy seed layer showed excellent adhesion/wetting to the TaN layer.

[0074] While the foregoing is directed to embodiments of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.

Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US6905541 *May 27, 2003Jun 14, 2005Applied Materials, Inc.Method and apparatus of generating PDMAT precursor
US7186385Jul 17, 2002Mar 6, 2007Applied Materials, Inc.For semiconductor processing system
US7265048Mar 1, 2005Sep 4, 2007Applied Materials, Inc.Reduction of copper dewetting by transition metal deposition
US7303991 *Jun 7, 2004Dec 4, 2007Micron Technology, Inc.Atomic layer deposition methods
US7368382Apr 28, 2006May 6, 2008Micron Technology, Inc.Atomic layer deposition methods
US7378354Apr 28, 2006May 27, 2008Micron Technology, Inc.Atomic layer deposition methods
US7402210 *Mar 1, 2007Jul 22, 2008Applied Materials, Inc.Apparatus and method for hybrid chemical processing
US7429402 *Dec 10, 2004Sep 30, 2008Applied Materials, Inc.Depositing a barrier layer on the substrate, such as a titanium or tantalum containing barrier layer and depositing a ruthenium layer on the barrier layer; depositing a tungsten nucleation layer on the ruthenium layer and depositing a tungsten bulk layer on the tungsten nucleation layer
US7524374May 27, 2004Apr 28, 2009Applied Materials, Inc.Method and apparatus for generating a precursor for a semiconductor processing system
US7591907 *Jul 11, 2008Sep 22, 2009Applied Materials, Inc.Apparatus for hybrid chemical processing
US7699023 *Oct 26, 2007Apr 20, 2010Applied Materials, Inc.Gas delivery apparatus for atomic layer deposition
US8062422Feb 13, 2009Nov 22, 2011Applied Materials, Inc.Method and apparatus for generating a precursor for a semiconductor processing system
US8070879 *Aug 20, 2009Dec 6, 2011Applied Materials, Inc.Apparatus and method for hybrid chemical processing
US8107274 *Jul 30, 2009Jan 31, 2012Chrong-Jung LinVariable and reversible resistive element, non-volatile memory device and methods for operating and manufacturing the non-volatile memory device
US8486845 *Mar 21, 2005Jul 16, 2013Tokyo Electron LimitedPlasma enhanced atomic layer deposition system and method
US8491967 *Sep 8, 2008Jul 23, 2013Applied Materials, Inc.In-situ chamber treatment and deposition process
US20120111271 *Oct 9, 2008May 10, 2012Begarney Michael JChemical vapor deposition reactor
US20120156872 *Nov 30, 2011Jun 21, 2012Applied Materials, Inc.Methods for depositing materials in high aspect ratio features
EP1507289A2 *Aug 13, 2004Feb 16, 2005Texas Instruments IncorporatedDiffusion barrier for copper lines in integrated circuits
WO2004106584A1 *May 27, 2004Dec 9, 2004Applied Materials IncMethod and apparatus for generating a precursor for a semiconductor processing system
Classifications
U.S. Classification427/402, 427/304, 427/404, 257/E21.171, 427/419.7, 427/58
International ClassificationC23C16/34, C23C16/44, C23C16/455, H01L21/285, H01L21/768
Cooperative ClassificationC23C16/4411, C23C16/45504, H01L21/28562, C23C16/45563, H01L21/76871, C23C16/45544, C23C16/45512, C23C16/45525, C23C16/34, C23C16/45508, H01L21/76843, C23C16/4412, C23C16/45582, H01L21/76846
European ClassificationC23C16/34, C23C16/44H, C23C16/455F2D, C23C16/44C, C23C16/455K, H01L21/768C3B4, H01L21/768C3S, H01L21/285B4H2, H01L21/768C3B, C23C16/455B, C23C16/455M, C23C16/455A2, C23C16/455A6, C23C16/455F2
Legal Events
DateCodeEventDescription
Jul 10, 2002ASAssignment
Owner name: APPLIED MATERIALS, INC., CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:CHUNG, HUA;CHEN, LING;REEL/FRAME:013099/0317
Effective date: 20020710