US20030085740A1 - Rail-to-rail cmos comparator - Google Patents
Rail-to-rail cmos comparator Download PDFInfo
- Publication number
- US20030085740A1 US20030085740A1 US10/047,285 US4728502A US2003085740A1 US 20030085740 A1 US20030085740 A1 US 20030085740A1 US 4728502 A US4728502 A US 4728502A US 2003085740 A1 US2003085740 A1 US 2003085740A1
- Authority
- US
- United States
- Prior art keywords
- input
- circuit
- rail
- signal
- bias
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
- H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
- H03K5/2472—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors
- H03K5/2481—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors with at least one differential stage
Definitions
- the present invention generally relates to integrated circuits and, more particularly, to a CMOS comparator having a rail-to-rail common mode input voltage range.
- Comparators are a common type of integrated circuit used in many electrical circuit applications. Many such applications often require that a comparator operate over a wide common mode input voltage range. As improvements in technology have led to lower device supply voltage:threshold voltage ratios, integrated circuit developers have found it increasingly more difficult to design and manufacture comparators that operate over a wide common mode input voltage range. Typically, as the common mode voltage at the input of the comparator approaches either the positive supply rail or the negative supply rail of the device, the comparator ceases to function properly, resulting in an output signal which is not indicative of the signals at the input of the comparator. For instance, in comparators which have a limited common mode range, the comparator output signal may collapse and/or duty cycle distortion of the output signal may result.
- comparators which have a rail-to-rail common mode range are available, many such comparators either perform poorly and/or the manufacturing process for producing such comparators is costly due to the complexity.
- a known CMOS comparator implements an n-channel differential gain stage which operates at the high end of the common mode voltage range and a p-channel differential gain stage which operates at the low end of the common mode input voltage range. The outputs of the two differential gain stages are combined in an output stage which provides the appropriate gain and level shifting to generate the comparator output signals.
- the operation of the design suffers from uncertain performance in the range in which the comparator is transitioning between the n-channel and p-channel differential gain stages, slow performance due to the delays introduced by the multiple cascaded stages, and high power consumption due to a large component count. Further, the response time of the comparator may vary depending on the input voltage due to the differences in response time of the n-channel differential gain stage relative to the p-channel differential gain stage.
- the present invention may address one or more of the problems set forth above.
- FIG. 1 is an electrical schematic symbol representative of a comparator
- FIG. 2 illustrates an exemplary configuration of a comparator which is configured to operate over a wide common mode input range in accordance with the invention
- FIG. 3 illustrates a block diagram representative of an exemplary embodiment of the bias stage of the comparator of FIG. 2;
- FIG. 4 illustrates a block diagram representative of an exemplary embodiment of the gain stage of the comparator of FIG. 2;
- FIG. 5 illustrates an electrical schematic of an exemplary embodiment of the bias stage of FIG. 3 and the gain stage of FIG. 4.
- the comparator 10 includes a positive input A, a negative input AN, an output Z, and a complementary output ZN.
- the positive voltage supply is labeled VDD (i.e., the positive rail 12 ) and the negative supply is connected to ground GND (i.e., the negative rail 14 ).
- the output signals provided at Z and ZN are responsive to the difference in the voltage between the inputs A and AN.
- the comparator 10 is illustrated as being disposed on a substrate 11 , such as a semiconductor substrate for an integrated circuit, a printed circuit board, etc.
- comparators 10 may be used in many different types of electrical circuits, such as logic circuits, control circuits, circuits for use with a memory device (e.g., an SRAM, DRAM, etc.), and so forth.
- a memory device e.g., an SRAM, DRAM, etc.
- FIG. 2 illustrates an exemplary configuration of the comparator 10 which is configured to operate over a wide common mode input voltage range.
- the comparator 10 can generate output signals Z and ZN which are responsive to the difference in the voltage at the inputs A and AN over a full common mode range between the positive rail 12 and the negative rail 14 .
- the bias stage 16 which provides a bias signal 18 to a differential gain stage 20 based on the common mode voltage at the inputs A and AN.
- the bias signal 16 is a compensation signal that maintains the gain stage 20 within an optimal operating range even as the common mode voltage at the inputs A and AN approaches the positive rail 12 or the negative rail 14 . That is, by providing the bias signal 18 to the gain stage 20 , the gain stage 20 can be maintained within an active region in which the outputs Z and ZN remain responsive to the differential signal at the inputs A and AN regardless of the common mode voltage.
- the bias signal maintains the gain stage 20 within an operating range in which it can generate an output signal having a rise time that is substantially the same as the fall time over a full common mode input voltage range.
- the comparator 10 is manufactured using 0.18 micron CMOS processing technology and operates at a frequency of 1 GHz, the comparator 10 can generate an output signal having rise times and fall times on the order of 200 picoseconds.
- the duty cycle distortion of the output signal may range from less than 1% when the common mode input voltage is about midway between the positive and negative rails to about a maximum of 5%. In other embodiments using different processing technologies and operating frequencies, the duty cycle distortion may vary over a different range, a smaller range, or even a greater range.
- the bias stage 16 includes a p-channel common mode stage 22 referenced to the positive rail 12 and an n-channel common mode stage 24 referenced to the negative rail 14 , each of which are configured to respond to the common mode voltage on the inputs A and AN.
- the p-channel common mode stage 22 and the n-channel common mode stage 24 each provides an output signal to a gain stage/bias source 26 which, in turn, generates an appropriate bias signal 18 responsive to the value of the common mode voltage.
- the gain stage/bias source 26 is configured to provide a suitable gain for the bias signal 18 and/or to shift the level of the bias signal 18 as appropriate for receipt by the gain stage 20 of the comparator 10 .
- the n-channel common mode stage 24 is operative to affect the bias signal 18 generated by the gain stage/bias source 26 .
- the p-channel common mode stage 22 is operative to affect the bias signal 18 .
- both the p-channel common mode stage 22 and the n-channel common mode stage 24 are operative.
- the n-channel stage 24 is operative when the common mode voltage ranges from 0.5V up to the positive rail 12
- the p-channel stage 22 is operative when the common mode voltage ranges between the negative rail 14 and up to 0.5V below the positive rail 12 .
- the gain stage 20 includes a p-channel differential mode stage 28 , an n-channel differential mode stage 30 , and an output signal gain stage 32 .
- the p-channel differential stage 28 provides an output signal 34 to the output signal gain stage 32 when the common mode voltage at the inputs A and AN approaches the negative rail 14 .
- the n-channel differential stage 30 provides an output signal 36 to the output signal gain stage 32 when the common mode voltage at the inputs A and AN approaches the positive rail 12 .
- both the p-channel differential stage 28 and the n-channel differential stage 30 provide output signals to the output gain stage 32 .
- the output signal gain stage 32 responds to the signals 34 and 36 from the p-channel differential mode stage 28 and the n-channel differential mode stage 30 , respectively, to provide the output signals Z and ZN. Additionally, operation of the output signal gain stage 32 is influenced by the bias signal 18 , which contributes to maintaining the output signals Z and ZN responsive to the differential between the inputs A and AN even when the common mode voltage at the inputs A and AN approaches the positive rail 12 or the negative rail 14 . For instance, the bias signal 18 may maintain the gain stage 32 within an operating range in which the gain stage 32 can generate signals at the outputs Z and ZN that have substantially equal rise and fall times regardless of the common mode voltage. Accordingly, collapse of the output signals Z and ZN and/or distortion of the duty cycle of the output signals Z and ZN can be curtailed as the common mode input voltage approaches either rail.
- the common mode p-channel stage 22 includes a matched pair of p-channel transistors 38 and 40 referenced to the positive rail 12 through a p-channel transistor 42 .
- the p-channel transistors 28 , 40 , and 42 are configured as a current source in which the magnitude of the current at node 44 is dependent on the common mode voltage at the inputs A and AN and the bias signal 18 applied to the gate of the p-channel transistor 42 . As the common mode voltage at inputs A and AN approaches the negative rail 14 , more current is provided at node 44 .
- the common mode n-channel stage 24 of the bias stage 16 includes a matched pair of n-channel transistors 46 and 48 referenced to the negative rail 14 through an n-channel transistor 50 .
- the n-channel transistor 46 , 48 , and 50 are configured as a current source in which the magnitude of the current at node 52 is dependent on the common mode voltage at the inputs A and AN and the bias signal 18 applied to the gate of the n-channel transistor 50 . As the common mode voltage at inputs A and AN approaches the positive rail 12 , more current is provided at node 52 .
- the bias signal 18 is fed back to the gates of the transistors 42 and 50 to stabilize the operation of the bias stage 16 .
- the current signals at nodes 44 and 52 are provided to the bias source 26 , which includes a pair of n-channel transistors 54 and 56 and a pair of p-channel transistors 58 and 60 arranged as an inverter having its output (i.e., node 62 ) connected back to its input (i.e., node 64 ).
- the connection of the output 62 to the input 64 causes the inverter to operate at its highest gain. Further, this operating state typically generates a bias signal 18 which is about midway between the positive rail 12 and the negative rail 14 .
- Node 44 is connected to the node between the n-channel transistors 54 and 56 .
- the transistors 54 and 56 produce an increasing bias signal 18 .
- This increase in the bias signal 18 causes a corresponding increase in the current through differential mode p-channel stage 28 of the gain stage 20 , which, in turn, allows the output signal gain stage 32 of the comparator 10 to operate within an operating region in which it can produce output signals at Z and ZN that are responsive to the differential signals at the inputs A and AN, even though the common mode input voltage at A and AN is approaching a supply rail. That is, the output signal gain stage 32 operates in a range in which duty cycle distortion of the output signals at Z and ZN is minimized regardless of the common mode input voltage.
- the node 52 is connected to the junction of the p-channel transistors 58 and 60 .
- the transistors 58 and 60 produce an increasing bias signal 18 .
- This increase in the bias signal 18 causes a corresponding increase in the current through differential mode n-channel stage 30 of the gain stage 20 , which, in turn, allows the output signal gain stage 32 of the comparator 10 to remain within an operating region in which it can produce output signals at Z and ZN that are responsive to the differential signals at the inputs A and AN, even though the common mode input voltage at A and AN is approaching a supply rail, which, again, results in output signals having minimal duty cycle distortion.
- the gain stage 20 of the comparator 10 includes the differential mode p-channel stage 28 , the differential mode n-channel stage 30 , and the output signal gain stage 32 .
- the differential stage 28 includes a matched differential pair of p-channel transistors 66 and 68 referenced to the positive rail 12 through a p-channel transistor 70 .
- the differential stage 30 includes a matched differential pair of n-channel transistors 72 and 74 referenced to the negative rail 14 through an n-channel transistor 76 .
- the p-channel transistors 66 , 68 , and 70 are configured as a current source in which the magnitude of the current at node 78 is dependent on the differential signal at inputs A and AN and the magnitude of the bias signal 18 applied to the gate of the transistor 70 .
- the current at node 78 divides between the transistors 66 and 68 in a ratio that is dependent on the difference in voltage between the inputs A and AN.
- the n-channel transistors 72 , 74 , and 76 are configured as a current source in which the magnitude of the current at node 80 is dependent on the differential signal at inputs A and AN and the magnitude of the bias signal 18 applied to the gate of the transistor 76 .
- the current at node 80 divides between the transistors 72 and 74 in a ratio that is dependent on the difference in voltage between the inputs A and AN.
- the p-channel stage 68 In operation, as the common mode voltage at the inputs A and AN approaches the negative rail 14 , the p-channel stage 68 is operational. Further, as described above, the bias stage 16 provides an increased bias signal 18 to the gate of the transistor 70 , thus causing an increase in the current at the node 78 . This increase in current corrects for the non-linear operation that may otherwise occur as the common mode voltage approaches the negative rail 14 . As a result, the gain stage 20 remains within an active operating region and the output signals Z and ZN can remain responsive to the differential signal at the inputs A and AN.
- the output of the p-channel differential stage 28 is a differential current which is provided to the output signal stage 32 at the nodes 82 and 84 .
- the n-channel stage 30 is operational.
- the bias stage 16 provides an increased bias signal to the gate of the transistor 76 , thus causing an increase in the current at the node 80 .
- the increase in current maintains the gain stage 20 within an active operating region such that the output signals Z and ZN can remain responsive to the differential signal at the inputs A and AN as the common mode voltage approaches the positive rail 12 .
- the output of the n-channel differential gain stage 30 is a differential current which is provided to the output signal stage 32 at the nodes 86 and 88 .
- the output signal stage 32 of the gain stage 20 has a dual fully symmetrical folded cascode configuration which provides the appropriate level shifting and gain to generate the outputs Z and ZN based on the differential current signals received from the differential stages 28 and 30 .
- the differential current signal from the p-channel differential gain stage 28 is provided at nodes 82 and 84 to a negative-rail-referenced folded cascode gain stage which includes n-channel transistors 90 , 92 , 94 , and 96 .
- the differential current signal from the n-channel differential gain stage 30 is provided at nodes 86 and 88 to a positive-rail-referenced folded cascode gain stage which includes the p-channel transistors 98 , 100 , 102 , and 104 .
- the final output Z of the comparator 10 is provided at the junction between the transistors 94 and 104 .
- the final output ZN of the comparator 10 is provided at the junction between the transistors 90 and 100 . Buffering not shown in FIG. 5 may be provided for the outputs Z and ZN depending on the operating parameters of particular application in which the comparator 10 is intended for use. For example, buffering may vary depending on the amplitude of the input voltage, the gain, and the intended load on the outputs Z and ZN.
- the size of the various transistors of the comparator 10 may vary depending on the processing technology used and the voltage supply levels. In one embodiment, 0.3 um CMOS device sizes may be used with a 3V voltage supply (i.e., VDD). Further, the transistors 38 / 40 , 46 / 48 , 66 / 68 , and 72 / 74 each are matched pairs. Still further, in one embodiment, transistors in the bias stage 16 are sized relative to transistors in the gain stage 20 such that the operating point of the bias stage 16 maintains the output signal stage 32 of the gain stage 20 at an operating point at which the duty cycle distortion at the outputs Z and ZN is minimized for all common mode input voltage levels.
- the bias signal 18 matches the output signals Z and ZN. This matching is achieved by sizing the transistor 50 at half the size of the transistor 76 , and sizing the transistor 42 at half the size of the transistor 70 .
- the comparator 10 is exemplary only, and it should be understood that the particular configurations of the bias stage 16 and the gain stage 20 may vary without departing from the scope of the invention. Further, it is contemplated that the comparator may be manufactured as an integrated circuit on a semiconductor substrate or may be implemented as discrete components supported by a substrate, such as a printed circuit board. Moreover, the comparator may be implemented using CMOS devices or devices manufactured using other technology.
Abstract
Description
- 1. Field of the Invention
- The present invention generally relates to integrated circuits and, more particularly, to a CMOS comparator having a rail-to-rail common mode input voltage range.
- 2. Description of the Related Art
- This section is intended to introduce the reader to various aspects of art that may be related to various aspects of the present invention, which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present invention. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.
- Comparators are a common type of integrated circuit used in many electrical circuit applications. Many such applications often require that a comparator operate over a wide common mode input voltage range. As improvements in technology have led to lower device supply voltage:threshold voltage ratios, integrated circuit developers have found it increasingly more difficult to design and manufacture comparators that operate over a wide common mode input voltage range. Typically, as the common mode voltage at the input of the comparator approaches either the positive supply rail or the negative supply rail of the device, the comparator ceases to function properly, resulting in an output signal which is not indicative of the signals at the input of the comparator. For instance, in comparators which have a limited common mode range, the comparator output signal may collapse and/or duty cycle distortion of the output signal may result.
- Although comparators which have a rail-to-rail common mode range are available, many such comparators either perform poorly and/or the manufacturing process for producing such comparators is costly due to the complexity. For example, to achieve rail-to-rail operation, a known CMOS comparator implements an n-channel differential gain stage which operates at the high end of the common mode voltage range and a p-channel differential gain stage which operates at the low end of the common mode input voltage range. The outputs of the two differential gain stages are combined in an output stage which provides the appropriate gain and level shifting to generate the comparator output signals. Although such a design may achieve operation over a full range between the positive supply rail and the negative supply rail, the operation of the design suffers from uncertain performance in the range in which the comparator is transitioning between the n-channel and p-channel differential gain stages, slow performance due to the delays introduced by the multiple cascaded stages, and high power consumption due to a large component count. Further, the response time of the comparator may vary depending on the input voltage due to the differences in response time of the n-channel differential gain stage relative to the p-channel differential gain stage.
- Accordingly, it would be desirable to provide a comparator that is operational over a full rail-to-rail common mode input voltage ranges, satisfies high speed operational requirements, minimizes power consumption, and places minimal demands on the manufacturing process.
- The present invention may address one or more of the problems set forth above.
- The foregoing and other advantages of the invention may become apparent upon reading the following detailed description and upon reference to the drawings in which:
- FIG. 1 is an electrical schematic symbol representative of a comparator;
- FIG. 2 illustrates an exemplary configuration of a comparator which is configured to operate over a wide common mode input range in accordance with the invention;
- FIG. 3 illustrates a block diagram representative of an exemplary embodiment of the bias stage of the comparator of FIG. 2;
- FIG. 4 illustrates a block diagram representative of an exemplary embodiment of the gain stage of the comparator of FIG. 2; and
- FIG. 5 illustrates an electrical schematic of an exemplary embodiment of the bias stage of FIG. 3 and the gain stage of FIG. 4.
- One or more specific embodiments of the present invention will be described below. In an effort to provide a concise description of these embodiments, not all features of an actual implementation are described in the specification. It should be appreciated that in the development of any such actual implementation, as in any engineering or design project, numerous implementation-specific decisions are made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which may vary from one implementation to another. Moreover, it should be appreciated that such a development effort might be complex and time consuming, but would nevertheless be a routine undertaking of design, fabrication, and manufacture for those of ordinary skill having the benefit of this disclosure.
- Turning now to the figures and initially referring to FIG. 1, an electrical schematic symbol representative of a comparator is shown. The
comparator 10 includes a positive input A, a negative input AN, an output Z, and a complementary output ZN. The positive voltage supply is labeled VDD (i.e., the positive rail 12) and the negative supply is connected to ground GND (i.e., the negative rail 14). The output signals provided at Z and ZN are responsive to the difference in the voltage between the inputs A and AN. In FIG. 1, thecomparator 10 is illustrated as being disposed on asubstrate 11, such as a semiconductor substrate for an integrated circuit, a printed circuit board, etc. It should be understood throughout the following description that one or more of thecomparators 10 may be used in many different types of electrical circuits, such as logic circuits, control circuits, circuits for use with a memory device (e.g., an SRAM, DRAM, etc.), and so forth. - FIG. 2 illustrates an exemplary configuration of the
comparator 10 which is configured to operate over a wide common mode input voltage range. For instance, in one embodiment, thecomparator 10 can generate output signals Z and ZN which are responsive to the difference in the voltage at the inputs A and AN over a full common mode range between thepositive rail 12 and thenegative rail 14. - In the embodiment of the
comparator 10 illustrated in FIG. 2, wide range common mode operation is achieved through the use of abias stage 16 which provides abias signal 18 to adifferential gain stage 20 based on the common mode voltage at the inputs A and AN. In the exemplary embodiment, and as will be described in detail below, thebias signal 16 is a compensation signal that maintains thegain stage 20 within an optimal operating range even as the common mode voltage at the inputs A and AN approaches thepositive rail 12 or thenegative rail 14. That is, by providing thebias signal 18 to thegain stage 20, thegain stage 20 can be maintained within an active region in which the outputs Z and ZN remain responsive to the differential signal at the inputs A and AN regardless of the common mode voltage. - In an exemplary embodiment described below, the bias signal maintains the
gain stage 20 within an operating range in which it can generate an output signal having a rise time that is substantially the same as the fall time over a full common mode input voltage range. Thus, distortion of the duty cycle of the output signal which might otherwise result due to the inability of thecomparator 10 to drive a signal high at the same rate at which the signal is driven low over a full common mode range can be minimized. In one exemplary embodiment in which thecomparator 10 is manufactured using 0.18 micron CMOS processing technology and operates at a frequency of 1 GHz, thecomparator 10 can generate an output signal having rise times and fall times on the order of 200 picoseconds. In such an embodiment, the duty cycle distortion of the output signal may range from less than 1% when the common mode input voltage is about midway between the positive and negative rails to about a maximum of 5%. In other embodiments using different processing technologies and operating frequencies, the duty cycle distortion may vary over a different range, a smaller range, or even a greater range. - Turning now to FIG. 3, a block diagram representative of the
bias stage 16 of thecomparator 10 is illustrated. Thebias stage 16 includes a p-channelcommon mode stage 22 referenced to thepositive rail 12 and an n-channelcommon mode stage 24 referenced to thenegative rail 14, each of which are configured to respond to the common mode voltage on the inputs A and AN. As the common mode voltage on the inputs A and AN changes (i.e., approaches either thepositive rail 12 or the negative rail 14), the p-channelcommon mode stage 22 and the n-channelcommon mode stage 24 each provides an output signal to a gain stage/bias source 26 which, in turn, generates anappropriate bias signal 18 responsive to the value of the common mode voltage. The gain stage/bias source 26 is configured to provide a suitable gain for thebias signal 18 and/or to shift the level of thebias signal 18 as appropriate for receipt by thegain stage 20 of thecomparator 10. - In the exemplary embodiment of the
bias stage 16 illustrated in FIG. 3, as the common mode voltage on the inputs A and AN approaches thepositive rail 12, the n-channelcommon mode stage 24 is operative to affect thebias signal 18 generated by the gain stage/bias source 26. Similarly, as the common mode voltage approaches thenegative rail 14, the p-channelcommon mode stage 22 is operative to affect thebias signal 18. When the common mode voltage at inputs A and AN is in a range between thepositive rail 12 and thenegative rail 14, both the p-channelcommon mode stage 22 and the n-channelcommon mode stage 24 are operative. For instance, in one embodiment, the n-channel stage 24 is operative when the common mode voltage ranges from 0.5V up to thepositive rail 12, and the p-channel stage 22 is operative when the common mode voltage ranges between thenegative rail 14 and up to 0.5V below thepositive rail 12. - Turning now to FIG. 4, a block diagram of an exemplary embodiment of the
gain stage 20 of thecomparator 10 is illustrated. Thegain stage 20 includes a p-channeldifferential mode stage 28, an n-channeldifferential mode stage 30, and an outputsignal gain stage 32. The p-channeldifferential stage 28 provides anoutput signal 34 to the outputsignal gain stage 32 when the common mode voltage at the inputs A and AN approaches thenegative rail 14. Similarly, the n-channeldifferential stage 30 provides anoutput signal 36 to the outputsignal gain stage 32 when the common mode voltage at the inputs A and AN approaches thepositive rail 12. In the mid-range region, both the p-channeldifferential stage 28 and the n-channeldifferential stage 30 provide output signals to theoutput gain stage 32. - The output
signal gain stage 32 responds to thesignals differential mode stage 28 and the n-channeldifferential mode stage 30, respectively, to provide the output signals Z and ZN. Additionally, operation of the outputsignal gain stage 32 is influenced by thebias signal 18, which contributes to maintaining the output signals Z and ZN responsive to the differential between the inputs A and AN even when the common mode voltage at the inputs A and AN approaches thepositive rail 12 or thenegative rail 14. For instance, thebias signal 18 may maintain thegain stage 32 within an operating range in which thegain stage 32 can generate signals at the outputs Z and ZN that have substantially equal rise and fall times regardless of the common mode voltage. Accordingly, collapse of the output signals Z and ZN and/or distortion of the duty cycle of the output signals Z and ZN can be curtailed as the common mode input voltage approaches either rail. - An electrical schematic illustrating one exemplary implementation of the
bias stage 16 and gainstage 20 of thecomparator 10 is shown. The common mode p-channel stage 22 includes a matched pair of p-channel transistors positive rail 12 through a p-channel transistor 42. The p-channel transistors node 44 is dependent on the common mode voltage at the inputs A and AN and thebias signal 18 applied to the gate of the p-channel transistor 42. As the common mode voltage at inputs A and AN approaches thenegative rail 14, more current is provided atnode 44. - Similarly, the common mode n-
channel stage 24 of thebias stage 16 includes a matched pair of n-channel transistors negative rail 14 through an n-channel transistor 50. The n-channel transistor node 52 is dependent on the common mode voltage at the inputs A and AN and thebias signal 18 applied to the gate of the n-channel transistor 50. As the common mode voltage at inputs A and AN approaches thepositive rail 12, more current is provided atnode 52. - In the embodiment illustrated in FIG. 5, the
bias signal 18 is fed back to the gates of thetransistors bias stage 16. Further, the current signals atnodes bias source 26, which includes a pair of n-channel transistors channel transistors output 62 to theinput 64 causes the inverter to operate at its highest gain. Further, this operating state typically generates abias signal 18 which is about midway between thepositive rail 12 and thenegative rail 14. -
Node 44 is connected to the node between the n-channel transistors node 44 increases, thetransistors bias signal 18. This increase in thebias signal 18 causes a corresponding increase in the current through differential mode p-channel stage 28 of thegain stage 20, which, in turn, allows the outputsignal gain stage 32 of thecomparator 10 to operate within an operating region in which it can produce output signals at Z and ZN that are responsive to the differential signals at the inputs A and AN, even though the common mode input voltage at A and AN is approaching a supply rail. That is, the outputsignal gain stage 32 operates in a range in which duty cycle distortion of the output signals at Z and ZN is minimized regardless of the common mode input voltage. - Similarly, the
node 52 is connected to the junction of the p-channel transistors node 52 increases, thetransistors bias signal 18. This increase in thebias signal 18 causes a corresponding increase in the current through differential mode n-channel stage 30 of thegain stage 20, which, in turn, allows the outputsignal gain stage 32 of thecomparator 10 to remain within an operating region in which it can produce output signals at Z and ZN that are responsive to the differential signals at the inputs A and AN, even though the common mode input voltage at A and AN is approaching a supply rail, which, again, results in output signals having minimal duty cycle distortion. - Turning now to the
gain stage 20 of thecomparator 10, it includes the differential mode p-channel stage 28, the differential mode n-channel stage 30, and the outputsignal gain stage 32. Thedifferential stage 28 includes a matched differential pair of p-channel transistors 66 and 68 referenced to thepositive rail 12 through a p-channel transistor 70. Similarly, thedifferential stage 30 includes a matched differential pair of n-channel transistors 72 and 74 referenced to thenegative rail 14 through an n-channel transistor 76. The p-channel transistors node 78 is dependent on the differential signal at inputs A and AN and the magnitude of thebias signal 18 applied to the gate of thetransistor 70. The current atnode 78 divides between thetransistors 66 and 68 in a ratio that is dependent on the difference in voltage between the inputs A and AN. - Similarly, the n-
channel transistors node 80 is dependent on the differential signal at inputs A and AN and the magnitude of thebias signal 18 applied to the gate of thetransistor 76. The current atnode 80 divides between thetransistors 72 and 74 in a ratio that is dependent on the difference in voltage between the inputs A and AN. - In operation, as the common mode voltage at the inputs A and AN approaches the
negative rail 14, the p-channel stage 68 is operational. Further, as described above, thebias stage 16 provides an increasedbias signal 18 to the gate of thetransistor 70, thus causing an increase in the current at thenode 78. This increase in current corrects for the non-linear operation that may otherwise occur as the common mode voltage approaches thenegative rail 14. As a result, thegain stage 20 remains within an active operating region and the output signals Z and ZN can remain responsive to the differential signal at the inputs A and AN. The output of the p-channel differential stage 28 is a differential current which is provided to theoutput signal stage 32 at thenodes - Similarly, as the common mode voltage at the in puts A and AN approaches the
positive rail 12, the n-channel stage 30 is operational. Thebias stage 16 provides an increased bias signal to the gate of thetransistor 76, thus causing an increase in the current at thenode 80. As previously discussed, the increase in current maintains thegain stage 20 within an active operating region such that the output signals Z and ZN can remain responsive to the differential signal at the inputs A and AN as the common mode voltage approaches thepositive rail 12. The output of the n-channeldifferential gain stage 30 is a differential current which is provided to theoutput signal stage 32 at thenodes - The
output signal stage 32 of thegain stage 20 has a dual fully symmetrical folded cascode configuration which provides the appropriate level shifting and gain to generate the outputs Z and ZN based on the differential current signals received from the differential stages 28 and 30. The differential current signal from the p-channeldifferential gain stage 28 is provided atnodes channel transistors differential gain stage 30 is provided atnodes channel transistors comparator 10 is provided at the junction between thetransistors comparator 10 is provided at the junction between thetransistors comparator 10 is intended for use. For example, buffering may vary depending on the amplitude of the input voltage, the gain, and the intended load on the outputs Z and ZN. - The size of the various transistors of the
comparator 10 may vary depending on the processing technology used and the voltage supply levels. In one embodiment, 0.3 um CMOS device sizes may be used with a 3V voltage supply (i.e., VDD). Further, thetransistors 38/40, 46/48, 66/68, and 72/74 each are matched pairs. Still further, in one embodiment, transistors in thebias stage 16 are sized relative to transistors in thegain stage 20 such that the operating point of thebias stage 16 maintains theoutput signal stage 32 of thegain stage 20 at an operating point at which the duty cycle distortion at the outputs Z and ZN is minimized for all common mode input voltage levels. For instance, in one embodiment, at the operating point at which the input signals A and AN cross (regardless of the common mode level), thebias signal 18 matches the output signals Z and ZN. This matching is achieved by sizing thetransistor 50 at half the size of thetransistor 76, and sizing thetransistor 42 at half the size of thetransistor 70. - The foregoing embodiment of the circuitry of the
comparator 10 is exemplary only, and it should be understood that the particular configurations of thebias stage 16 and thegain stage 20 may vary without departing from the scope of the invention. Further, it is contemplated that the comparator may be manufactured as an integrated circuit on a semiconductor substrate or may be implemented as discrete components supported by a substrate, such as a printed circuit board. Moreover, the comparator may be implemented using CMOS devices or devices manufactured using other technology. - Still further, while the invention may be susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and have been described in detail herein. However, it should be understood that the invention is not intended to be limited to the particular forms disclosed. Rather, the invention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the following appended claims.
Claims (21)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/335,825 US6630847B2 (en) | 2001-11-08 | 2002-12-31 | Rail-to-rail CMOS comparator |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB0126893A GB2381971B (en) | 2001-11-08 | 2001-11-08 | Rail-to-rail CMOS comparator |
GB0126893.7 | 2001-11-08 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/335,825 Continuation US6630847B2 (en) | 2001-11-08 | 2002-12-31 | Rail-to-rail CMOS comparator |
Publications (2)
Publication Number | Publication Date |
---|---|
US6559687B1 US6559687B1 (en) | 2003-05-06 |
US20030085740A1 true US20030085740A1 (en) | 2003-05-08 |
Family
ID=9925442
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/047,285 Expired - Lifetime US6559687B1 (en) | 2001-11-08 | 2002-01-14 | Rail-to-rail CMOS comparator |
US10/335,825 Expired - Lifetime US6630847B2 (en) | 2001-11-08 | 2002-12-31 | Rail-to-rail CMOS comparator |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/335,825 Expired - Lifetime US6630847B2 (en) | 2001-11-08 | 2002-12-31 | Rail-to-rail CMOS comparator |
Country Status (2)
Country | Link |
---|---|
US (2) | US6559687B1 (en) |
GB (1) | GB2381971B (en) |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3990966B2 (en) * | 2002-10-08 | 2007-10-17 | 松下電器産業株式会社 | Differential amplifier |
US7400173B1 (en) | 2003-09-19 | 2008-07-15 | Cypress Semicondductor Corp. | Differential receiver with wide input common mode range and low duty cycle distortion |
US7250790B2 (en) * | 2003-09-22 | 2007-07-31 | Nxp B.V. | Circuit for providing a logic gate function and a latch function |
US7375585B2 (en) * | 2005-05-02 | 2008-05-20 | Texas Instruments Incorporated | Circuit and method for switching active loads of operational amplifier input stage |
US7579877B2 (en) * | 2005-08-15 | 2009-08-25 | Winbond Electronics Corporation | Comparator |
CN101064503B (en) * | 2006-04-30 | 2010-05-12 | 中芯国际集成电路制造(上海)有限公司 | Wide-input common-mode voltage comparator and low common-mode voltage comparator |
US7525381B2 (en) * | 2007-03-09 | 2009-04-28 | Analog Devices, Inc. | Amplifier structures that enhance transient currents and signal swing |
US7659753B2 (en) * | 2007-03-30 | 2010-02-09 | Intel Corporation | Analog comparator with precise threshold control |
DE102010013958A1 (en) * | 2010-04-06 | 2011-10-06 | Siemens Aktiengesellschaft | Differential amplifier with a rail-to-rail input voltage range |
US8614602B2 (en) * | 2011-09-30 | 2013-12-24 | Stmicroelectronics International N.V. | Differential amplifier |
US8680922B2 (en) | 2012-01-18 | 2014-03-25 | Analog Devices, Inc. | Rail-to rail input circuit |
US8638126B2 (en) | 2012-01-18 | 2014-01-28 | Richtek Technology Corporation, R.O.C. | Rail-to-rail comparator |
CN106612112B (en) | 2015-10-21 | 2022-02-08 | 恩智浦美国有限公司 | Rail-to-rail comparator with shared active load |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4958133A (en) * | 1989-11-13 | 1990-09-18 | Intel Corporation | CMOS complementary self-biased differential amplifier with rail-to-rail common-mode input-voltage range |
DE69315251T2 (en) * | 1992-05-08 | 1998-05-14 | Koninkl Philips Electronics Nv | Differential amplifier with an input voltage range equal to the supply voltage and with square root current control |
US5311145A (en) * | 1993-03-25 | 1994-05-10 | North American Philips Corporation | Combination driver-summing circuit for rail-to-rail differential amplifier |
US5384548A (en) * | 1993-08-25 | 1995-01-24 | The Ohio State University | Constant transconductance bias circuit and method |
EP0690561B1 (en) * | 1994-06-30 | 2001-10-31 | STMicroelectronics S.r.l. | Method for erasing a common mode current signal and transconductor assembly using such method |
US5517134A (en) * | 1994-09-16 | 1996-05-14 | Texas Instruments Incorporated | Offset comparator with common mode voltage stability |
US5550510A (en) * | 1994-12-27 | 1996-08-27 | Lucent Technologies Inc. | Constant transconductance CMOS amplifier input stage with rail-to-rail input common mode voltage range |
EP0837558A1 (en) * | 1996-10-18 | 1998-04-22 | Hewlett-Packard Company | A CMOS op-amp input stage with constant small signal gain from rail-to-rail |
KR0183290B1 (en) * | 1996-11-16 | 1999-04-15 | 삼성전자주식회사 | Cmrr auto control circuit and management method |
US6154548A (en) * | 1997-09-27 | 2000-11-28 | Ati Technologies | Audio mute control signal generating circuit |
JP3557110B2 (en) * | 1998-11-12 | 2004-08-25 | 株式会社東芝 | Voltage-current converter |
US6429734B1 (en) * | 2001-12-19 | 2002-08-06 | Neoaxiom Corporation | Differential active loop filter for phase locked loop circuits |
-
2001
- 2001-11-08 GB GB0126893A patent/GB2381971B/en not_active Expired - Lifetime
-
2002
- 2002-01-14 US US10/047,285 patent/US6559687B1/en not_active Expired - Lifetime
- 2002-12-31 US US10/335,825 patent/US6630847B2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
US6630847B2 (en) | 2003-10-07 |
US20030132785A1 (en) | 2003-07-17 |
US6559687B1 (en) | 2003-05-06 |
GB2381971B (en) | 2006-01-11 |
GB0126893D0 (en) | 2002-01-02 |
GB2381971A (en) | 2003-05-14 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US5621340A (en) | Differential comparator for amplifying small swing signals to a full swing output | |
US6118318A (en) | Self biased differential amplifier with hysteresis | |
EP0594305B1 (en) | Comparator circuit | |
US7391825B2 (en) | Comparator circuit having reduced pulse width distortion | |
EP0688097B1 (en) | Operational amplifiers and current detector circuits | |
US6559687B1 (en) | Rail-to-rail CMOS comparator | |
US7425847B2 (en) | Input buffer with optimal biasing and method thereof | |
US20040100838A1 (en) | Buffer circuit device supplying a common mode voltage applicable to a next-stage circuit receiving output signals of the buffer circuit device | |
KR100366626B1 (en) | Mismatch immune duty cycle detection circuit | |
JPH033416A (en) | Integrated circuit with signal level converter | |
US4871933A (en) | High-speed static differential sense amplifier | |
US6169424B1 (en) | Self-biasing sense amplifier | |
US20060012429A1 (en) | Self biased differential amplifier | |
US7342418B2 (en) | Low voltage differential signal receiver | |
US6924702B2 (en) | Low supply voltage and self-biased high speed receiver | |
US5132560A (en) | Voltage comparator with automatic output-level adjustment | |
US20020063586A1 (en) | Receiver immune to slope-reversal noise | |
CN112769419B (en) | Hysteresis comparator | |
US7057438B2 (en) | Output circuit and semiconductor integrated circuit incorporating it therein | |
US7071772B2 (en) | Differential amplifier | |
US7170329B2 (en) | Current comparator with hysteresis | |
US11848649B2 (en) | Low power VB class AB amplifier with local common mode feedback | |
JP3628189B2 (en) | Differential amplifier circuit | |
US11626868B1 (en) | Comparator circuit with dynamic biasing | |
CN114362700B (en) | Differential amplifier and back gate control method thereof |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: MICRON TECHNOLOGY, INC., IDAHO Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:HUNT, KEN S.;REEL/FRAME:012517/0349 Effective date: 20011212 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
FPAY | Fee payment |
Year of fee payment: 8 |
|
FPAY | Fee payment |
Year of fee payment: 12 |
|
AS | Assignment |
Owner name: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT, CALIFORNIA Free format text: SECURITY INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:038669/0001 Effective date: 20160426 Owner name: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGEN Free format text: SECURITY INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:038669/0001 Effective date: 20160426 |
|
AS | Assignment |
Owner name: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT, MARYLAND Free format text: PATENT SECURITY AGREEMENT;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:038954/0001 Effective date: 20160426 Owner name: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL Free format text: PATENT SECURITY AGREEMENT;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:038954/0001 Effective date: 20160426 |
|
AS | Assignment |
Owner name: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT, CALIFORNIA Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:043079/0001 Effective date: 20160426 Owner name: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGEN Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:043079/0001 Effective date: 20160426 |
|
AS | Assignment |
Owner name: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT, ILLINOIS Free format text: SECURITY INTEREST;ASSIGNORS:MICRON TECHNOLOGY, INC.;MICRON SEMICONDUCTOR PRODUCTS, INC.;REEL/FRAME:047540/0001 Effective date: 20180703 Owner name: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT, IL Free format text: SECURITY INTEREST;ASSIGNORS:MICRON TECHNOLOGY, INC.;MICRON SEMICONDUCTOR PRODUCTS, INC.;REEL/FRAME:047540/0001 Effective date: 20180703 |
|
AS | Assignment |
Owner name: MICRON TECHNOLOGY, INC., IDAHO Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT;REEL/FRAME:047243/0001 Effective date: 20180629 |
|
AS | Assignment |
Owner name: MICRON TECHNOLOGY, INC., IDAHO Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT;REEL/FRAME:050937/0001 Effective date: 20190731 |
|
AS | Assignment |
Owner name: MICRON SEMICONDUCTOR PRODUCTS, INC., IDAHO Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT;REEL/FRAME:051028/0001 Effective date: 20190731 Owner name: MICRON TECHNOLOGY, INC., IDAHO Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT;REEL/FRAME:051028/0001 Effective date: 20190731 |