Search Images Maps Play YouTube News Gmail Drive More »
Sign in
Screen reader users: click this link for accessible mode. Accessible mode has the same essential features but works better with your reader.

Patents

  1. Advanced Patent Search
Publication numberUS20030087492 A1
Publication typeApplication
Application numberUS 10/000,922
Publication dateMay 8, 2003
Filing dateNov 2, 2001
Priority dateNov 2, 2001
Also published asUS7537915, US20070134704
Publication number000922, 10000922, US 2003/0087492 A1, US 2003/087492 A1, US 20030087492 A1, US 20030087492A1, US 2003087492 A1, US 2003087492A1, US-A1-20030087492, US-A1-2003087492, US2003/0087492A1, US2003/087492A1, US20030087492 A1, US20030087492A1, US2003087492 A1, US2003087492A1
InventorsBrian Lee, Jan Zieleman
Original AssigneePromos Technologies, Inc.
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Semiconductor device and method of manufacturing the same
US 20030087492 A1
Abstract
The present invention discloses structure and manufacturing method of binary nitride-oxide (NO) dielectric node for deep trench based DRAM devices. In the present invention, a thin strained SiGe layer is deposited prior to poly deposition to modulate the chemical potential unbalance caused by work-function (WF) differences between buried plate and poly. The thin strained SiGe layer will lower the differences by its lower band-gap characteristics at the same doping level, thereby balancing the chemical potential despite of a different doping. The modulation of the chemical potential can be achieved by a proper control of a stochimetric x value. The optimized chemical potential will assure the reliability and robustness of the dielectric node, especially the binary NO dielectric node by suppressing asymmetric charging trapping and charge injection nature.
Images(6)
Previous page
Next page
Claims(19)
1. A method for manufacturing a semiconductor device, comprising the steps of:
(a) forming a trench in a substrate;
(b) forming a recessed arsenic silicate glass (ASG) in the trench;
(c) depositing an oxide layer covering the ASG recess in the trench;
(d) forming a buried plate in the substrate;
(e) removing the oxide layer and the ASG in the trench;
(f) forming a dielectric layer in the trench;
(g) depositing a thin strained layer in the trench; and
(h) filling a poly filler in the trench.
2. The method for manufacturing a semiconductor device as claimed in claim 1, wherein the semiconductor device is a DRAM.
3. The method for manufacturing a semiconductor device as claimed in claim 1, wherein the substrate is a silicon substrate.
4. The method for manufacturing a semiconductor device as claimed in claim 1, wherein step (b) comprises the steps of depositing an ASG layer in the trench and recessing the ASG layer in the trench.
5. The method for manufacturing a semiconductor device as claimed in claim 1, wherein the buried plate is formed by an annealling process.
6. The method for manufacturing a semiconductor device as claimed in claim 1, wherein the oxide layer and the ASG recess in the trench are removed by etching.
7. The method for manufacturing a semiconductor device as claimed in claim 1, wherein the dielectric layer is a NO layer.
8. The method for manufacturing a semiconductor device as claimed in claim 1, wherein step (f) comprises the steps of depositing a nitride layer and re-oxidizing the nitride layer.
9. The method for manufacturing a semiconductor device as claimed in claim 8, wherein the step of depositing the nitride layer is performed by LPCVD.
10. The method for manufacturing a semiconductor device as claimed in claim 1, wherein the thin strained layer is a SiGe layer of a thickness less than 50 angstroms.
11. The method for manufacturing a semiconductor device as claimed in claim 10, wherein the SiGe layer is of a formula SixGe1−x and has an energy gap (Eg) of 0.67 eV when x=1 and an energy gap (Eg) of 1.1 eV when x=0.
12. The method for manufacturing a semiconductor device as claimed in claim 1, wherein the poly filler is an As poly filler.
13. A semiconductor device, comprising
a substrate;
a trench in the substrate;
a buried plate in the substrate adjacent the trench;
a dielectric layer overlaying the trench;
a thin strained layer overlaying the dielectric layer; and
a poly filler in the trench.
14. The semiconductor device as claimed in claim 13, wherein the semiconductor device is a DRAM.
15. The semiconductor device as claimed in claim 13, wherein the dielectric layer is a NO layer.
16. The semiconductor device as claimed in claim 15, wherein the NO layer is formed by depositing a nitride layer and re-oxidizing the nitride layer.
17. The semiconductor device as claimed in claim 13, wherein the thin strained layer is a SiGe layer of a thickness less than 50 angstroms.
18. The semiconductor device as claimed in claim 17, wherein the SiGe layer is of a formula SixGe1−x and has an energy gap (Eg) of 0.67 eV when x=1.
19. The semiconductor device as claimed in claim 13, wherein the poly filler is an As poly filler.
Description
BACKGROUND OF THE INVENTION

[0001] (A) Field of the Invention

[0002] The present invention relates to a semiconductor device and method for manufacturing the same, and particularly to a deep trench based dynamic random access memory (DRAM) and method for manufacturing the same.

[0003] (B) Description of Related Art

[0004] As DRAM cell sizes continuously shrink, the design rules get strict. Therefore, a higher doping for a buried plate is needed to minimize a capacitance loss by junction depletion. Gas phase doping (GPD) or plasma doping (PLAD) has been used to increase the doping concentration (>1E20 As/cm3) to suppress the depletion capacitance of the buried plate. However, the doping concentration of a poly is somewhat limited to 5E19 As (or P)/cm3. This unbalance of dopants results in asymmetric C-V characteristics, appearing as an asymmetric profile. The asymmetric profile is due to a chemical potential mismatch caused by a work-function difference, or equivalently a Fermi level shift. This means that a node is stressed by a voltage shift ΔV even at a 0V bias or the node is biased by ΔV+V0 at a V0 bias, thus causing more leaking than normally expected. This situation becomes even more severe for the case of a binary nitride-oxide (NO) dielectric system than that of a convention ternary oxidenitride-oxide (ONO) system due to its asymmetric charge trapping in a nitride layer (see “Thickness and Polarity Dependence of Intrinsic Breakdown of Ultra-Thin Reoxidized-Nitride for DRAM Technology Application,” by E. Wu et. al.). The charge trapping in the nitride layer will aggravate the voltage shift, thus adding electric stress accelerating intrinsic breakdown of the node. Nevertheless, the binary NO is a preferred option for an advanced DRAM due to its scalability.

[0005] In view of the above, there is a need to provide a static voltage for compensation by employing a low band gap layer in a poly and node dielectric layer, which will lower the static voltage, even with a different doping level between the buried plate and the poly. The balance of the static potential (or surface chemical potential) can be controlled by selecting a proper stochimetric constant.

SUMMARY OF THE INVENTION

[0006] An object of the present invention is to provide a semiconductor device and a method for manufacturing the semiconductor device, wherein a thin SiGe layer is deposited prior to poly deposition so as to provide a symmetric C-V profile by overcoming unbalanced chemical potential without jeopardizing depletion capacitance.

[0007] Another object of the present invention is to provide a semiconductor device and a method for manufacturing the semiconductor device, wherein the semiconductor device can be operated at a higher voltage than that of the conventional scheme by operating at a node-high bias condition.

[0008] Another object of the present invention is to provide a semiconductor device and a method for manufacturing the semiconductor device, wherein a more robust process window with a nominal dielectric thickness variation and/or thickness modulation between the nitride and oxide can be achieved.

[0009] To achieve the above objects, the present invention provides a semiconductor device and a method for manufacturing the semiconductor device. The method comprises the steps of forming a trench in a substrate; forming an arsenic silicate glass (ASG) in the trench; recessing the ASG layer, depositing an oxide layer covering the ASG recess in the trench; forming a buried plate in the substrate; removing the oxide layer and the ASG recess in the trench; forming a dielectric layer in the trench; depositing a thin strained layer in the trench; and filtering a poly filler in the trench. The semiconductor device of the present invention includes a substrate; a trench in the substrate; a buried plate in the substrate adjacent the trench; a dielectric layer overlaying the trench; a thin strained layer overlaying the dielectric layer; and a poly filler in the trench.

BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The present invention is described below by way of examples with reference to the accompanying drawings which will make readers easier to understand the objects, technical contents, characteristics and effects of the present invention, wherein

[0011] FIGS. 1-9 illustrate cross-sectional views of an embodiment of a semiconductor device structure at various stages of a process according to the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0012] FIGS. 1-9 illustrate cross-sectional views of an embodiment of a semiconductor device structure (such as a DRAM) at various stages of a process according to the present invention. Referring to FIG. 1, a trench 11 is first formed in a substrate 10 (such as a silicon substrate).

[0013] Referring to FIGS. 2 and 3, after formation of the trench 11, an arsenic silicate glass (ASG) recess 14 is formed in the trench 11. The formation of the ASG recess 14 comprises the steps of (1) depositing an ASG layer 12 in the trench 11; and (2) recessing the ASG layer 12 in the trench 11.

[0014] Referring to FIG. 4, an oxide layer 15 is formed in the trench 11 to cover the ASG recess 14.

[0015] Referring to FIG. 5, the semi-finished structure is annealed to diffuse dopants into the substrate 10 to form a buried plate 16.

[0016] Referring to FIG. 6, after the buried plate 16 is formed, the oxide layer 15 and the ASG recess 14 in the trench 11 are removed by etching.

[0017] Referring to FIG. 7, a dielectric layer 17 (such as a NO layer) is formed in the trench 11. The formation of the dielectric layer 17 comprises the steps of depositing a nitride layer and re-oxidizing the nitride layer, wherein the step of depositing the nitride layer is performed by LPCVD.

[0018] Referring to FIG. 8, a thin strained layer 18 is formed in the trench 11 to cover the dielectric layer 17. The thin strained layer is a SiGe layer of a thickness less than 50 angstroms. In addition, the SiGe layer is of a formula SixGe1−x and has an energy gap (Eg) of 0.67 eV when x=1 and an energy gap (Eg) of 1.1 eV when x=0.

[0019] Referring to FIG. 9, a poly filler 19 (such as an As poly filler) is filled in the trench 11.

[0020] Finally, other essential steps for forming other elements in the semiconductor device may be additionally performed.

[0021] The present invention also includes a semiconductor device formed by a process as described above. The semiconductor device of the present invention includes a substrate; a trench in the substrate; a buried plate in the substrate adjacent the trench; a dielectric layer overlaying the trench; a thin strained layer overlaying the dielectric layer; and a poly filler in the trench. Alternatively, other processes may be utilized to form a semiconductor device according to the present invention.

[0022] According to the present invention, a thin strained SiGe layer is deposited prior to the poly deposition to modulate the chemical potential unbalance caused by work-function (WF) differences between the buried plate and the poly. The thin strained SiGe layer will lower the differences by its lower band-gap characteristics at the same doping level, thereby balancing the chemical potential despite of a different doping. The modulation of the chemical potential can be achieved by a proper control of a stochimetric x value. The optimized chemical potential will assure the reliability and robustness of the dielectric node, especially the binary NO dielectric node by suppressing asymmetric charging trapping and charge injection nature. In addition, the present invention can be used for a high voltage operation of the node yet with the same node thickness and composition by suppressing the node breakdown mechanism by static voltage compensation.

[0023] Although the present invention and its advantages have been described in detail, it should be understood that various changes, substitutions and alternations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.

Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US7129126Nov 5, 2003Oct 31, 2006International Business Machines CorporationMethod and structure for forming strained Si for CMOS devices
US7223994Jun 3, 2004May 29, 2007International Business Machines CorporationStrained Si on multiple materials for bulk or SOI substrates
US7429752Sep 22, 2006Sep 30, 2008International Business Machines CorporationMethod and structure for forming strained SI for CMOS devices
US7550338Sep 13, 2007Jun 23, 2009International Business Machines CorporationMethod and structure for forming strained SI for CMOS devices
US7560328Mar 30, 2007Jul 14, 2009International Business Machines CorporationStrained Si on multiple materials for bulk or SOI substrates
US7700951Jul 15, 2008Apr 20, 2010International Business Machines CorporationMethod and structure for forming strained Si for CMOS devices
US7928443Jan 11, 2010Apr 19, 2011International Business Machines CorporationMethod and structure for forming strained SI for CMOS devices
WO2005045901A2 *Nov 5, 2004May 19, 2005IbmMETHOD AND STRUCTURE FOR FORMING STRAINED Si FOR CMOS DEVICES
Classifications
U.S. Classification438/249, 257/E21.274, 257/E21.268, 438/392, 257/E21.396
International ClassificationH01L21/334, H01L21/314, H01L21/316, H01L21/8242
Cooperative ClassificationH01L29/66181, C07K2319/60, C07K14/43595, H01L21/31604, H01L21/3144, C07K14/43504, H01L27/1087
European ClassificationH01L27/108M4B6T, H01L29/66M6D6, C07K14/435A, C07K14/435A5, H01L21/316B
Legal Events
DateCodeEventDescription
Nov 2, 2001ASAssignment
Owner name: PROMOS TECHNOLOGIES, INC., TAIWAN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:LEE, BRIAN;ZIELEMAN, JAN;REEL/FRAME:012349/0657
Effective date: 20011023