US20030094696A1 - Stacked fill structures for support of dielectric layers - Google Patents
Stacked fill structures for support of dielectric layers Download PDFInfo
- Publication number
- US20030094696A1 US20030094696A1 US09/991,769 US99176901A US2003094696A1 US 20030094696 A1 US20030094696 A1 US 20030094696A1 US 99176901 A US99176901 A US 99176901A US 2003094696 A1 US2003094696 A1 US 2003094696A1
- Authority
- US
- United States
- Prior art keywords
- fill
- dielectric
- conductive
- fill shapes
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 claims abstract description 64
- 238000005304 joining Methods 0.000 claims abstract description 15
- 238000000034 method Methods 0.000 claims description 38
- 239000003989 dielectric material Substances 0.000 claims description 26
- 238000004519 manufacturing process Methods 0.000 claims description 22
- 239000004642 Polyimide Substances 0.000 claims description 17
- 229920001721 polyimide Polymers 0.000 claims description 17
- 229920000642 polymer Polymers 0.000 claims description 17
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 15
- 239000010432 diamond Substances 0.000 claims description 13
- 239000000758 substrate Substances 0.000 claims description 11
- 239000011521 glass Substances 0.000 claims description 9
- UFWIBTONFRDIAS-UHFFFAOYSA-N Naphthalene Chemical compound C1=CC=CC2=CC=CC=C21 UFWIBTONFRDIAS-UHFFFAOYSA-N 0.000 claims description 8
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 8
- 239000004809 Teflon Substances 0.000 claims description 8
- 229920006362 Teflon® Polymers 0.000 claims description 8
- 239000004964 aerogel Substances 0.000 claims description 8
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 claims description 8
- KPUWHANPEXNPJT-UHFFFAOYSA-N disiloxane Chemical class [SiH3]O[SiH3] KPUWHANPEXNPJT-UHFFFAOYSA-N 0.000 claims description 8
- 239000006260 foam Substances 0.000 claims description 8
- 239000010410 layer Substances 0.000 claims description 8
- 229920000098 polyolefin Polymers 0.000 claims description 8
- 229910021426 porous silicon Inorganic materials 0.000 claims description 8
- 229910052710 silicon Inorganic materials 0.000 claims description 8
- 239000010703 silicon Substances 0.000 claims description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 8
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 8
- 229910052721 tungsten Inorganic materials 0.000 claims description 8
- 239000010937 tungsten Substances 0.000 claims description 8
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 7
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 7
- 229910001080 W alloy Inorganic materials 0.000 claims description 7
- 229910052782 aluminium Inorganic materials 0.000 claims description 7
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 7
- WPPDFTBPZNZZRP-UHFFFAOYSA-N aluminum copper Chemical compound [Al].[Cu] WPPDFTBPZNZZRP-UHFFFAOYSA-N 0.000 claims description 7
- -1 aluminum-copper-silicon Chemical compound 0.000 claims description 7
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 7
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 claims description 7
- 239000010936 titanium Substances 0.000 claims description 7
- 229910052719 titanium Inorganic materials 0.000 claims description 7
- MAKDTFFYCIMFQP-UHFFFAOYSA-N titanium tungsten Chemical compound [Ti].[W] MAKDTFFYCIMFQP-UHFFFAOYSA-N 0.000 claims description 7
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 claims description 5
- 229910003460 diamond Inorganic materials 0.000 claims description 5
- 229910052731 fluorine Inorganic materials 0.000 claims description 5
- 239000011737 fluorine Substances 0.000 claims description 5
- CIYRLONPFMPRLH-UHFFFAOYSA-N copper tantalum Chemical compound [Cu].[Ta] CIYRLONPFMPRLH-UHFFFAOYSA-N 0.000 claims 5
- 239000004020 conductor Substances 0.000 description 19
- 239000000463 material Substances 0.000 description 16
- 230000009977 dual effect Effects 0.000 description 7
- 229910052751 metal Inorganic materials 0.000 description 7
- 239000002184 metal Substances 0.000 description 7
- 230000032798 delamination Effects 0.000 description 6
- 230000000694 effects Effects 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 230000035882 stress Effects 0.000 description 5
- 239000011248 coating agent Substances 0.000 description 4
- 238000000576 coating method Methods 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 238000005352 clarification Methods 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 238000005336 cracking Methods 0.000 description 3
- RTZKZFJDLAIYFH-UHFFFAOYSA-N Diethyl ether Chemical compound CCOCC RTZKZFJDLAIYFH-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000011295 pitch Substances 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 2
- 230000008646 thermal stress Effects 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229920000412 polyarylene Polymers 0.000 description 1
- 230000008707 rearrangement Effects 0.000 description 1
- 230000002787 reinforcement Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/562—Protection against mechanical damage
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Definitions
- the present invention relates to the field of semiconductor device design and fabrication; more specifically, it relates to a structure for structural reinforcement and support of interlevel dielectric layers and the method of fabricating said structure.
- the interconnect structure of semiconductor devices comprise layers (wiring levels) containing conductive wires separated by interlevel dielectric layers (levels.)
- the conductive wires are electrically isolated from one another by the dielectric layers.
- the conductive wires in each wiring level are interconnected by conductive vias extending from the conductive wires in one wiring level, through the interlevel dielectric layer, to the conductive wires in a second wiring level.
- the conductive wires are partially embedded in or damascened into the dielectric layers.
- interlevel-wiring capacitance As the speed of modern semiconductor devices has increased, interlevel-wiring capacitance has become a problem. Methods were sought to reduce interlevel wiring capacitance.
- One solution that is becoming popular is the use of low-k dielectric materials such as SILKTM (a polyarylene ether manufactured by Dow Chemical, Midland, Mich.), spin on glass, polyimide or other polymers. These have replaced traditional dielectric materials such a silicon oxide and silicon nitride.
- Low-k dielectric materials are not rigid like the traditional dielectric materials.
- Low-k materials are soft, compressible and flexible, have a low modulus and poor interfacial strength, i.e., they tend to delaminate or collapse under mechanical and thermal stress resulting in low yield, poor reliability and higher costs.
- Some low-k materials are brittle and tend to crack under mechanical or thermal stress.
- semiconductor devices present two problems.
- CMP chemical-mechanical-polish
- a first aspect of the present invention is a semiconductor device comprising: a first wiring level having a first conductive fill shape embedded in a first dielectric; a second wiring level having a second conductive fill shape embedded in a second dielectric; and a conductive via extending between and joining the first and second conductive fill shapes.
- a second aspect of the present invention is a semiconductor device comprising: a multiplicity of wiring levels, each wiring level comprising conductive wires and a multiplicity of conductive fill shapes embedded in a dielectric; at least some of the fill shapes in at least two adjacent wiring levels being co-aligned; and where the fill shapes on adjacent levels are aligned, one or more conductive vias extending between and joining each co-aligned fill shape in each adjacent wiring level.
- a third aspect of the present invention is a semiconductor device comprising:
- a first wiring level comprising a conductive wires and a multiplicity of conductive fill shapes embedded in a first dielectric material; a multiplicity of higher wiring levels, each higher wiring level comprising conductive wires and a multiplicity of conductive fill shapes embedded in a second dielectric material; at least some of the fill shapes in one or more pairs of adjacent wiring levels being co-aligned; and where the fill shapes on adjacent levels are aligned, one or more conductive vias extending between and joining each co-aligned fill shape in each pair of adjacent wiring levels.
- a fourth aspect of the present invention is a semiconductor device comprising: a first wiring level having a first conductive fill shape having corners, embedded in a first dielectric; a second wiring level having a second conductive fill shape having corners, embedded in a second dielectric, the second conductive fill shape co-aligned with the first fill shape; and a conductive via aligned with each corner of the first and second fill shapes and extending between and joining the first and second conductive fill shapes.
- a fifth aspect of the present invention is a semiconductor device comprising: a first wiring level having a first conductive fill shape having corners, embedded in a first dielectric; a second wiring level having a second conductive fill shape having corners, embedded in a second dielectric, the second conductive fill shape co-aligned with the first fill shape; and at least two conductive vias each aligned with a corner of the first and second fill shapes and extending between and joining the first and second conductive fill shapes.
- a sixth aspect of the present invention is a method of fabricating a semiconductor device, comprising: providing a substrate; forming on the substrate, a multiplicity of wiring levels, each wiring level comprising conductive wires and a multiplicity of conductive fill shapes embedded in a dielectric; at least some of the fill shapes in at least two adjacent wiring levels being co-aligned; and where the fill shapes on adjacent levels are aligned, forming one or more conductive vias extending between and joining each co-aligned fill shape in each adjacent wiring level.
- a seventh aspect of the present invention is a method of fabricating a semiconductor device, comprising: providing a substrate; forming a first wiring level on the substrate, the first wiring level comprising a conductive wires and a multiplicity of conductive fill shapes embedded in a first dielectric material; forming a multiplicity of higher wiring levels on the first wiring level, each higher wiring level comprising conductive wires and a multiplicity of conductive fill shapes embedded in a second dielectric material; at least some of the fill shapes in one or more pairs of adjacent wiring levels being co-aligned; and where the fill shapes on adjacent levels are aligned, forming one or more conductive vias extending between and joining each co-aligned fill shape in each pair of adjacent wiring levels.
- An eighth aspect of the present invention is a method of designing a semiconductor device having wiring levels containing wires and fill shapes interspersed with interconnecting via levels containing vias, comprising: selecting a pair of adjacent wiring levels; finding pairs of vertically aligned fill shapes in the adjacent wiring levels; and creating and placing, in the interconnecting via levels between the adjacent wiring levels, one or more vias to interconnect the pairs of fill shapes.
- a ninth aspect of the present invention is A method of designing a semiconductor device having wiring levels interspersed with interconnecting via levels, comprising: placing fill shapes at least some of the wiring levels; selecting a pair of adjacent wiring levels; finding pairs of vertically aligned fill shapes in the adjacent wiring levels; and creating and placing, in the interconnecting via levels between the adjacent wiring levels, one or more vias to interconnect the pairs of fill shapes.
- FIGS. 1, 3, 3 A, 6 , 9 and 12 are partial cross-section views illustrating fabrication of a semiconductor device according to the present invention.
- FIGS. 2, 4, 5 , 7 , 8 10 and 11 are partial top views of wiring and via photomasks used in the fabrication of the semiconductor device according to the present invention.
- FIGS. 13 through 16 are top view schematic diagrams illustrating alternative placement of via mask features relative to fill shape mask features according to the present invention.
- FIG. 17 is a flowchart illustrating the method of adding fill shape interconnecting vias to via masks according to the present invention.
- FIG. 1 is a partial cross-section view illustrating the initial structure of the fabrication of a semiconductor device according to the present invention.
- a first dielectric layer 100 is formed on a silicon substrate 105 .
- Silicon substrate 105 may include active devices such as transistors and diodes and inactive devices such as resistors and capacitors.
- First dielectric layer is preferably, but not necessarily, a rigid (high modulus) dielectric layer. Examples of rigid dielectrics include silicon oxide, silicon nitride, diamond or fluorine doped silicon or combinations of layers thereof.
- first dielectric layer 100 be a rigid dielectric in order to anchor firmly to silicon substrate 105 the subsequent stack of vias and fill shapes that will be fabricated according to the present invention. Fill shapes are added to wiring levels in order to increase the uniformity of CMP processes.
- the present invention utilizes pre-existing fill shapes added to the design for CMP purposes, joined by vias, to tie dielectric layers together. If first dielectric layer is, a non-rigid dielectric (low modulus) or low-k dielectric (k ⁇ 3.5) the present invention will still provide the benefit of tying dielectric layers together.
- non-rigid dielectrics or low-k dielectric examples include spin on glass, porous silicon oxide, polyimide, polyimide siloxane, polysilsequioxane polymer, benzocyclobutene, paralyene N, paralyene F, polyolefin, poly-naphthalene, amorphous Teflon, SILKTM (Dow Chemical, Midland, Mich.), black diamond (Applied Materials, Santa Clara, Calif.), polymer foam or aerogel or layers thereof.
- conductive contact 110 is formed by a single damascene process.
- a single damascene process will now be defined.
- a single damascene process first a trench is formed in a dielectric layer, for example by reactive ion etching (RIE).
- RIE reactive ion etching
- an optional conductive conformal liner is deposited coating the top surface of the dielectric and the sidewalls and bottom of the trench.
- a core conductor is deposited to completely fill the trench as well as coating the top surface of the dielectric layer.
- conductive contact 115 comprises tungsten, aluminum, aluminum-copper, aluminum-copper-silicon or copper and may include a liner formed on the sidewalls and bottom of trench 110 .
- the liner may be formed from tantalum, tantalum nitride, titanium, titanium nitride, a titanium-tungsten alloy or layers thereof.
- FIG. 2 is a partial top view of a first wiring level photomask used in the fabrication of the semiconductor device according to the present invention.
- first wiring level photomask 120 includes a first wire feature 125 and a plurality of first fill shape features 130 .
- First wiring level photomask 120 is used to fabricate a first wiring level as illustrated in FIG. 3 and described below.
- FIG. 3 is a partial cross-section view through 3 - 3 of FIG. 2 illustrating a first step in the fabrication of a semiconductor device according to the present invention.
- a second dielectric layer 135 is formed on a top surface 140 of first dielectric layer 100 .
- a first conductive wire 145 (corresponding to first wire feature 125 of mask of first photomask 120 ) comprising a core conductor 150 and an optional liner 155 is formed in second dielectric layer 135 .
- Also formed in second dielectric layer 135 is a plurality of first fill shapes 160 (corresponding to first fill shape features 130 of first wiring level photomask 120 .)
- a single damascene process is used to form first conductive wire 145 and first fill shapes 160 .
- Each fill shape 160 is formed from core conductor 150 and optional liner 155 .
- First conductive wire 145 , and first fill shapes 160 are formed in second dielectric 135 using photomask 120 and a single damascene process. Fill shapes 160 are in contact with top surface 140 of first dielectric layer 100 .
- First conductive wire is electrical contact with conductive contact 115 .
- Liner 155 among other purposes, by selection of material combinations, serves to improve adhesion of core conductor 150 to first dielectric layer 100 .
- Second dielectric layer 135 is preferably a non-rigid dielectric layer (or a dielectric with a coefficient of expansion greater than the metal used for wiring).
- second dielectric layer 135 is spin on glass, porous silicon oxide, polyimide, polyimide siloxane, polysilsequioxane polymer, benzocyclobutene, paralyene N, paralyene F, polyolefin, poly-naphthalene, amorphous Teflon, SILKTM (Dow Chemical, Midland, Mich.), black diamond (Applied Materials, Santa Clara, Calif.), polymer foam or aerogel or layers thereof.
- second dielectric layer 135 may be a rigid dielectric.
- second dielectric layer 135 is silicon oxide, silicon nitride, diamond or fluorine doped silicon or combinations of layers thereof.
- Second dielectric layer 135 may also be formed from a combination of rigid and non-rigid dielectrics, an example of which would be a thin layer of silicon nitride over a thicker layer of SILKTM (Dow Chemical, Midland, Mich.).
- core conductor 150 comprises tungsten, aluminum, aluminum-copper, aluminum-copper-silicon or copper and may include a liner 155 formed on the sidewalls and bottom of trench 110 .
- liner 155 comprises tantalum, tantalum nitride, titanium, titanium nitride, a titanium-tungsten alloy or layers thereof.
- first conductive wire 145 and first fill shapes 160 have been described as being formed in second dielectric 135 using a single damascene process, a dual damascene process may just as easily be used. However, since fill shapes 160 should be in bonding contact with first dielectric layer 100 , the present invention would then require forming vias under each first fill shape 160 , the vias in contact with and providing the bonding contact to the first dielectric layer. This is illustrated in FIG. 3A. The significant difference between FIG. 3 and FIG. 3A, is the presence of vias 162 between first fill shapes 160 and top surface 140 of first dielectric layer 100 . A dual damascene process will now be defined.
- a trench is formed in a dielectric layer (using a first photomask) for example by RIE.
- the trench is formed to a depth less than the total thickness of the dielectric layer.
- This step defines the wires and fill shapes.
- vias are formed in the bottom of the trench (using a second photomask) through to the underlying material, again by RIE.
- This step defines the interconnections between wiring levels.
- an optional conductive conformal liner is deposited coating the top surface of the dielectric and the sidewalls and bottom of the trench, via sidewalls and the underlying layer exposed at the bottom of the vias.
- a core conductor is deposited to completely fill the trench as well as coating the top surface of the dielectric layer.
- a CMP process performed to remove all conductive material from the top surface of the dielectric layer and polish the top of surface of the conductor filled trench even with the top surface of the dielectric layer.
- the vias are integral with the wires and fill shapes in a dual damascene process.
- FIG. 4 is a partial top view of a second wiring level photomask used in the fabrication of the semiconductor device according to the present invention.
- FIG. 4 illustrates the same region of the semiconductor device as illustrated in FIG. 2.
- second wiring level photomask 165 includes a second wire feature 170 and a plurality of second fill shape features 175 A and second fill shape features 175 B.
- Second wiring level photomask 165 is used in conjunction with a first via photomask to fabricate a second wiring level as illustrated in FIG. 6 and described below.
- the first via photomask is illustrated in FIG. 5 and described below.
- the difference between second fill shape features 175 A and second fill shape features 175 B is second fill shape features 175 B overlay first fill shape features 130 of first wiring level photomask 120 while second fill shape features 175 A do not.
- FIG. 5 is a partial top view of a first via level photomask used in the fabrication of the semiconductor device according to the present invention.
- FIG. 5 illustrates the same region of the semiconductor device as illustrated in FIGS. 2 and 4.
- first via level photomask 180 includes a plurality of via feature sets 185 .
- Each via feature set 185 includes one or more individual via features 190 .
- four via features 190 are included in each via feature set 185 .
- Second fill shape features 175 B are illustrated by dashed lines for clarification of the placement of vias 190 .
- Via features 190 are added to photomask 180 in addition to the normal via features for interconnecting first and second level wires.
- FIG. 6 is a partial cross-section view through 6 - 6 of FIG. 5 illustrating a second step in the fabrication of a semiconductor device according to the present invention.
- a third dielectric layer 195 is formed on a top surface 200 of second dielectric layer 135 .
- Formed in second dielectric layer 195 is a plurality of second fill shapes 205 and second fill shape/via combinations 210 formed by a dual damascene process.
- Second fill shapes 205 correspond to second fill shape features 175 A of second wiring level mask 165 and second fill shape/via combinations 210 correspond to second fill shape features 175 B of second wiring level photomask 165 in combination with via features 190 of first via level photomask 180 .
- Each second fill shape 205 and second fill shape/via combinations 210 are formed from a core conductor 215 and an optional liner 220 .
- Fill shapes 205 are embedded in second dielectric layer 195 .
- Second fill shape/via combinations 210 are in bonding (and electrical) contact with first fill shapes 160 .
- Materials for third dielectric layer 195 are the same as listed above for second dielectric layer 135 .
- Materials for core conductor 215 are the same as listed above for core conductor 150 .
- Materials for liner 220 are the same as listed above for liner 155 .
- Second fill shape/via combinations 210 are contact bonded to first dielectric layer 100 through first fill shapes 160 .
- Third dielectric layer 195 is locked between first fill shapes 160 and second fill shapes 175 B by vias 222 .
- This locking of third dielectric layer 195 imparts additional mechanical strength and rigidity to the third dielectric layer.
- the locking of third dielectric layer 195 also and reduces the effect of any thermal expansion mismatch between the third dielectric layer and metal features such as wires and fill shapes.
- third dielectric layer 195 is in effect spot fastened to second dielectric layer 135 , reducing the tendency to delamination of the two dielectric layers under thermal or mechanical stress.
- FIG. 7 is a partial top view of a third wiring level photomask used in the fabrication of the semiconductor device according to the present invention.
- FIG. 7 illustrates the same region of the semiconductor device as illustrated in FIGS. 2, 4 and 5 .
- third wiring level photomask 255 includes a third wire feature 230 and a plurality of third fill shape features 235 A and third fill shape features 235 B.
- Third wiring level photomask 255 is used in conjunction with a second via photomask to fabricate a third wiring level as illustrated in FIG. 9 and described below.
- the second via photomask is illustrated in FIG. 8 and described below.
- the difference between third fill shape features 235 A and third fill shape features 235 B is third fill shape features 235 B overlay second fill shape features 175 A or 175 B of second wiring level photomask 165 while third fill shape features 235 A do not.
- FIG. 8 is a partial top view of a second via level photomask used in the fabrication of the semiconductor device according to the present invention.
- FIG. 8 illustrates the same region of the semiconductor device as illustrated in FIGS. 2, 4, 5 and 7 .
- second via level photomask 240 includes a plurality of via feature sets 245 .
- Each via feature set 245 includes one or more individual via features 250 .
- four via features 250 are included in each via feature set 245 .
- Third fill shape features 235 B are illustrated by dashed lines for clarification of the placement of via features 250 .
- Via features 250 are added to photomask 240 in addition to the normal via features for interconnecting second and third level wires.
- FIG. 9 is a partial cross-section view through 9 - 9 of FIG. 8 illustrating a third step in the fabrication of a semiconductor device according to the present invention.
- a fourth dielectric layer 255 is formed on a top surface 260 of third dielectric layer 195 .
- Formed in third dielectric layer 255 is a plurality of third fill shape/via combinations 265 formed by a dual damascene process.
- Third fill shape/via combinations 265 correspond to third fill shape features 235 B of third wiring level photomask 225 in combination with via features 250 of second via level photomask 240 .
- Each third fill shape/via combination 265 is formed from a core conductor 270 and an optional liner 275 .
- Third fill shape/via combinations 265 are in bonding (and electrical) contact with second fill shapes 205 or second fill shape/via combinations 210 .
- Materials for fourth dielectric layer 255 are the same as listed above for second dielectric layer 135 .
- Materials for core conductor 270 are the same as listed above for core conductor 150 .
- Materials for liner 275 are the same as listed above for liner 155 .
- first fill shape/via stacks 280 third fill shape/via combinations 265 are contact bonded to first dielectric layer 100 through first fill shapes 160 and second fill shape/via combinations 210 .
- third fill shape/via combinations 265 are contact bonded to second fill shapes 205 .
- Fourth dielectric layer 255 is locked between third fill shapes 265 and second fill shapes 175 A and 175 B by vias 287 . This locking of fourth dielectric layer 255 imparts additional mechanical strength and rigidity to the fourth dielectric layer. The locking of fourth dielectric layer 255 also and reduces the effect of any thermal expansion mismatch between the fourth dielectric layer and metal features such as wires and fill shapes. Further, fourth dielectric layer 255 is in effect spot fastened to third dielectric layer 195 , reducing the possibility of delamination of the two dielectric layers under stress, either thermal or mechanical.
- the fill shape size and pitch has been the same on all the wiring levels so far described.
- the invention can also be applied between two wiring levels having different fill shape sizes and pitches. This is illustrated in FIGS. 10, 11 and 12 and described below.
- FIG. 10 is a partial top view of a fourth wiring level photomask used in the fabrication of the semiconductor device according to the present invention.
- FIG. 10 illustrates the same region of the semiconductor device as illustrated in FIGS. 2, 4 and 5 , 7 and 8 .
- fourth wiring level photomask 285 includes a fourth wire feature 290 and a plurality of fourth fill shape features 295 A and fourth fill shape features 295 B.
- Fourth wiring level photomask 285 is used in conjunction with a third via photomask to fabricate a fourth wiring level as illustrated in FIG. 12 and described below.
- the third via photomask is illustrated in FIG. 11 and described below.
- the difference between fourth fill shape features 295 A and fourth fill shape features 295 B is fourth fill shape features 295 B overlay third fill shape features 235 A or 235 B of third wiring level photomask 225 while fourth fill shape features 295 A do not.
- FIG. 11 is a partial top view of a third via level photomask used in the fabrication of the semiconductor device according to the present invention.
- FIG. 11 illustrates the same region of the semiconductor device as illustrated in FIGS. 2, 4, 5 , 7 , 8 and 10 .
- third via level photomask 300 includes a plurality of via features 305 .
- Third fill shape features 235 A and 235 B are illustrated by dashed lines for clarification of the placement of via features 305 .
- Via features 305 are added to photomask 300 in addition to the normal via features for interconnecting second and third level wires.
- FIG. 12 is a partial cross-section view through 12 - 12 of FIG. 11, illustrating a fourth step in the fabrication of a semiconductor device according to the present invention.
- a fifth dielectric layer 305 is formed on a top surface 310 of fourth dielectric layer 255 .
- Formed in fourth dielectric layer 305 is plurality of fourth fill shapes (one illustrated) 312 , a plurality of fourth fill shape/via combinations 315 (one illustrated) and a fourth conductive wire 320 , all formed by a dual damascene process.
- Fourth fill shape 310 corresponds to fill shape feature 295 A of fourth wiring level photomask 285 .
- Fill shape/via combinations 315 correspond to fourth fill shape features 235 B of fourth wiring level photomask 285 in combination with via features 305 of third via level photomask 300 .
- Each fourth fill shape 310 , fourth fill shape/via combinations 315 and fourth conductive wire 320 is formed from a core conductor 325 and an optional liner 330 .
- Fourth fill shape/via combinations 325 are in bonding (and electrical) contact with third fill shapes 235 A (not illustrated) or third fill shape/via combinations 235 B.
- Materials for fifth dielectric layer 305 are the same as listed above for second dielectric layer 135 .
- fifth dielectric layer 305 is the uppermost dielectric layer of the semiconductor device, it may be preferable for contamination reasons, that the dielectric layer comprise a rigid dielectric or comprise a lower layer of non-rigid dielectric and an upper layer of rigid dielectric such as a layer of silicon oxide or silicon nitride over SILKTM.
- Materials for core conductor 325 are the same as listed above for core conductor 150 .
- Materials for liner 330 are the same as listed above for liner 155 .
- fourth fill shape/via combination 315 is contact bonded to third fill shape/via combinations 265 .
- Fifth dielectric layer 305 is locked between fourth fill shapes 315 and third fill shapes 265 by via 335 .
- This locking of fifth dielectric layer 305 imparts additional mechanical strength and rigidity to the fifth dielectric layer.
- the locking of fifth dielectric layer 305 also and reduces the effect of any thermal expansion mismatch between the fifth dielectric layer and metal features such as wires and fill shapes.
- fifth dielectric layer 305 is in effect spot fastened to fourth dielectric layer 255 , reducing the possibility of delamination of the two dielectric layers under stress, either thermal or mechanical.
- FIGS. 13 through 16 are top view schematic diagrams illustrating alternative placement of via mask features relative to fill shape mask features according to the present invention.
- four via features 350 are placed between co-aligned upper and lower fill shape features 355 and 360 (indicated by dotted lines).
- Fill shape features 355 and 360 are “W1” wide by “W2” long.
- Each via feature 350 is “W3” wide by “W4” long and spaced a distance “W5” apart.
- two via features 350 are placed between co-aligned upper and lower fill shape features 355 and 360 (indicated by dotted lines). Via features 350 is located in opposite corners of fill shape 355 .
- Fill shape features 355 and 360 are “W1” wide by “W2” long.
- Each via feature 350 is “W3” wide by “W4” long and spaced a distance “W6” apart along diagonal line A-A.
- W1 “W2”
- W6 “W1”/3 where “W1” is about 0.05 micron to 2.0 microns.
- a single via feature 350 is placed between co-aligned upper and lower fill shape features 355 and 360 (indicated by dotted lines).
- Fill shape features 355 and 360 are “W1” wide by “W2” long.
- Via feature 350 is “W7” wide by “W8” long and approximately centered on fill shape features 355 and 360 .
- a single via feature 350 is placed between offset upper fill shape feature 360 and lower fill shape feature 355 (indicated by dotted lines).
- Fill shape features 355 and 360 are “W1” wide by “W2” long and overlap by distances “W9” and “W10.”
- via feature 350 is “W9” wide by “W10” long and corresponds in size to the overlap of upper fill shape feature 360 with lower fill level feature 355 .
- a via feature 350 A is “W11” wide by “W12” long where “W11” ⁇ “W10” and “W12” ⁇ “W10.”
- FIG. 17 is a flowchart illustrating the method of adding fill shape interconnecting vias to via masks according to the present invention.
- fill shapes are placed on all wiring levels of the device design. These are normal fill shapes, added to each metal level to compensate for CMP process attributes such as uneven polishing that occur when fill shapes are not used.
- the lowest wiring level is selected. The first wiring level is defined as the lowest wiring level.
- the selected wiring level is made the current wiring level.
- step 415 the wiring level immediately above the current level is selected. If the current wiring level is the first wiring level, then the second wiring level is selected. If the current wiring level is the second, then the third wiring level is selected.
- step 420 vertically aligned fill shape pairs are found.
- a fill shape pair consists of one fill shape form the current wiring level and one fill shape from the next immediately higher wiring level.
- step 425 a check for sufficient overlap between each fill shape pair is made.
- Vertical alignment may range from exact overlap (see FIGS. 13, 14 and 15 ) to a partial overlap (see FIG. 16) of the upper and lower fill shapes.
- the overlap In the case of a partial overlap, the overlap must be of at least a minimum predetermined amount. The amount of overlap must be sufficient to place one or more vias of a predetermined size and layout geometry into the via level design of the via level between two selected wiring levels containing the upper and lower fill shapes.
- step 430 vias are created and placed in the via level between the two selected wiring levels. These vias are in addition to the normal vias already existing in the via levels design and used to interconnect wires from adjacent wiring levels.
- step 435 it is determined if the current wiring level is the next to highest wiring level. If the current wiring level is the next to highest wiring level, the method terminates. If the current wiring level is not the next to highest wiring level, then in step 440 , the next higher (relative to the current wiring level) wiring level is selected and the method loops back to step 410 .
Abstract
Description
- The present invention relates to the field of semiconductor device design and fabrication; more specifically, it relates to a structure for structural reinforcement and support of interlevel dielectric layers and the method of fabricating said structure.
- The interconnect structure of semiconductor devices comprise layers (wiring levels) containing conductive wires separated by interlevel dielectric layers (levels.) The conductive wires are electrically isolated from one another by the dielectric layers. The conductive wires in each wiring level are interconnected by conductive vias extending from the conductive wires in one wiring level, through the interlevel dielectric layer, to the conductive wires in a second wiring level. In modern semiconductor devices, the conductive wires are partially embedded in or damascened into the dielectric layers.
- As the speed of modern semiconductor devices has increased, interlevel-wiring capacitance has become a problem. Methods were sought to reduce interlevel wiring capacitance. One solution that is becoming popular is the use of low-k dielectric materials such as SILK™ (a polyarylene ether manufactured by Dow Chemical, Midland, Mich.), spin on glass, polyimide or other polymers. These have replaced traditional dielectric materials such a silicon oxide and silicon nitride.
- A problem with low-k dielectric materials is they are not rigid like the traditional dielectric materials. Low-k materials are soft, compressible and flexible, have a low modulus and poor interfacial strength, i.e., they tend to delaminate or collapse under mechanical and thermal stress resulting in low yield, poor reliability and higher costs.
- Some low-k materials are brittle and tend to crack under mechanical or thermal stress. There use in semiconductor devices present two problems. First, because the conductive wires are comprised of metals (such as copper and tungsten) there is a mismatch in thermal expansion between low-k dielectrics and the metal which can lead to delamination, cracking or collapse of the low-k material during manufacture or in use in the field. Second, since the wires are formed by damascene process, which process includes a chemical-mechanical-polish (CMP) step, mechanical stress is induced into the device during CMP, which can lead to delamination, cracking or collapse.
- Since low-k dielectric materials, damascene wiring levels, and CMP are basic to the fabrication of high performance semiconductor devices, a method for reducing or eliminating stress induced delamination, cracking or collapse of low-k dielectric layers is highly desirable.
- A first aspect of the present invention is a semiconductor device comprising: a first wiring level having a first conductive fill shape embedded in a first dielectric; a second wiring level having a second conductive fill shape embedded in a second dielectric; and a conductive via extending between and joining the first and second conductive fill shapes.
- A second aspect of the present invention is a semiconductor device comprising: a multiplicity of wiring levels, each wiring level comprising conductive wires and a multiplicity of conductive fill shapes embedded in a dielectric; at least some of the fill shapes in at least two adjacent wiring levels being co-aligned; and where the fill shapes on adjacent levels are aligned, one or more conductive vias extending between and joining each co-aligned fill shape in each adjacent wiring level. A third aspect of the present invention is a semiconductor device comprising:
- a first wiring level, the first wiring level comprising a conductive wires and a multiplicity of conductive fill shapes embedded in a first dielectric material; a multiplicity of higher wiring levels, each higher wiring level comprising conductive wires and a multiplicity of conductive fill shapes embedded in a second dielectric material; at least some of the fill shapes in one or more pairs of adjacent wiring levels being co-aligned; and where the fill shapes on adjacent levels are aligned, one or more conductive vias extending between and joining each co-aligned fill shape in each pair of adjacent wiring levels.
- A fourth aspect of the present invention is a semiconductor device comprising: a first wiring level having a first conductive fill shape having corners, embedded in a first dielectric; a second wiring level having a second conductive fill shape having corners, embedded in a second dielectric, the second conductive fill shape co-aligned with the first fill shape; and a conductive via aligned with each corner of the first and second fill shapes and extending between and joining the first and second conductive fill shapes.
- A fifth aspect of the present invention is a semiconductor device comprising: a first wiring level having a first conductive fill shape having corners, embedded in a first dielectric; a second wiring level having a second conductive fill shape having corners, embedded in a second dielectric, the second conductive fill shape co-aligned with the first fill shape; and at least two conductive vias each aligned with a corner of the first and second fill shapes and extending between and joining the first and second conductive fill shapes.
- A sixth aspect of the present invention is a method of fabricating a semiconductor device, comprising: providing a substrate; forming on the substrate, a multiplicity of wiring levels, each wiring level comprising conductive wires and a multiplicity of conductive fill shapes embedded in a dielectric; at least some of the fill shapes in at least two adjacent wiring levels being co-aligned; and where the fill shapes on adjacent levels are aligned, forming one or more conductive vias extending between and joining each co-aligned fill shape in each adjacent wiring level.
- A seventh aspect of the present invention is a method of fabricating a semiconductor device, comprising: providing a substrate; forming a first wiring level on the substrate, the first wiring level comprising a conductive wires and a multiplicity of conductive fill shapes embedded in a first dielectric material; forming a multiplicity of higher wiring levels on the first wiring level, each higher wiring level comprising conductive wires and a multiplicity of conductive fill shapes embedded in a second dielectric material; at least some of the fill shapes in one or more pairs of adjacent wiring levels being co-aligned; and where the fill shapes on adjacent levels are aligned, forming one or more conductive vias extending between and joining each co-aligned fill shape in each pair of adjacent wiring levels.
- An eighth aspect of the present invention is a method of designing a semiconductor device having wiring levels containing wires and fill shapes interspersed with interconnecting via levels containing vias, comprising: selecting a pair of adjacent wiring levels; finding pairs of vertically aligned fill shapes in the adjacent wiring levels; and creating and placing, in the interconnecting via levels between the adjacent wiring levels, one or more vias to interconnect the pairs of fill shapes.
- A ninth aspect of the present invention is A method of designing a semiconductor device having wiring levels interspersed with interconnecting via levels, comprising: placing fill shapes at least some of the wiring levels; selecting a pair of adjacent wiring levels; finding pairs of vertically aligned fill shapes in the adjacent wiring levels; and creating and placing, in the interconnecting via levels between the adjacent wiring levels, one or more vias to interconnect the pairs of fill shapes.
- The features of the invention are set forth in the appended claims. The invention itself, however, will be best understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein:
- FIGS. 1, 3,3A, 6, 9 and 12 are partial cross-section views illustrating fabrication of a semiconductor device according to the present invention;
- FIGS. 2, 4,5, 7, 8 10 and 11 are partial top views of wiring and via photomasks used in the fabrication of the semiconductor device according to the present invention;
- FIGS. 13 through 16 are top view schematic diagrams illustrating alternative placement of via mask features relative to fill shape mask features according to the present invention; and
- FIG. 17 is a flowchart illustrating the method of adding fill shape interconnecting vias to via masks according to the present invention.
- FIG. 1 is a partial cross-section view illustrating the initial structure of the fabrication of a semiconductor device according to the present invention. In FIG. 1, a first
dielectric layer 100 is formed on asilicon substrate 105. Formed intrench 110 in first dielectric layer is aconductive contact 115.Silicon substrate 105 may include active devices such as transistors and diodes and inactive devices such as resistors and capacitors. First dielectric layer is preferably, but not necessarily, a rigid (high modulus) dielectric layer. Examples of rigid dielectrics include silicon oxide, silicon nitride, diamond or fluorine doped silicon or combinations of layers thereof. It is preferred that firstdielectric layer 100 be a rigid dielectric in order to anchor firmly tosilicon substrate 105 the subsequent stack of vias and fill shapes that will be fabricated according to the present invention. Fill shapes are added to wiring levels in order to increase the uniformity of CMP processes. The present invention utilizes pre-existing fill shapes added to the design for CMP purposes, joined by vias, to tie dielectric layers together. If first dielectric layer is, a non-rigid dielectric (low modulus) or low-k dielectric (k<3.5) the present invention will still provide the benefit of tying dielectric layers together. Examples of non-rigid dielectrics or low-k dielectric include spin on glass, porous silicon oxide, polyimide, polyimide siloxane, polysilsequioxane polymer, benzocyclobutene, paralyene N, paralyene F, polyolefin, poly-naphthalene, amorphous Teflon, SILK™ (Dow Chemical, Midland, Mich.), black diamond (Applied Materials, Santa Clara, Calif.), polymer foam or aerogel or layers thereof. - In the present example,
conductive contact 110 is formed by a single damascene process. A single damascene process will now be defined. In a single damascene process, first a trench is formed in a dielectric layer, for example by reactive ion etching (RIE). Next, an optional conductive conformal liner is deposited coating the top surface of the dielectric and the sidewalls and bottom of the trench. Then a core conductor is deposited to completely fill the trench as well as coating the top surface of the dielectric layer. - Finally, a CMP process performed to remove all conductive material from the top surface of the dielectric layer and polish the top of surface of the conductor filled trench even with the top surface of the dielectric layer.
- In one example,
conductive contact 115 comprises tungsten, aluminum, aluminum-copper, aluminum-copper-silicon or copper and may include a liner formed on the sidewalls and bottom oftrench 110. The liner may be formed from tantalum, tantalum nitride, titanium, titanium nitride, a titanium-tungsten alloy or layers thereof. - FIG. 2 is a partial top view of a first wiring level photomask used in the fabrication of the semiconductor device according to the present invention. In FIG. 2, first
wiring level photomask 120 includes afirst wire feature 125 and a plurality of firstfill shape features 130. Firstwiring level photomask 120 is used to fabricate a first wiring level as illustrated in FIG. 3 and described below. - Fill Shapes
- FIG. 3 is a partial cross-section view through3-3 of FIG. 2 illustrating a first step in the fabrication of a semiconductor device according to the present invention. In FIG. 3, a second
dielectric layer 135 is formed on atop surface 140 of firstdielectric layer 100. A first conductive wire 145 (corresponding tofirst wire feature 125 of mask of first photomask 120) comprising acore conductor 150 and anoptional liner 155 is formed in seconddielectric layer 135. Also formed in seconddielectric layer 135 is a plurality of first fill shapes 160 (corresponding to first fill shape features 130 of firstwiring level photomask 120.) A single damascene process is used to form firstconductive wire 145 andfirst fill shapes 160. Eachfill shape 160 is formed fromcore conductor 150 andoptional liner 155. Firstconductive wire 145, and first fill shapes 160 are formed insecond dielectric 135 usingphotomask 120 and a single damascene process. Fill shapes 160 are in contact withtop surface 140 of firstdielectric layer 100. First conductive wire is electrical contact withconductive contact 115.Liner 155, among other purposes, by selection of material combinations, serves to improve adhesion ofcore conductor 150 to firstdielectric layer 100. -
Second dielectric layer 135 is preferably a non-rigid dielectric layer (or a dielectric with a coefficient of expansion greater than the metal used for wiring). In one example,second dielectric layer 135 is spin on glass, porous silicon oxide, polyimide, polyimide siloxane, polysilsequioxane polymer, benzocyclobutene, paralyene N, paralyene F, polyolefin, poly-naphthalene, amorphous Teflon, SILK™ (Dow Chemical, Midland, Mich.), black diamond (Applied Materials, Santa Clara, Calif.), polymer foam or aerogel or layers thereof. While rigid dielectrics may not benefit as greatly from the present invention,second dielectric layer 135 may be a rigid dielectric. In a second example,second dielectric layer 135 is silicon oxide, silicon nitride, diamond or fluorine doped silicon or combinations of layers thereof.Second dielectric layer 135 may also be formed from a combination of rigid and non-rigid dielectrics, an example of which would be a thin layer of silicon nitride over a thicker layer of SILK™ (Dow Chemical, Midland, Mich.). - In one example,
core conductor 150 comprises tungsten, aluminum, aluminum-copper, aluminum-copper-silicon or copper and may include aliner 155 formed on the sidewalls and bottom oftrench 110. In one example,liner 155 comprises tantalum, tantalum nitride, titanium, titanium nitride, a titanium-tungsten alloy or layers thereof. - While first
conductive wire 145 and first fill shapes 160 have been described as being formed insecond dielectric 135 using a single damascene process, a dual damascene process may just as easily be used. However, since fill shapes 160 should be in bonding contact with firstdielectric layer 100, the present invention would then require forming vias under eachfirst fill shape 160, the vias in contact with and providing the bonding contact to the first dielectric layer. This is illustrated in FIG. 3A. The significant difference between FIG. 3 and FIG. 3A, is the presence ofvias 162 between first fill shapes 160 andtop surface 140 of firstdielectric layer 100. A dual damascene process will now be defined. - In a dual damascene process, first a trench is formed in a dielectric layer (using a first photomask) for example by RIE. The trench is formed to a depth less than the total thickness of the dielectric layer. This step defines the wires and fill shapes. Then vias are formed in the bottom of the trench (using a second photomask) through to the underlying material, again by RIE. This step defines the interconnections between wiring levels. Next, an optional conductive conformal liner is deposited coating the top surface of the dielectric and the sidewalls and bottom of the trench, via sidewalls and the underlying layer exposed at the bottom of the vias. Then a core conductor is deposited to completely fill the trench as well as coating the top surface of the dielectric layer. Finally, a CMP process performed to remove all conductive material from the top surface of the dielectric layer and polish the top of surface of the conductor filled trench even with the top surface of the dielectric layer. The vias are integral with the wires and fill shapes in a dual damascene process.
- FIG. 4 is a partial top view of a second wiring level photomask used in the fabrication of the semiconductor device according to the present invention. FIG. 4 illustrates the same region of the semiconductor device as illustrated in FIG. 2. In FIG. 4, second
wiring level photomask 165 includes asecond wire feature 170 and a plurality of second fill shape features 175A and second fill shape features 175B. Secondwiring level photomask 165 is used in conjunction with a first via photomask to fabricate a second wiring level as illustrated in FIG. 6 and described below. The first via photomask is illustrated in FIG. 5 and described below. The difference between second fill shape features 175A and second fill shape features 175B is second fill shape features 175B overlay first fill shape features 130 of firstwiring level photomask 120 while second fill shape features 175A do not. - FIG. 5 is a partial top view of a first via level photomask used in the fabrication of the semiconductor device according to the present invention. FIG. 5 illustrates the same region of the semiconductor device as illustrated in FIGS. 2 and 4. In FIG. 5, first via
level photomask 180 includes a plurality of via feature sets 185. Each via feature set 185 includes one or more individual via features 190. In the present example, four viafeatures 190 are included in each viafeature set 185. Second fill shape features 175B are illustrated by dashed lines for clarification of the placement ofvias 190. Via features 190 are added tophotomask 180 in addition to the normal via features for interconnecting first and second level wires. - FIG. 6 is a partial cross-section view through6-6 of FIG. 5 illustrating a second step in the fabrication of a semiconductor device according to the present invention. In FIG. 6, a third
dielectric layer 195 is formed on atop surface 200 of seconddielectric layer 135. Formed in seconddielectric layer 195 is a plurality of second fill shapes 205 and second fill shape/viacombinations 210 formed by a dual damascene process. - Second fill shapes205 correspond to second
fill shape features 175A of secondwiring level mask 165 and second fill shape/viacombinations 210 correspond to second fill shape features 175B of secondwiring level photomask 165 in combination with viafeatures 190 of first vialevel photomask 180. - Each
second fill shape 205 and second fill shape/viacombinations 210 are formed from acore conductor 215 and anoptional liner 220. Fill shapes 205 are embedded in seconddielectric layer 195. Second fill shape/viacombinations 210 are in bonding (and electrical) contact with first fill shapes 160. Materials for thirddielectric layer 195 are the same as listed above for seconddielectric layer 135. Materials forcore conductor 215 are the same as listed above forcore conductor 150. Materials forliner 220 are the same as listed above forliner 155. - Second fill shape/via
combinations 210 are contact bonded to firstdielectric layer 100 through first fill shapes 160.Third dielectric layer 195 is locked between first fill shapes 160 and second fill shapes 175B byvias 222. This locking of thirddielectric layer 195 imparts additional mechanical strength and rigidity to the third dielectric layer. The locking of thirddielectric layer 195 also and reduces the effect of any thermal expansion mismatch between the third dielectric layer and metal features such as wires and fill shapes. Further, thirddielectric layer 195 is in effect spot fastened to seconddielectric layer 135, reducing the tendency to delamination of the two dielectric layers under thermal or mechanical stress. - FIG. 7 is a partial top view of a third wiring level photomask used in the fabrication of the semiconductor device according to the present invention. FIG. 7 illustrates the same region of the semiconductor device as illustrated in FIGS. 2, 4 and5. In FIG. 7, third
wiring level photomask 255 includes athird wire feature 230 and a plurality of third fill shape features 235A and third fill shape features 235B. Thirdwiring level photomask 255 is used in conjunction with a second via photomask to fabricate a third wiring level as illustrated in FIG. 9 and described below. The second via photomask is illustrated in FIG. 8 and described below. The difference between third fill shape features 235A and third fill shape features 235B is third fill shape features 235B overlay secondfill shape features wiring level photomask 165 while third fill shape features 235A do not. - FIG. 8 is a partial top view of a second via level photomask used in the fabrication of the semiconductor device according to the present invention. FIG. 8 illustrates the same region of the semiconductor device as illustrated in FIGS. 2, 4,5 and 7. In FIG. 8, second via
level photomask 240 includes a plurality of via feature sets 245. Each via feature set 245 includes one or more individual via features 250. In the present example, four viafeatures 250 are included in each viafeature set 245. Third fill shape features 235B are illustrated by dashed lines for clarification of the placement of via features 250. Via features 250 are added tophotomask 240 in addition to the normal via features for interconnecting second and third level wires. - FIG. 9 is a partial cross-section view through9-9 of FIG. 8 illustrating a third step in the fabrication of a semiconductor device according to the present invention. In FIG. 9, a fourth
dielectric layer 255 is formed on atop surface 260 of thirddielectric layer 195. Formed in thirddielectric layer 255 is a plurality of third fill shape/viacombinations 265 formed by a dual damascene process. - Third fill shape/via
combinations 265 correspond to third fill shape features 235B of thirdwiring level photomask 225 in combination with viafeatures 250 of second vialevel photomask 240. - Each third fill shape/via
combination 265 is formed from acore conductor 270 and anoptional liner 275. Third fill shape/viacombinations 265 are in bonding (and electrical) contact with second fill shapes 205 or second fill shape/viacombinations 210. Materials for fourthdielectric layer 255 are the same as listed above for seconddielectric layer 135. Materials forcore conductor 270 are the same as listed above forcore conductor 150. Materials forliner 275 are the same as listed above forliner 155. - In first fill shape/via
stacks 280, third fill shape/viacombinations 265 are contact bonded to firstdielectric layer 100 through first fill shapes 160 and second fill shape/viacombinations 210. In a second fill shape/viastack 285, third fill shape/viacombinations 265 are contact bonded to second fill shapes 205.Fourth dielectric layer 255 is locked between third fill shapes 265 and second fill shapes 175A and 175B byvias 287. This locking of fourthdielectric layer 255 imparts additional mechanical strength and rigidity to the fourth dielectric layer. The locking of fourthdielectric layer 255 also and reduces the effect of any thermal expansion mismatch between the fourth dielectric layer and metal features such as wires and fill shapes. Further, fourthdielectric layer 255 is in effect spot fastened to thirddielectric layer 195, reducing the possibility of delamination of the two dielectric layers under stress, either thermal or mechanical. - The fill shape size and pitch has been the same on all the wiring levels so far described. The invention can also be applied between two wiring levels having different fill shape sizes and pitches. This is illustrated in FIGS. 10, 11 and12 and described below.
- FIG. 10 is a partial top view of a fourth wiring level photomask used in the fabrication of the semiconductor device according to the present invention. FIG. 10 illustrates the same region of the semiconductor device as illustrated in FIGS. 2, 4 and5, 7 and 8. In FIG. 10, fourth
wiring level photomask 285 includes afourth wire feature 290 and a plurality of fourth fill shape features 295A and fourth fill shape features 295B. Fourthwiring level photomask 285 is used in conjunction with a third via photomask to fabricate a fourth wiring level as illustrated in FIG. 12 and described below. The third via photomask is illustrated in FIG. 11 and described below. The difference between fourth fill shape features 295A and fourth fill shape features 295B is fourth fill shape features 295B overlay thirdfill shape features wiring level photomask 225 while fourth fill shape features 295A do not. - FIG. 11 is a partial top view of a third via level photomask used in the fabrication of the semiconductor device according to the present invention. FIG. 11 illustrates the same region of the semiconductor device as illustrated in FIGS. 2, 4,5, 7, 8 and 10. In FIG. 11, third via
level photomask 300 includes a plurality of via features 305. Third fill shape features 235A and 235B are illustrated by dashed lines for clarification of the placement of via features 305. Via features 305 are added tophotomask 300 in addition to the normal via features for interconnecting second and third level wires. - FIG. 12 is a partial cross-section view through12-12 of FIG. 11, illustrating a fourth step in the fabrication of a semiconductor device according to the present invention. In FIG. 12, a fifth
dielectric layer 305 is formed on atop surface 310 of fourthdielectric layer 255. Formed in fourthdielectric layer 305 is plurality of fourth fill shapes (one illustrated) 312, a plurality of fourth fill shape/via combinations 315 (one illustrated) and a fourthconductive wire 320, all formed by a dual damascene process. -
Fourth fill shape 310 corresponds to fillshape feature 295A of fourthwiring level photomask 285. Fill shape/viacombinations 315 correspond to fourth fill shape features 235B of fourthwiring level photomask 285 in combination with viafeatures 305 of third vialevel photomask 300. - Each
fourth fill shape 310, fourth fill shape/viacombinations 315 and fourthconductive wire 320 is formed from acore conductor 325 and anoptional liner 330. Fourth fill shape/viacombinations 325 are in bonding (and electrical) contact with third fill shapes 235A (not illustrated) or third fill shape/viacombinations 235B. Materials for fifthdielectric layer 305 are the same as listed above for seconddielectric layer 135. However, if fifthdielectric layer 305 is the uppermost dielectric layer of the semiconductor device, it may be preferable for contamination reasons, that the dielectric layer comprise a rigid dielectric or comprise a lower layer of non-rigid dielectric and an upper layer of rigid dielectric such as a layer of silicon oxide or silicon nitride over SILK™. Materials forcore conductor 325 are the same as listed above forcore conductor 150. Materials forliner 330 are the same as listed above forliner 155. - In FIG. 12, fourth fill shape/via
combination 315 is contact bonded to third fill shape/viacombinations 265.Fifth dielectric layer 305 is locked between fourth fill shapes 315 and third fill shapes 265 by via 335. This locking of fifthdielectric layer 305 imparts additional mechanical strength and rigidity to the fifth dielectric layer. The locking of fifthdielectric layer 305 also and reduces the effect of any thermal expansion mismatch between the fifth dielectric layer and metal features such as wires and fill shapes. Further, fifthdielectric layer 305 is in effect spot fastened to fourthdielectric layer 255, reducing the possibility of delamination of the two dielectric layers under stress, either thermal or mechanical. - FIGS. 13 through 16 are top view schematic diagrams illustrating alternative placement of via mask features relative to fill shape mask features according to the present invention. In FIG. 13, four via
features 350 are placed between co-aligned upper and lower fill shape features 355 and 360 (indicated by dotted lines). Fill shape features 355 and 360 are “W1” wide by “W2” long. Each viafeature 350 is “W3” wide by “W4” long and spaced a distance “W5” apart. In one example “W1”=“W2” and “W3”=“W4”=“W5” where “W1” is about 0.05 micron to 2.0 microns. - In FIG. 14, two via
features 350 are placed between co-aligned upper and lower fill shape features 355 and 360 (indicated by dotted lines). Via features 350 is located in opposite corners offill shape 355. Fill shape features 355 and 360 are “W1” wide by “W2” long. Each viafeature 350 is “W3” wide by “W4” long and spaced a distance “W6” apart along diagonal line A-A. In one example “W1”=“W2,” “W3”=“W4”=“W6” and “W6”=“W1”/3 where “W1” is about 0.05 micron to 2.0 microns. - In FIG. 15, a single via
feature 350 is placed between co-aligned upper and lower fill shape features 355 and 360 (indicated by dotted lines). Fill shape features 355 and 360 are “W1” wide by “W2” long. Viafeature 350 is “W7” wide by “W8” long and approximately centered on fill shape features 355 and 360. In one example “W1”=“W2”,“W7”=“W8” and “W6”=“W1”/3 where “W1” is about 0.05 micron to 2.0 microns and “W7” is about 0.05 micron to 2.0 but not larger than “W1.” - In FIG. 16, a single via
feature 350 is placed between offset upperfill shape feature 360 and lower fill shape feature 355 (indicated by dotted lines). Fill shape features 355 and 360 are “W1” wide by “W2” long and overlap by distances “W9” and “W10.” In a first example, viafeature 350 is “W9” wide by “W10” long and corresponds in size to the overlap of upper fill shape feature 360 with lowerfill level feature 355. “W1”=“W2”,“W9”=“W10” where “W1” is about 0.05 micron to 2.0 microns and “W9” is about 0.05 micron to 2.0 but not larger than “W1.” In a second example, a via feature 350A is “W11” wide by “W12” long where “W11”<“W10” and “W12”<“W10.” - FIG. 17 is a flowchart illustrating the method of adding fill shape interconnecting vias to via masks according to the present invention. In
step 400, fill shapes are placed on all wiring levels of the device design. These are normal fill shapes, added to each metal level to compensate for CMP process attributes such as uneven polishing that occur when fill shapes are not used. Instep 405, the lowest wiring level is selected. The first wiring level is defined as the lowest wiring level. Instep 410, the selected wiring level is made the current wiring level. Instep 415, the wiring level immediately above the current level is selected. If the current wiring level is the first wiring level, then the second wiring level is selected. If the current wiring level is the second, then the third wiring level is selected. Instep 420, vertically aligned fill shape pairs are found. A fill shape pair consists of one fill shape form the current wiring level and one fill shape from the next immediately higher wiring level. Instep 425, a check for sufficient overlap between each fill shape pair is made. Vertical alignment may range from exact overlap (see FIGS. 13, 14 and 15) to a partial overlap (see FIG. 16) of the upper and lower fill shapes. In the case of a partial overlap, the overlap must be of at least a minimum predetermined amount. The amount of overlap must be sufficient to place one or more vias of a predetermined size and layout geometry into the via level design of the via level between two selected wiring levels containing the upper and lower fill shapes. Instep 430, vias are created and placed in the via level between the two selected wiring levels. These vias are in addition to the normal vias already existing in the via levels design and used to interconnect wires from adjacent wiring levels. Instep 435, it is determined if the current wiring level is the next to highest wiring level. If the current wiring level is the next to highest wiring level, the method terminates. If the current wiring level is not the next to highest wiring level, then instep 440, the next higher (relative to the current wiring level) wiring level is selected and the method loops back tostep 410. - The description of the embodiments of the present invention is given above for the understanding of the present invention. It will be understood that the invention is not to the particular embodiments described herein, but is capable of various modifications, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, it is intended that the following claims cover all such modifications and changes as fall within the true spirit and scope of the invention.
Claims (36)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/991,769 US6559543B1 (en) | 2001-11-16 | 2001-11-16 | Stacked fill structures for support of dielectric layers |
US10/345,441 US6743710B2 (en) | 2001-11-16 | 2003-01-15 | Stacked fill structures for support of dielectric layers |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/991,769 US6559543B1 (en) | 2001-11-16 | 2001-11-16 | Stacked fill structures for support of dielectric layers |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/345,441 Division US6743710B2 (en) | 2001-11-16 | 2003-01-15 | Stacked fill structures for support of dielectric layers |
Publications (2)
Publication Number | Publication Date |
---|---|
US6559543B1 US6559543B1 (en) | 2003-05-06 |
US20030094696A1 true US20030094696A1 (en) | 2003-05-22 |
Family
ID=25537538
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/991,769 Expired - Lifetime US6559543B1 (en) | 2001-11-16 | 2001-11-16 | Stacked fill structures for support of dielectric layers |
US10/345,441 Expired - Lifetime US6743710B2 (en) | 2001-11-16 | 2003-01-15 | Stacked fill structures for support of dielectric layers |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/345,441 Expired - Lifetime US6743710B2 (en) | 2001-11-16 | 2003-01-15 | Stacked fill structures for support of dielectric layers |
Country Status (1)
Country | Link |
---|---|
US (2) | US6559543B1 (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050032356A1 (en) * | 2003-06-04 | 2005-02-10 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
US20050255650A1 (en) * | 2002-09-03 | 2005-11-17 | Kabushiki Kaisha Toshiba | Semiconductor device |
US20060118960A1 (en) * | 2003-04-01 | 2006-06-08 | International Business Machines Corporation | Dummy metal fill shapes for improved reliability of hybrid oxide/low-k dielectrics |
US20070284748A1 (en) * | 2006-06-08 | 2007-12-13 | Advanced Micro Devices, Inc. | Copper interconnects with improved electromigration lifetime |
US20120313256A1 (en) * | 2011-06-10 | 2012-12-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Non-Hierarchical Metal Layers for Integrated Circuits |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7180187B2 (en) * | 2004-06-22 | 2007-02-20 | International Business Machines Corporation | Interlayer connector for preventing delamination of semiconductor device |
US7287325B2 (en) * | 2005-05-10 | 2007-10-30 | International Business Machines Corporation | Method of forming interconnect structure or interconnect and via structures using post chemical mechanical polishing |
JP4550678B2 (en) * | 2005-07-07 | 2010-09-22 | 株式会社東芝 | Semiconductor device |
US7473636B2 (en) * | 2006-01-12 | 2009-01-06 | International Business Machines Corporation | Method to improve time dependent dielectric breakdown |
JP4828451B2 (en) * | 2006-03-27 | 2011-11-30 | 東京エレクトロン株式会社 | Substrate processing method, semiconductor device manufacturing method, and substrate processing apparatus |
US8110906B2 (en) * | 2007-01-23 | 2012-02-07 | Infineon Technologies Ag | Semiconductor device including isolation layer |
US7923823B2 (en) * | 2007-01-23 | 2011-04-12 | Infineon Technologies Ag | Semiconductor device with parylene coating |
US8138607B2 (en) * | 2009-04-15 | 2012-03-20 | International Business Machines Corporation | Metal fill structures for reducing parasitic capacitance |
US9666514B2 (en) * | 2015-04-14 | 2017-05-30 | Invensas Corporation | High performance compliant substrate |
IT201700053902A1 (en) * | 2017-05-18 | 2018-11-18 | Lfoundry Srl | HYBRID BONDING METHOD FOR WAFER WITH SEMICONDUCTOR AND ITS INTEGRATED THREE-DIMENSIONAL DEVICE |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5278105A (en) | 1992-08-19 | 1994-01-11 | Intel Corporation | Semiconductor device with dummy features in active layers |
US5869880A (en) | 1995-12-29 | 1999-02-09 | International Business Machines Corporation | Structure and fabrication method for stackable, air-gap-containing low epsilon dielectric layers |
US5886410A (en) * | 1996-06-26 | 1999-03-23 | Intel Corporation | Interconnect structure with hard mask and low dielectric constant materials |
US6100184A (en) * | 1997-08-20 | 2000-08-08 | Sematech, Inc. | Method of making a dual damascene interconnect structure using low dielectric constant material for an inter-level dielectric layer |
US6072690A (en) | 1998-01-15 | 2000-06-06 | International Business Machines Corporation | High k dielectric capacitor with low k sheathed signal vias |
JP3469771B2 (en) * | 1998-03-24 | 2003-11-25 | 富士通株式会社 | Semiconductor device and manufacturing method thereof |
JPH11340321A (en) * | 1998-05-27 | 1999-12-10 | Sony Corp | Semiconductor device and its manufacture |
JP3080071B2 (en) * | 1998-06-12 | 2000-08-21 | 日本電気株式会社 | Semiconductor device and manufacturing method thereof |
JP4425432B2 (en) * | 2000-06-20 | 2010-03-03 | Necエレクトロニクス株式会社 | Manufacturing method of semiconductor device |
-
2001
- 2001-11-16 US US09/991,769 patent/US6559543B1/en not_active Expired - Lifetime
-
2003
- 2003-01-15 US US10/345,441 patent/US6743710B2/en not_active Expired - Lifetime
Cited By (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050255650A1 (en) * | 2002-09-03 | 2005-11-17 | Kabushiki Kaisha Toshiba | Semiconductor device |
US7180192B2 (en) * | 2002-09-03 | 2007-02-20 | Kabushiki Kaisha Toshiba | Semiconductor device |
US20060118960A1 (en) * | 2003-04-01 | 2006-06-08 | International Business Machines Corporation | Dummy metal fill shapes for improved reliability of hybrid oxide/low-k dielectrics |
US7479701B2 (en) * | 2003-04-01 | 2009-01-20 | International Business Machines Corporation | Dummy metal fill shapes for improved reliability of hybrid oxide/low-k dielectrics |
US20090032956A1 (en) * | 2003-04-01 | 2009-02-05 | International Business Machines Corporation | Dummy metal fill shapes for improved reliability of hybrid oxide/low-k dielectrics |
US7888800B2 (en) | 2003-04-01 | 2011-02-15 | International Business Machines Corporation | Dummy metal fill shapes for improved reliability of hybrid oxide/low-k dielectrics |
US20050032356A1 (en) * | 2003-06-04 | 2005-02-10 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
US20070284748A1 (en) * | 2006-06-08 | 2007-12-13 | Advanced Micro Devices, Inc. | Copper interconnects with improved electromigration lifetime |
US8723321B2 (en) * | 2006-06-08 | 2014-05-13 | GLOBALFOUNDIES Inc. | Copper interconnects with improved electromigration lifetime |
US20120313256A1 (en) * | 2011-06-10 | 2012-12-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Non-Hierarchical Metal Layers for Integrated Circuits |
US9117882B2 (en) * | 2011-06-10 | 2015-08-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Non-hierarchical metal layers for integrated circuits |
US9543193B2 (en) | 2011-06-10 | 2017-01-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Non-hierarchical metal layers for integrated circuits |
Also Published As
Publication number | Publication date |
---|---|
US6559543B1 (en) | 2003-05-06 |
US20030141598A1 (en) | 2003-07-31 |
US6743710B2 (en) | 2004-06-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6650010B2 (en) | Unique feature design enabling structural integrity for advanced low K semiconductor chips | |
US7250681B2 (en) | Semiconductor device and a method of manufacturing the semiconductor device | |
US6743710B2 (en) | Stacked fill structures for support of dielectric layers | |
US7397125B2 (en) | Semiconductor device with bonding pad support structure | |
US7888800B2 (en) | Dummy metal fill shapes for improved reliability of hybrid oxide/low-k dielectrics | |
US6908841B2 (en) | Support structures for wirebond regions of contact pads over low modulus materials | |
US6972209B2 (en) | Stacked via-stud with improved reliability in copper metallurgy | |
US7470613B2 (en) | Dual damascene multi-level metallization | |
US7144804B2 (en) | Semiconductor device and method of manufacturing the same | |
US20040222533A1 (en) | Semiconductor device and method of manufacturing the same | |
US7642658B2 (en) | Pad structure to prompt excellent bondability for low-k intermetal dielectric layers | |
JP2000150429A (en) | Semiconductor device and its manufacture | |
US9490207B2 (en) | Semiconductor device having a copper wire within an interlayer dielectric film | |
US20020068385A1 (en) | Method for forming anchored bond pads in semiconductor devices and devices formed | |
US6566244B1 (en) | Process for improving mechanical strength of layers of low k dielectric material | |
JPH08195437A (en) | Flattening structure for reducing line capacity |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, NEW Y Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:DUNHAM, TIMOTHY G.;LANDIS, HOWARD S.;MOTSIFF, WILLIAM T.;REEL/FRAME:012325/0675;SIGNING DATES FROM 20010703 TO 20010709 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
FPAY | Fee payment |
Year of fee payment: 8 |
|
FPAY | Fee payment |
Year of fee payment: 12 |
|
AS | Assignment |
Owner name: GLOBALFOUNDRIES U.S. 2 LLC, NEW YORK Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INTERNATIONAL BUSINESS MACHINES CORPORATION;REEL/FRAME:036550/0001 Effective date: 20150629 |
|
AS | Assignment |
Owner name: GLOBALFOUNDRIES INC., CAYMAN ISLANDS Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:GLOBALFOUNDRIES U.S. 2 LLC;GLOBALFOUNDRIES U.S. INC.;REEL/FRAME:036779/0001 Effective date: 20150910 |
|
AS | Assignment |
Owner name: AURIGA INNOVATIONS, INC., CANADA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:GLOBALFOUNDRIES INC.;REEL/FRAME:041741/0358 Effective date: 20161207 |