Search Images Maps Play YouTube News Gmail Drive More »
Sign in
Screen reader users: click this link for accessible mode. Accessible mode has the same essential features but works better with your reader.

Patents

  1. Advanced Patent Search
Publication numberUS20030095453 A1
Publication typeApplication
Application numberUS 10/299,965
Publication dateMay 22, 2003
Filing dateNov 19, 2002
Priority dateNov 20, 2001
Also published asUS6760265
Publication number10299965, 299965, US 2003/0095453 A1, US 2003/095453 A1, US 20030095453 A1, US 20030095453A1, US 2003095453 A1, US 2003095453A1, US-A1-20030095453, US-A1-2003095453, US2003/0095453A1, US2003/095453A1, US20030095453 A1, US20030095453A1, US2003095453 A1, US2003095453A1
InventorsFrancesco La Rosa
Original AssigneeStmicroelectronics S.A.
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Read amplifier with a low current consumption differential output stage
US 20030095453 A1
Abstract
The present invention relates to a read amplifier (SA2) comprising a read stage (RDST), a reference stage (RFST) and a differential output stage comprising PMOS and NMOS type transistors. According to the present invention, the transistors of the differential stage (DIFST2) comprise only one PMOS transistor (TP3) and one NMOS transistor (TN3) in series, the PMOS transistor (TP3) having its gate linked to one node of the read stage (RDST), the NMOS transistor (TN3) having its gate linked to one node of the reference stage (RFST), the mid-point of the PMOS and NMOS transistors of the differential stage forming a data output node (DATAOUT) of the read amplifier. The read amplifier according to the present invention has the combined advantages of a short read time and a low electrical consumption. Application to EPROM, EEPROM and FLASH type non-volatile memories.
Images(4)
Previous page
Next page
Claims(8)
1. Read amplifier (SA2, SA3) comprising a read stage (RDST) linked or intended to be linked to a memory cell (MCELL) that must be read, a reference stage (RFST) passed through by a reference current (Iref) and a differential output stage comprising PMOS and NMOS type transistors,
characterised in that the transistors of the differential stage (DIFST2) comprise only one PMOS transistor (TP3) and one NMOS transistor (TN3) in series, the PMOS transistor (TP3) having its gate linked to one node of the read stage (RDST), the NMOS transistor (TN3) having its gate linked to the gate of a transistor (TN1) of the reference stage (RFST) on which a gate voltage occurs that is representative of the reference current (Iref), the mid-point of the PMOS and NMOS transistors forming a data output node (DATAOUT) of the read amplifier.
2. Read amplifier according to claim 1, in which the read stage (RDST) comprises a PMOS transistor (TP2) receiving a reference voltage (Vref) at its gate, in series with an NMOS transistor (TN2) the source of which forms a link point (SENSEOUT) of the read amplifier to a memory cell (MCELL, FGT), the drain of the PMOS transistor (TP2) of the read stage (RDST) being linked to the gate of the PMOS transistor (TP3) of the differential stage (DIFST2).
3. Read amplifier according to claim 2, in which the reference stage (RFST) comprises a PMOS transistor (TP1) receiving the reference voltage (Vref) at its gate, in series with an NMOS transistor (TN1) having its gate linked to the gate of the NMOS transistor (TN3) of the differential stage (DIFST2).
4. Read amplifier according to claim 3, in which the gate of the NMOS transistor (TN2) of the read stage (RDST) is linked to the drain of the NMOS transistor (TN1) of the reference stage (RFST), and the gate of the NMOS transistor (TN1) of the reference stage (RFST) is linked to the source of the NMOS transistor (TN2) of the read stage (RDST).
5. Read amplifier according to one of claims 2 to 4, comprising a precharge transistor (TP5, TN5) linked to the drain of the NMOS transistor (TN2) of the read stage.
6. Read amplifier (SA3) according to claim 5, in which the precharge transistor (TN5) has its gate driven by the data output node (DATAOUT) of the read amplifier.
7. Non-volatile memory comprising a memory array (MA) having at least one memory cell (MCELL), characterised in that it comprises at least one read amplifier according to one of claims 1 to 7, to read the memory cell.
8. Non-volatile memory according to claim 7, in which the memory cell comprises a floating-gate transistor.
Description
  • [0001]
    The present invention relates to a non-volatile memory cell read amplifier, applicable, in particular, to EPROM, EEPROM, FLASH EEPROM memories . . .
  • [0002]
    The present invention relates more particularly to a read amplifier with a differential output stage.
  • [0003]
    In order to read a datum present in a non-volatile memory cell the programmed or erased state of which determines the value of a datum saved in the memory cell, it is common to use a read amplifier provided to detect the programmed or erased state of the cell by comparing a current passing through the cell with a reference current. The programmed state corresponds conventionally to the storage of a 0 and the erased state to the storage of a 1, or vice-versa.
  • [0004]
    Some known read amplifiers comprise an output stage formed by an inverting gate, while others comprise a differential output stage.
  • [0005]
    A classical read amplifier with a differential output stage is represented in FIG. 1. In this figure and in the rest of the present application, PMOS type transistors are designated by references starting by “TP” and NMOS type transistors are designated by references starting by “TN”.
  • [0006]
    The read amplifier SA1 comprises a reference stage RFST, a read stage RDST and a differential stage DIFST1 electrically supplied by a voltage Vcc and receiving a reference voltage Vref delivered by a generator RGEN. The read amplifier SA1 has an output node SENSEOUT intended to be linked to a memory cell that must be read, and an output node DATAOUT delivering a datum to 1 (Vcc) or to 0 (ground) depending on the conductivity state of the memory cell.
  • [0007]
    The generator RGEN comprises for example a transistor TP0 the source S of which receives the voltage Vcc, the drain D of which is connected to a current generator IGEN, and the gate G of which is linked to the drain D. The transistor TP0 is passed through by a current Iref imposed by the current generator IGEN, and the voltage Vref is sampled at its gate G.
  • [0008]
    The reference stage RFST comprises two transistors TP1, TN1 in series. The transistor TP1 receives the voltage Vcc at its source, the signal Vref at its gate, and its drain is connected to the drain of the transistor TN1 the source of which is linked to the ground.
  • [0009]
    The read stage RDST comprises two transistors TP2, TN2 in series. The transistor TP2 receives the voltage Vcc at its source, the voltage Vref at its gate, and its drain is connected to the drain of the transistor TN2. The source of the transistor TN2 is connected to the gate of the transistor TN1 and forms the output SENSEOUT of the read amplifier, at which a voltage VSENSE is found.
  • [0010]
    The differential output stage DIFST1 comprises a first branch comprising two transistors TP3, TN3 in series and a second branch comprising two transistors TP4, TN4 in series. The transistor TP3 receives the voltage Vcc at its source, a voltage VMAT sampled at the drain of the transistor TP2 (also the drain of the transistor TN2) at its gate, and its drain is connected to the drain of the transistor TN3 the source of which is linked to the ground. The transistor TP4 receives the voltage Vcc at its source, the voltage Vref at its gate, and its drain is connected to the drain of the transistor TN4 the source of which is linked to the ground. The transistor TN4 has its drain connected to its gate and its gate connected to the gate of the transistor TN3. The output DATAOUT is formed by the mid-point of the transistors TP3, TN3, i.e. the drain of the transistor TP3 and the drain of the transistor TN3.
  • [0011]
    The read amplifier also comprises a precharge transistor TP5 the source of which receives the voltage Vcc, and the drain of which is linked to the drain of the transistor TN2, the gate of the transistor TP5 being driven by a voltage Vp.
  • [0012]
    The transistors TP0, TP1, TP2, TP3, TP4 are preferably identical and the transistors TN1, TN2, TN3, TN4 are also identical (same gate aspect ratio).
  • [0013]
    As an example of an application, it will now be assumed that the output SENSEOUT is linked to a memory cell MCELL through a column decoder COLDEC and a bit line BLj of a memory array MA. The memory cell comprises a floating-gate transistor FGT receiving a read voltage Vread at its gate and the conductivity state of which depends on its programmed or erased state.
  • [0014]
    The reading as such of the memory cell MCELL is preceded by a precharge phase during which the voltage Vp is taken to 0. The transistor TP5 is in a transmission state and a precharge current is delivered by the output SENSEOUT. This precharge current aims to charge stray capacitances of the bit line BLj and to bring the voltage VSENSE to a determined value, in the order of Vtn (threshold voltage of an NMOS transistor). The transistor TP5 allows the precharge time to be accelerated and, as a result, the global read time, as the transistor TP2 operates as current generator and is not capable of delivering a high precharge current. During the precharge phase, the voltage VMAT is equal to Vcc and the transistor TP3 is blocked. The transistor TN4 is passed through by the current Iref present in the generator RGEN, by current mirror effect between the transistors TP4 and TP0. The transistor TN3 is also passed through by the current Iref by current mirror effect with the transistor TN3. The output DATAOUT is therefore on 0.
  • [0015]
    The read step as such starts when the voltage Vp is taken to Vcc, the transistor TP5 then being blocked. The output SENSEOUT delivers in the bit line BLj a current Icell the value of which depends on the conductivity state of the memory cell MCELL. The reference stage RFST is passed through by the current Iref by current mirror effect between the transistors TP1 and TP0, and the drain of the transistor TP2 of the read stage RDST also delivers the current Iref by current mirror effect with the transistor TP0. If the current Icell is higher than Iref, the voltage VMAT drops, the transistor TP3 goes into a transmission state and the output DATAOUT goes to 1. If the current Icell is lower than Iref, the voltage VMAT stays at the high level and the output DATAOUT stays on 0.
  • [0016]
    As indicated above, other types of read amplifiers comprise an output stage with an inverting gate. In this case, the differential stage DIFST1 is replaced by an inverting gate that receives the signal VMAT at input and the output of which forms the output DATAOUT of the read amplifier. In this case, the output DATAOUT is on 1 or 0 depending on whether the signal VMAT is lower or higher than a trip point of the inverting gate.
  • [0017]
    The advantage of a read amplifier with a differential output stage of the type that has just been described is that it is accurate because the value of the output DATAOUT does not depend on the trip point of an inverting gate and is a function of a comparison of the voltage VMAT with the reference voltage Vref. Therefore, the output DATAOUT goes to 0 as soon as VMAT becomes lower than Vref.
  • [0018]
    Another advantage of such a read amplifier is that it has a short read time as the voltage Vref is generally higher than the trip point of an inverting gate, such that the detection of the low level of the voltage VMAT is faster with a differential stage than with an inverting gate.
  • [0019]
    However, such a read amplifier has a double drawback. First, the differential output stage is more complex than an output stage with an inverting gate (two MOS transistors being sufficient to obtain an inverting gate). Furthermore, the electrical consumption of the differential output stage is considerable while the electrical consumption of an inverting gate is zero outside commutation periods.
  • [0020]
    The present invention aims to overcome these drawbacks.
  • [0021]
    More particularly, the present invention aims to provide a read amplifier of the type described above in which the differential stage is of a simpler structure and has a lower current consumption.
  • [0022]
    This object is achieved by providing a read amplifier comprising a read stage linked or intended to be linked to a memory cell that must be read, a reference stage passed through by a reference current and a differential output stage comprising PMOS and NMOS type transistors, in which the transistors of the differential stage comprise only one PMOS transistor and one NMOS transistor in series, the PMOS transistor having its gate linked to one node of the read stage, the NMOS transistor having its gate linked to the gate of a transistor of the reference stage on which a gate voltage occurs that is representative of the reference current, the mid-point of the PMOS and NMOS transistors forming a data output node of the read amplifier.
  • [0023]
    According to one embodiment, the read stage comprises a PMOS transistor receiving a reference voltage at its gate, in series with an NMOS transistor the source of which forms a link point of the read amplifier to a memory cell, the drain of the PMOS transistor of the read stage being linked to the gate of the PMOS transistor of the differential stage.
  • [0024]
    According to one embodiment, the reference stage comprises a PMOS transistor receiving the reference voltage at its gate, in series with an NMOS transistor having its gate linked to the gate of the NMOS transistor of the differential stage.
  • [0025]
    According to one embodiment, the gate of the NMOS transistor of the read stage is linked to the drain of the NMOS transistor of the reference stage, and the gate of the NMOS transistor of the reference stage is linked to the source of the NMOS transistor of the read stage.
  • [0026]
    According to one embodiment, the read amplifier comprises a precharge transistor linked to the drain of the NMOS transistor of the read stage.
  • [0027]
    According to one embodiment, the precharge transistor has its gate driven by the data output node of the read amplifier.
  • [0028]
    The present invention also relates to a nonvolatile memory comprising a memory array having at least one memory cell, and at least one read amplifier according to the present invention.
  • [0029]
    According to one embodiment, the memory cell comprises a floating-gate transistor.
  • [0030]
    These and other objects, advantages and features of the present invention shall be explained in greater detail in the following description of a read amplifier according to the present invention, and of an embodiment of this read amplifier, given in relation with, but not limited to, the following figures, in which:
  • [0031]
    [0031]FIG. 1 previously described is the wiring diagram of a read amplifier with a classical differential output stage,
  • [0032]
    [0032]FIG. 2 is the wiring diagram of a read amplifier with a differential output stage according to the present invention, and
  • [0033]
    [0033]FIG. 3 is the wiring diagram of a variation of the read amplifier in FIG. 2.
  • [0034]
    [0034]FIG. 2 represents a read amplifier SA2 according to the present invention. The read amplifier comprises a reference stage RFST, a read stage RDST and a differential stage DIFST2 electrically supplied by a voltage Vcc and receiving a reference voltage Vref delivered by a generator RGEN. It has an output node SENSEOUT intended to be linked to a memory cell that must be read, and an output node DATAOUT delivering a datum to 1 (Vcc) or to 0 (ground) depending on the conductivity state of the memory cell.
  • [0035]
    The reference stage RFST, the read stage RDST and the reference generator RGEN are identical to those described in the preamble in relation with FIG. 1, the same elements being designated by the same references.
  • [0036]
    Therefore, the generator RGEN comprises a transistor TP0 the source S of which receives the voltage Vcc, the drain D of which is connected to a current generator IGEN, and the gate G of which is linked to the drain D. The transistor TP0 is passed through by a current Iref imposed by the current generator IGEN, and the voltage Vref is sampled at its gate G. The reference stage RFST comprises two transistors TP1, TN1 in series. The transistor TP1 receives the voltage Vcc at its source, the signal Vref at its gate, and its drain is connected to the drain of the transistor TN1 the source of which is linked to the ground. The read stage RDST comprises two transistors TP2, TN2 in series. The transistor TP2 receives the voltage Vcc at its source, the voltage Vref at its gate, and its drain is connected to the drain of the transistor TN2. The source of the transistor TN2 forms the output node SENSEOUT of the read amplifier and is connected to the gate of the transistor TN1, which imposes the voltage VSENSE on the output node SENSEOUT.
  • [0037]
    The read amplifier also comprises, in a classical manner, a precharge transistor TP5 the source of which receives the voltage Vcc and the drain of which is linked to the drain of the transistor TN2, the gate of the transistor TP5 being driven by a voltage Vp.
  • [0038]
    According to the present invention, the differential output stage DIFST2 comprises a single branch comprising only two transistors TP3, TN3 in series. The output node DATAOUT is the mid-point of the transistors TP3, TN3, i.e. the connection point of the drain of the transistor TP3 and of the drain of the transistor TN3. The transistor TP3 receives the voltage Vcc at its source, the voltage VMAT sampled on the drain of the transistor TP2 (also the drain of the transistor TN2) at its gate, and its drain is connected to the drain of the transistor TN3. The transistor TN3 has its source linked to the ground and its gate receives the voltage VSENSE present at the gate of the transistor TN1 and at the output node SENSEOUT.
  • [0039]
    The stage DIFST2 is therefore the equivalent of the classical stage DIFST1 in FIG. 1 in which the transistors TP4 and TN4 have been removed and the gate drive signal of the transistor TN3 has been changed, which is now the voltage VSENSE instead of being the gate voltage of the removed transistor TN4.
  • [0040]
    The present invention is, in fact, based on the observation according to which, in the classical read amplifier in FIG. 1, the function of the transistor TN4 is to apply a control voltage representative of the reference current Iref to the gate of the transistor TN3. However, in the reference stage RFST, the transistor TP1 has its gate biased by the voltage Vref and imposes the current Iref in the transistor TN1. The gate voltage of the transistor TN1, i.e. the voltage VSENSE, is therefore itself representative of the reference current Iref. The voltage VSENSE is particularly equal to the gate voltage of the transistor TN4 when TP1=TP4 and TN1=TN4 (same gate aspect ratio), the transistors TN1 and TN4 being passed through by the same current and both operating in saturated mode. Therefore, the removal of the transistors TP4 and TN4 does not change the operation of the read amplifier if the voltage VSENSE is used to drive the gate of the transistor TN3, instead of using the gate voltage of the transistor TN4. The removal of the transistors TN4 and TP4 can also be considered when the transistors TP1 and TP4 do not have the same dimensions. It will be assumed for example that TP4=2*TP1 (gate aspect ratio of TP4 double of that of TP1). In this case, the voltage VSENSE corresponds to a current that is equal to half of the current passing through the transistor TN4. The voltage VSENSE remains useable however to drive the gate of the transistor TN3, as it is always representative of the reference current Iref. Therefore, the transistor TN4 and, as a result, the transistor TP4 can be removed.
  • [0041]
    In one preferred embodiment, the transistors TP0 TP2 and TP3 are identical and the transistors TN1, TN2 and TN3 are also identical (same gate aspect ratio).
  • [0042]
    Such an improvement of the differential stage noticeably reduces the electrical consumption of the read amplifier SA2 without affecting its performances in terms of reading speed. In fact, in FIG. 1, the branch comprising the transistors TP4 and TN4 consumes current permanently when the read amplifier is on and it is receiving the voltage Vref. The removal of this branch therefore leads to a corresponding reduction in the current consumption.
  • [0043]
    Moreover, the reduction of the electrical consumption of the read amplifier gives those skilled in the art an additional degree of freedom to optimise the reading speed, the electrical consumption being one of the factors that limits the possibilities of improving the reading speed of a read amplifier at the design stage, particularly at the stage of determining the size of the transistors.
  • [0044]
    Another advantage of the present invention is that the removal of the transistor TP4 leads to a reduction in the stray capacitance on the voltage Vref distribution line. This reduction is in the order of 25% since there are only three remaining PMOS transistors compared to four connected to the generator RGEN, and improves the speed of establishing the voltage Vref at the gates of the three transistors. Therefore, a reading operation can be carried out from a standby mode in which the generator RGEN is turned off and is only reactivated at the time of the reading.
  • [0045]
    As an example of an application, it will be assumed as above that the output SENSEOUT is linked to a memory cell MCELL through a column decoder COLDEC and a bit line BLj of a memory array MA. The memory cell comprises a floating-gate transistor FGT receiving a read voltage Vread at its gate and the conductivity state of which depends on its programmed or erased state.
  • [0046]
    The reading of the memory cell MCELL is preceded by a precharge phase during which the voltage Vp is taken to 0. The transistor TP5 is in a transmission state and a precharge current is delivered by the output SENSEOUT. During the precharge phase, the voltage VMAT is equal to Vcc and the transistor TP3 is blocked. The transistor TN3 is passed through by the current Iref passing through the transistor TN1, as explained above. The output DATAOUT is therefore on 0.
  • [0047]
    The reading step starts when the voltage Vp is taken to Vcc, the transistor TP5 then being blocked. The output SENSEOUT delivers a current Icell that depends on the conductivity state of the memory cell MCELL. The reference stage RFST is passed through by the current Iref by current mirror effect between the transistors TP1, TP0. The drain of the transistor TP2 of the read stage RDST also delivers the current Iref by current mirror effect with the transistor TP0. The output SENSEOUT delivers a current Icell that is compared to the current Iref. If the current Icell is higher than Iref, the voltage VMAT drops, the transistor TP3 goes into a transmission state and the output DATAOUT goes to 1 (Vcc). If the current Icell is lower than Iref, the voltage VMAT remains at high level and the output DATAOUT remains on 0.
  • [0048]
    [0048]FIG. 3 represents an embodiment SA3 of the read amplifier according to the present invention. This embodiment is a combination of the present invention with the invention described by the U.S. Pat. No. 6,094,394, done by the author of the present invention. In this embodiment, the precharge transistor TP5 is removed and is replaced by an NMOS transistor TN5 the drain of which receives the voltage Vcc and the source of which is connected to the drain of the transistor TN2. In compliance with U.S. Pat. No. 6,094,394, the gate of the precharge transistor TN5 is driven by the signal delivered by the output DATAOUT of the read amplifier.
Patent Citations
Cited PatentFiling datePublication dateApplicantTitle
US5363340 *Aug 31, 1992Nov 8, 1994Nec CorporationSemiconductor memory
US5754010 *May 21, 1997May 19, 1998Motorola, Inc.Memory circuit and method for sensing data
US6442090 *Apr 24, 2000Aug 27, 2002Mosaid Technologies Inc.Differential sensing amplifier for content addressable memory
US20010024381 *Mar 2, 2001Sep 27, 2001Ikuo FuchigamiCurrent sense amplifier circuit
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US7724578Dec 15, 2006May 25, 2010Globalfoundries Inc.Sensing device for floating body cell memory and method thereof
US9099167Sep 4, 2012Aug 4, 2015Stmicroelectronics (Rousset) SasCurrent detector allowing a large supply voltage range
US20060220459 *Feb 13, 2006Oct 5, 2006Seiko Epson CorporationSensing circuits
US20080144367 *Dec 15, 2006Jun 19, 2008Advanced Micro Devices, Inc.Sensing device for floating body cell memory and method thereof
WO2008076307A1 *Dec 13, 2007Jun 26, 2008Advanced Micro Devices, Inc.Sensing device for floating body cell memory and method thereof
Classifications
U.S. Classification365/200
International ClassificationH03F3/18, G11C7/06, G11C16/28
Cooperative ClassificationG11C16/28, G11C7/062, G11C2207/063
European ClassificationG11C16/28, G11C7/06C
Legal Events
DateCodeEventDescription
Jan 29, 2003ASAssignment
Owner name: STMICROELECTRONICS S.A., FRANCE
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:LA ROSA, FRANCESCO;REEL/FRAME:013706/0329
Effective date: 20030107
Dec 28, 2007FPAYFee payment
Year of fee payment: 4
Sep 21, 2011FPAYFee payment
Year of fee payment: 8
Sep 19, 2013ASAssignment
Owner name: MICRON TECHNOLOGY, INC., IDAHO
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:STMICROELECTRONICS S. A. ( FORMERLY KNOWN AS SGS-THOMSON MICROELECTRONICS S.A.);REEL/FRAME:031334/0684
Effective date: 20120523
Dec 23, 2015FPAYFee payment
Year of fee payment: 12
May 12, 2016ASAssignment
Owner name: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGEN
Free format text: SECURITY INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:038669/0001
Effective date: 20160426
Jun 2, 2016ASAssignment
Owner name: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL
Free format text: PATENT SECURITY AGREEMENT;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:038954/0001
Effective date: 20160426