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Publication numberUS20030112038 A1
Publication typeApplication
Application numberUS 10/020,114
Publication dateJun 19, 2003
Filing dateDec 18, 2001
Priority dateDec 18, 2001
Also published asUS6586971
Publication number020114, 10020114, US 2003/0112038 A1, US 2003/112038 A1, US 20030112038 A1, US 20030112038A1, US 2003112038 A1, US 2003112038A1, US-A1-20030112038, US-A1-2003112038, US2003/0112038A1, US2003/112038A1, US20030112038 A1, US20030112038A1, US2003112038 A1, US2003112038A1
InventorsSamuel Naffziger, Eric Fetzer
Original AssigneeSamuel Naffziger, Fetzer Eric S.
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Adapting vlsi clocking to short term voltage transients
US 20030112038 A1
Abstract
A system and method of compensating for voltage droop in an integrated circuit. The integrated circuit may include a plurality of chip circuits, a clock control system, a clock distribution network including at least one delay element and a voltage droop detector. The clock control system adapts cycle time in the clock distribution network through use of the at least one delay element when a voltage droop is detected. The method may include detecting a voltage droop in an integrated circuit where the integrated circuit is driven by a clock signal, determining an optimum frequency change to compensate for the voltage droop, and adapting cycle time of the clock signal in an incremental manner to achieve the optimum frequency change.
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Claims(21)
What is claimed is:
1. A method of compensating for voltage droop in an integrated circuit comprising:
detecting a voltage droop in an integrated circuit, the integrated circuit being driven by a clock signal;
determining an optimum frequency change to compensate for the voltage droop; and
adapting cycle time of the clock signal in an incremental manner to achieve the optimum frequency change.
2. The method of claim 1 wherein adapting the cycle time comprises increasing the cycle length by a determined value for a designated number of cycles.
3. The method of claim 2 wherein the designated number of cycles comprises one of the number of cycles the voltage droop lasts and the number of cycles until a phase locked loop producing the clock signal can respond to a request to reduce frequency.
4. The method of claim 1 wherein detecting a voltage droop comprises monitoring time relative changes of a voltage of operation for the integrated circuit.
5. The method of claim 1 wherein adapting the cycle time in an incremental manner comprises increasing the cycle time for all chip circuits in a progressive manner.
6. The method of claim 4 wherein increasing the cycle time comprises using a large range delay line to increase the cycle time.
7. The method of claim 1 wherein the integrated circuit comprises a very large scale integrated circuit.
8. An integrated circuit having voltage droop compensation capability comprising:
a plurality of chip circuits;
a clock control system;
a clock distribution network including at least one delay element; and
a voltage droop detector, wherein the clock control system adapts cycle time in the clock distribution network through use of the at least one delay element when a voltage droop is detected.
9. The integrated circuit of claim 8 wherein the clock control system determines an optimum frequency to compensate for the voltage droop detector.
10. The integrated circuit of claim 8 wherein the clock control system incrementally adapts the cycle time for all of the plurality of chip circuits through a designated number of cycles.
11. The integrated circuit of claim 10 wherein the designated number of cycles comprises one of the number of cycles the voltage droop lasts and the number of cycles until a phase locked loop producing the clock signal can respond to a request to reduce frequency.
12. The integrated circuit of claim 8 wherein the voltage droop detector comprises a operational amplifier having a first input of a local supply voltage and a second input of a reference voltage.
13. The integrated circuit of claim 8 wherein the clock distribution network comprises at least one second level clock buffer.
14. The integrated circuit of claim 13 wherein the clock distribution network comprises a plurality of second level clock buffers, each clock buffer having at least one associated delay element.
15. The integrated circuit of claim 14 wherein each second level clock buffer has an associated voltage droop indicator.
16. The integrated circuit of claim 8 wherein the at least one delay element comprises a controllable delay element.
17. A system for compensating for voltage droop in an integrated circuit comprising:
means for detecting a voltage droop in an integrated circuit, the integrated circuit driven by a clock signal;
means for determining an optimum frequency change to compensate for the voltage droop; and
means for adapting cycle time of the clock signal in an incremental manner to achieve the optimum frequency change.
18. The system of claim 17 wherein the means for adapting the cycle time comprises means for increasing the cycle length by a determined value for a designated number of cycles.
19. The system of claim 17 wherein the means for detecting a voltage droop comprises means for monitoring time relative changes of a voltage of operation for the integrated circuit.
20. The system of claim 17 wherein the means for adapting the cycle time in an incremental manner comprises means for increasing the cycle time for all chip circuits in a progressive manner.
21. The system of claim 20 wherein the means for increasing the cycle time comprises a large range delay line to increase the cycle time.
Description
    FIELD OF THE INVENTION
  • [0001]
    The invention is generally related to very large scale integrated circuits. More particularly, the invention is related to compensating for voltage transients in very large scale integrated circuits.
  • BACKGROUND OF THE INVENTION
  • [0002]
    As silicon technology is scaled down in integrated circuit (“IC”) design, the voltage at which the integrated circuit operates is also reduced. However, power consumption tends to increase for the scaled down ICs, increasing the current going through the power supply and the power delivery network.
  • [0003]
    Because of this large amount of current in integrated circuits, such as, for example, very large scale integrated (“VLSI”) circuits used for microprocessor design, a large transient may occur in the power supply network due to switching events and instantaneous changes in the current function. This change in the current may cause the voltage to vary by a large percentage of the supply. A reduction in the operating voltage due to the change in current is known as a “voltage droop”. Voltage droops may cause delays in circuit operation.
  • [0004]
    Traditionally, processors and most VLSI circuits operate at a fixed frequency, such as, for example, 1 GHz. Because of the frequency is fixed, the VLSI circuits should maintain the frequency of operation for the lowest voltage point that may be seen in the circuit. Thus, a voltage droop may require a VLSI circuit to operate at lower frequency than it could support if the frequency were based on the average voltage of operation.
  • SUMMARY OF THE INVENTION
  • [0005]
    A method for compensating for voltage droop in an integrated circuit is described. The method may include detecting a voltage droop in an integrated circuit driven by a clock signal and determining an optimum frequency change to compensate for the voltage droop. The method may further include adapting cycle time of the clock signal in an incremental manner to achieve the optimum frequency change.
  • [0006]
    An integrated circuit having voltage droop compensation capability is also described. The integrated circuit may include a plurality of chip circuits, a clock control system, a clock distribution network including at least one delay element and a voltage droop detector. In one embodiment, the clock control system may adapt cycle time in the clock distribution network through use of the at least one delay element when a voltage droop is detected.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • [0007]
    The invention is illustrated by way of example and not limitation in the accompanying figures in which like numeral references refer to like elements, and wherein:
  • [0008]
    [0008]FIG. 1 is a schematic diagram illustrating an exemplary embodiment of a clock distribution system;
  • [0009]
    [0009]FIG. 2 is a circuit diagram illustrating an exemplary embodiment of a clock distribution circuit employing principles of an embodiment of the invention;
  • [0010]
    [0010]FIG. 3 is a circuit diagram illustrating one embodiment of a droop indicator for use with the clock distribution circuit of FIG. 2;
  • [0011]
    [0011]FIG. 4 is a block diagram illustrating one embodiment of a system for compensating for voltage droop in a VLSI circuit;
  • [0012]
    [0012]FIG. 5 is a flow diagram of one embodiment of a process for adapting a VLSI clocking circuit to a voltage droop; and
  • [0013]
    [0013]FIG. 6 is a graphic representation of the operation of an exemplary embodiment of the clock distribution circuit adapting in response to a voltage droop.
  • DETAILED DESCRIPTION OF THE INVENTION
  • [0014]
    In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the invention. However, it will be apparent to one of ordinary skill in the art that these specific details need not be used to practice the invention. In other instances, well known structures, interfaces, and processes have not been shown in detail in order not to obscure unnecessarily the invention.
  • [0015]
    [0015]FIG. 1 is a schematic diagram illustrating an exemplary embodiment of a clock distribution system. The clock distribution system 100 is a typical clock distribution system for a VLSI circuit. The system 100 may include a central primary buffer 101, at least one second level control buffer (“SLCB”)102, and quadrant repeaters 103.
  • [0016]
    This figure indicates the complexity and span of an advanced microprocessor clock distribution. The buffer 101 initiates the clock distribution which proceeds along matched delay paths to the four quadrant repeaters 103. Each of these quadrant repeaters 103 includes a matched route out to a number of SLCBs 102 which provide the final level of buffering before contact with the local clock gating circuits. The span across this distribution is approximately 14 mm×18 mm. This is enough distance to accumulate large voltage differentials across a VLSI chip with transfer times of at least a nanosecond, which is larger than the clock cycle for high speed microprocessors.
  • [0017]
    [0017]FIG. 2 is a circuit diagram illustrating an exemplary embodiment of a clock distribution circuit 200 employing principles of an embodiment of the invention. The clock distribution circuit 200 may receive a clock signal 220 as an input. The clock signal 220 is received by core primary driver 221 which transmits the clock signal to repeaters 203. The repeaters 203 transmit the clock signal to SLCBs 202. Although three SLCBs 202 are shown, the clock distribution circuit may include any number of SLCBs.
  • [0018]
    Each SLCB 202 may include at least one controllable delay element (not shown). In one embodiment, the controllable delay element(s) of the SLCB 202 may provide delays in the range of 0 to 1 cycle. Each SLCB 202 is coupled to a circuitry using the clock signal 220. The circuitry using the clock signal may include gates 225 and latches 227. The clock signal 220 is also forwarded to a phase locked loop 229, where the signal is taken as the clock feedback, enabling the elimination of the distribution delay from the clock phase.
  • [0019]
    [0019]FIG. 3 is a circuit diagram illustrating one embodiment of a droop indicator 300 for use with the clock distribution circuit of FIG. 2. In one embodiment, the droop indicator 300 may detect voltage droop by monitoring the time relative changes of a voltage of operation of the integrated circuit 100. The droop indicator 300 may include an operational amplifier 335 to determine when a voltage droop occurs.
  • [0020]
    In one embodiment, the operational amplifier 335 may be a subtracting op amp having a positive input and a negative input. In the example shown, the operational amplifier 335 receives a voltage signal from a local supply as the first (positive) input 331 and a voltage signal from a reference voltage source as the second (negative) input 333. The output 337 of the operational amplifier 335 may indicate the polarity of a comparison of the first input 331 and the second input 333 (i.e. a high output may indicate input 331 is at a greater voltage potential than input 333, and a low output may indicate the reverse).
  • [0021]
    In one embodiment, these voltage droop indicator(s) 300 may be placed around the chip in sufficient quantity to quickly and accurately detect voltage droops that may originate from any circuits on the chip. Since SLCB 102 placements have already been arranged on the chip for the clock distribution and there are typically a large number (32 in FIG. 1), a voltage droop indicator may be included along with each SLCB in one embodiment.
  • [0022]
    [0022]FIG. 4 is a block diagram illustrating one embodiment of a VLSI clocking adapting system 400. Adapting system 400 may include a droop indicator 402, a control system 404 and at least one delay element 406. The droop indicator 402 may be similar to the droop indicator 300 described above. The control system 404 may be similar to or include the control system for clock distribution circuit 200. Delay element(s) 406 may be or include a switched capacitor element, a current starved inverter, a switchable delay element or any other appropriate delay element that may be used with VLSI clock distribution circuit 200.
  • [0023]
    The droop indicator 402 may detect a droop in the operating voltage of clock distribution circuit 200. The control system 404 may receive the indication of a voltage droop from the droop indicator 402. The control system may determine the optimum frequency to compensate for the voltage droop, and then activate one or more delay elements 406 as described below with respect to processing block 530 of FIG. 5.
  • [0024]
    [0024]FIG. 5 is a flow diagram of one embodiment of a process for adapting a VLSI clocking circuit to a voltage droop. At processing block 510, the droop indicator 300, 402 detects a voltage droop as described above with reference to FIG. 3. Since each droop indicator 300, 402 is associated with a SLCB 202, the following process will be performed with reference to the SLCB 202 with which the droop indicator 300,402 indicating the droop is associated.
  • [0025]
    At processing block 520, the control system 404 determines the optimum frequency for the SLCB 202 to operate as a result of the voltage droop. In one embodiment, the control system 404 may determine the optimum frequency change for the clock signal to compensate for the voltage droop.
  • [0026]
    At processing block 530, the control system 404 adapts the cycle time of the clock signal through the SLCB 202 associated with the droop indicator 300, 402 indicating the voltage droop. In one embodiment, the control system 404 uses delay elements 406 to implement changes in cycle time. For example, the control system 404 may add delays to the cycle time using delay elements 406 so that the cycle time of the clock signal through the clock distribution network is increased, thereby producing a temporary frequency reduction.
  • [0027]
    In one embodiment, the control system 404 may implement the change in frequency incrementally. For example, the control system 404 may increase the cycle time for all chip circuits in a progressive manner using a large range delay line including delay elements 406. Thus, if the frequency is to be decreased by 1%, the cycle times may be increased by 1%, then 2%, then 3%, etc. to effect the desired decrease in frequency. In one embodiment, the control system 404 may determine the number of cycles the delay lasts based on at least one of the amount of time the voltage droop lasts and the amount of time needed by the phase locked loop (“PLL”), or the source of the clock frequency, to respond to a request to reduce frequency. Thus, in this embodiment, either the voltage transient or droop goes away before the delay line range is consumed, or the clock system adjusts the actual clock frequency. The temporary decrease in frequency allows the PLL to have enough time to adjust the actual clock frequency if the voltage droop does not go away.
  • [0028]
    [0028]FIG. 6 is a graphic representation of the operation of an exemplary embodiment of the clock distribution circuit adapting in response to a voltage droop. At time 642, a voltage droop is detected by droop indicator 300, 402 associated with a SLCB 202.
  • [0029]
    As shown by signal 644, the normal clock signal at this time has a period of T. When the control system 404 receives indication of the voltage droop at time 642, the control system 404 determines an optimum frequency change. The control system 404 implements the optimum frequency change by progressively increasing the clock cycle time distributed by the SLCB 202 with which the voltage droop indicator 300, 402 indicating the voltage droop 642 is associated, as shown by signal 646. For example, the clock system adds a delay of ΔT to the first cycle after the droop is detected. The clock system then continues to add a delay of 2ΔT to the second cycle, and a delay of 3ΔT to the third cycle.
  • [0030]
    While this invention has been described in conjunction with the specific embodiments thereof, it is evident that many alternatives, modifications and variations will be apparent to those skilled in the art. These changes may be made without departing from the spirit and scope of the invention.
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US7076679Oct 6, 2003Jul 11, 2006Hewlett-Packard Development Company, L.P.System and method for synchronizing multiple variable-frequency clock generators
US7225349 *Jul 25, 2003May 29, 2007Intel CorporationPower supply voltage droop compensated clock modulation for microprocessors
US7409568Jul 5, 2006Aug 5, 2008Intel CorporationPower supply voltage droop compensated clock modulation for microprocessors
US8006115Oct 6, 2003Aug 23, 2011Hewlett-Packard Development Company, L.P.Central processing unit with multiple clock zones and operating method
US8060766 *Mar 6, 2009Nov 15, 2011Oracle America, Inc.Microprocessor performance and power optimization through inductive voltage droop monitoring and correction
US8099619Sep 28, 2006Jan 17, 2012Intel CorporationVoltage regulator with drive override
US8930741Dec 12, 2011Jan 6, 2015Intel CorporationVoltage regulator with drive override
US9483098Apr 1, 2010Nov 1, 2016Qualcomm IncorporatedCircuits, systems and methods to detect and accommodate power supply voltage droop
US9600024Sep 25, 2013Mar 21, 2017Mediatek Singapore Pte. Ltd.Control method of clock gating for dithering in the clock signal to mitigate voltage transients
US20050022042 *Jul 25, 2003Jan 27, 2005Tam Simo M.Power supply voltage droop compensated clock modulation for microprocessors
US20060253719 *Jul 5, 2006Nov 9, 2006Tam Simon MPower supply voltage droop compensated clock modulation for microprocessors
US20080082839 *Sep 28, 2006Apr 3, 2008Ted DibeneVoltage regulator with drive override
US20140254734 *Mar 7, 2013Sep 11, 2014Mohamed A. AbdelmoneumApparatus for dynamically adapting a clock generator with respect to changes in power supply
CN103716045A *Sep 26, 2013Apr 9, 2014联发科技(新加坡)私人有限公司时钟信号控制方法及电路
CN104462672A *Nov 25, 2014Mar 25, 2015上海高性能集成电路设计中心Clock skew estimation method
DE10354215B4 *Nov 20, 2003Feb 25, 2010Infineon Technologies AgTaktregulierungsvorrichtung sowie Schaltungsanordnung
WO2011123453A1 *Mar 29, 2011Oct 6, 2011Qualcomm IncorporatedCircuits, systems, and methods to detect and accommodate power supply voltage droop
Classifications
U.S. Classification327/100
International ClassificationG06F1/30, G06F1/10
Cooperative ClassificationG06F1/305, G06F1/10
European ClassificationG06F1/30F, G06F1/10
Legal Events
DateCodeEventDescription
Dec 18, 2001ASAssignment
Owner name: HEWLETT-PACKARD COMPANY, COLORADO
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:NAFFZIGER, SAMUEL;FETZER ERIC S.;REEL/FRAME:012385/0135
Effective date: 20011203
Jul 31, 2003ASAssignment
Owner name: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P., TEXAS
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:HEWLETT-PACKARD COMPANY;REEL/FRAME:013862/0623
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Dec 10, 2014ASAssignment
Owner name: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.,
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.;REEL/FRAME:034591/0627
Effective date: 20141103
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