RELATED APPLICATIONS

[0001]
The present disclosure is a continuationinpart of U.S. application Ser. No. 10/071,771 to Sreen A. Raghavan, Thulasinath G. Manickam, Peter J. Sallaway, and Gerard E. Taylor, which is a continuationinpart of U.S. application Ser. No. 09/965,242 to Sreen Raghavan, Thulasinath G. Manickam, and Peter J. Sallaway, filed Sep. 26, 2001, which is a continuationinpart of U.S. application Ser. No. 09/904,432, by Sreen Raghavan, filed on Jul. 11, 2001, assigned to the same entity as is the present application, each of which are herein incorporated by reference in its entirety.
BACKGROUND

[0002]
1. Field of the Invention

[0003]
The present invention is related to highspeed communications of data in a communication system and, in particular, to high data rate transmission of data between components in a communication system.

[0004]
2. Discussion of Related Art

[0005]
Many conventional systems for transmitting data between components within a cabinet or between cabinets of components utilize copper or optical backplanes for transmission of digital data. For example, high data rate transceiver systems are utilized in many backplane environments, including optical switching devices, router systems, switches, chiptochip communications and storage area networking switches. Other environments that utilize high speed communication between components include intercabinet communications and chiptochip communications. Typical separations of components in such systems is between about 0.1 and about 10 meters.

[0006]
Existing techniques utilized in such environments typically use nonreturn to zero (NRZ) modulation to send and receive information over highspeed backplanes or for high data rate chiptochip interconnects. Typically, the transceiver for sending highspeed data over a backplane is called a serializer/deserializer, or SERDES, device.

[0007]
[0007]FIG. 1A shows a block diagram of a backplane environment 100. Components 1011 through 101Q are coupled to transmit and receive data through input/output (I/O) ports 1021 through 102Q, respectively, to backplane 110. Conventionally, components 1011 through 101Q are SERDES devices.

[0008]
[0008]FIG. 1B shows a block diagram of a conventional transmitter portion of one of SERDES devices 1011 through 101Q on I/O ports 1021 through 102Q, respectively. Parallel data is received in a bit encoder 105. Bit encoder 105 encodes the parallel data, for example by adding redundancy in the input data, to ensure a minimum rate of data transitions in the output data stream. Typical encoding schemes include rate 8/10 (8 bit input to 10 bit output) encoding. The parallel data is serialized in parallel to serial converter 106. Output driver 107 then receives the serialized data from parallel to serial converter 106 and outputs, usually, a differential voltage signal for transmission over backplane 110. In addition, there is typically a phase locked loop (PLL) 114 that provides the necessary clock signals for encoder 105 and paralleltoserial converter 106. The input signal to PLL 114 is a reference clock signal from a system PLL 103.

[0009]
[0009]FIG. 1C shows a conventional receiver 108 of one of SERDES devices 1011 through 101Q on I/O ports 1021 through 102Q, respectively, of FIG. 1A. Input driver 109 receives differential voltage signal from backplane 110 and outputs the analog data signal to clock and data recovery circuit 113. Data recovery 113 can, in some systems, perform equalization, recover the timing and output a serial bit stream of data to serialtoparallel converter 111. The serial data is input to bit decoder 112 which converts the parallel data to parallel decoded data. Clock and data recovery circuit 113 also outputs the necessary clock signals to serialtoparallel converter 111 and bit decoder 112.

[0010]
A conventional SERDES system 100 can enable serial data communication at data rates as high as 2.5 Gbps to 3.125 Gbps over a pair of FR4 copper traces in a copper backplane communication system. One of the biggest problems with existing SERDES systems 100 is that they are very bandwidth inefficient, i.e., they require 3.125 GHz of bandwidth to transmit and receive2.5 Gbps of data over a single pair of copper wires. Therefore, it is very difficult to increase the data rates across backplane bus 110. Additionally, SERDES system 100 requires the implementation of a high clock rate (3.125 GHz for 2.5 Gbps data rates) phase locked loop (PLL) 114 implemented to transmit data and recover high clock rates in data recovery 113. The timing window within which receiver 108 needs to determine whether the received symbol in data recovery 110 is a 1 or a 0 is about 320 ps for the higher data rate systems. This timing window creates extremely stringent requirements on the design of data recovery 113 and PLL 114, as they must have very low peaktopeak jitter.

[0011]
Conventional SERDES system 100 also suffers from other problems, including eye closure due to intersymbol interference (ISI) from the dispersion introduced by backplane 110. The ISI is a direct result of the fact that the copper traces of backplane 110 attenuate higher frequency components in the transmitted signals more than the lower frequency components in the transmitted signal. Therefore, the higher the data rate the more ISI suffered by the transmitted data. In addition, electrical connectors and electrical connections (e.g., vias and other components) used in SERDES device 100 cause reflections, which also cause ISI.

[0012]
To overcome these problems, equalization must be performed on the received signal in data recovery 113. However, in existing very high datarate communication systems, equalization is very difficult to perform, if not impossible due to the high baud rate. A more commonly utilized technique for combating ISI is known as “preemphasis”, or preequalization, performed in bit encoder 105 and output driver 107 during transmission. In some conventional systems, the amplitude of the lowfrequencies in the transmitted signal is attenuated to compensate for the higher attenuation of the high frequency component by the transmission medium of bus 110. While this makes the receiver more robust to ISI, preemphasis reduces the overall noise tolerance of transmission over backplane 110 of backplane communication system 100 due to the loss of signaltonoise ratio (SNR). At higher data rates, conventional systems quickly become intractable due to the increased demands.

[0013]
Therefore, there is a need for a more robust system for transmitting data between components on a backplane or data bus at very high speeds.
SUMMARY

[0014]
In accordance with the present invention, a data transmission system is presented that allows very high data transmission rates over a data bus that utilizes the signal attenuation properties of the copper based backplane interconnect system. In addition, this transmission scheme does not result in increased intersymbol interference at the receiver despite transmitting data at a very high speed. The data transmission system includes a transmitter system and a receiver system coupled through a transmission medium. The transmitter system receives parallel data having N bits and separates the N bits into (K+1) subsets for transmission into the base band and K frequency separated channels on the transmission medium. The receiver system receives the data from the base band and the K frequency separated channels from the transmission medium and recovers the N parallel bits of data. In some embodiments, the N parallel bits are separated into (K+1) subsets of bits, the (K+1) subsets of bits are encoded into (K+1) symbols, K of which are upconverted to a carrier frequency appropriate to that channel. The summed output signal resulting from the summation of the K upconverted channels and the baseband channel is transmitted over the transmission medium.

[0015]
Transmitted data in each of the (K+1) channels can suffer from intersymbol interference (ISI) as well as crosschannel interference due to harmonic generation in upconversion and downconversion processes in the transmitter and receiver. In accordance with the present invention, a receiver which corrects for crosschannel interference as well as for intersymbol interference is presented.

[0016]
In some embodiments, the transmitter system includes (K+1) separate transmitters. Each of the (K+1) transmitters receives a subset of the Nbits and maps the subset of bits onto a symbol set. K of the transmitters modulate the symbols with a carrier signal at a frequency separated from that of others of the (K+1) transmitters. The summed signals from each of the (K+1) separate transmitters is transmitted over the transmission medium. The transmission medium can be any medium, including optical, infrared, wireless, twisted copper pair, or copper based backplane interconnect channel.

[0017]
In some embodiments, each of the (K+1) transmitters receives a subset of the N data bits, encodes the subset, maps the encoded subset onto a symbol set appropriate for that transmitter. K of the transmitters, for example, upconvert its analog symbol stream to a carrier frequency assigned to that transmitter. The remaining transmitter transmits into the base band. The output signal from each of the transmitters is then transmitted through the transmission medium to a receiver system having a receiver for recovering the data stream transmitted on each of the carrier frequencies.

[0018]
For example, in some embodiments each of the K upconverting transmitters receives the subset of bits and encodes them with a trellis encoder. One of the transmitters maps its subset of bits into a pulsed amplitude modulation (PAM) symbol set and the remaining K upconverting transmitters each maps its subset onto a quadratureamplitude modulated (QAM) symbol set. In some embodiments, the symbols output from the QAM mapping are processed through a digitaltoanalog converter before being upconverted to a carrier frequency to produce the output signal from the transmitter. The PAM transmitters can utilize a digitaltoanalog converter to create the PAM symbol output voltage levels. Any combination of encoding and symbol mapping schemes can be utilized in the (K+1) transmitters.

[0019]
In some embodiments, a PAM channel and one or more QAM channels can be utilized such that there is no crosschannel interference between the QAM channels and the PAM channel. In some embodiments, a single QAM channel combined with a PAM channel can be utilized.

[0020]
Each of the output signals from the (K+1) transmitters are summed for transmission in (K+1) separate transmission channels on the transmission medium. The receiver receives the summed signals, with data transmitted at (K+1) separate channels. In some embodiments, the receiver downconverts the summed signals by the frequency of each of the (K) separate nonbaseband channels to recover the symbols transmitted in each of the (K+1) separate channels. The baseband receiver can include a lowpass filter to separate the baseband channel from the higher frequency channels on the transmission medium. The subsets of digital data can then be recovered from the recovered symbols.

[0021]
The receiver system receives the combined signal, separates the signal by carrier frequency, and recovers the bits from each carrier frequency. In some embodiments, the signal received from the transmission medium is received into (K+1) parallel receivers. Each of the (K+1) receivers separates out the signal centered around the carrier frequency allocated to that channel by the transmitter or the baseband signal, equalizes the signal, and decodes the signal to retrieve the subset of the N bits assigned to that corresponding transmitter modulator.

[0022]
As a result, parallel streams of serial data bits are separated into separate subsets which are transmitted on different frequency bands to form separate channels on the transmission medium. Therefore, the data rate and the symbol rate transmitted in each of the separate channels can be much lower than the overall data transmission rate. The lower data rate and symbol rate in each channel provides for simpler receiver processing with many fewer problems (e.g., speed of components utilized for equalization and data recovery) than the high data rate transmissions. In addition, because the symbol rates are lower, the amount of receiver equalization needed on each of the (K+1) channels can be smaller, and can be implemented with simpler equalization structures. Because of the lower symbol rates, receiver signals can be processed with complex, optimal algorithms.

[0023]
A complex crosschannel correction algorithm according to the present invention can also be implemented. The crosschannel correction involves adjusting each of the signals of each of the channels by some portions of the signals from the other channels in order to eliminate the interference. The parameters of the crosschannel correction can be adaptively chosen to optimize receiver performance. In some embodiments, no crosschannel interference occurs between the baseband channel and the K high frequency channels and therefore no crosschannel correction is needed between the baseband channel and the K high frequency channels.

[0024]
Data transmission according to the present invention can utilize any combination of symbol mappings. For example, in some embodiments a baseband transmitter utilizing 4, 8, 16 or 32PAM symbol mapping can be combined with one or more upconverting transmitters with 16, 32, 64, 128 or 256 QAM symbol mappers, for example. In some embodiments, an encoder can be used to encode any of the subset of bits, for example the mostsignificant bit before the bits are mapped onto a symbol set. For example, a 10 Gbps transceiver can utilize uncoded (no error correction coded) 16PAM with baud rate of 1.25 GHz in combination with uncoded 16 QAM with baud rate 1.25 GHz. In another example, 4/5 trellis encoded 32QAM can be combined with uncoded 16PAM. In yet another example, uncoded 8PAM can be combined with five (5) 6/7 trellis encoded 128QAM to form a 10 Gbps transmission system. Many other examples can be utilized.

[0025]
In some embodiments, the output signals from each of the upconverting transmitters transmitting into the K high frequency channels are summed and the sum signal filtered with a highpass filter to eliminate any baseband component before the output signal from the baseband transmitter is added. Further, the baseband transmitter can include a lowpass filter to eliminate any higher frequency component of the baseband transmitter's output signal which can interfere with the signals from the upconverting transmitters.

[0026]
A transmission system in accordance with the present invention can include a plurality of receivers and a crosschannel interference canceller coupled to each of the receivers for receiving signals from the high frequency channels. Each of the plurality of receivers receives signals from one of a plurality of transmission bands. One receiver receives signals from the base band channel and the remaining receive signals from higher frequency channels.

[0027]
In some embodiments, at least one of the plurality of receivers that receives signals from a higher frequency channel includes a down converter that converts an input signal from the one of the plurality of transmission bands to a base band. A filter coupled to receive signals from the down converter can substantially filter out signals not in the base band after downconversion. Further, an analogtodigital converter coupled to receive signals from the filter and generate digitized signals and an equalizer coupled to receive the digitized signals can be included. In some embodiments, a trellis decoder coupled to receive signals from the equalizer and generate recreated data, the recreated data being substantially the same data transmitted by a corresponding transmitter. In some embodiments, a crosschannel interference canceller can be coupled to receive output signals from each of the equalizers and to provide signals to a digital filter or the trellis decoder.

[0028]
In some embodiments, the receiver that receives signals from the base band channel includes a low pass filter to filter out signals at high frequencies (e.g., the remaining channels), an analog to digital converter, an equalizer, and a data recovery circuit. In some embodiments, the equalizer can have adaptively chosen equalization parameters.

[0029]
These and other embodiments are further discussed below with respect to the following figures.
SHORT DESCRIPTION OF THE FIGURES

[0030]
[0030]FIGS. 1A, 1B and 1C show block diagrams for a conventional system of transmitting data over a backplane.

[0031]
[0031]FIG. 2A shows a block diagram of a transmission system according to the present invention.

[0032]
[0032]FIG. 2B shows a block diagram of a transmitter according to the present invention.

[0033]
[0033]FIG. 2C shows a block diagram of a receiver according to the present invention.

[0034]
[0034]FIG. 3 shows a graph of attenuation versus transmission band on the transmission medium according to the present invention.

[0035]
[0035]FIG. 4 shows a block diagram of an embodiment of a transmission modulator according to the present invention.

[0036]
[0036]FIG. 5A shows a block diagram of an embodiment of a receiver according to the present invention.

[0037]
[0037]FIG. 5B shows a block diagram of a downconversion module of a receiver as shown in FIG. 5A.

[0038]
[0038]FIG. 5C shows an embodiment of a block diagram of an analog filter of a receiver as shown in FIG. 5A.

[0039]
[0039]FIG. 5D shows an embodiment of a digital filter of a receiver as shown in FIG. 5A.

[0040]
[0040]FIG. 5E shows an embodiment of a second digital filter of a receiver as shown in FIG. 5A.

[0041]
[0041]FIG. 5F shows an embodiment of a crosschannel interference canceller of the receiver shown in FIG. 5A in accordance with the present invention.

[0042]
[0042]FIG. 6A shows a schematic diagram of a trellis encoder according to the present invention.

[0043]
[0043]FIG. 6B shows a schematic diagram of a symbol mapper according to the present invention.

[0044]
[0044]FIG. 6C shows a schematic diagram of a 128 QAM constellation.

[0045]
[0045]FIG. 6D shows filtering of the output signal from a digital to analog converter according to the present invention.

[0046]
[0046]FIG. 6E shows raised square root cosine filter response.

[0047]
[0047]FIG. 7 shows a block diagram of an embodiment of a tracking and errorrecovery circuit of the receiver shown in FIG. 5A.

[0048]
[0048]FIGS. 8A and 8B show a block diagram of an embodiment of an automatic gain control circuit of a receiver demodulator according to the present invention.

[0049]
[0049]FIG. 9 shows a block diagram of a transceiver chip according to the present invention.

[0050]
[0050]FIGS. 10A, 10B and 10C illustrate an embodiment of a trellis decoder.

[0051]
[0051]FIG. 11 shows an embodiment of a baseband transmitter according to the present invention.

[0052]
[0052]FIG. 12A shows an embodiment of a baseband receiver according to the present invention.

[0053]
[0053]FIGS. 12B through 12C show embodiments of components of the embodiment of the baseband receiver shown in FIG. 12A.

[0054]
In the figures, elements designated with the same identifications on separate figures are considered to have the same or similar functions.
DETAILED DESCRIPTION

[0055]
[0055]FIG. 2A shows a block diagram of a transmission system 200 according to the present invention. System 200 includes any number of components 2011 through 201P, with component 201p representing an arbitrary one of components 2011 through 201P, coupled through a transmission medium 250. Transmission medium 250 may couple component 201p to all of the components 2011 through 201P or may couple component 201p to selected ones of components 2011 through 201P. In some embodiments, components 2011 through 201P are coupled through FR4 copper traces.

[0056]
System 200 can represent any backplane system, any chassistochassis digital communication system, or any chiptochip interconnect with components 2011 through 201P representing individual cards, cabinets, or chips, respectively.

[0057]
Transmission channel 250 can represent any transmission channel, including optical channels, wireless channels, or metallic conductor channels such as copper wire or FR4 copper traces. Typically, transmission channel 250 attenuates higher frequency signals more than lower frequency signals. As a result, intersymbol interference problems are greater for high data rate transmissions than for low data rate transmissions. In addition, crosstalk from neighboring signals increases with transmission frequency.

[0058]
Components 2011 through 201P include transmitter systems 2101 through 210P, respectively, and receiver systems 2201 through 220P, respectively. In operation, one of transmitter systems 2101 through 210P from one of components 2011 through 201P is in communication with one of receiver systems 2201 through 220P from a different one of components 2011 through 201P. Further, in some embodiments, timing for all of components 2011 through 201P can be provided by a phaselockedloop (PLL) 203 synchronized to a transmit source clock signal. In some embodiments, PLL 203 provides a reference clock signal and each of components 2011 through 201P can include any number of phase locked loops to provide internal timing signals.

[0059]
In some systems, for example backplane systems or cabinet interconnects, the transmission distance through transmission channel 250, i.e. the physical separation between components 2011 through 201P, can be as low as 1 to 1.5 meters. In some chiptochip environments, the physical separation between components 2011 though 201P can be much less (for example a few millimeters or a few centimeters). In some embodiments of the present invention, separations between components 2011 through 201P as high as about 100 meters can be realized. Furthermore, in some embodiments transmission channel 250 can be multiple twisted copper pair carrying differential signals between components 2011 through 201P. In some embodiments, components 2011 through 201P can share wires so that fewer wires can be utilized. In some embodiments, however, dedicated twisted copper pair can be coupled between at least some of components 2011 through 201P. Further, transmission medium 250 can be an optical medium, wireless medium, or data bus medium.

[0060]
[0060]FIG. 2B shows a block diagram of an embodiment of transmitter system
210p an arbitrary one of transmitter systems
210
1 through
210P. Transmitter system
210p receives an Nbit parallel data signal at a bit allocation block
211. Bit allocation block
211 also receives the reference clock signal from PLL
203. Bit allocation block
211 segregates the N input bits into K+1 individual channels such that there are n
_{1 }through n
_{K }bits input to transmitters
212
1 through
212K, respectively, and n
_{0 }bits input to baseband transmitter
217. Transmitter
217 and transmitters
212
1 through
212K transmit into (K+1) channels. In some embodiments, each of the N bits is assigned to one of the K+1 individual channels so that the sum of n
_{0 }through n
_{K }is the total number of bits N. In some embodiments, bit allocation block
211 may include error precoding, redundancy, or other overall encoding such that the number of bits output, i.e.
$\sum _{i=0}^{K}\ue89e{n}_{i},$

[0061]
is greater than N.

[0062]
Each of transmitters 2121 through 212K encodes the digital data input to it and outputs a signal modulated at a different carrier frequency. Therefore, the n_{k }digital data bits input to transmitter 212k, an arbitrary one of transmitters 2121 through 212K, is output as an analog signal in a kth transmission channel at a carrier frequency f_{k}. Additionally, baseband transmitter 217 transmits into the baseband channel.

[0063]
[0063]FIG. 3 shows schematically the transport function for a typical transmission channel 250 (FIG. 2A), H(f). As is shown, the attenuation at higher frequencies is greater than the attenuation at lower frequencies. Transmitters 2121 through 212K transmit analog data at carrier frequencies centered about frequencies f_{1 }through f_{K}, respectively. Therefore, transmitters 2121 through 212K transmit into transmission channels 3011 through 301K, respectively. Transmitter 217 transmits into transmission channel 3010, which is centered at 0 frequency. In some embodiments, the width of each of transmission channels 3010 through 301K can be the same. The width of the bands of each of transmission channels 3010 through 301K can be narrow enough so that there is little to no overlap between adjacent ones of transmission channels 3010 through 301K. In some embodiments, since the attenuation for the lower frequency channels is much smaller than the attenuation for the higher frequency channels, lower frequency channels can be bitloaded to carry a higher number of bits per baud interval than the number of bits per baud interval that can be carried at higher carrier frequencies.

[0064]
As shown in FIG. 2B, the analog output signal from each of transmitters 2121 through 212K, y_{1}(t) through y_{K}(t), then represents the transmission signal in each of channels 3011 through 301K, respectively. Signals y_{1}(t) through y_{K}(t), then, are input to summer 213 and the summed analog signal output from summer 213 can be input to a high pass filter 215. The output signal from high pass filter 215 is input to summer 216 where it is summed with the baseband signal y_{0}(t) from baseband transmitter 217. High pass filter 215 prevents transmitters 2121 through 212K from transmitting signals into the baseband channel and reduces or eliminates the need to consider crosschannel interference between signals produced by baseband transmitter 217 and those generated by transmitters 2121 through 212K.

[0065]
The output signal from summer 216, z(t), is input to an output driver 214. In some embodiments, output driver 214 generates a differential transmit signal corresponding to signal z(t) for transmission over transmission medium 250. Output driver 214, if transmission medium 250 is an optical medium, can also be an optical driver modulating the intensity of an optical signal in response to the signal z(t).

[0066]
[0066]FIG. 2C shows an embodiment of a receiver system 220p which can be an arbitrary one of receiver systems 2201 through 220P of FIG. 2A. Receiver system 220p can receive a differential receive signal, which originated from one of transmitter systems 2101 through 210P (typically not transmitter 210p), into an input buffer 224. In some embodiments, an optical signal can be received at input buffer 224, in which case input buffer 224 includes an optical detector. The output signal from input buffer 224, Z(t), is closely related to the output signal z(t) of summer 213. However, the signal Z(t) shows the effects of transmission through transmission medium 250 on z(t), including intersymbol interference (ISI).

[0067]
The signal Z(t) is input to each of receivers 2221 through 222K and into baseband receiver 223. Receivers 2221 through 222K demodulate the signals from each of the transmission channels 3011 through 301K, respectively, and recovers the bit stream from each of carrier frequencies f_{1 }through f_{K}, respectively. Baseband receiver 223 recovers the bit stream which has been transmitted into the baseband channel. The output signals from each of receivers 2221 through 222K, then, include n_{1 }through n_{K }parallel bits, respectively, and the output signal from baseband receiver 223 include n_{0 }parallel bits. The output signals are input to bit parsing 221 where the transmitted signal having N parallel bits is reconstructed. Receiver system 220p also receives the reference clock signal from PLL 203, which can be used to generate internal timing signals. Furthermore, receiver system 220p outputs a receive clock signal with the Nbit output signal from bit parsing 221.

[0068]
Further, demodulators (receivers) 2221 through 222K are coupled so that crosschannel interference can be cancelled. In embodiments where filter 215 of transmitter 210p is not present or does not completely remove the baseband from the output signal of adder 213, then crosschannel interference in the baseband channel also will need to be considered. As discussed further below, due to the mixers in the upconversion process, multiple harmonics of each signal may be generated from each of transmitters 2121 through 212K. For example, in some embodiments transmitters 2121 through 212K transmit at carrier frequencies f_{1 }through f_{K }equal to f_{0}, 2f_{0 }. . . Kf_{0}, respectively. The baseband transmitter 213 transmits at the baseband frequency, e.g. transmitter 213 transmits with no carrier.

[0069]
Due to the harmonics in the mixer, the signal transmitted at carrier frequency f_{1 }will also be transmitted in the base band and at frequencies 2f_{1}, 3f_{1 }. . . Additionally, the signal transmitted at carrier frequency f_{2 }will also be transmitted in the base band and at 2f_{2}, 3f_{2}, . . . Therefore, any time any of the bandwidth of any harmonics of the channels overlap with other channels or the other channel's harmonics, significant crosschannel symbol interference can occur due to harmonics in the mixers of transmitters 2121 through 212K. For example, in the case where the carrier frequencies are multiples of f_{0}, channel 1 transmitting at f_{0 }will also transmit at 0, 2f_{0}, 3f_{0}, . . . , i.e. into each of the other channels. Additionally, the down converters also create harmonics, which means that some of the transmission of the third channel will be downconverted into the first channel, for example. Therefore, further crosschannel interference can be generated in the downconversion process of receivers 2211 through 222K. Embodiments of the present invention correct for the crosschannel symbol interference as well as the intersymbol interference. Note that it is well known that if the duty cycle of the harmonic wave that is being mixed with an input signal is 50%, only odd harmonics will be generated. Even harmonics require higher or lower duty cycles.

[0070]
In some embodiments, Nbits of highspeed parallel digital data per time period is input to bit allocation
211 of transmitter system
210p along with a reference clock signal. Data is transmitted at a transmit clock rate of CK
1, which can be determined by an internal phaselockedloop from the reference clock signal. Each of these input signals of Nbits can change at the rate of a transmit clock signal CK
1. The transmit clock signal CK
1 can be less than or equal to ηGHz/N, where η represents the total desired bit rate for transmission of data from transmitter system
210p over transmission medium
250. The resultant maximum aggregate input data rate, then, equals ηGbps. The ηGbps of aggregate input data is then split into K+1 subchannels
301
0 through
301K (see FIG. 3) which are generated by transmitters
217 and
212
1 through
212K, respectively, such that:
$\begin{array}{cc}\sum _{k=0}^{K}\ue89e{B}_{k}\ue89e{n}_{k}=\eta \ue89e\text{\hspace{1em}}\ue89e\mathrm{Gbps},& \left(1\right)\end{array}$

[0071]
where n_{k }is the number of bits transmitted through the kth transmission band, centered about frequency f_{k }for k equal to 1 or greater and the base band for k=0, with a symbol baud rate on the k^{th }subchannel being equal to B_{k}.

[0072]
In some embodiments of the invention, each of transmitters 217 and 2121 through 212K operate at the same baud rate B_{k}. Furthermore, the center frequency of transmitter 212k (corresponding to channel k), or one of its harmonics, is substantially the same as harmonics of the center frequencies of other ones of transmitters 2121 through 212K. One skilled in the art will recognize that in other embodiments of the invention one or both of these conditions may not be satisfied.

[0073]
In some embodiments of the invention, each of the K+1 subchannels 3010 through 301K can have the same baud rate B. In general, the baud rate B_{k }of one subchannel 301k, which is an arbitrary one of subchannels 3010 through 301K, can differ from the baud rate of other subchannels. Additionally, bitloading can be accomplished by choosing symbol sets which carry a larger number of bits of data for transmission channels at lower frequencies and symbol sets which carry a lower number of bits of data for transmission channels at higher frequencies (i.e., n_{k }is higher for lower frequencies).

[0074]
In the case of a copper backplane interconnect channel of trace length l<2 meters, for example, the signaltonoise ratio of the lower carrier frequency channels is substantially greater than the signaltonoise ratio available on the higher subchannels because the signal attenuation on the copper trace increases with frequency and because the channel noise resulting from alien signal crosstalk increases with frequency. These properties of the copper interconnect channel can be exploited to “load” the bits/baud of the K subchannels so that the overall throughput of the interconnect system is maximized. For example, digital communication signaling schemes (modulation+coding), see, e.g. Bernard Sklar, Digital Communications, Fundamentals and Applications (PrenticeHall, Inc., 1988), can be utilized that provide higher bit density per baud interval over channels occupying the lower region of the frequency spectrum, and that result in lower bit density over channels that occupy higher frequencies. This “bitloading” is especially important when the data rates over copper interconnect channel need to be increased, for example to a rate in excess of 10 Gbps per differential copper pair.

[0075]
[0075]FIG. 4 shows an embodiment of transmitter 212k, an arbitrary one of transmitters 2121 through 212K. Transmitter 212k receives n_{k }bits per baud interval, 1/B_{k}, for transmission into subchannel 301k. The n_{k }bits are received in scrambler 401. Scrambler 401 scrambles the n_{k }bits and outputs a scrambled signal of n_{k }bits, which “whitens” the data.

[0076]
The output signal of n_{k }parallel bits is then input to encoder 402. Although any encoding scheme can be utilized, encoder 402 can be a trellis encoder for the purpose of providing error correction capabilities. Trellis coding allows for redundancy in data transmission without increase of baud rate, or channel bandwidth. Trellis coding is further discussed in, for example, Bernard Sklar, Digital Communications, Fundamentals and Applications (PrenticeHall, Inc.,1988), G. Ungerboeck., “Trellis Coding Modulation with Redundant Signal Sets, Part I. Introduction,” IEEE Communications Magazine, vol. 25, no. 2, February 1987, pp. 511, and G. Ungerboeck., “Trellis Coding Modulation with Redundant Signal Sets, Part II. State of the Art,” IEEE Communications Magazine, vol. 25, no. 2, February 1987, pp. 1221. Other encoding schemes include block coding schemes such as ReedSolomon encoders, and BCH encoders, see, e.g., G. C. Clark, Jr., and J. B. Cain., Error Correction Coding for Digital Communications (Plenum Press, New York, 1981), however they result in an increase of channel bandwidth usage. Typically, the signal output from encoder 402 includes more bits than n_{k}, n_{k}+1e. In some embodiments, encoder 402 can be a trellis encoder which adds one additional bit, in other words encoder 402 can be a rate n_{k}/n_{k}+1 encoder, see, e.g., G. Ungerboeck., “Trellis Coding Modulation with Redundant Signal Sets, Part I. Introduction,” IEEE Communications Magazine, vol. 25, no. 2, Februray 1987, pp. 511, and G. Ungerboeck., “Trellis Coding Modulation with Redundant Signal Sets, Part II. State of the Art,” IEEE Communications Magazine, vol. 25, no. 2, February 1987, pp. 1221. In some embodiments, additional bits can be added to insure a minimum rate of transitions so that timing recovery can be efficiently accomplished at receiver 220p.

[0077]
[0077]FIG. 6A shows an embodiment of encoder 402. Encoder 402 of FIG. 6A is an n_{k}/n_{k}+1 trellis encoder. Encoder 402 of FIG. 6A performs a rate ½ convolutional coding on the mostsignificantbit (MSB) of the n_{k }bit input signal. The MSB is input to delay 601. The output signal from delay 601 is input to delay 602. The MSB and the output signal from delay 602 are input to XOR adder 603. The output from XOR adder 603 provides a coded bit. The MSB, the output signal from delay 601, and the output signal from delay 602 are XORed in adder 604 to provide another coded bit. The two coded bits are joined with the remaining n_{k}−1 bits to form a n_{k}+1 bit output signal. Delays 601 and 602 are each clocked at the symbol baud rate B. One skilled in the art will recognize that other embodiments of encoder 402 can be utilized with embodiments of this invention.

[0078]
In transmitter 212k of FIG. 4, the output signal from encoder 402 is input to symbol mapper 403. Symbol mapper 403 can include any symbol mapping scheme for mapping the parallel bit signal from encoder 402 onto symbol values for transmission. In some embodiments, symbol mapper 403 is a QAM mapper which maps the (n_{k}+le) bits from encoder 402 onto a symbol set with at least 2^{(n} ^{ k } ^{+le) }symbols. As shown in FIG. 6A, le=1 in the output signal from encoder 402. A trellis encoder in conjunction with a QAM mapper can provide a trellis encoded QAM modulation for subchannel 301k.

[0079]
[0079]FIG. 6B shows an embodiment of symbol mapper 403. Symbol mapper 403 receives the n_{k}+1 data bits from encoder 402 and generates a symbol, which can include an inphase component I_{k }and a quadrature component Q_{k}. In some embodiments, symbol mapper 403 includes a lookup table 605 which maps the n_{k}+1 input bits to the complex output symbol represented by I_{k }and Q_{k}.

[0080]
Table I shows an example symbol lookup table for conversion of a 7bit data signal into a 128symbol QAM scheme. Table entries are in decimal format with the inphase values along the bottom row and the quadrature values represented along the last column. From Table I, a decimal value of 96, for example, results in an I value of −1 and a Q value of −1.

[0081]
In some embodiments, encoder
402 could be a 16 state, rate 2/3 encoder, encoding the 2 most significant bits (MSBs) of the n
_{k }bit input signal. In general, any pair of bits could be chosen for encoding in this example. This 16 state encoder could determine its future state from the current state and the 2 incoming bits. If the old state is 4 bits, x=[x
3 x
2 x
1 x
0 ] and the incoming bits are [y
1 y
0], the next state could be 4 bits, z=[z
3 z
2 z
1 z
0]=[x
1 x
0 y
1 y
0]. The values x
3 and z
3 are the most significant bits (MSBs) of the state. The transition from the old state to the next state can define the 3 bit output of the encoder as shown in table II. In table II, the notation a
b, means that the transition from old_state=a to next_state=b. The encoded 3bits corresponding to that transition in this example is listed as the encoded value.

[0082]
The encoded output bits from encoder 402 are input to mapper 403. In an example where n_{k}=6 and le=1, 7 bits from encoder 402 are input to mapper 403. If encoder 402 is the 16 state, rate 2/3 encoder discussed above, the 3 bit output of encoder 402 can be the 3 MSBs and the 4 uncoded bits can be the least significant bits (LSBs). An example of mapper 403 can be found in table III.

[0083]
In some embodiments, a 16 symbol QAM scheme can be utilized. In those embodiments, 4 bits with no encoding (or 3 bits in an 3/4 encoding scheme) can be directly mapped onto 16 QAM symbols. In some embodiments, 4 bits can be encoded (with a 4/5 encoding scheme) into a 32 QAM symbol set. In general, any size symbol set can be utilized.

[0084]
In some embodiments, the QAM mapping can be segregated into groups of four as is shown in FIG. 6C. In some embodiments, with a 128 QAM system, then n_{k}+1 is 7 (referred to as 6/7 encoding). The two control bits from encoder 402 are arranged so that in groups of four symbols, the two control bits determine placement in the group. Control bits 00 and 11 and control bits 01 and 10 are in opposite comers of the groupings of four. This leads to a 6 dB gain in decoding at the receiver using this mapping scheme. Furthermore, the remaining five bits determine the actual grouping of four.

[0085]
The output signal from symbol mapper 403 can be a complex signal represented by inphase signal I_{k}(n) and a quadrature signal Q_{k}(n), where n represents the nth clock cycle of the clock signal CK1, whose frequency equals the baud rate B_{k}. Each of signals I_{k}(n) and Q_{k}(n) are digital signals representing the values of the symbols they represent. In some embodiments, a QAM mapper onto a constellation with 128 symbols can be utilized. An embodiment of a 128symbol QAM constellation is shown in Table I. Other constellations and mappings are well known to those skilled in the art, see, e.g., Bernard Sklar, Digital Communications, Fundamentals and Applications (PrenticeHall, Inc., 1988) and E. A. Lee and D. G. Messerschmitt, Digital Communications (Kluwer Academic Publishers, 1988). The number of distinct combinations of I_{k}(n) and Q_{k}(n), then, represents the number of symbols in the symbol set of the QAM mapping and their values represent the constellation of the QAM mapping. Further examples of QAM symbol sets include 16 QAM symbol sets (16QAM) and 4/5 encoded 32QAM symbol sets (4/5 encoded 32 QAM).

[0086]
The signals from symbol mapper 403, I_{k}(n) and Q_{k}(n), are input to digitaltoanalog converters (DACs) 406 and 407, respectively. DACs 406 and 407 operate at the same clock rate as symbol mapper 403. In some embodiments, therefore, DACs 406 and 407 are clocked at the symbol rate, which is the transmission clock frequency B_{k}.

[0087]
The analog output signals from DACs 406 and 407, represented by I_{k}(t) and Q_{k}(t), respectively, can be input to lowpass filters 408 and 409, respectively. Low pass filters 408 and 409 are analog filters that pass the symbols represented by I_{k}(t) and Q_{k}(t) in the base band while rejecting the multiple frequency range reflections of the base band signal. FIG. 6D shows a schematic diagram of the ideal requirements for filters 408 and 409. The filter function h(f) cuts off to include all of the base band signal while rejecting all of the higher frequency reflections of the base band signal created by DACs 406 and 407.

[0088]
An example embodiment of filters
408 and
409 can be described by a twozero, fivepole filter function of the form
$\begin{array}{cc}{H}_{\mathrm{TX}}\ue8a0\left(s\right)=\frac{{b}_{2}\ue89e{s}^{2}+{b}_{1}\ue89es+{b}_{0}}{{s}^{5}+{a}_{4}\ue89e{s}^{4}\ue89e\text{\hspace{1em}}\ue89e\cdots +{a}_{0}},& \left(2\right)\end{array}$

[0089]
where s=j(2πf) (j is {square root}{square root over (−1)}) and the coefficients b
_{2}, b
_{1}, b
_{0}, and a
_{4 }through a
_{0 }are the parameters of filters
408 and
409. The parameters for filters
408 and
409, then, can be found by minimizing the cost function
$\begin{array}{cc}{\int}_{0}^{\infty}\ue89e{\uf603{H}_{\mathrm{DAC}}\ue8a0\left(f\right)\ue89e{H}_{\mathrm{TX}}\ue8a0\left(s\right){H}_{\mathrm{RRC}}\ue8a0\left(f\right)\ue89e{\uf74d}^{\mathrm{j2\pi}\ue89e\text{\hspace{1em}}\ue89ef\ue89e\text{\hspace{1em}}\ue89e\tau}\uf604}^{2}\ue89eW\ue8a0\left(f\right)\ue89e\uf74cf,& \left(3\right)\end{array}$

[0090]
where H
_{DAC}(f) is the response of DACs
406 and
407, which can be given by
$\begin{array}{cc}{H}_{\mathrm{DAC}}\ue8a0\left(f\right)=\frac{\mathrm{sin}\ue8a0\left(\pi \ue89e\text{\hspace{1em}}\ue89e{\mathrm{fT}}_{k}\right)}{\pi \ue89e\text{\hspace{1em}}\ue89ef},& \left(4\right)\end{array}$

[0091]
where T_{k }is the symbol period, W(f) is a weighting function, H_{RRC}(f) is a target overall response and τ is the time delay on the target response. The cost function is minimized with respect to the parameters of the filter (e.g., coefficients b_{2}, b_{1}, b_{0}, and a_{4 }through a_{0}) and the time delay τ. FIG. 6E shows an example of a target overall response function H_{RRC}(f), which is a squareroot raised cosine function. The function H_{RRC}(f) can be determined by a parameter α_{k }along with the baud rate frequency 1/T_{k }(which is the baud rate B_{k }for transmitter 212k). The parameter α_{k }is the excess bandwidth of the target function H_{RRC}(f). In some embodiments, α_{k }can be set to 0. In some embodiments of the invention, α_{k }can be set to 0.6.

[0092]
The weight function W(f) can be chosen such that the stop band rejection of H_{TX}(s) is less than about −50 dB. Initially, W(f) can be chosen to be unity in the pass band frequency 0<f<(1+γ_{k})/2T_{k }and zero in the stop band frequency f>(1+γ_{k})/2T_{k}, where γ_{k }is the excess bandwidth factor of the kth channel. The minimization of the cost function of Equation 3 can be continued further by increasing W(f) in the stop band until the rejection of analog filters 408 and 409 is less than −50 dB.

[0093]
In some embodiments, the overall impulse response of the transmit signal is a convolution of the impulse response of DACs 406 and 407 and the impulse response of transmit analog filters 408 and 409, i.e.

h _{k} ^{Tx}(t)=h _{k} ^{f}(t){circle over (x)}h _{k} ^{DAC}(t), (5)

[0094]
where h_{k} ^{f}(t) is the response of the filter and h_{k} ^{DAC }(t) is the response of DACs 406 and 407. In some embodiments, the DAC response h_{k} ^{DAC }(t) is a sinc function in the frequency domain and a rectangular pulse in the time domain. As shown in Equation 5, the overall response is a convolution of filters 408 and 409 with the response of DACs 406 and 407. The overall filter response can be close to the target response H_{RRC}(f) when h_{k} ^{TX}(t) is determined with the cost function of Equation 3.

[0095]
The output signals from lowpass filters 408 and 409, designated I_{k} ^{LPF}(t) and Q_{k} ^{LPF}(t), respectively, are then upconverted to a center frequency f_{k }to generate the output signal of y_{k}(t), the kth channel signal. The output signal from lowpass filter 408, I_{k} ^{LPF}(t), is multiplied by cos(2πf_{k}t) in multiplier 410. The output signal from lowpass filter 409, Q_{k} ^{LPF}(t), is multiplied by sin(2πf_{k}t) in multiplier 411. The signal sin(2πf_{k}t) can be generated by PLL 414 based on the reference clock signal and the signal cos(2πf_{k}t) can be generated by a π/2 phase shifter 413.

[0096]
However, since mixers 410 and 411 are typically not ideal mixers and the harmonic sine wave input to mixer 410, and the resulting cosine wave input to mixer 411, often varies from a sine wave, signals having harmonics of the frequency f_{k }are also produced. Often, the harmonic signals input to mixers 410 and 411 may more closely resemble squarewave signals than harmonic sine wave signals. Even if the “sine wave input” is a true sine wave, the most commonly utilized mixers, such as Gilbert Cells, may act as a bandlimited switch, resulting in a harmonic signal with alternating positive and negative voltages with frequency the same as the “sine wave input” signal. Therefore, the output signals from filters 408 and 409 are still multiplied by signals that more closely resemble square waves than sine waves. As a result, signals having frequency 2f_{k}, 3f_{k}, . . . are also produced, as well as signals in the base band (0f_{k}). Although the amplitude of these signals may be attenuated with higher harmonics, they are nonnegligible in the output signal. Additionally, even harmonics (i.e., 0f_{k}, 2f_{k}, 4f_{k}. . . ) are absent if the duty cycle of the harmonic sine wave input to mixers is 50%. Otherwise, some component of all of the harmonics will be present.

[0097]
The output signals from multipliers
410 and
411 are summed in summer
412 to form
$\begin{array}{cc}\begin{array}{c}{y}_{k}\ue8a0\left(t\right)=\text{\hspace{1em}}\ue89e{\xi}_{k}^{0}\ue89e{I}_{k}^{\mathrm{LPF}}\ue8a0\left(t\right){\zeta}_{k}^{0}\ue89e{Q}_{k}^{\mathrm{LPF}}\ue89e\left(t\right)+\\ \text{\hspace{1em}}\ue89e\sum _{n>0}\ue89e\left({\xi}_{k}^{n}\ue89e{I}_{k}^{\mathrm{LPF}}\ue89e\mathrm{cos}\ue8a0\left(2\ue89e\pi \ue89e\text{\hspace{1em}}\ue89e{\mathrm{nf}}_{k}\ue89et\right){\zeta}_{k}^{n}\ue89e{Q}_{k}^{\mathrm{LPF}}\ue89e\mathrm{sin}\ue8a0\left(2\ue89e\pi \ue89e\text{\hspace{1em}}\ue89e{\mathrm{nf}}_{k}\ue89et\right)\right)\ue89e\text{\hspace{1em}}\ue89e\left(k\ge 1\right).\end{array}& \left(6\right)\end{array}$

[0098]
where ξ_{k} ^{n }and ζ_{k} ^{n }is the contribution of the nth harmonic to y_{k}(t). If the duty cycle of the harmonic input signals to mixers 410 and 411 is near 50%, the even harmonics are low and the odd harmonics are approximately given by ξ_{k} ^{n}=I_{k} ^{LPF}/n and ζ_{k} ^{n=Q} _{k} ^{LPF}/n for odd n.

[0099]
[0099]FIG. 11 shows an embodiment of baseband transmitter 217. Transmitter 217 may include a scrambler 1104 and encoder 1105. Scrambler 1104 can be similar to that described as scrambler 401 described above and functions to whiten the data. In some embodiments, scrambler 1104 may utilize a different function for scrambling the incoming bits than that described above as scrambler 401. Encoder 1105 can be similar to that described as encoder 402 above and encodes the n_{0 }bits input to transmitter 217 to n_{0}+l bits. The output signal from encoder 1105 is then input to symbol mapper 1101. Symbol mapper 1101 converts the n_{0}+l parallel bits into a symbol for transmission. In some embodiments, symbol mapper 1101 can be a PAM encoder. The PAM symbol set can be of any size. In some embodiments, for example, a 16 level symbol set (16PAM) can be utilized to represent n_{0}+l=4 parallel bits. Encoder 1105 can provide 3/4 encoding or no encoding. The output signal from symbol mapper 1101 is input to digitaltoanalog converter 1102 which converts the symbol set determined by symbol mapper 1101 into the corresponding output voltages.

[0100]
In some embodiments, the analog output signal from DAC 1102 is prefiltered through filter 1103. In some embodiments, filter 1103 may prepare the output signal for transmission through medium 250 (see FIG. 2A) so that the signal received by a receiver is corrected for distortions caused by the channel. For example, if the baseband channel of transmission medium 250 is known to have a transfer function of (1+D(z)), then filter 1103 may execute a transfer function equal to 1/(1+D(z)) in order to cancel the transfer function of transmission medium 250. The output signal from filter 1103 can be input to lowpass filter 1106. Filter 1106 removes the higher frequency content, which may interfere with transmissions on the higher frequency channels. The output signal from filter 1106 is the base band signal y_{0}(t). With a combination of low pass filter 1106 and high pass filter 215 coupled to summer 213, crosschannel interference between the base band channel, channel 3010, and higher frequency channels 3011 through 301K can be minimized or eliminated.

[0101]
The overall output of transmitter
210p (FIG. 2B), the output from summer
216, is then given by
$\begin{array}{cc}z\ue8a0\left(t\right)=\sum _{n=0}^{K}\ue89e{y}_{n}\ue8a0\left(t\right).& \left(7\right)\end{array}$

[0102]
In an example where the frequencies f
_{1 }through f
_{K }are given by frequencies f
_{0 }through (Kf
_{0}), respectively, then, the overall output signal z(t) is given by:
$\begin{array}{cc}\begin{array}{c}z\ue8a0\left(t\right)=\text{\hspace{1em}}\ue89e{y}_{0}\ue8a0\left(t\right)+\sum _{k=1}^{K}\ue89e\left({\xi}_{k}^{0}\ue89e{I}_{k}^{\mathrm{LPF}}\ue8a0\left(t\right){\zeta}_{k}^{0}\ue89e{Q}_{k}^{\mathrm{LPF}}\right)+\\ \text{\hspace{1em}}\ue89e{\xi}_{1}^{1}\ue89e{I}_{1}^{\mathrm{LPF}}\ue8a0\left(t\right)\ue89e\mathrm{cos}\ue89e\text{\hspace{1em}}\ue89e{\omega}_{0}\ue89et{\zeta}_{1}^{1}\ue89e{Q}_{1}^{\mathrm{LPF}}\ue8a0\left(t\right)\ue89e\mathrm{sin}\ue89e\text{\hspace{1em}}\ue89e{\omega}_{0}\ue89et+\\ \text{\hspace{1em}}\ue89e\left({\xi}_{1}^{2}\ue89e{I}_{1}^{\mathrm{LPF}}\ue8a0\left(t\right)+{\xi}_{2}^{1}\ue89e{I}_{2}^{\mathrm{LPF}}\ue8a0\left(t\right)\right)\ue89e\mathrm{cos}\ue89e\text{\hspace{1em}}\ue89e2\ue89e\text{\hspace{1em}}\ue89e{\omega}_{0}\ue89et\\ \text{\hspace{1em}}\ue89e\left({\zeta}_{1}^{2}\ue89e{Q}_{1}^{\mathrm{LPF}}\ue8a0\left(t\right)+{\zeta}_{2}^{1}\ue89e{Q}_{2}^{\mathrm{LPF}}\ue8a0\left(t\right)\right)\ue89e\mathrm{sin}\ue89e\text{\hspace{1em}}\ue89e2\ue89e{\omega}_{0}\ue89et+\\ \text{\hspace{1em}}\ue89e\left({\xi}_{1}^{3}\ue89e{I}_{1}^{\mathrm{LPF}}\ue8a0\left(t\right)+{\zeta}_{3}^{1}\ue89e{I}_{3}^{\mathrm{LPF}}\ue8a0\left(t\right)\right)\ue89e\mathrm{cos}\ue89e\text{\hspace{1em}}\ue89e3\ue89e{\omega}_{0}\ue89et\\ \text{\hspace{1em}}\ue89e\left({\zeta}_{1}^{3}\ue89e{Q}_{1}^{\mathrm{LPF}}\ue8a0\left(t\right)+{\zeta}_{3}^{1}\ue89e{Q}_{3}^{\mathrm{LPF}}\ue8a0\left(t\right)\right)\ue89e\mathrm{sin}\ue89e\text{\hspace{1em}}\ue89e3\ue89e{\omega}_{0}\ue89et+\\ \text{\hspace{1em}}\ue89e\left({\xi}_{1}^{4}\ue89e{I}_{1}^{\mathrm{LPF}}\ue8a0\left(t\right)+{\xi}_{2}^{2}\ue89e{I}_{2}^{\mathrm{LPF}}\ue8a0\left(t\right)+{\xi}_{4}^{1}\ue89e{I}_{4}^{\mathrm{LPF}}\ue8a0\left(t\right)\right)\ue89e\mathrm{cos}\ue89e\text{\hspace{1em}}\ue89e4\ue89e{\omega}_{0}\ue89et\\ \text{\hspace{1em}}\ue89e\left({\zeta}_{1}^{4}\ue89e{Q}_{1}^{\mathrm{LPF}}\ue8a0\left(t\right)+{\zeta}_{2}^{2}\ue89e{Q}_{2}^{\mathrm{LPF}}\ue8a0\left(t\right)+{\zeta}_{4}^{1}\ue89e{Q}_{4}^{\mathrm{LPF}}\ue8a0\left(t\right)\right)\ue89e\mathrm{cos}\ue89e\text{\hspace{1em}}\ue89e4\ue89e{\omega}_{0}\ue89et+\cdots \\ =\text{\hspace{1em}}\ue89e{y}_{0}\ue8a0\left(t\right)+\sum _{k=1}^{K}\ue89e\left({\xi}_{k}^{0}\ue89e{I}_{k}^{\mathrm{LPF}}\ue8a0\left(t\right){\zeta}_{k}^{0}\ue89e{Q}_{k}^{\mathrm{LPF}}\ue8a0\left(t\right)\right)+\\ \text{\hspace{1em}}\ue89e\sum _{M=1}^{\infty}\ue89e\sum _{\forall k,n\in {k}^{*}\ue89en=M}\ue89e\left({\xi}_{k}^{n}\ue89e{I}_{k}^{\mathrm{LPF}}\ue8a0\left(t\right)\ue89e\mathrm{cos}\ue89e\text{\hspace{1em}}\ue89eM\ue89e\text{\hspace{1em}}\ue89e{\omega}_{0}\ue89et{\zeta}_{k}^{n}\ue89e{Q}_{k}^{\mathrm{LPF}}\ue8a0\left(t\right)\ue89e\mathrm{sin}\ue89e\text{\hspace{1em}}\ue89eM\ue89e\text{\hspace{1em}}\ue89e{\omega}_{0}\ue89et\right)\end{array}& \left(8\right)\end{array}$

[0103]
where ω_{0 }is 2πf_{0 }and where I_{k} ^{LPF }(t) and Q_{k} ^{LPF }(t) are 0 for all k>K.

[0104]
As shown in Equation 8, the signal on channel one is replicated into all of higher K channels, the baseband, and into harmonic frequencies beyond the base band and the K channels. Filter 215 can remove the contribution to the baseband channel from transmitters 2121 through 212K. The signal on channel two, for example, is also transmitted on channels 4, 6, 8, . . . , and the baseband. The signal on channel 3 is transmitted on channels 6, 9, 12, . . . and the base band. In general, the signal on channel k will be mixed into channels 2k, 3k, . . . and the baseband. Further, the attenuation of the signals with higher harmonics in some systems can be such that the signal from channel k is non negligible for a large number of harmonics, potentially up to the bandwidth of the process, which can be 3040 GHz.

[0105]
In some embodiments of the invention, a high pass filter
215 (see FIG. 2B) receives the signal from summer
213. High pass filter
215 can, for example, be a firstorder highpass filter with 3 dB attenuation at f
_{1}/2. Filter
215 removes the DC harmonics, i.e. the baseband transmissions, from the transmitter. In embodiments with a separate baseband transmission, then, crosschannel coupling into the baseband is minimized or eliminated. Further, removing the baseband harmonics from the transmitted signals simplifies crosschannel cancellation at receiver
220p. In embodiments where high pass filter
215 exists, the baseband contribution from each of transmitters
212
1 through
212K,
$\sum _{k=1}^{K}\ue89e\left({\xi}_{k}^{0}\ue89e{I}_{k}^{\mathrm{LPF}}\ue8a0\left(t\right){\zeta}_{k}^{0}\ue89e{Q}_{k}^{\mathrm{LPF}}\ue8a0\left(t\right)\right),$

[0106]
is filtered out and becomes close to 0. The output signal from transmitter
210p then becomes
$\begin{array}{cc}{z}^{\prime}\ue8a0\left(t\right)={y}_{0}\ue8a0\left(t\right)+\sum _{M=1}^{\infty}\ue89e\sum _{\forall k,n\in {k}^{*}\ue89en=M}\ue89e\left({\xi}_{k}^{n}\ue89e{I}_{k}^{\mathrm{LPF}}\ue8a0\left(t\right)\ue89e\mathrm{cos}\ue89e\text{\hspace{1em}}\ue89eM\ue89e\text{\hspace{1em}}\ue89e{\omega}_{0}\ue89et{\zeta}_{k}^{n}\ue89e{Q}_{k}^{\mathrm{LPF}}\ue8a0\left(t\right)\ue89e\mathrm{sin}\ue89e\text{\hspace{1em}}\ue89eM\ue89e\text{\hspace{1em}}\ue89e{\omega}_{0}\ue89et\right).& \left(9\right)\end{array}$

[0107]
In some embodiments, B_{k }and γ_{k }can be the same for all channels and the center frequencies of channels 3011 through 301K, frequencies f_{1 }through f_{K}, respectively, can be chosen by

f _{k} =B _{k} k(1+γ_{k});1≦k≦K. (10)

[0108]
In some embodiments, other center frequencies can be chosen, for example:

f _{1}≧0.5B _{k}(1+γ_{k})

(f _{k} −f _{k−1})≧B _{k}(1+γ_{k});k≧2. (11)

[0109]
The parameter γ_{k }is the excess bandwidth factor. The bandwidth of the kth channel, then , is (1+γ_{k})B_{k}. In general, the center frequencies of channels 3011 through 301K can be any separated set of frequencies which substantially separate (i.e., minimizing overlap between channels) in frequency the transmission bands of transmission channels 3011 through 301K.

[0110]
In many embodiments, however, the frequencies f_{1 }through f_{K }are chosen as multiplies of a single frequency f_{0 }which can fulfill equations 10 and/or 11 and results in the harmonic mixing of channels as shown in Equation 8 and 9.

[0111]
In some embodiments of the invention, DACs 406 and 407 of the embodiment of transmitter 212k shown in FIG. 4 may be moved to receive the output of summer 412. Further, in some embodiments DACs 406 and 407 can be replaced by a single DAC to receive the output of summer 213. However, such DACs should have very high sampling rates. One advantage of utilizing highsampling rate DACs is that ideal mixing could take place and the number of harmonics that need to be cancelled can be greatly reduced or even eliminated.

[0112]
As an example, then, embodiments of transmitter 210p capable of 10 Gbps transmission can be formed. In that case, η=10, i.e., an overall throughput of 10 Gbps from the transmitter to the receiver. Some embodiments, for example, can have (K+1)=8 channels 3010 through 3017. Channels 3011 through 3017 can be 6/7 trellis encoded 128 QAM with the baud rate on each channel B_{k }being 1.25 GHz/6 or about 208.333 Msymbols/sec. Channel 3010, the baseband channel, can be PAM8 with no error correction coding (i.e., uncoded PAM8) with baud rate B_{0 }being 416.667 Msymbols/sec. In other words, n_{k}=6; 1≦k≦7 and encoder 402 is a 6/7 rate trellis encoder. In this example, channels 3011 thorugh 3017 can be transmitted at frequencies 2f_{0}, 3f_{0}, 4f_{0}, 5f_{0}, 6f_{0}, 7f_{0 }and 8f_{0}, respectively, where f_{0 }can be example, 1.5*B_{k }or 312.5 MHz.

[0113]
In another example embodiment, 10 Gbps (η=10) can utilize (K+1)=2 channels 3010 and 3011. Channel 3011 can be, for example, 16 QAM with no error correction coding (i.e., uncoded 16QAM) with baud rate B_{1 }of 1.25 GHz and Channel 3010 can be, for example, 16PAM with no error correction coding (i.e., uncoded 16PAM) with baud rate B_{0 }at 1.25 GHz. The baud rate for both the PAM channel and the QAM channel is then 1.25 Gsps. The throughput is 5 Gbps each for a total transmission rate of 10 Gbps. With an excess bandwidth of the channels of about 50%, the center frequency of the QAM channel can be f_{1}≧(1.5)*1.25 GHz or above about 1.8 GHz.

[0114]
In another example embodiment, 10 Gbps can utilize (K+1)=2 channels 3010 and 3011 as above with channel 3011 being a 4/5 trellis encoded 32 QAM with a baud rate B, of 1.25 GHz with channel 3010 being uncoded 16PAM with baud rate B_{0 }1.25 GHz. Again, the center frequency of channel 3011 can be f_{1}≧(1.5)*1.25 GHz or above about 1.8 GHz.

[0115]
In yet another example, (K+1)=6 channels, channels 3010 through 3015, can be utilized. Channels 3011 thorugh 3015 can be 6/7 trellis encoded 128QAM with baud rate B_{k }of 1.25 GHz/6 or 208 MHz. Channel 3010, the baseband channel, can be 3/4 encoded 16 PAM or uncoded 8PAM with baud rate B_{0}=1.25 GHz. The center frequencies of channels 3011 through 3015 can be 4f_{0}, 5f_{0}, 6f_{0}, 7f_{0}, and 8f_{0}, respectively, with f_{0 }being about 312.5 MHz.

[0116]
In some embodiments, DACs 406 and 407 of each of transmitters 2121 through 212K can each be 4 bit DACs. A schematic diagram of an embodiment of trellis encoder 402 and an embodiment of the resultant 128QAM constellation mapping are shown in FIGS. 6A, 6B, and 6C, respectively. An example of a 128 symbol QAM mapping table is shown as Table I. The above described trellis encoder 402, in this embodiment, provides an asymptotic coding gain of about 6 dB over uncoded 128QAM modulation with the same data rate, see, e.g., G. Ungerboeck., “Trellis Coding Modulation with Redundant Signal Sets, Part I. Introduction,” IEEE Communications Magazine, vol. 25, no. 2, February 1987, pp. 511, and G. Ungerboeck., “Trellis Coding Modulation with Redundant Signal Sets, Part II. State of the Art,” IEEE Communications Magazine, vol. 25, no. 2, February 1987, pp. 1221.

[0117]
[0117]FIG. 5A shows an example of one of receiver systems 220p where receiver system 220p is an arbitrary one of receiver systems 2201 through 220P of system 200. Receiver system 220p includes receivers 2211 through 221K and baseband receiver 223 to form a (K+1)channel receiver. As shown in FIG. 2C, the output signals from receiver input buffer 224, Z(t), is received in each of receivers 2221 through 222K and 223. The signal Z(t), then, is the transmitted signal z(t) after transmission through medium 250. As shown in FIG. 3, the attenuation of signals at each of the K carrier frequencies after transmission through medium 250 can be different. Additionally, the signal Z(t) suffers from intersymbol interference caused by the dispersive effects of medium 250. The dispersive effects cause the signals received within a particular timing cycle to be mixed with those signals at that carrier frequency received at previous timing cycles. Therefore, in addition to crosschannel interference effects caused by the harmonic generation in mixers of the transmitter (an arbitrary one of which being designated transmitter 210p), but also the signals for each channel are temporally mixed through dispersion effects in medium 250.

[0118]
Signal Z(t) is then received into each of receivers 2221 through 222K. As shown in FIG. 5A, receiver 222k, an arbitrary one of receivers 2221 through 222K, for example, receives the signal Z(t) into down converter 560k which, in the embodiment shown in FIG. 5A, down converts the channel transmitted at frequency f_{k }back into the baseband and recovers inphase and quadrature components Z_{k} ^{I }and Z_{k} ^{Q}, respectively.

[0119]
[0119]FIG. 5A shows an embodiment of downconverter 560k. Signal Z(t) is received in multipliers 501k and 502k where it is downconverted to baseband to obtain an inphase component Z_{k} ^{I }(t) and a quadrature component Z_{k} ^{Q }(t). Multiplier 501k multiplies signal Z(t) with cos(2π{circumflex over (f)}_{k}t) and multiplier 502k multiplies signal Z(t) with sin(2π{circumflex over (f)}_{k}t), where {circumflex over (f)}_{k }can be the locally generated estimate of the carrier center frequency f_{k }from the corresponding transmitter. The clock signals within component 201p an arbitrary one of components 2011 through 201P, which are generated based on the reference signal from PLL 230 as shown in FIG. 2A, will have the same frequencies. However, the frequencies between differing ones of components 2011 through 201P can be slightly different. Therefore, {f_{k}} denotes the set of frequencies at the transmitter and {{circumflex over (f)}_{k}} denotes the set of frequencies at the receiver.

[0120]
In some embodiments, component 201p is a slave component where the frequencies {{circumflex over (f)}_{k}} can be adjusted to match those of the component that includes the transmitter, which is also one of components 2011 through 201P. In some embodiments, component 201p is a master component, in which case the transmitter of the component communicating with component 201p adjusts frequencies {f^{k}} to match those of {{circumflex over (f)}_{k}}. Arbitration in any given communication link between receiver 220p of component 201p and a transmitter in one of the other of components 2011 through 201P can be accomplished in several ways. In some embodiments, priority may be set between pairs of components 2011 through 201P so that the master/slave relationship between those pairs is predetermined. In some embodiments, an overall system control chooses at the start of each communication which component is master and which is slave. In some embodiments, the two components may negotiate, for example by each randomly choosing one of the k channels on which to transmit and designating the one that transmits on the lowest numbered channel as master. In any event, in any transmission either the transmitter adjusts {f^{k}} or the receiver adjusts {{circumflex over (f)}_{k}} depending on which has been designated master and which slave upon start of the communications

[0121]
As shown in FIG. 5A, PLL 523 generates the clock signals for each of receivers 2221 through 222K and receiver 223 and, in particular, generates the sin(2π{circumflex over (f)}_{k}t) signal for receiver 222k. The cos(2π{circumflex over (f)}_{k}t) signal can be generated by π/2 phase shifter 524k. PLL 523 generates the sampling clock signal utilized in analog to digital converters (ADCs) 506k and 507k as well as other timing signals utilized in receivers 2221 through 222K and receiver 223. PLL 523 also generates an RX CLK signal for output with the n_{k }bit output signal from receiver 222k.

[0122]
Down converters 5601 through 560K also generate harmonics for very much the same reasons that harmonics are generated in transmitters 2121 through 212K. Therefore, down converter 560k will downconvert into the base band signals from signals having center frequencies 0, {circumflex over (f)}_{k}, 2 {circumflex over (f)}_{k}, 3 {circumflex over (f)}_{k}, . . . For example, if {circumflex over (f)}_{1 }through {circumflex over (f)}_{K }correspond to frequencies {circumflex over (f)}_{0 }through K {circumflex over (f)}_{0}, then the down conversion process for down converter 5601 will result in the output signals Z_{1 } ^{I }and Z_{1} ^{Q }including interference contributions from the received signals from all of the other channels. Additionally, the output signals Z_{2} ^{I }and Z_{2} ^{Q }include contributions from channels with frequencies 0, 2 {circumflex over (f)}_{0}, 4 {circumflex over (f)}_{0}, 6 {circumflex over (f)}_{0 }. . . and those channels with harmonics at these frequencies. For example, if a channel has a center frequency at 3f_{0 }and transmits a second harmonic at 6f_{0}, then the receiver will bring signals at 6 {circumflex over (f)}_{0 }back to the baseband by the third harmonic of the mixer for the channel at 2 {circumflex over (f)}_{0}. Therefore, signals from channel k=3 need to be cancelled from signals transmitted on channel k=2. Each of the channels also include the crosschannel interference generated by the transmitter mixers and the dispersive interference created by the channel. If the baseband component of the harmonics is not filtered in filter 215 (FIG. 2B) out between the transmit and receive mixers, then every channel could put a copy of its transmit signal onto the baseband and every channel will receive the baseband signal at the receive side.

[0123]
PLL 523 can be a freerunning loop generating clock signals for receiver 222k based on a reference clock signal. In some embodiments transmitter 212k of transmitter and demodulator 222k of the receiver system 220p because they are part of different ones of components 2011 through 201P, are at different clock signals. This means that the digital PLLs for timing recovery and carrier recovery correct both phase and frequency offsets between the transmitter clock signals and receiver clock signals. Within one of components 2011 through 201P, a transmitter/receiver pair (i.e., transmitter 210p and receiver 220p of component 201p) can operate with the same PLL and therefore will operate with the same clock signals. Components 201i and 201j, where i and j refer to different ones of components 2011 through 201P, in general may operate at different clock signal frequencies.

[0124]
Therefore, in some embodiments the signals Z_{k} ^{I }and Z_{k} ^{Q }output from down converter 560k suffer the effects of crosschannel interference resulting from harmonic generation in the transmitter mixers, the effects of crosschannel interference resulting from harmonic generation in the receiver mixers, and the effects of temporal, intersymbol interference, resulting from dispersion in the transport media. As an additional complicating factor, in some embodiments the transmitter and receiver clocks can be different. Therefore, as an example, in embodiments where f_{1 }through f_{K }of the transmitter correspond to frequencies f_{0 }through Kf_{0}, respectively, then {circumflex over (f)}_{1 }through {circumflex over (f)}_{K }of the receiver will correspond to frequencies (f_{0}+Δ) through K(f_{0}+Δ), where Δ represents the frequency shift between PLL 523 of receiver 220p and the PLL of the transmitter component. The transmitter mixers then cause crosschannel interference by mixing the signals transmitted at frequency f_{k }into 2f_{k}, 3f_{k }. . . (2kf_{0}, 3kf_{0 }. . . in one example). The receiver mixers cause crosschannel interference by downconverting the signals received at {circumflex over (f)}_{k}, 2 {circumflex over (f)}_{k}, 3 {circumflex over (f)}_{k }. . . to the baseband. If the frequencies {circumflex over (f)}_{0 }is f_{0}+Δ, then the harmonics will be downconverted to a baseband shifted in frequency by kΔ, 2kΔ, 3kΔ, . . . , respectively.

[0125]
In some embodiments of the invention, receiver 220p includes a frequency shift 563 which supplies a reference clock signal to PLL 523. The reference clock signal supplied to PLL 523 can be frequency shifted so that Δ becomes 0. The frequency supplied to PLL 523 by frequency shift 563 can be digitally created and the input parameters to frequency shift 563 can be adaptively chosen to match the receiver frequency with the transmitter frequency. Embodiments of frequency adjustments in frequency shift 563 and PLL 523 are further discussed below.

[0126]
As shown in FIG. 5A, the output signals from downconverter 560k, Z_{k} ^{I }and Z_{k} ^{Q}, are input to analog filter 5612. An embodiment of analog filter 5612 is shown in FIG. 5C. The signals Z_{k} ^{I }and Z_{k} ^{Q }are input to offset corrections 530k and 531k, respectively. DC offset corrections 530k and 531k provide a DC offset for each of the outputs Z_{k} ^{I }and Z_{k} ^{Q }from downconverter 560k to correct for any leakage onto signal Z(t) from the sine and cosine signals provided by PLL 523, plus any DC offset in filters 504k and 505k and ADCs 506k and 507k. Leakage onto Z(t) can, in some cases, provide a significant DC signal component of the output signals Z_{k} ^{I }and Z_{k} ^{Q }from downconverter 560k. In some embodiments, offsets 530k and 531k can offset by the same amount. In some embodiments, different offset values, DCOI and DCOQ in FIG. 5C, can be provided for each of the output signals Z_{k} ^{I }and Z_{k} ^{Q }from downconverter 560k. The DC offset values can be adaptively chosen in blocks 543k and 544k. In some embodiments, after an initial startup procedure, the DC offset values are fixed.

[0127]
In some embodiments, the DC offsets, DCOI and DCOQ inputs to offsets 530k and 531k, respectively, can be generated by providing a low frequency integration of the output signal from analogtodigital converters (ADCs) 506k and 507k (FIG. 5A). In FIG. 5C, for example, lowfrequency integrator 543k receives the output signal from of ADC 506k, R_{k} ^{I}, and provides the DCOI input signal to offset 530k; integrator 544k receives the output signal from ADC 507k, R_{k} ^{Q}, and provides the DCOQ input signal to offset 531k. The low frequency integration of integrators 544k and 543k provides signals that set the average output signal of each of ADCs 506k and 507k to zero. In some embodiments of the invention, integrators 543k and 544k hold the offset values DCOI and DCOQ, respectively, constant after a set period time of integration when receiver 222k is first started.

[0128]
The output signals Z_{k} ^{I }and Z_{k} ^{Q }from downconverter 560k, or from offsets 530k and 531k in embodiments with offsets, can be input to lowpass filters 504k and 505k. Lowpass filters 504k and 505k are analog filters that filter out signals not associated with the baseband signal (i.e., signals from the remaining bands of transmitter 210p) for the kth transmission band. Low pass filters 504k and 505k, however, do not remove the interference caused by harmonic generation in transmit and receive mixers involved in the upconversion and downconversion process.

[0129]
Filters
504k and
505k again, in some embodiments, can be parameterized by the twozero, fivepole filter design described by Equation 2,
$\begin{array}{cc}{H}_{\mathrm{RX}}\ue8a0\left(s\right)=\frac{{b}_{2}\ue89e{s}^{2}+{b}_{1}\ue89es+{b}_{0}}{{s}^{5}+{a}_{4}\ue89e{s}^{4}+\dots +{a}_{0}}.& \left(12\right)\end{array}$

[0130]
Furthermore, the parameters b
_{2}, b
_{1}, b
_{0}, and a
_{4 }through a
_{0 }can be found by minimizing the cost function
$\begin{array}{cc}{\int}_{0}^{\infty}\ue89e{\uf603{H}_{\mathrm{RX}}\ue8a0\left(s\right){H}_{\mathrm{RRC}}\ue8a0\left(f\right)\ue89e{\uf74d}^{j\ue89e\text{\hspace{1em}}\ue89e2\ue89e\text{\hspace{1em}}\ue89e\pi \ue89e\text{\hspace{1em}}\ue89ef\ue89e\text{\hspace{1em}}\ue89e\tau}\uf604}^{2}\ue89eW\ue8a0\left(f\right)\ue89e\uf74cf.& \left(13\right)\end{array}$

[0131]
The cost function is minimized with respect to the parameters of the filter and the time delay τ. Again in Equation 13, the weighting function W(f) can be chosen such that the stop band rejection of H_{RX}(s) is less than −50 dB. Furthermore, the function H_{RRC}(f) is the square root raised cosine function shown in FIG. 6E. As shown in FIG. 6E, the function H_{RRC}(f) is characterized by a parameter α_{k }and baud frequency 1/T_{k}. The parameter α_{k }is the excess bandwidth of the target function H_{RRC}(f). In some embodiments, α_{k }can be 0. In some embodiments, α_{k }can be 0.6. In general, the parameter α_{k }can be any value, with smaller values providing better filtering but larger values being easier to implement. The parameter T_{k }is related to the baud rate, T_{k}=1/B_{k}.

[0132]
In some embodiments ofthe invention, filters
504k and
505k can be determined by minimizing the function
$\begin{array}{cc}{\int}_{0}^{\infty}\ue89e{\uf603{H}_{\mathrm{DAC}}\ue8a0\left(f\right)\ue89e{H}_{\mathrm{TX}}\ue8a0\left(s\right)\ue89e{H}_{\mathrm{RX}}\ue8a0\left(s\right){H}_{\mathrm{RC}}\ue8a0\left(f\right)\ue89e{\uf74d}^{j\ue89e\text{\hspace{1em}}\ue89e2\ue89e\text{\hspace{1em}}\ue89e\pi \ue89e\text{\hspace{1em}}\ue89ef\ue89e\text{\hspace{1em}}\ue89e\tau}\uf604}^{2}\ue89eW\ue8a0\left(f\right)\ue89e\uf74cf,& \left(14\right)\end{array}$

[0133]
where the function H_{RC}(f) is a squareroot raised cosine function. The function H_{RC}(f) is characterized by the parameters α_{k }and 1/T_{k}. Equation 14 includes the effects of the transmit digital to analog converters 406 and 407 (FIG. 4) as well as the analog transmit filters 408 and 409 (FIG. 4) to set the overall response of filters 408 and 409, filters 504k and 505k, and transmitter digital to analog converters 406 and 407 to the target response function H_{RC}(f). In some embodiments, H_{TX}(f) and H_{RX}(f) can be the same.

[0134]
The output signals from lowpass filters 504k and 505k can, in some embodiments, be amplified in variable gain amplifiers 521k and 522k, respectively. In some embodiments, the gains g_{k} ^{1(I) }and g_{k} ^{1(Q) }of amplifiers 521k and 522k, respectively, are set such that the dynamic range of analogtodigital converters 506k and 507k, respectively, is filled. The output signals from amplifiers 521k and 522k, then, are

r _{k} ^{I}(t)=LPF[Z(t)cos(2π{circumflex over (f)} _{k} t)]g _{k} ^{1(I)}

r _{k} ^{Q}(t)=LPF[Z(t)sin(2π{circumflex over (f)} _{k} t)]g _{k} ^{1(Q)}, (15)

[0135]
where g_{k} ^{1(I) }and g_{k} ^{1(Q) }represents the gain of amplifiers 521k and 522k, respectively. The gains of amplifiers 521k and 522k can be set in an automatic gain control circuit (AGC) 520k. An embodiment of automatic gain circuit 520k where g_{k} ^{1(I) }and g_{k} ^{1(Q) }are set equal to one another is shown in FIGS. 8A and 8B. In some embodiments, amplifiers 521k and 522k can be before or incorporated within filters 504k and 505k, respectively.

[0136]
As shown in FIG. 5A, the signals output from analog filter 561k, signals r_{k} ^{I}(t) and r_{k} ^{Q}(t), are input to analogtodigital converters (ADC) 506k and 507k, respectively, which forms digitized signals R_{k} ^{I}(t) and R_{k} ^{Q}(t) corresponding with the analog signals r_{k} ^{I}(t) and r_{k} ^{Q}(t), respectively. In some embodiments, ADCs 506k and 507k operate at a sampling rate that is the same as the transmission symbol rate, e.g. the QAM symbol rate. In some embodiments, ADCs 506k and 507k can operate at higher rates, for example twice the QAM symbol rate. The timing clock signal SCLK, as well as the sine and cosine functions of Equation 15, is determined by PLL 523. In outputs with η=10, K=8, and n_{k}=6, as described above, ADCs 506k and 507k can operate at a rate of about 208 Msymbols/sec or, in embodiments with K=16, about 104 Msymbols/sec. In some embodiments, ADCs 506k and 507k can be 8bit ADCs. However, for 128 QAM operation, anything more than 7 bits can be utilized.

[0137]
In some embodiments, the gain of amplifiers 521k and 522k of analog filters 560k can be set by automatic gain control circuit (AGC) 520k (see FIG. 5C). Gain control circuit 520k can receive the digital output signals from ADCs 506k and 507k, R_{k} ^{I}(n) and R_{k} ^{Q}(n), respectively, and determines the gain g^{1} _{k}(n+1) for each of amplifiers 521k and 522k (i.e., in this embodiment g^{1(I)} _{k}(n) and g^{1(Q)} _{k}(n) are equal). FIGS. 8A and 8B show some embodiments of AGC 520k. The embodiment of AGC 520k shown in FIG. 8A includes an AGC phase detector 801 and an integrator 802. Phase detector 801 estimates whether or not the meansquaredpower of signals R_{k} ^{I}(t) and R_{k} ^{Q}(t) are at a predetermined threshold value and, if not, provides a correction signal to adjust the amplitudes of signals r_{k} ^{I(t) }and r_{k} ^{Q}(t). The output signal from phase detector 801 can be given by

p _{k} ^{g}(n)=[G _{th}−(R _{k} ^{I}(n)^{2} +R _{k} ^{Q}(n)^{2})], (16)

[0138]
where G_{th }is the mean squared power of the signals input to ADCs 506k and 507k once AGC 520k converges. The output signal from phase detector 801, p_{k} ^{g}(n), is then input to integrator 802. Integrator 802 digitally adjusts the gain g_{k }according to

g _{k} ^{1}(n+1)=g _{k} ^{1}(n)+α_{g} p _{k} ^{g}(n), (17)

[0139]
where α_{g }determines the rate of adaptation of the AGC algorithm. The constant α_{g }can be chosen to be a negative power of 2 for ease of implementation.

[0140]
The embodiment of phase detector 520k shown in FIG. 8B includes two phase detectors 803 and 804 which calculate the mean squared powers of R_{k} ^{I}(n) and R_{k} ^{Q}(n) separately and compare them with thresholds G_{th} ^{I }and G_{th} ^{Q}, respectively. The output signals from phase detectors 803 and 804 can be given by

p _{k} ^{g−I}(n)=[G _{th} ^{I}−(R _{k} ^{I}(n)^{2})]

p _{k} ^{g−Q}(n)=[G _{th} ^{Q}−(R _{k} ^{Q}(n)^{2})], (18)

[0141]
respectively. The output signals from detectors 803 and 804 can then be integrated in integrators 805 and 806 according to

g _{k} ^{1−I}(n+1)=g _{k} ^{1−I}(n)+α_{g} ^{I} p _{k} ^{g−I}(n),

[0142]
and

g _{k} ^{1−Q}(n+1)=g _{k} ^{1−Q}(n)+α_{g} ^{Q} p _{k} ^{g−Q}(n), (19)

[0143]
where α_{g} ^{I }and α_{g} ^{Q }determine the rate of adaptation of the AGC algorithm as in Equation 17 above.

[0144]
In some embodiments AGC 520k can include a peak detection algorithm so that the gain values g_{k} ^{1(I) }and g_{k} ^{1(Q) }are determined from the peak values of R_{k} ^{I }and R_{k} ^{Q}, respectively. Again, the peak values of R_{k} ^{I }and R_{k} ^{Q }can be compared with threshold values and the gain values g_{k} ^{1(I) }and g_{k} ^{1(Q) }adjusted accordingly.

[0145]
As shown in FIG. 5A, the output signals from ADCs
506k and
507k, R
_{k} ^{I }and R
_{k} ^{Q}, respectively, are input to a first digital filter
562k. An embodiment of first digital filter
562k is shown in FIG. 5D. In some embodiments of the invention, the inphase and quadrature data paths may suffer from small differences in phase and small differences in gain. Therefore, in some embodiments a phase and amplitude correction is included in digital filter
562k. In order to correct the phase and amplitude between the inphase and quadrature data paths, one of the values R
_{k} ^{I}(n) and R
_{k} ^{Q}(n) is assumed to be of the correct phase and amplitude. The opposite value is then corrected. In the embodiment shown in FIG. 5D, R
_{k} ^{I}(n) is assumed to be correct and R
_{k} ^{Q}(n) is corrected. The phase error can be corrected by using the approximation for small θ
_{k} ^{c }where sin θ
_{k} ^{c }is approximately θ
_{k} ^{c}, and cos θ
_{k} ^{c }is approximately one. This correction can be implemented by subtracting in summer
536k the value θ
_{k} ^{c}R
_{k} ^{I}(n) calculated in multiplier
535k to R
_{k} ^{Q}(n). The amplitude of R
_{k} ^{Q}(n) can be corrected by adding a small portion η
_{k} ^{c }of R
_{k} ^{Q}(n), calculated in multiplier
533k, in summer
536k. The value η
_{k} ^{c }can be determined in tracking and recovery block
517k by integrating the difference in magnitude of the output signals from summer
534k and
536k, F
_{k} ^{I}(n) and F
_{k} ^{Q}(n), in a very low frequency integration block (for example several kHz), such that
$\begin{array}{cc}{\eta}_{k}^{c}=\int \left(\uf603{F}_{k}^{I}\ue8a0\left(n\right)\uf604\uf603{F}_{k}^{Q}\ue8a0\left(n\right)\uf604\right)\ue89e\uf74cn.& \left(20\right)\end{array}$

[0146]
The value θ
_{k} ^{c }can be chosen in tracking and recovery block
517k by
$\begin{array}{cc}{\theta}_{k}^{c}=\int \left(\mathrm{sign}\ue89e\text{\hspace{1em}}\ue89e\left({F}_{k}^{I}\ue8a0\left(n\right)\right)\ue89e{F}_{k}^{Q}\ue8a0\left(n\right)+\mathrm{sign}\ue89e\text{\hspace{1em}}\ue89e\left({F}_{k}^{Q}\ue8a0\left(n\right)\right)\ue89e{F}_{k}^{I}\ue8a0\left(n\right)\right)\ue89e\uf74cn.& \left(21\right)\end{array}$

[0147]
Additionally, an arithmetic offset can be implemented by subtracting the value OFFSET_{1} ^{I }in summer 534k to R_{k} ^{I}(n) and subtracting the value OFFSET_{1} ^{Q }in summer 536k. The offset values OFFSET_{1} ^{I }and OFFSET_{1} ^{Q }can be adaptively chosen in tracking and recovery block 517k by integrating the output signals from summer 534k and summer 536k, F_{k} ^{I}(n) and F_{k} ^{Q}(n), respectively, in a low frequency integration. The offsets implemented in summer 534k and 536k offset the dc offset not corrected in analog filter 561k, e.g. by offsets 530k and 531k, for example, as well as arithmetic errors in summers 534k, 536k and multipliers 535k and 533k.

[0148]
The output signals from summers 534k and 536k, then, can be given by

F _{k} ^{I}(n)=R _{k} ^{I}(n)−OFFSET_{1,k} ^{I},

[0149]
and

F _{k} ^{Q}(n)=(1+η_{k} ^{c})R _{k} ^{Q}(n)−θ_{k} ^{c} R _{k} ^{I}(n)−OFFSET_{1,k} ^{Q}. (22)

[0150]
In some embodiments, the parameters OFFSET_{1,k} ^{I}, OFFSET_{1,k} ^{Q}, η_{k} ^{c }and θ_{k} ^{c }vary for each cycle n. Additionally, the parameters can be different for each of the k receivers 2221 through 222k.

[0151]
The output signals from summers 534k and 536k, F_{k} ^{I}(n) and F_{k} ^{Q}(n), respectively, are then input to a phase rotation circuit 512k. Phase rotation 512k rotates signals F_{k} ^{I}(n) and F_{k} ^{Q}(n) according to the output of a carrier phase and frequency offset correction circuit, which depends on the difference between {circumflex over (f)}_{k }and f_{k}, and the relative phase of the transmit mixers (multipliers 410 and 411) and the receive mixers (multipliers 501k and 502k) and transmission channel 250 (FIG. 2A). The rotation angle θ^ _{k} ^{I}(n) is computed in carrier tracking and timing recovery block 517. The resultant output signals of carrier phase rotation circuit 512, D_{k} ^{I}(n) and D_{k} ^{Q}(n), can be given by:

D _{k} ^{I}(n)=F _{k} ^{I}(n)cos({circumflex over (θ)}_{k} ^{I}(n))+F _{k} ^{Q}(n)sin(θ^ _{k} ^{I}(n))

D _{k} ^{Q}(n)=F _{k} ^{Q}(n)cos({circumflex over (θ)}_{k} ^{I}(n))−F _{k} ^{I}(n)sin(θ^ _{k} ^{I}(n)). (23)

[0152]
The output signals from rotation circuit 512k, D_{k} ^{I}(n) and D_{k} ^{Q}(n), are then input to a complex adaptive equalizer 513k to counter the intersymbol interference caused by frequency dependent channel attenuation, and the reflections due to connectors and vias that exist in communication system 200 (which can be a backplane communication system, an intercabinet communication system, or a chiptochip communication system) and both transmit and receive low pass filters, e.g. filters 408 and 409 of FIG. 4 and filters 504k and 505k of FIG. 5C.

[0153]
It should be noted that because of the frequency division multiplexing of data signals, as is accomplished in transmitter system 210p and receiver system 220p, the amount of equalization needed in any one of channels 3010 through 301K is minimal. In some embodiments, such as the 16channel, 6 bit per channel, 10 Gbps example, only about 12 dB of transmission channel magnitude distortion needs to be equalized. In 8 channel embodiments, 34 dB of distortion needs to be equalized. In other words, the number of taps required in a transport function for equalizer 513k can be minimal (e.g., 14 complex taps) in some embodiments of the present invention, which can simplify receiver 220p considerably. In some embodiments of the invention, equalizer 513 can have any number of taps.

[0154]
Complex Equalizer 513k can be either a linear equalizer (i.e., having a feedforward section only) or a decision feedback equalizer (i.e., having a feedforward and a feedback portion). The coefficients of the equalizer transfer function are complexvalued and can be adaptive. In some embodiments, the complex equalizer coefficients that operate on signals D_{k} ^{I }and D_{k} ^{Q }are the same, but in other embodiments the complex equalizer coefficients are allowed to be different for D_{k} ^{I }and D_{k} ^{Q}.

[0155]
Additionally, the feedforward portion of an adaptive equalizer (either a linear equalizer or decision feedback equalizer) can be preceded by a nonadaptive allpole filter with transfer function 1/A(z). In some embodiments, the coefficients of A(z), which can be found by a minimum mean squared error technique, can be realvalued, for example

A(Z)=1.0+0.75Z ^{−1}+0.0625Z ^{−2}+0.0234375Z ^{−3}+0.09375Z ^{−4}, (24)

[0156]
which can be rewritten as
$\begin{array}{cc}A\ue8a0\left(Z\right)=1+0.75\ue89e{Z}^{1}+\frac{1}{16}\ue89e{Z}^{2}+\left(\frac{1}{64}+\frac{1}{128}\right)\ue89e{Z}^{3}+\left(\frac{1}{16}+\frac{1}{32}\right)\ue89e{Z}^{4}.& \left(25\right)\end{array}$

[0157]
The resulting transfer function H(z)=1/A(z) can be implemented in a linear equalizer or a decision feedback equalizer. In some embodiments, however, complex adaptive equalizer 513k includes adaptively chosen parameters.

[0158]
In general, complex adaptive equalizer
513k can be a decision feedback equalizer (DFE) or a linear equalizer. See, e.g., Edward A. Lee, and David G. Messerschmitt, Digital Communication, pp. 371402 (Kluwer Academic Publishers, 1988). The inphase and quadrature output signals from adaptive equalizer
513 in embodiments with linear equalization can be given by:
$\begin{array}{cc}{E}_{k}^{I}\ue8a0\left(n\right)=\sum _{j=M}^{N}\ue89e{C}_{k}^{x,I}\ue8a0\left(j,n\right)\ue89e{D}_{k}^{I}\ue8a0\left(nj\right){C}_{k}^{y,I}\ue8a0\left(j,n\right)\ue89e{D}_{k}^{Q}\ue8a0\left(nj\right)\ue89e\text{}\ue89e\mathrm{and}\ue89e\text{}\ue89e{E}_{k}^{Q}\ue8a0\left(n\right)=\sum _{j=M}^{N}\ue89e{C}_{k}^{x,Q}\ue8a0\left(j,n\right)\ue89e{D}_{k}^{Q}\ue8a0\left(nj\right)+{C}_{k}^{y,Q}\ue8a0\left(j,n\right)\ue89e{D}_{k}^{I}\ue8a0\left(nj\right).& \left(26\right)\end{array}$

[0159]
where j refers to the tap Z^{31 j}. The complex adaptive equalizer coefficients C_{k} ^{x,I}(j,n), C_{k} ^{y,I}(j,n), C_{k} ^{x,Q}(j,n) and C_{k} ^{y,Q }(j,n) can be updated according to the least mean squares (LMS) algorithm as described in Bernard Sklar, Digital Communications, Fundamentals and Applications (PrenticeHall, Inc.,1988), for example. In some embodiments, equalizer coefficients C_{k} ^{x,I}(j,n) and C_{k} ^{x,Q}(j,n) are the same and equalizer coefficients C_{k} ^{y,Q}(j,n) and C_{k} ^{y,Q}(j,n) are the same.

[0160]
In some embodiments of the invention, the center coefficients of the feedforward part of equalizer 513k, C_{k} ^{x,I}(0,n), C_{k} ^{y,I}(0,n), C_{k} ^{x,Q}(0,n) and C_{k} ^{y,Q}(0,n) can each be fixed at 1 and 0, respectively, to avoid interaction with the adaptation of gain coefficients g_{k} ^{2(I) }and g_{k} ^{2(Q) }used in amplifiers 537k and 538k of a second digital filter 563k and the carrier phase correction performed in phase rotator 512k. Additionally, in some embodiments the coefficients C_{k} ^{x,I}(−1,n), C_{k} ^{y,I}(−1,n), C_{k} ^{x,Q}(−1,n) and C_{k} ^{y,Q}(−1,n) can be fixed at constant values to avoid interaction with the adaptation of the phase parameter τ^ _{k }by tracking and timing recovery 517k. For example, the parameters C_{k} ^{x,I}(−1,n) and C_{k} ^{x,Q}(−1,n) can be −¼{fraction (1/16)}, which is −0.3125, and the parameters C_{k} ^{y,I}(−1,n) and C_{k} ^{y,Q}(−1,n) can be −{fraction (1/64)}, which is −0.015625. In some embodiments, one set of parameters, for example C_{k} ^{x,I}(−1,n) and C_{k} ^{x,Q}(−1,n), are fixed while the other set of parameters, for example C_{k} ^{y,I}(−1,n) and C_{k} ^{y,Q}(−1,n), can be adaptively chosen.

[0161]
In some embodiments of the invention, for example, C_{k} ^{x,I}(−1,n) and C_{k} ^{y,I}(−1,n) are fixed and the timing recover loop of adaptive parameters 5172 for determining the phase parameter τ^ _{k }utilizes errors e_{k} ^{I }only (see FIG. 7). In that way, adaptively choosing parameters in the Q channel do not interact with the timing loop. In some embodiments, the opposite can be utilized (i.e., C_{k} ^{x,Q}(−1,n) and C_{k} ^{y,Q}(−1,n) are fixed and the timing loop determines the phase parameter τ^ _{k }from error parameter e_{k} ^{Q}).

[0162]
The output signals from each of digital filters 5621 through 562K, signals E_{1} ^{I}(n) and E_{1} ^{Q}(n) through E_{K} ^{I}(n) and E_{K} ^{Q}(n), respectively, are input to crosschannel interference filter 570. Crosschannel interference canceller 570 removes the effects of crosschannel interference. Crosschannel interference can result, for example, from harmonic generation in the transmitter and receiver mixers, as has been previously discussed. As described in the embodiment of digital filter 562k shown in FIG. 5D, equalization for intersymbol interference can be performed in digital filter 562k. In some embodiments of the invention, crosschannel interference filter 570 may be placed before equalizer 513k (in other words, equalizer 513k may be placed in digital filter 5632 instead of digital filter 5622).

[0163]
The output signals from digital filter 5622, E_{k} ^{I}(n) and E_{k} ^{Q}(n), for each of receivers 2221 through 222K are input to crosschannel interference filter 570. An embodiment of crosschannel interference canceller 570 is shown in FIG. 5F. For convenience of discussion, the input signals E_{k} ^{I}(n) and E_{k} ^{Q}(n) are combined into a complex value E_{k}(n)=E_{k} ^{I}(n)+iE_{k} ^{Q}(n) (where i is {square root}{square root over (−1)}). Each of the complex values E_{1 }through E_{K }is input to a summer 5711 through 571K, respectively, where contributions from all of the other channels are removed. The output signals from summers 5711 through 571K, H_{1 }through H_{K}, respectively, are the output signals from crosschannel interference filter 570. Again, the complex value H_{k}(n) is H_{k} ^{1}(n)+iH_{k} ^{Q}(n), representing the inphase and quadrature output signals.

[0164]
The signal E
_{k }is also input to blocks
572k,
1 through
572k,k−1 and blocks
572k,k+1 to
572k,K. Block
572k,l, an arbitrary one of blocks
572
1,
2 through
572K, K−1, performs a transfer function Q
_{k,l }which determines the amount of signal E
_{k }which should be removed from E
_{l }to form H
_{l}. Further, delays
573
1 through
573K delay signals E
_{1 }through E
_{K }for a set number of cycles N to center the cancellations in time. Therefore, the output signals H
_{1 }through H
_{K }can be determined as
$\begin{array}{cc}\left(\begin{array}{c}{H}_{1}\\ {H}_{2}\\ \vdots \\ {H}_{k}\\ \vdots \\ {H}_{K}\end{array}\right)=\left(\begin{array}{cccccc}{Z}^{N}& 0& \cdots & 0& \cdots & 0\\ 0& {Z}^{N}& \cdots & 0& \cdots & 0\\ \vdots & \vdots & \u22f0& \vdots & \cdots & \vdots \\ 0& 0& \cdots & {Z}^{N}& \cdots & 0\\ \vdots & \vdots & \cdots & \vdots & \u22f0& \vdots \\ 0& 0& \cdots & 0& \cdots & {Z}^{N}\end{array}\right)\ue89e\left(\begin{array}{c}{E}_{1}\\ {E}_{2}\\ \vdots \\ {E}_{k}\\ \vdots \\ {E}_{K}\end{array}\right)\left(\begin{array}{cccccc}0& {Q}_{2,1}& \cdots & {Q}_{k,1}& \cdots & {Q}_{K,1}\\ {Q}_{1,2}& 0& \cdots & {Q}_{k,2}& \cdots & {Q}_{K,2}\\ \vdots & \vdots & \u22f0& \vdots & \vdots & \vdots \\ {Q}_{1,k}& {Q}_{2,k}& \cdots & 0& \cdots & {Q}_{K,k}\\ \vdots & \vdots & \vdots & \vdots & \u22f0& \vdots \\ {Q}_{1,K}& {Q}_{2,K}& \cdots & {Q}_{k,K}& \cdots & 0\end{array}\right)\ue89e\left(\begin{array}{c}{E}_{1}\\ {E}_{2}\\ \vdots \\ {E}_{k}\\ \vdots \\ {E}_{K}\end{array}\right),& \left(27\right)\end{array}$

[0165]
where Z^{−1 }represents a once cycle delay. The transfer functions Q_{k,l }can have any number of taps and, in general, can be given by

Q _{k,l}=σ_{k,l} ^{0}+σ_{k,l} ^{1} Z ^{−1}+σ_{k,l} ^{2} Z ^{−2}+ . . . +σ_{k,l} ^{M} Z ^{−M}. (28)

[0166]
In general, each of the functions Q_{k,l }can have a different number of taps M and N can be different for each channel In some embodiments, the number of taps M for each function Q_{k,l }can be the same. In some embodiments, delays can be added in order to match the timing between all of the channels. Further, in general delays 5731 through 573K can delay signals E_{1 }through E_{K }by a different number of cycles. In some embodiments, where each of functions Q_{k,l }includes M delays, each of delays 5731 through 573K includes N=M/2 delays where N is rounded to the nearest integer.

[0167]
The coefficients σ_{k,l} ^{0 }through σ_{k,l} ^{M }can be adaptively chosen in crosschannel adaptive parameter block 571 as shown in FIG. 5A in order to optimize the performance of receiver system 220p. In some embodiments, M is chosen to be 5. In some embodiments, transfer function Q_{k,l }may be constants, M=0. Crosschannel adaptive parameter block 571 is further discussed below.

[0168]
Therefore, in cross channel interference canceller 570 the cross channel interference is subtracted from the output signals from digital filters 5621 through 562K as indicated by Equation 26. The output signals from crosschannel interference canceller 570 for an arbitrary one of receivers 222k, H_{k} ^{I }and H_{k} ^{Q}, can be input to a second digital filter 563k. An embodiment of second digital filter 563k is shown in FIG. 5E.

[0169]
The parameters σ_{k,l} ^{m }of Equation 28 can be adaptively chosen. In the adaptation algorithm, the real and imaginary parts of σ_{k,l} ^{m }can be adjusted separately. The adaptive adjustments of parameters σ_{k,l} ^{m }is further discussed below.

[0170]
As shown in FIG. 5E, the signals H_{k} ^{I }and H_{k} ^{Q }can be input to AGC controlled amplifiers 537k and 538k, respectively. The gains of amplifiers 537k and 538k, g_{k} ^{2(I) }and g_{k} ^{2(Q)}, respectively, are set such that the output signals from amplifiers 537k and 538k yield appropriate levels for the symbol set. The gain values g_{k} ^{2(I) }and g_{k} ^{2(Q) }are set in tracking and timing recovery 517k and can be determined in much the same fashion as in AGC 520k of FIG. 5C. In the embodiment shown in FIG. 7, the gain values g_{k} ^{2(I) }and g_{k} ^{2(Q) }are determined based on the sign of the determined symbol from decision unit 516k and the error signal. These calculations are discussed further below.

[0171]
The output signals from amplifiers 537k and 538k can be input to quadrature correction 540k. Quadrature correction 540k corrects for the phase error between the inphase and quadrature mixers at the transmitter. The angle θ^ _{k} ^{(2)}(n) of the phase error can be adaptively chosen in tracking and timing recovery 517. The value θ^ _{k} ^{(2)}(n) can be changed very slowly and can be almost constant.

[0172]
Additionally, arithmetic offsets OFFSET_{2} _{I }and OFFSET_{2} ^{Q }can be subtracted in summers 541k and 542k, respectively. The values of OFFSET_{2} ^{I }and OFFSET_{2} ^{Q }can be adaptively chosen in tracking and timing recovery 517k. In some embodiments, the OFFSET_{2} ^{I }and OFFSET_{2} ^{Q }can be set by integrating the output signals of summers 541k and 542k, G_{k} ^{I}(n) and G_{k} ^{Q}(n), respectively. Alternatively, as shown in FIG. 7, OFFSET_{2k} ^{I }and OFFSET_{2} ^{Q }can be set such that the error at decision unit 516k is zero. In that embodiment, data dependent jitter can be reduced. In some embodiments, tracking and timing recovery 517k integrates the error values between the output samples from decision unit 516k and the output signals G_{k} ^{I}(n) and G_{k} ^{Q}(n) to minimize the error values.

[0173]
The output signals G_{k} ^{I}(n) and G_{k} ^{Q}(n), then, are given by

G _{k} ^{I}(n)=g _{k} ^{2−I} E _{k} ^{I}(n)−OFFSET_{2} ^{I}

G _{k} ^{Q}(n)=g _{k} ^{2−Q} E _{k} ^{Q}(n)−g _{k} ^{2−I} E _{k} ^{I}(n)θ^ _{k} ^{(2)}−OFFSET_{2} ^{Q}. (29)

[0174]
[0174]FIG. 7 shows an embodiment of Tracking and Timing Recovery 517k. Tracking and timing recovery 517k inputs decision values â_{k} ^{I}(n) and â_{k} ^{Q}(n), which are decisions of the symbol values based on the signals G_{k} ^{I}(n) and G_{k} ^{Q}(n) in decision unit 516k, and error values e_{k} ^{I}(n) and e_{k} ^{Q}(n) based on the decided values â_{k} ^{I}(n) and â_{k} ^{Q}(n) and the values G_{k} ^{I}(n) and G_{k} ^{Q}(n). In some embodiments, the error values e_{k} ^{I}(n) and e_{k} ^{Q}(n) are the differences between the decided values â_{k} ^{I}(n) and â_{k} ^{Q}(n) and the values G_{k} ^{I}(n) and G_{k} ^{Q}(n). The coefficients of equalizer 513k of first digital filter 562k are computed in coefficient update 702k.

[0175]
The coefficients of Equalizer
513k of FIG. 5D are updated in tracking and timing recovery block
517k. In a multitop equalizer, for example, equalizer coefficients can be updated according to the following update equations:
$\begin{array}{cc}{C}_{k}^{x}\ue8a0\left(j,n+1\right)={C}_{k}^{x}\ue8a0\left(j,n\right)\mu \ue89e\text{\hspace{1em}}\left[{e}_{k}^{I}\ue8a0\left(n\right)\ue89e{D}_{k}^{I}\ue8a0\left(nj\right)+{e}_{k}^{Q}\ue8a0\left(n\right)\ue89e{D}_{k}^{Q}\ue8a0\left(nj\right)\right]\ue89e\text{}\ue89e\mathrm{and}\ue89e\text{}\ue89e{C}_{k}^{y}\ue8a0\left(j,n+1\right)={C}_{k}^{y}\ue8a0\left(j,n\right)\mu \ue89e\text{\hspace{1em}}\left[{e}_{k}^{Q}\ue8a0\left(n\right)\ue89e{D}_{k}^{I}\ue8a0\left(nj\right){e}_{k}^{I}\ue8a0\left(n\right)\ue89e{D}_{k}^{Q}\ue8a0\left(nj\right)\right],& \left(30\right)\end{array}$

[0176]
where μ is the constant that determines the rate of adaptation of the coefficients, j indicates the tap of the coefficient, and e_{k} ^{I}(n) and e_{k} ^{Q}(n) are estimated error values. The constant μ is chosen to control the rate of adaptation, and, in some embodiments, is in the range of 2^{−8 }to 2^{−14}. In some embodiments, the coefficient μ can be different for the update equation for C_{k} ^{x }and the update equation for C_{k} ^{y}. The estimated error values, which are computed by decision block 516k, can be computed according to:

e _{k} ^{I}(n)=G _{k} ^{I}(n)−â_{k} ^{I}(n)

[0177]
and

e _{k} ^{Q}(n)=G _{k} ^{Q}(n)−â_{k} ^{Q}(n), (31)

[0178]
where G_{k} ^{I}(n) and G_{k} ^{Q}(n) are corrected values of E_{k} ^{I}(n) and E_{k} ^{Q}(n), respectively, and {â_{k} ^{I}(n),â_{k} ^{Q}(n)} is the decision set based on the sample set {G_{k} ^{I}(n),G_{k} ^{Q}(n)}, and represents the closest QAM symbol in Euclidean distance to the sample set. See, e.g., Edward A. Lee, and David G. Messerschmitt, Digital Communication, pp. 371402 (Kluwer Academic Publishers, 1988). A decision set {â_{k} ^{I}(n),â_{k} ^{Q}(n)} can be computed based on sample set {G_{k} ^{I}(n),G_{k} ^{Q}(n)} in decision unit 516k and the results received into tracking and timing recovery circuit 517 where the estimated error values of Equation 30 and the resulting coefficient updates of Equation 30 are computed.

[0179]
[0179]FIG. 7 shows a block diagram of equalizer coefficient update, carrier tracking and timing recovery block 517k. Block 517k includes coefficient update block 702k. Errors e_{k} ^{I}(n) and e_{k} ^{Q}(n) are computed in decision block 516k according to Equation 30. Coefficient update 702k receives errors e_{k} ^{I}(n) and e_{k} ^{Q}(n) signals D_{k} ^{I}(n) and D_{k} ^{Q}(n) from phase rotator circuit 512k shown in FIG. 5D and calculates updated equalizer coefficients for complex adaptive equalizer 513k shown in FIG. 5D according to Equation 30.

[0180]
Tracking and timing recovery circuit 517k can also include a carrier recovery loop for controlling carrier phase rotation circuit 512k shown in FIG. 5D and a timing recovery loop for controlling the phase of sampling clock signal SCLK from PLL 523. In some embodiments, the timing recovery loop for determining τ_{k}(n+1) in tracking and timing recovery 517 can be implemented as a 2^{nd }order digital phase locked loop as shown in FIG. 7.

[0181]
The errors e
_{k} ^{I}(n) and e
_{k} ^{Q}(n) and the decisions â
_{k} ^{I}(n) and â
_{k} ^{Q}(n) from decision unit
516k are input to phase detector
703k. Phase detector
703k can produce an estimate of the phase error p
_{k} ^{τ}, in some embodiments according to the following equation:
$\begin{array}{cc}{p}_{k}^{\tau}\ue8a0\left(n\right)=\left[{e}_{k}^{I}\ue8a0\left(n1\right)\ue89e{\hat{a}}_{k}^{I}\ue8a0\left(n\right){e}_{k}^{I}\ue8a0\left(n\right)\ue89e{\hat{a}}_{k}^{I}\ue8a0\left(n1\right)\right]+\left[{e}_{k}^{Q}\ue8a0\left(n1\right)\ue89e{\hat{a}}_{k}^{Q}\ue8a0\left(n\right){e}_{k}^{Q}\ue8a0\left(n\right)\ue89e{\hat{a}}_{k}^{Q}\ue8a0\left(n1\right)\right].& \left(32\right)\end{array}$

[0182]
Alternatively, the phase error p
_{k} ^{τ} can be calculated from
$\begin{array}{cc}{p}_{n}^{\tau}\ue8a0\left(n\right)={e}_{k}^{I}\ue8a0\left(n1\right)\ue8a0\left[{\hat{a}}_{k}^{I}\ue8a0\left(n\right){\hat{a}}_{k}^{I}\ue8a0\left(n2\right)\right]+{e}_{k}^{Q}\ue8a0\left(n1\right)\ue8a0\left[{\hat{a}}_{k}^{Q}\ue8a0\left(n\right){\hat{a}}_{k}^{Q}\ue8a0\left(n2\right)\right],& \left(33\right)\end{array}$

[0183]
which can be simpler to implement than Equation 32. In embodiments where the phase correction τ^ _{k }is calculated from e_{k} ^{I }only or from e_{k} ^{Q }only, as discussed above, then the terms containing e_{k} ^{Q }or the terms containing e_{k} ^{I}, respectively, are dropped from Equations 32 and 33.

[0184]
The output signal from phase detector
703k, p
_{k} ^{τ}, can then be input to a 2
^{nd }order loop filter, which in some embodiments can have a transfer function given by
$\begin{array}{cc}L\ue8a0\left(z\right)={\alpha}_{\tau}+{\beta}_{\tau}\ue89e\frac{{z}^{1}}{1{z}^{1}}& \left(34\right)\end{array}$

[0185]
where α_{τ} and β_{τ} are the loop filter coefficients that determine the timing recovery loop bandwidth and damping factor. In some embodiments, a loop bandwidth equal to 1% of baud rate, and damping factor equal to 1 can be implemented. The loop bandwidth and damping factors can depend not only on loop filter coefficients, but also on phase detector slope, and the digital integrator gain. Thus, the output signal L_{k} ^{τ}(n) from loop filter 705k is given by

L _{k} ^{τ}(n)=α_{τ} p _{k} ^{τ}(n)+I _{k} ^{τ}(n),

[0186]
where

I _{k} ^{τ}(n)=I _{k} ^{τ}(n−1)+β_{τ} p _{k} ^{τ}(n−1). (35)

[0187]
The output signal from loop filter 705k, L_{k} ^{τ}(n), is then input to a digitally implemented integrator 707k, the output of which is the phase correction τ{circumflex over (0 )}_{k}(n) given by

{circumflex over (τ)}_{k}(n+1)={circumflex over (τ)}_{k}(n)+L _{k} ^{τ}(n). (36)

[0188]
The phase correction τ^ _{k}(n) is then received by PLL 523, as described above.

[0189]
The carrier phase recovery loop which computes the parameter θ^ utilized in phase rotation
512k can also be implemented as a 2
^{nd }order digital phase locked loop as shown in FIG. 7. Phase detector
704k receives decision values {â
_{k} ^{I}(n),â
_{k} ^{Q}(n)} and error signals {e
_{k} ^{I}(n),e
_{k} ^{Q}(n)} from decision unit
516k, and produces an estimate of the phase error. In some embodiments, the estimate of the phase error p
_{k} ^{θ}(n) performed by phase detector
704k can be given by:
$\begin{array}{cc}{p}_{k}^{\theta}\ue8a0\left(n\right)=\left[{e}_{k}^{Q}\ue8a0\left(n\right)\ue89e\mathrm{sign}\ue89e\left\{{\hat{a}}_{k}^{I}\ue8a0\left(n\right)\right\}{e}_{k}^{I}\ue8a0\left(n\right)\ue89e\mathrm{sign}\ue89e\left\{{\hat{a}}_{k}^{Q}\ue8a0\left(n\right)\right\}\right],\mathrm{where}& \left(37\right)\\ \mathrm{sign}\ue8a0\left(x\right)=\{\begin{array}{cc}1& \mathrm{if}\ue89e\text{\hspace{1em}}\ue89ex\ge 0\\ 1& \mathrm{if}\ue89e\text{\hspace{1em}}\ue89ex<0\end{array}.& \left(38\right)\end{array}$
sign(
x)=1 if
x≧0−1 if
x<0. (38)

[0190]
The output signal from phase detector
704k can be input to a 2
^{nd }order loop filter
706k with a transfer function given by
$\begin{array}{cc}L\ue8a0\left(z\right)={\alpha}_{\theta}+{\beta}_{\theta}\ue89e\frac{{z}^{1}}{1{z}^{1}},& \left(39\right)\end{array}$

[0191]
where α_{θ} and β_{θ} are the loop filter coefficients that determine the carrier tracking loop bandwidth and the damping factor. Thus, the output signal from loop filter 706k is given by

L _{k} ^{θ}(n)=α_{θ} p _{k} ^{θ}(n)+I _{k} ^{θ}(n)

[0192]
where

I _{k} ^{θ}(n)=I _{k} ^{θ}(n−1)+β_{θ} p _{k} ^{θ}(n−1). (40)

[0193]
The output signal from loop filter 706k is then input to a digitally implemented integrator 708k. The output signal from integrator 708, θ^ _{k}(n+1), is then given by

{circumflex over (θ)}_{k}(n+1)={circumflex over (θ)}_{k}(n)+L _{k} ^{θ}(n). (41)

[0194]
The carrier tracking loop output signal θ^ _{k}((n), output from integrator 708k, is then input to phase rotation circuit 512k of FIG. 5D.

[0195]
Further, as shown in FIG. 7, the parameter θ_{k} ^{c}(n+1) can be calculated by phase detector 720k and integrator 722k as described in Equation 21. As described above, the parameter η_{k} ^{c}(n+1) input into multiplier 533k shown in FIG. 5D can be calculated by blocks 723 and integration block 724 according to Equation 20.

[0196]
As shown in Blocks 725k and 726k, the offset values OFFSET_{1} ^{I }and OFFSET_{1} ^{Q }input to summers 534k and 536k, respectively, of the embodiment of digital filter 562k shown in FIG. 5D can be determined by integrating the signals F_{k} ^{I}(n) and F_{k} ^{Q}(n), respectively. Similarly, the offset values OFFSET_{2} ^{I }and OFFSET_{2} ^{Q }input to sununers 541k and 542k, respectively, of digital filter 563k shown in FIG. 5E can be calculated by integrating the signals G_{k} ^{I}(n) and G_{k} ^{Q}(n), respectively. The embodiment of adaptive parameter block 517k shown in FIG. 7 calculates OFFSET_{2} ^{I }and OFFSET_{2} ^{Q }by integrating the error signals e_{k} ^{I}(n) and e_{k} ^{Q}(n), respectively.

[0197]
Further, the coefficient θ^
_{k} ^{(2) }to quadrature correction
540k of FIG. 5E can be calculated by phase detector
729k and integrator
731k. The output signal from phase detector
729k can be calculated by
$\begin{array}{cc}{P}_{k}^{\mathrm{\theta 2}}=\mathrm{sign}\ue8a0\left({\hat{a}}_{k}^{I}\ue8a0\left(n\right)\right)\ue89e{e}_{k}^{Q}\ue8a0\left(n\right)\mathrm{sign}\ue8a0\left({\hat{a}}_{k}^{Q}\ue8a0\left(n\right)\right)\ue89e{e}_{k}^{I}\ue8a0\left(n\right)& \left(42\right)\end{array}$

[0198]
The output signal from integrator 731 k, then, can be given by

θ_{k} ^{(2)}(n+1)=θ_{k} ^{(2)}(n)+α_{θ} P _{k} ^{θ2} (43)

[0199]
The gains g_{k} ^{2−1 }and g_{k} ^{2−Q }can be calculated by phase detector 732 and integrator 734. In some embodiments, phase detector 732k calculates the quantities

[0200]
and

p _{k} ^{g2−I}(n)=−e _{k} ^{I}(n)sign(â_{k} ^{I}(n))

[0201]
and

p _{k} ^{g2−Q}(n)=−e _{k} ^{Q})(n)sign(â_{k} ^{Q}(n)). (44)

[0202]
The output signals from integrator 734k, then, can be given by

g _{k} ^{2−I}(n+1)=g _{k} ^{2−I}(n)+α_{g} p _{k} ^{g2−I}

[0203]
and

g _{k} ^{2−Q}(n+1)=g _{k} ^{2−Q}(n)+α_{g} p _{k} ^{g2−Q}, (45)

[0204]
where α_{g }determines how fast the gain values respond to changes.

[0205]
As show in FIG. 5A, crosschannel adaptive parameter block 571 adaptively adjusts the parameters of crosschannel interference canceller 570, all of the σ_{k,I} ^{i }parameters of Equations 26 and 27. In an embodiment where the crosschannel transfer functions Q_{k,l }is a 5 tap function and K=8, there are 5*K*(K−1)=280 individual complex parameters σ_{k,I} ^{i }to adjust in Equations 27 and 28.

[0206]
In some embodiments, crosschannel adaptive parameter block 571 receives the complex input values E_{1 }through E_{K}, where E_{k}, an arbitrary one of them, is given by E_{k}=E_{k} ^{I}+iE_{k} ^{Q }(see FIG. 5F), and error signals {e_{k}(n)=e_{k} ^{I}(n)+ie_{k} ^{Q}(n)} from decision unit 516k of each of receivers 2221 through 222K. On startup of receiver system 220p, all of complex parameters σ_{k,I} ^{j }can be set to 0. Each of complex parameters σ_{k,I} ^{j }can then be updated according to

σ_{k,l} ^{m,x}(n+1)=σ_{k,l} ^{m,x}(n)−ν_{k,l} ^{m,x}(e _{1} ^{I}(n)E _{k} ^{I}(n−m)+e _{1} ^{Q}(n)E _{k} ^{Q}(n−m), (b 46)

[0207]
and

σ_{k,l} ^{m,y}(n+1)=σ_{k,l} ^{m,y}(n)−ν_{k,l} ^{m,y}(e _{1} ^{Q}(n)E _{k} ^{I}(n−m)−e _{1} ^{I}(n)E _{k} ^{Q}(n−m), (47)

[0208]
where

σ_{k,1} ^{m}=σ_{k,1} ^{m,x} +iσ _{k,1} ^{m,y}, (48)

[0209]
where ν_{k,l} ^{m}=ν_{k,1} ^{m,x}+iν_{k,1} ^{m,y }is the complex update coefficient for parameter σ_{k,1} ^{m }and controls how fast parameter σ_{k,1} ^{m }can change, in similar fashion as has been described with other update equations above. In some embodiments, all of the parameters ν_{k,l} ^{m,x }and ν_{k,l} ^{m,y }each have values on the order of 10^{−3 }to 10^{−5}.

[0210]
In some embodiments, frequency shift 563 generates a reference signal input to PLL 523 such that the frequency of component 201p with receiver system 220p, {circumflex over (f)}_{1 }through {circumflex over (f)}_{K}, matches the frequency of the corresponding component 201q with transmitter system 210q, f_{1 }through f_{K}, where component 201q is transmitting data to component 201p. In embodiments where f_{1 }through f_{K }correspond to frequencies f_{0 }through Kf_{0}, respectively, then frequency shift 563 shifts the frequency of a reference clock such that the frequency shift Δ is zero. The frequencies {circumflex over (f)}_{1 }through {circumflex over (f)}_{K}, then, are also frequencies f_{0 }through Kf_{0}. In some embodiments, frequency shift 563 can receive input from any or all loop filters 706k (FIG. 7) and adjusts the frequency shift such that θ^ _{k} ^{(1) }through θ^ _{k} ^{(K) }remain a constant, for example 0 or any other angle. In some embodiments, frequency shift 563 receives the output signals from any or all loop filters 705k.

[0211]
As shown in FIG. 5A, the output signals from digital filter 563k, equalized samples {G_{k} ^{I}(n),G_{k} ^{Q}(n)}, are input to trellis decoder 514k. Trellis decoding can be performed using the Viterbi algorithm, see, e.g., G. Ungerboeck., “Channel Coding with Multilevel/Phase Signals,” IEEE Transactions on Information Theory, vol. IT28, January 1982, pp. 5567, G. Ungerboeck., “Trellis Coding Modulation with Redundant Signal Sets, Part I. Introduction,” IEEE Communications Magazine, vol. 25, no. 2, February 1987, pp. 511, G. Ungerboeck., “Trellis Coding Modulation with Redundant Signal Sets, Part II. State of the Art,” IEEE Communications Magazine, vol. 25, no. 2, February 1987, pp. 1221, or G. C. Clark, Jr., and J. B. Cain, Error Correction Coding for Digital Communications, pp.253264(Plenum Press, New York, 1981). Additionally, trellis decoder 514 converts from the QAM symbol set back to parallel bits. The output signal from trellis decoder 514, which now contains n_{k }parallel bits, is input to descrambler 515k. Descrambler 515k of receiver demodulator 222k operates to reverse the scrambling operation of scrambler 401 of transmitter modulator 212k.

[0212]
As is shown in FIG. 2C, the output signals from each of demodulators 2221 through 222K are recombined into an Nbit parallel signal in bit parsing 221. Additionally, the RX clock signal is output from bit parsing 221.

[0213]
[0213]FIG. 10 shows an example embodiment of trellis decoder 514 according to the present invention. Trellis decoder 514 of FIG. 10A includes a slicer 1001, a branch metric 1002, an addcompareselect (ACS) block 1003, a normalization and saturation block 1004, a trace back 1005, and a trellis decision block 1006. The output signal from trellis decoder 514 is the received bits, which are substantially as transmitted by transmitter 210p.

[0214]
Slicer
1001 receives the output signals G
_{k} ^{I}(n) and G
_{k} ^{Q}(n) from offset blocks
541 and
542, respectively. FIG. 10B shows an embodiment of slicer
1001. The value G
_{k} ^{I}(n) is received in x and y slicers
1010 and
1011, respectively. Slicer
1010 slices G
_{k} ^{I}(n) to a first set of symbol values while slicer
1011 slices G
_{k} ^{I}(n) to a second set of slicer values. For example, in a 128 QAM system as shown in Table I, xslicer
1010 can slice to the symbol values −11, −7, −3, 1, 5, and 9 and yslicer
1011 can slice to the symbol values −9, −5, −1, 3, 7, 11. In some embodiments, the number of bits can be reduced by mapping the decided symbols from slicers
1010 and
1011 using table
1016 and
1021, respectively. The output signal from tables
1016 and
1021, then, are i
_{x }and i
_{y}, indicating decisions based on the input value G
_{k} ^{I}(n).
TABLE II 


INPUT  08  9,10  11,12,13  >14 
OUTPUT  0  1  2  3 


[0215]
The errors δi_{x }and δi_{y }are also calculated. The output signals from slicers 1010 and 1011 are subtracted from the input signal G_{k} ^{I}(n) in summers 1015 and 1020, respectively. In some embodiments, the output signals from slicers 1010 and 1011 are input to blocks 1014 and 1019, respectively, before subtraction in summers 1015 and 1020. Blocks 1014 and 1019 represent shifts. In some embodiments, the input signals to slicers 1010 and 1011 are 8bit signed numbers. The value 8 slices to a perfect 1. Similarly, the value −56 slices to a perfect −7. So if the input signal is a −56 it would be sliced to −7. To calculate the error, we need to multiply the −7 by 8 before it is subtracted from the incoming signal. Multiplying by 8 is the same as a shift to the left by 3.

[0216]
The absolute values of the output signals from summers 1015 and 1020 are then taken by blocks 1017 and 1022, respectively. The output signal from ABS blocks 1017 and 1022 can be mapped into a set of values requiring a smaller number of bits by tables 1018 and 1023, as in Table II above, respectively, to generate δi_{x }and δi_{y}, respectively.

[0217]
The output signals corresponding to the quadrature data path, q_{x}, q_{y}, δq_{x }and δq_{y }are generated by substantially identical procedure by slicers 1012, 1013, summers 1025, 1030, and blocks 1024, 1026, 1027, 1028, 1029, 1031, 1032 and 1033.

[0218]
Branch metric 1002 receives the error signals from slicer 1001 and calculates the signals δa, δb, δc, and δd. The branch metric values δa, δb, δc, and δd indicate the path metric errors. In some embodiments, the path metric errors δa, δb, δc, and δd can be calculated as

δa=δi _{x} +δq _{x},

δb=δi _{y} +δq _{x},

δc=δi _{x} +δq _{y},

δd=δi _{y} +δq _{y}, (49)

[0219]
AddCompare Select 1003 receives the path metrics δa, δb, δc, and δd along with state metric values s_{0}, s_{1}, s_{2 }and s_{3}, which are calculated in normalization and saturation block 1004. In some embodiments, the output values of ACS 1003 include path metrics p_{0}, p_{1}, p_{2 }and p_{3 }along with choice indicators c_{0}, c_{1}, c_{2 }and c_{3}. The path metrics p_{0}, p_{1}, p_{2 }and p_{3 }can be given by

p _{0}=MIN(s _{0} +δa, s _{2} +δd),

p _{1}=MIN(s _{0} +δd, s _{2} +δa),

p _{2}=MIN(s _{1} +δb, s _{3} +δc),

[0220]
and

p _{3}=MIN(s _{1} +δc, s _{3} +δb), (50)

[0221]
The choice indicators c_{0}, c_{1}, c_{2 }and c_{3 }indicate which of the values was chosen in each of the minimization in Equation 43.

[0222]
Normalization and saturation 1004 receives the path metrics p_{0}, p_{1}, p_{2 }and p_{3 }and calculates the state metrics s_{0}, s_{1}, s_{2 }and s_{3}. In some embodiments, if the path metrics are above a threshold value, the threshold value is subtracted from each of the path metrics. In some embodiments, the smallest path metric can be subtracted from each of the path metrics p_{0}, p_{1}, p_{2 }and p_{3}. Normalization and Saturation block 1004 also ensures that path metrics p_{0}, p_{1}, p_{2 }and p_{3 }are limited to a maximum value. For example, in an embodiment where p_{0}, p_{1}, p_{2 }and p_{3 }are a fourbit number (range 015), if p_{0}, p_{1}, p_{2 }and p_{3 }is greater than 15, then the corresponding path metric is limited to the maximum value of 15. Then, the state metrics for the next baud period, s_{0}, s_{1}, s_{2}, and s_{3}, are set to the path metrics p_{0}, p_{1}, p_{2 }and p_{3}.

[0223]
Traceback 1005 receives and stores the choice indicators c_{0}, c_{1}, c_{2 }and c_{3 }as well as the decided values from slicer 1001 in that baud period, i_{x}, i_{y}, q_{x}, and q_{y}. The choice indicators c_{0}, c_{1}, c_{2 }and c_{3 }indicate the previous state values. As shown in the state transition diagram of FIG. 10C, which indicates state transitions between the encoded bits, for each of the states 03, there are only two possible previous states 03. For example, if the current state is 1, the previous state was either 0 or 2. Although any traceback depth can be utilized in traceback 1005, in some embodiments a traceback depth of 6 is utilized. With the use of mapping tables 1016, 1021, 1026 and 1031 reducing the number of bits required to store i_{x}, i_{y}, q_{x}, and q_{y}, (for example a total of 8 in 128 QAM systems) and the low number of bits required to store choice indicators c_{0}, c_{1}, c_{2 }and c_{3}, a low number of bits is needed. For example, in some embodiments a total of 12 bits is utilized.

[0224]
For calculating the trellis output from trace back 1005, the most recently stored memory locations are utilized first with the first choice being the state with the lowest state metric. The algorithm then traces back through the stored choice indications c_{0}, c_{1}, c_{2 }and c_{3 }to the end of the traceback memory (in some embodiments, the sixth state) and arrives at state S. In the example trellis discussed above, the MSB of the output is the LSB of the state, S. The final state S and the choice indicator c_{s }will determine which pair of symbols were transmitted (I_{x}/I_{y}, Q_{x}/Q_{y}). By reading the values of these symbols from the traceback memory, a lookup in, for example, Table I will result in a read value. The five least significant bits of the read value from the lookup table, e.g. Table I, becomes the five least significant bits of the output signal. The most significant bit was determined earlier and supplies the most significant bit (MSB).

[0225]
If the example 16 state encoder described earlier is used, then a standard 16 state trellis decoder using the Viterbi algorithm can be utilized in the decoding. The 2/3 bit encoding is illustrated in Table II for the most significant bits and a lookup table for a 7 bit data mapper is illustrated in Table III.

[0226]
[0226]FIG. 9 shows a transceiver chip 900 according to the present invention. Transceiver chip 900 includes transmitter 210p and receiver 220p formed on a single semiconductor chip. In some embodiments, transceiver chip 900 is formed in silicon using CMOS technology. Transceiver chip 900 can receive N bits into transmitter 210p and output N bits from receiver 220p. In some embodiments, different pins may be utilized for input bits and output bits, as shown in FIG. 9. In some embodiments, transmitter 210p and receiver 220p share the same N pins. Transmitter 900 receives a reference clock signal and outputs a receive clock signal from receiver 220p. Further, transceiver 220 includes output pins for transmitting and receiving differential signals. In some embodiments, transmitter 210p and receiver 220p share the same output pins and in some embodiments transmitter 210p and receiver 220p are coupled to separate output pins. In some embodiments, transceiver chip 900 may be coupled to an optical driver for optical transmission.

[0227]
Although the digital algorithms described in this disclosure are presented as digital circuitry elements, one skilled in the art will recognize that these algorithms can also be performed by one or more digital processors executing software code to perform the same functions.

[0228]
[0228]FIG. 12A shows an embodiment of baseband receiver 223. Baseband transmitter 217 and baseband receiver 223 may, for example, form a PAM transceiver. The signal from medium 250 (see FIG. 2A) is received by analog processing 1201. Analog processing 1201, for example, can include a lowpass filter in order to separate the baseband signal from those signals transported with carrier frequencies, such as those transmitted by transmitters 2121 through 212K. Filter 1201 can further include some analog correction of the signals, including antialiasing filters, baseline wander filters, or other filters.

[0229]
[0229]FIG. 12B shows an embodiment of analog processing 1201. The input signal Z(t) is received by a low pass filter 1210. The parameters of low pass filter 1210 can be fixed, however in some embodiments the filter can be adjusted dynamically, for example, by adaptive parameter control 1207 of FIG. 12A. The output signal from filter 1210 is input to amplifier 1211. In some embodiments, the gain of amplifier 1211, g_{A, }can be given by

g _{A}(n+1)=g _{A}(n)+α_{A}(P _{A−Th} −P) (51)

[0230]
where α_{A }is a multiplier which controls convergence of the gain, P_{A−TH }is a threshold value on peak power, and P is the mean squared power S^{2}, where S is the digitized signal from ADC 1202. Amplifier 1211, then, arranges that the range of ADC 1202 is filled.

[0231]
The output signal from amplifier 1211 can be input to offset 1212. The offset value OFFSET_{A }can be arranged by adaptive parameter control 1207 such that the average output signal S from ADC 1202 is zero. The offset value OFFSET_{A}, for example, can be given by

OFFSET_{A}(n+1)=OFFSET_{A}(n)−α_{OFF} S, (52)

[0232]
where α_{OFF }is again the multiplicative factor that controls convergence and S is the signal output from ADC converter 1202.

[0233]
The output signal from analog processing 1201 is input to ADC 1202 where it is digitized. ADC 1202 can have any number of bits of resolution. At least a four bit ADC, for example, can be utilized in a 16PAM system. ADC 1202 can be clocked from a clock signal generated by receiver 120p in general, for example in PLL 523 as shown in FIG. 5A. In some embodiments, adaptive parameter control 1207 can generate a phase signal which can add a phase to the timing of ADC 1202. In those embodiments, the phase signal Ph can be given by the same technique as described with the calculation of phase performed by phase detector 703k, loop filter 705k, and integrator 707k, shown in FIG. 7, for the inphase signal.

[0234]
The output signal from ADC 1202, S, can be input to a digital filter 1203. Further filtering and shaping of the signal can occur in digital filter 1203. Filter 1203 can be, for example, a digital baseline wander filter, a digital automatic gain control circuit, an echo or next canceller, or any other filter. For example, if necessary, digital filter 1203 can be part of cross channel interference filter 570 (shown in FIG. 5A). The output signal from digital filter 1203 is input to equalizer 1204.

[0235]
Equalizer 1204 equalizes the signal for intersymbol interference. Equalizer 1203 can include a feedforward section, a feedback section, or a combination of feedforward and feedback sections. FIG. 12C shows an embodiment of equalizer 1204 with a combination of a feedforward section 1215 and feedback section 1216. Each of feedforward section 1215 and feedback section 1216 can include any number of taps. Each of the equalization parameters C_{0 }through C_{M }of feedforward section 1215 and B_{1 }through B_{N }of feedback section 1216 can be adaptively chosen in adaptive parameter control 1207 similarly to the methods previously discussed above.

[0236]
The output signal from equalizer 1204 can then be input to data recovery 1205. Data recovery 1205 recovers the digital signal from the signals. In some embodiments, data recovery 1205 is a PAM slicer. In some embodiments, data recovery 1205 can also include an error correction decoder such as a trellis decoder, a ReedSolomon decoder or other decoder. The output signal from data recovery 1205 is then input to descrambler 1206 so that the transmitted parallel bits are recovered.

[0237]
The embodiments of the invention described above are exemplary only and are not intended to be limiting. One skilled in the art will recognize various modifications to the embodiments disclosed that are intended to be within the scope and spirit of the present disclosure. As such, the invention is limited only by the following claims.
TABLE I 


  47  111  43  107  59  123  63  127    11 
  15  79  11  75  27  91  31  95    9 
42  106  45  109  41  105  57  121  61  125  58  122  7 
10  74  13  77  9  73  25  89  29  93  26  90  5 
46  110  44  108  40  104  56  120  60  124  62  126  3 
14  78  12  76  8  72  24  88  28  92  30  94  1 
38  102  36  100  32  96  48  112  52  116  54  118  −1 
6  70  4  68  0  64  16  80  20  84  22  86  −3 
34  98  37  101  33  97  49  113  53  117  50  114  −5 
2  66  5  69  1  65  17  81  21  85  18  82  −7 
  39  103  35  99  51  115  55  119    −9 
  7  71  3  67  19  83  23  87    −11 
−11  −9  −7  −5  −3  −1  1  3  5  7  9  11  I/Q 


[0238]
[0238]
 TABLE II 
 
 
 State Transition  Encoded value 
 
 0=>0  0 
 3=>14 
 4=>1 
 7=>12 
 8=>2 
 11=>15 
 12=>3 
 15=>3 
 0=>1  1 
 3=>12 
 4=>3 
 7=>13 
 8=>0 
 11=>14 
 12=>2 
 15=>15 
 0=>2  6 
 3=>15 
 4=>0 
 7=>14 
 8=>3 
 11=>13 
 12=>1 
 15=>12 
 0=>3  7 
 3=>13 
 4=>2 
 7=>15 
 8=>1 
 11=>12 
 12=>0 
 15=>14 
 1=>6  2 
 2=>8 
 5=>5 
 6=>10 
 9=>7 
 10=>9 
 13=>4 
 14=>11 
 1=>5  3 
 2=>10 
 5=>7 
 6=>9 
 9=>4 
 10=>11 
 13=>6 
 14=>8 
 1=>7  4 
 2=>9 
 5=>4 
 6=>11 
 9=>6 
 10=>8 
 13=>5 
 14=>10 
 1=>4  5 
 2=>11 
 5=>6 
 6=>8 
 9=>5 
 10=>10 
 13=>7 
 14=>9 
 

[0239]
[0239]
TABLE III 


  24  88  3  67  29  93  0  64    11 
  56  120  35  99  61  125  32  96    9 
20  84  2  66  25  89  7  71  30  94  12  76  7 
52  116  34  98  57  121  39  103  62  126  44  108  5 
1  65  21  85  6  70  26  90  11  75  31  95  3 
33  97  53  117  38  102  58  122  43  107  63  127  1 
17  81  5  69  22  86  10  74  27  91  15  79  −1 
49  113  37  101  54  118  42  106  59  123  47  111  −3 
4  68  18  82  9  73  23  87  14  78  28  92  −5 
36  100  50  114  41  105  55  119  46  110  60  124  −7 
  8  72  19  83  13  77  16  80    −9 
  40  104  51  115  45  109  48  112    −11 
−11  −9  −7  −5  −3  −1  1  3  5  7  9  11  I/Q 
