US20030119276A1 - Semiconductor device and process for producing the same - Google Patents

Semiconductor device and process for producing the same Download PDF

Info

Publication number
US20030119276A1
US20030119276A1 US10/141,422 US14142202A US2003119276A1 US 20030119276 A1 US20030119276 A1 US 20030119276A1 US 14142202 A US14142202 A US 14142202A US 2003119276 A1 US2003119276 A1 US 2003119276A1
Authority
US
United States
Prior art keywords
oxide film
groove
silicon oxide
semiconductor substrate
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US10/141,422
Inventor
Norio Ishitsuka
Hideo Miura
Shuji Ikeda
Norio Suzuki
Yasushi Matsuda
Yasuko Yoshida
Hirohiko Yamamoto
Masamichi Kobayashi
Akira Takamatsu
Hirofumi Shimizu
Kazushi Fukuda
Shinichi Horibe
Toshio Nozoe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to US10/141,422 priority Critical patent/US20030119276A1/en
Publication of US20030119276A1 publication Critical patent/US20030119276A1/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/05—Etch and refill

Definitions

  • the present invention relates to a semiconductor device having a highly reliable groove isolation structure and a process for producing the same.
  • a shallow groove isolation (SGI) structure is now available to make an electrical insulation or isolation between adjacent elements such as transistors, etc. on a semiconductor substrate.
  • the SGI structure typically comprises a shallow groove formed on a semiconductor substrate 31 of silicon and an oxide film 35 and the like embedded in the groove and is suitable for devices requiring processing dimensional precision of 0.25 ⁇ n or under, because its processing dimensional precision is higher than that of the structure so far by local oxidation of silicon (LOCOS).
  • LOCS local oxidation of silicon
  • the SGI structure sometimes suffers from formation of sharp protrusions 34 of semiconductor substrate 31 of silicon formed in the oxide film 35 formed by oxidation at the upper edge of the groove during the oxidation step, as shown in FIG. 1C.
  • step (or unevenness) 44 is formed on the upper surface of semiconductor substrate silicon 31 around the groove upper edge, as shown in FIG. 1C′.
  • step 44 can be formed presumably due to the following mechanism. That is, semiconductor substrate 31 of silicon has a silicon-exposed region and a silicon-unexposed region in the recessed area at the edge of pad oxide film 32 ; the silicon-exposed region undergoes faster oxidant diffusion, i.e. faster oxidation, than the silicon-unexposed region resulting in formation of step 44 at the edge of pad oxide film 32 as a boundary.
  • Gate oxide film 37 when formed in such a step region, has an uneven thickness, which leads to variations of electrical properties. Furthermore, stresses are liable to concentrate therein, resulting in a possible decrease in the electrical reliability of a transistors to be formed on step 44 .
  • the silicon oxide film 36 is deposited on the semiconductor substrate 31 by chemical vapor deposition (CVD) to embed the silicon oxide film 36 in the groove and then the semiconductor substrate 31 is heat treated to sinter the silicon oxide film 36 embedded in the groove. Sintering is carried out for improving the quality of the silicon oxide film 36 embedded in the groove. If the sintering is insufficient, voids are often generated in the groove in the subsequent steps.
  • CVD chemical vapor deposition
  • wet or steam oxidation is effective for sintering the silicon oxide film 36 embedded in the groove, but the wet or steam oxidation is liable to oxidize the inside, particularly side wall, of the groove. Oxidation starts from the groove surface and thus the groove bottom is less oxidized. Once the groove side wall is oxidized, the active region is narrowed. This is another problem. Thicker oxide film will cause a larger stress on the boundary between the oxide film and the substrate and the once rounded shoulder edge will return to the original sharp one and crystal defects are also generated. This is a further problem. To overcome these problems, it was proposed to provide a silicon nitride film along the groove inside wall.
  • a groove is trenched on a silicon substrate at first, and then an oxide film is formed on the groove inside surfaces (side wall and bottom surfaces) by heat oxidation, followed by further formation of a silicon nitride film thereon and still further formation of a silicon film such as anyone of amorphous, polycrystalline and monocrystalline silicon films on the silicon nitride film. Then, the groove is embedded with a silicon oxide film completely, followed by flattening of the groove top After the deposition of the silicon oxide film on the entire surface of substrate, but before the fattening, the silicon film is oxidized in an oxidizing atmosphere including steam at about 950° C.
  • the silicon substrate is not oxidized during the oxidation, because the silicon substrate is protected by the silicon nitride film.
  • a film having a good compatibility with a silicon oxide film i.e. a silicon film is formed as a thin film on the groove inside surfaces and thus the groove can be embedded with the silicon oxide film without any remaining voids in the groove.
  • the silicon film in the groove must be then converted to a silicon oxide film by oxidation, but the silicon nitride film is provided between the silicon film and the silicon substrate, the silicon substrate is never oxidized during the oxidation of the silicon film. That is, no device characteristics are deteriorated at all.
  • An object of the present invention is to provide a semiconductor device with a desired radius of curvature formed at the groove upper end and without formation of any step there, and also a process for producing the same.
  • the object of the present invention can be attained by reducing the stress generation around the groove upper end of an element isolation groove on a semiconductor substrate.
  • Another object of the present invention is to provide a novel technique of optimizing the shape of an element isolation groove, thereby making the device finer and improving the device electric characteristics.
  • Other object of the present invention is to provide a novel technique of reducing an adverse effect of stresses to an active region due to the sintering of a silicon oxide film embedded (or buried) in an element isolation groove on the device characteristics.
  • present invention provides a process for producing a semiconductor device, which comprises the following steps:
  • the present invention further provides a semiconductor device which comprises a semiconductor (or silicon) substrate and an element isolation oxide film having a groove isolation structure formed on the circuit-forming side of the semiconductor substrate, where the substrate has a monotonously convexed shape around the upper edge of the groove of the groove isolation structure; the oxide film is oxidized to have a thickness of 5 to 70 nm, preferably 30 to 70 nm at the inside wall of the groove at the intermediate level of the groove isolation structure; and the semiconductor substrate has a radius of curvature in a range of 3 to 35 nm at the upper edge of the groove thereof.
  • the present invention further provides a process for producing a semiconductor device, which comprises the following steps:
  • the present invention further provides a process for producing a semiconductor device, which comprises the following steps:
  • the present invention further provides numbers of variations of the above-mentioned processes.
  • FIGS. 1A to 1 D and 1 B′ and 1 C′ schematically show steps of producing a groove isolation structure by the conventional selective oxidation process.
  • FIGS. 2A to 2 I schematically show steps of producing a groove isolation structure according to a first embodiment of the present invention.
  • FIG. 3 is a flow chart showing steps of producing a groove isolation structure according to the first embodiment of the present invention.
  • FIG. 4 is a diagram showing the working and effect of the first embodiment of the present invention.
  • FIGS. 5A and 5B show the working and effect of the first embodiment of the present invention.
  • FIG. 6 is a flowchart showing steps of producing a groove isolation structure according to a second embodiment of the present invention.
  • FIG. 7 is a diagram showing the working and effect of the second embodiment of the present invention.
  • FIG. 8 is a flowchart showing steps of producing a groove 1 isolation structure according to a third embodiment of the present invention.
  • FIG. 9 is a flowchart showing steps of producing a groove structure according to a fourth embodiment of the present invention.
  • FIG. 10 is a diagram showing the working and effect of the fourth embodiment of the present invention.
  • FIGS. 11 to 32 are cross-sectional elevation views of essential part of a semiconductor substrate showing a process for producing a semiconductor device according to Example 5 of the present invention.
  • FIGS. 33 to 36 are cross-sectional elevation views of essential part of a semiconductor device according to Example 6 of the present invention.
  • FIGS. 37 to 44 are cross-sectional elevation views of essential part of a semiconductor substrate showing a process for producing a semiconductor device according to Example 7 of the present invention.
  • FIGS. 45 to 48 are cross-sectional elevation view of essential part of a semiconductor substrate showing a process for producing a semiconductor device according to Example 8 of the present invention.
  • FIGS. 49 to 50 are cross-sectional elevation views of essential part of a semiconductor substrate showing a process for producing a semiconductor device according to Example 9 of the present invention.
  • FIGS. 51 to 54 are cross-sectional elevation views of part of a semiconductor substrate showing a process for producing a semiconductor device according to Example 10 of the present invention.
  • FIGS. 55 to 58 are cross-sectional elevation views of essential part of a semiconductor substrate showing a process for producing a semiconductor device according to Example 11 of the present invention.
  • FIGS. 59 to 64 are cross-sectional elevation views of essential part of a semiconductor substrate showing a process for producing a semiconductor device according to Example 12 of the present invention.
  • FIGS. 65 and 66 are cross-sectional elevation views of essential part of a semiconductor substrate showing a process for producing a semiconductor device according to Example 13 of the present invention.
  • FIGS. 67 and 68 are cross-sectional elevation views of essential part of a semiconductor substrate showing a process for producing a semiconductor device according to Example 14 of the present invention.
  • FIGS. 69 and 70 are cross-sectional elevation views of essential part of a semiconductor substrate showing a process for producing a semiconductor device according to Example 15 of the present invention.
  • the present process for producing a semiconductor device comprises the following steps:
  • the shoulder edge of the groove can be more effectively improved by providing a partial undercut a below the pad oxide film 2 , as shown in FIG. 34, before trenching the groove.
  • the substrate has no step on the upper surface, but a, monotonously convexed shape around the upper edge of the groove of the groove isolation structure;
  • the oxide film is oxidized to have a thickness t of 5 to 70 nm, preferably 30 to 70 nm at the inside wall of the groove at the intermediate level of the groove isolation structure, as shown in FIG. 10; and the semiconductor substrate has a radius of curvature in a range of 3 to 35 nm at the upper edge of the groove thereof.
  • a process for producing a semiconductor device comprises the following steps:
  • a thermally oxidizing temperature for forming the first silicon oxide film, a thermally oxidizing temperature for forming the second silicon oxide film and a heat-treating (or annealing) temperature for sintering the third silicon oxide film are all not more than 1,000° C.
  • the thermally oxidizing temperature for forming the second silicon oxide film is from 800to 1,000° C.
  • the groove has a taper angle ⁇ of not more than 85°.
  • the inside wall of the groove is subjected to an soft nitriding treatment after the step (c) but before the step (d), thereby forming a silicon nitride layer in an area near the boundary between the a second silicon oxide film formed on the inside wall of the groove and the active region of the semiconductor substrate.
  • an area near the boundary between the second silicon oxide film formed on the inside wall of the groove and a clement isolation region of the semiconductor substrate is subjected to nitrogen ion implantation after the step (c) but before the step (d), thereby forming a silicon nitride layer in the area near the second silicon oxide film formed on the inside wall of the groove and the clement isolation region of the semiconductor substrate.
  • the third silicon oxide film on the silicon nitride film is removed after the step (d), while leaving the third silicon oxide film only in the groove, thereby forming an element isolation groove embedded with the third silicon oxide film, and then heat-treating (or annealing) the semiconductor substrate, thereby sintering the third silicon oxide film embedded in the groove.
  • (c) is carried out in a nitrogen-containing atmosphere, thereby forming a second silicon nitride film on the inside wall of the groove just before fully tilling the space formed by recess of the pad oxide film, and rounding the shoulder edge of the groove at the same time.
  • a second silicon nitride film is formed at least on the surface of the second silicon oxide film after the step (c) but before the step (d).
  • a process for producing a semiconductor device comprises the following steps:
  • a process for producing a semiconductor device comprises the following steps:
  • a process for producing a semiconductor device comprises the following steps:
  • a process for producing a semiconductor device comprises the following steps:
  • a step of thermally oxidizing a semiconductor substrate thereby forming a first silicon oxide film (a pad oxide film) on the principal side (or surface) of the semiconductor substrate, then depositing a silicon nitride film on the first silicon oxide film, and then selectively etching the silicon nitride film, the first silicon oxide film and the semiconductor substrate residing in an element isolation region while masking an element region, thereby trenching a groove on the principal side (or surface) of the semiconductor substrate,
  • a process for producing a semiconductor device comprises the following steps:
  • a process for producing a semiconductor device comprises the following steps:
  • a process for producing a semiconductor device comprises the following steps:
  • a process for producing a semiconductor device comprises the following steps:
  • a step of oxidizing a semiconductor substrate thereby forming a first silicon oxide film (a pad oxide film) on the principal side (or surface) of the semiconductor substrate, then depositing a silicon nitride film on the first silicon oxide film, and then selectively etching the silicon nitride film, the first silicon oxide film and the semiconductor substrate residing in an element isolation region while masking an element region, thereby trenching a groove on the principal side (or surface) of the semiconductor substrate, nitride film on the first silicon oxide film, and then
  • a process for producing a semiconductor device comprises the following steps:
  • a process for producing a semiconductor device comprises the following steps:
  • FIGS. 2A to 2 I are cross-sectional structured elevation views of a semiconductor device according to the present process and FIG. 3 is a flow chart showing outlines of steps of the process. Steps will be explained, referring to FIGS. 2A to 2 I according to the flow chart of FIG. 3.
  • Silicon nitride film 42 was deposited to a thickness of about 200 nm on pad oxide film 32 and used as an anti-oxidation film when element isolation, thermally oxidized film 35 was formed ( 103 in FIG. 3).
  • Photoresist 43 was formed on silicon nitride film 42 ( 104 in FIG. 3).
  • Photoresist 43 at a desired position was removed by an ordinary light exposure procedure, and then parts of silicon nitride film 42 , pat oxide film 32 and silicon substrate 31 were removed by etching, and a shallow groove was trenched at a predetermined angle of the inside wall of the groove to the surface of silicon substrate 31 (for example, at an angle of 95° to 110° shown by A in FIG. 2D) ( 105 to 107 in FIG. 3).
  • Photoresist 43 was removed and then pad oxide film 32 was recessed (or partially removed) in an extent of to 40 nm by etching ( 108 and 109 in FIG. 3).
  • the surface of silicon substrate 31 was thermally oxidized to a thickness of about 30 nm, for example, in a dry oxidative atmosphere at 900° to 1,000° C. to form a heat (or thermal)-oxidized film 35 on the inside wall of the groove ( 110 in FIG. 3).
  • An isolation film such as a silicon oxide film, etc. was deposited thereon by chemical vapor deposition (CVD), sputtering etc. to embed (or bury) the isolation film in the groove (the isolation film will be hereinafter referred to as embedding isolation film 36 ).
  • the silicon oxide film, etc. deposited by chemical vapor deposition, sputtering, etc. are usually porous films, and thus after the deposition of embedding isolation film 36 silicon substrate 31 may be annealed at about 1,000 0 C. or oxidized in an oxidative atmosphere at 1,000° C. to make the film compact ( 111 In FIG. 3)
  • Embedding isolation film 36 was etched back by chemical mechanical polishing (CMP) or dry etching, where silicon nitride film 42 used as an anti-oxidation film served as an etching stopper to prevent silicon substrate 31 below silicon nitride film 42 from etching ( 112 in FIG. 3).
  • CMP chemical mechanical polishing
  • dry etching where silicon nitride film 42 used as an anti-oxidation film served as an etching stopper to prevent silicon substrate 31 below silicon nitride film 42 from etching ( 112 in FIG. 3).
  • FIG. 4 shows results of analyzing changes in radius of curvature of the silicon substrate 31 at the groove upper edge by changing the extent of recessing pad oxide film 32 , where the extent of recessing pad oxide film 32 is given on the axis of abscissa and the radius at curvature of silicon substrate at the groove upper edge on the exist of ordinate.
  • the radius of curvature of the substrate at the groove upper edge increases with increasing extent of recessing pad oxide film 32 from zero, reaches about 25 nm with a recessing extent of 5 nm and further increases to about 35 nm with a recess extent of 20 nm.
  • a step is formed on the upper side of the substrate at the groove upper edge, reducing the radius of curvature, for example, to 25 nm with a recessing extent of 60 nm.
  • the oxide film starts to grow during the groove oxidation, while undergoing approximately 2-fold volumic expansion between silicon nitride film 42 and silicon substrate 31 (FIGS. 5A and 5B).
  • edge of silicon nitride film 42 is pushed upwards by the volumic expansion, deforming the silicon nitride film into a upwardly warped concave shape.
  • a counterforce develops due to the warping deformation of silicon nitride film 42 , resulting in development of compression stress both in the oxide film (including part of pad oxide film 32 ) below silicon nitride film 42 and in the silicon substrate (FIG. SA).
  • the compression stress develops, diffusion of oxidative seeds, that is, progress of oxidation reaction, is suppressed, so that the rate of oxidation is considerably lowered at the groove upper edge.
  • the growth direction (direction normal to the inside wall surface) of the oxide film is free from any restriction, that is, there is no inhibiting factor against the volumic expansion of the growing oxide film, and thus oxidation can process on the inside wall surface without any restriction in contrast to the oxidation of the groove upper edge.
  • the substrate shape is sharpened at the groove upper edge of silicon substrate 31 with progress of oxidation, as shown by dotted lines in FIG. 5A.
  • the oxide film growing on the exposed part will be brought into contact with the silicon nitride film, followed by rapid development of a compression stress, as explained above. That is, the radius of curvature so far attained will be again decreased.
  • no step is formed any more on the substrate around the upper edge of groove isolation stricture and a much larger radius of curvature than 3 nm can be obtained by restricting an extent of recessing the pad oxide film to a range of 5 to 40 nm, and thus an increase in transistor leakage current or a decrease in gate breakdown voltage due to the field concentration around the edge of gate electrode film can be effectively prevented and also the transistor electric reliability can be be effectively improved.
  • the shoulder edge of the groove can more preferably rounded by providing an undercut, as shown in FIG. 34, before trenching the groove.
  • FIG. 6 is a modification of step
  • Silicon nitride film 42 was deposited on pad oxide film 32 to a thickness of about 200 nm, and used as an anti-oxidation film when element isolation, thermally oxidized film 35 was formed ( 203 in FIG. 6).
  • Photoresist 43 was formed on silicon nitride film 42 ( 204 in FIG. 6).
  • Photoresist 43 at a desired position was removed by an ordinary light exposure procedure, and then parts of silicon nitride film 42 , pad oxide film 32 and silicon substrate 31 were removed by etching, and a shallow groove was trenched at a predetermined angle of the inside wall of the groove to the surface of silicon substrate 31 (for example, at an angle of 95° to 110° as shown by A in FIG. 2D) ( 205 to 207 in FIG. 6).
  • Photoresist 43 was removed and then pad oxide film 32 was recessed in an extent of 5 to 40 nm by etching ( 208 and 209 in FIG. 6).
  • An isolation film such as a silicon oxide film, etc. was deposited thereon by chemical vapor deposition (CVD), sputtering, etc. to embed the isolation film in groove (the isolation film will be hereinafter referred to as embedding isolation film 36 ).
  • the silicon oxide film, etc. deposited by chemical vapor deposition, sputtering, etc. are usually porous films and thus after the deposition of embedding isolation film 36 silicon substrate 31 may be annealed at about 1,000° C. or oxidized in an oxidative atmosphere at about 1,000° C. to make the film compact ( 211 in FIG. 6).
  • Embedding isolation film 36 was etched back by chemical mechanical polishing (CMP) or dry etching, where silicon nitride film 42 used as an anti-oxidation film served as an etching stopper to prevent silicon substrate 31 below silicon nitride film 42 from etching ( 212 in FIG. 6).
  • CMP chemical mechanical polishing
  • dry etching where silicon nitride film 42 used as an anti-oxidation film served as an etching stopper to prevent silicon substrate 31 below silicon nitride film 42 from etching ( 212 in FIG. 6).
  • a gas flow rate ratio of H 2 /O 2 ofthe oxidative atmosphere can be changed in a range of 0 ⁇ r ⁇ 2 but when r reaches 2 the reaction proceeds explosively. From the viewpoint of safety, the upper limit to r will be substantially about 1.8.
  • the rate of oxidation increases with increasing gas flow rate ratio, whereas the rate of oxidation decreases with decreasing gas flow rate ratio.
  • Oxidation develops a strain (stress) around the boundary between the silicon substrate and the silicon oxide film, as already mentioned above.
  • the silicon oxide film shows a remarkable viscous behavior at a high temperature (900° C. or higher), and thus the developed stress is lessened at a high temperature with time.
  • the thickness of the oxide film is presumed constant, the time required for lessening the developed stress will be shorter with increasing rate of oxidation (larger gas flow rate ratio of H 2 /O 2 ), though the developed strain (stress) value is constant. Consequently, the residual stress will be increased.
  • the viscous effect of silicon oxide film can be brought about, so that the stress lessening proceeds relatively as compared under the conditions of constant oxide film thickness.
  • the region of silicon substrate around the upper edge of the groove is a stress-concentrated site due to the growth of oxide film on the substrate upper side and the groove inside, and when the residual stress becomes higher, the oxidation around the stress concentrated site will be inhibited, so that the upper edge of the groove in silicon substrate will be sharpened. That is, oxidation of the semiconductor substrate around the upper edge of the groove can proceed in a low stress state by making a gas flow rate ratio of H 2 /O 2 lower, so that the rounding of silicon substrate 31 can be attained around the upper edge of the groove.
  • the radius of curvature of the substrate around the upper edge of the groove in the groove isolation structure can be made much larger than 3 nm according to the second embodiment of the present invention
  • the extent of recessing the pad oxide film is set in a range of 5 to 40 nm as given in the first embodiment of the present invention, the step development on the upper surface of the substrate at the upper edge of the groove can be prevented. That is, an increase in transistor leakage current or a decrease in gate breakdown voltage due to the field concentration around the edge of gate electrode film can be effectively prevented and also the transistor electric reliability can be effectively improved.
  • the shoulder edge of the groove can be more preferably rounded by providing an undercut, as shown in FIG. 34, before trenching the groove.
  • Process for producing an embedded groove structure of a semiconductor device according to the third embodiment of the present invention (flow chart) shown in FIG. 8 is a modification of step (6) of the process according to the first embodiment of the present invention.
  • the embedded groove structure of the third embodiment is not largely different in structure, etc. from that of the first embodiment, and thus the steps of the third embodiment will be explained below, referring to the flow chart of FIG. 8, using the cross-sectional structural elevation views of the semiconductor device shown in FIGS. 2A to 2 I.
  • Silicon nitride film 42 was deposited on pad oxide film 32 to a thickness of about 200 nm, and used as an anti-oxidation (film when element isolation, thermally oxidized film 35 was formed ( 303 in FIG. 8).
  • Photoresist 43 was formed on silicon nitride film 42 ( 304 in FIG. 5).
  • Photoresist film 43 at a desired position was removed by an ordinary light exposure procedure, and then parts of silicon nitride film 42 , pad oxide film 32 and silicon substrate 31 were removed by etching, a shallow groove was trenched at a predetermined angle of inside wall of the groove to the surface of silicon substrate 31 (for example, at an angle of 95° to 110° as shown by A in FIG. 2D) ( 305 to 307 in FIG. 8).
  • Photoresist 43 was removed and then pad oxide film 32 was recessed in an extent of 5 to 40 nm by etching ( 308 and 309 in FIG. 8).
  • An isolation film such as a silicon oxide film, etc. was deposited thereon by chemical vapor deposition (CVD), sputtering, etc. to embed the isolation film in the groove (the isolation film will be hereinafter referred to as embedding isolation film 36 ).
  • the silicon oxide film, etc., deposited by chemical vapor deposition, sputtering, etc are usually porous films and thus after the deposition of embedding isolation film 36 silicon substrate 31 may be annealed at about 1,000° C. or oxidized in an oxidative atmosphere at about 1,000° C. to make the film compact ( 311 in FIG. 8).
  • Embedding isolation film 36 was etched back by chemical mechanical polishing (CMP) or dry etching, where silicon nitride film 42 used as an anti-oxidation film served as an etching stopper to prevent silicon substrate 31 below silicon nitride film 42 from etching ( 312 in FIG. 8)
  • CMP chemical mechanical polishing
  • dry etching silicon nitride film 42 used as an anti-oxidation film served as an etching stopper to prevent silicon substrate 31 below silicon nitride film 42 from etching ( 312 in FIG. 8)
  • silicon nitride film 42 undergoes upward warping deformation when the recess space formed up to the edge of the pad oxide film is fully filled by oxidation, and a compression stress develops on pad oxide film 32 below silicon nitride film 43 and silicon substrate 31 by a compression force due to the bending of film 43 , so that the oxidation is inhibited by the stress, sharpening the silicon substrate around the upper edge of the groove.
  • the oxidation is carried out just before the recess space formed up to the edge of pad oxide film 32 is fully filled, no compression stress due to the warping deformation develops any more, so that the oxidation smoothly proceeds at the upper corner end of silicon substrate 31 , rounding silicon substrate 31 around the upper end of the groove. Furthermore, the extent of recessing the pad oxide film is limited to a range of 5 to 40 nm, as given in the first embodiment of the present invention, development of a step on the upper surface of the silicon substrate at the upper edge of the groove can be prevented.
  • the radius of curvature of the substrate around the upper edge of the groove in the groove isolation structure can be made much larger than 3 nm according to the third embodiment of the present invention. Furthermore, the step development on the upper surface of the substrate at the upper edge of the groove can be prevented, so that an increase in transistor leakage current or a decrease in gate breakdown voltage due to the field concentration around the end of gate electrode film can be effectively prevented and also the transistor electric reliability can be effectively improved.
  • the shoulder edge of the groove can be more preferably rounded by providing an undercut, as shown in FIG. 34, before trenching the groove.
  • Embedded groove structure of a semiconductor device according to a fourth embodiment of the present invention and steps of producing the embedded groove structure will be explained below, referring to FIGS. 2A to 2 I and FIG. 9.
  • FIGS. 2A to 2 I are cross-sectional structural elevation views of a semiconductor device according to the fourth embodiment of the present invention and FIG. 9 is a flow chart showing outlines of steps of producing the present semiconductor device. Steps of producing the present semiconductor device will be explained below along the flow chart of FIG. 9, referring to FIGS. 2A to 2 I.
  • Silicon nitride film 42 was deposited on pad oxide film 32 to a thickness of 10 to 300 nm, and used as an anti-oxidation film when element isolation, thermally oxidized film 35 is formed ( 403 in FIG. 9).
  • Photoresist 43 was formed on silicon nitride film ( 404 in FIG. 9).
  • Photoresist film 43 at a desired position was removed by an ordinary light exposure procedure, and then parts of silicon nitride film 42 , pad oxide film 32 and silicon substrate 31 were removed by etching, and a shallow groove was trenched at a predetermined angle of inside wall of the groove to the surface of silicon substrate 31 (for example, at an angle of 95° to 110° as shown by A in FIG. 2D) ( 405 to 407 in FIG. 9).
  • Photoresist 43 was removed and then pad oxide film 32 was recessed in an extent of 5 to 40 nm by etching ( 408 and 409 in FIG. 9).
  • silicon substrate 31 was thermally oxidized at an oxidation temperature of 900° to 1,000° C. in an to form thermally oxidized film 35 in the range wherein the recess space formed up to the edge of the recessed pad oxide film is filled with the thermally oxidized film ( 410 in FIG. 9).
  • An isolation film such as a silicon oxide film, etc. was deposited thereon by chemical vapor deposition (CVD), sputtering, etc. to embed the isolation film in the groove (the isolation film will be hereinafter referred to as embedding isolation film 36 ).
  • the silicon oxide film, etc. deposited by chemical vapor deposition, sputtering, etc. are usually porous films and thus after the deposition of embedding isolation film 36 silicon substrate 31 may be annealed at about 1,000 C. or oxidized in an oxidative atmosphere at about 1,000° C. to make the film compact ( 411 in FIG. 9).
  • Embedding isolation film 36 was etched back by chemical mechanical polishing (CMP) or dry etching, where silicon nitride film 42 used as an anti-oxidation film served as an etching stopper to prevent silicon substrate 31 below silicon nitride film 42 from etching ( 412 in FIG. 9).
  • CMP chemical mechanical polishing
  • dry etching where silicon nitride film 42 used as an anti-oxidation film served as an etching stopper to prevent silicon substrate 31 below silicon nitride film 42 from etching ( 412 in FIG. 9).
  • Silicon nitride film 42 and pad oxide film 32 were removed, whereby the embedded groove structure was completed ( 413 in FIG. 9). Then, a semiconductor device was fabricated through necessary mounting procedures for producing a transistor structure, for example, by formation of gate oxide films and gate electrodes, doping with impurities, formation of wirings, interlayer insulating films, etc., and formation of a surface protective film, etc.
  • the substrate has no step on the upper surface, and a nonotonously convexed shape around the upper edge of the groove, the oxide film thickness is in a range of 5 to 70 nm at the inside wall of the groove at the intermediate level of the groove isolation structure and the radius of curvature at the upper corner edge of semiconductor substrate is in a range of 3 to 35 nm.
  • FIG. 10 shows results of simulation of relations between the oxidized amount (thickness) of the element isolation, thermally oxidized film at the inside wall of the groove at the intermediate level and the radius of curvature at the upper corner edge of the substrate according to the fourth embodiment of the present invention, where “a” indicates a thickness of pad oxide film.
  • the radius of curvature R at the upper corner edge of silicon substrate increases with increasing oxidized amount of inside wall of the groove, and reaches a maximum value.
  • the maximum value depends upon the thickness a of pad oxide film, and increases with increasing thickness a, but reaches a constant value (about 35 mn) above a thickness a of 10 nm or more.
  • the reason why the radius of curvature takes a maximum value is that the radius of curvature increase with progress of groove oxidation, and the recess space formed up to the edge of the recessed pad oxide film is gradually filled by the oxidation, resulting in development of upward warping deformation of the silicon nitride film (development of a compression stress on the silicon substrate and oxide film) with intrusion of oxidation therein, as shown in FIG. SA and consequent inhibition of oxidation by the compression stress, making the radius of curvature smaller. Further, with an increase of oxidation amount stress in the thermal oxide film at the upper edge portions of groove increases probably due to inhibition of the oxidation.
  • the radius of curvature R gives no adverse effect on the transistor characteristics, so far as it is about 3 nm or more.
  • the oxidized amount on the inside wall of the groove is 5 nm or more, which can ensure the necessary radius of curvature, as given in FIG. 10. Even by oxidation over an oxidized amount of 30 nm the radius of curvature no more increases. Thus, to maximize the radius of curvature, it is preferable to make the thickness of pad oxide film 10 nm or more and the oxidized amount of groove inside wall 30 nm or more.
  • the substrate at the upper edge ofthe groove can have a monotonously convexed surface.
  • the shoulder edge of the groove can be more preferably rounded by providing an undercut, as shown in FIG. 34, before trenching the groove.
  • the radius of curvature of the substrate around the upper edge of the groove can be made as large as about 35 nm, and the substrate has no step on the upper surface at the upper edge of the groove, and thus an increase in transistor leakage current or gate breakdown voltage due to the field concentration around the end of gate electrode film can be effectively prevented and also the transistor electric reliability can be effectively improved.
  • the present invention can provide a semiconductor device having a groove isolation structure without deterioration of gate breakdown voltage of transistors, and also a process for producing the same.
  • CMOSFET complementary MISFET
  • semiconductor substrate 1 of p-type single crystal silicon having a resistivity of about 1 to 10 ⁇ cm was thermally oxidized at a temperature of 800° to 850° C. to form a silicon oxide film (pad oxide film) 2 destined to stress lessening and protection of an active region on the principal side (or surface) thereof, and then silicon nitride film 3 was deposited on silicon oxide film 2 by CVD.
  • silicon nitride film 3 and silicon oxide film 2 in an element isolation region were removed by etching, using a photoresist as a mask, and then, as shown in FIG. 13, groove 4 a was trenched to a depth of 350 to 400 nm on semiconductor substrate 1 in the element isolation zone by etching, using silicon nitride film 3 as a mask.
  • the shoulder edge of the groove could be more preferably rounded by providing an undercut, as shown in FIG. 34, before trenching groove 4 a .
  • Inside wall of groove 4 a was tapered, for example, at angles ⁇ 1 and ⁇ 2 of 85° or less at the lower and upper corner ends of the substrate, respectively, by adjusting a gas composition for etching semiconductor substrate 1 .
  • a gas composition for etching semiconductor substrate 1 By taping the inside wall of groove 4 a , an isolation film can be easily embedded in groove 4 a.
  • Groove 4 a could be also trenched by successively etching silicon nitride film 3 , silicon oxide film 2 and semiconductor substrate 1 residing in the element isolation region, using the photoresist as a mask.
  • semiconductor substrate 1 was etched, using the photoresist as a mask, a decrease in the thickness of silicon nitride film 3 serving as a mask for heat oxidation could be prevented. That is, the initial thickness of silicon nitride film 3 could be made smaller.
  • FIG. 14 and FIG. 15 which is an enlarged view of the essential part of FIG. 14, silicon oxide film exposed to the inside wall of groove 4 a was removed by a hydrofluoric acid-based etching solution to recess the silicon oxide film towards the active region.
  • semiconductor substrate 1 was thermally oxidized, for example, at 950° C. to form silicon oxide film 5 on the inside wall of groove 4 a .
  • Silicon oxide film 5 was formed to remedy etching damages on the inside wall of groove 4 a and also to lessen a stress on silicon oxide film 6 to be embedded in groove 4 a in a successive step.
  • Thickness Tr of silicon oxide film 5 was made larger than thickness Tp of silicon oxide film (pad oxide film) 2 but three times as large as Tp, that is, in a range of Tp ⁇ Tr ⁇ 3Tp, by controlling the oxidation time, thereby rounding the shoulder edge of groove 4 a .
  • silicon oxide film 7 was deposited on the principal side (or surface) of semiconductor substrate 1 by CVD to embed silicon oxide film 7 in groove 4 a .
  • Silicon oxide film 7 was made from a silicon oxide material having a good flowability as in a silicon oxide film formed from, for example, ozone (O 3 ) and tetraethoxysilane ((C 2 H 5 ) 4 Si).
  • silicon nitride film 6 Prior to the step of depositing silicon oxide film 7 , silicon nitride film 6 could be thinly deposited on the inside wall of groove by CVD, as shown in FIG.
  • silicon nitride film 6 served to suppress growth of silicon oxide film 5 on the inside wall of groove 4 a towards the active region when sintering silicon oxide film 7 embedded in groove 4 a in a successive step and thus to suppress such an inconvenience as formation of leak path due to development of a stress on semiconductor substrate 1 in the active region by silicon oxide film 5 .
  • semiconductor substrate 1 was wet oxidized at a temperature of not more than 1,000 0 C., for example, 850° C., to sinter silicon oxide film 7 embedded in groove 4 a , thereby improving the quality of silicon oxide film 7 .
  • silicon oxide film 7 was polished, for example, by chemical mechanical polishing (CMP) to flatten the surface. Polishing was carried out with silicon nitride film 3 covering the active region as a stopper to leave silicon oxide film 7 only in groove 4 a , thereby an element isolation groove 4 embedded with silicon oxide film 7 was completed. Then, as shown in FIG. 2I, silicon nitride film 3 covering the active region was removed by an etching solution such as hot phosphoric acid, etc.
  • CMP chemical mechanical polishing
  • Sintering of silicon oxide film 7 embedded in groove 4 a could be carried out after silicon oxide film 7 was polished by CMP to leave silicon oxide film 7 only in groove 4 a .
  • the thickness of silicon oxide film 7 to be sintered was smaller than that when the sintering was carried out before polishing silicon oxide film 7 , and thus sintering time could be shortened.
  • silicon oxide film 7 having a thickness large enough to prevent formation of voids in the film was deposited, as shown in FIG. 22, and then polycrystalline silicon film 8 was deposited thereon by CVD, as shown in groove 4 a .
  • silicon nitride film 6 Prior to the step of depositing silicon oxide film 7 , silicon nitride film 6 could be thinly deposited on the inside wall of groove 4 a and silicon nitride film 3 by CVD to suppress growth of silicon oxide film 5 towards the active region during the sintering.
  • semiconductor substrate 1 was heat-treated (or annealed) under the above-mentioned conditions to sinter silicon oxide film 7 .
  • polycrystalline silicon film 8 on silicon oxide film 7 was thermally oxidized to and converted to silicon oxide film 8 a as shown in FIG. 24.
  • silicon oxide film 8 a and silicon oxide film 7 were polished to obtain an element isolation groove 4 free from voids.
  • a complementary MISFET was formed in the active region of semiconductor substrate 1 whose circumference was confined by element isolation groove 4 in the following manner:
  • silicon oxide film Grad oxide film) 2 remaining on the surface of the active region was removed by a hydrofluoric acid solution, etc. and then, as shown in FIG. 26, semiconductor substrate 1 was thermally oxidized at a temperature of 800° to 850° C. to form a clean gate oxide film 9 on the surface of semiconductor substrate 1 .
  • the shoulder edge of element isolation groove 4 was rounded, thereby preventing such an inconvenience as thinning of gate oxide film 9 at the shoulder edge.
  • n-type impurities such as phosphorous (P), etc. were ion-implanted onto part of semiconductor substrate 1 and p-type impurities such as boron (B), etc. were ion-implanted on the other part thereof, and then semiconductor substrate 1 was heat-treated at a temperature of not more than 1,000° C., conduct extended diffusion of the two kinds of impurities, thereby forming p-type well 10 in n-channel type MISFET-forming region an d n-type well 11 on p-channel type MISFET-forming region.
  • Gate oxide film 9 could be formed on the surfaces of p-type well 10 and n-type well 11 , after their respective formation.
  • gate electrode 12 for the n-channel type MISFET was formed on p-type well 10
  • gate electrode 12 for p-channel type MISFET was formed on n-type well 11 .
  • gate electrode 12 for example, a p-doped polycrystalline silicon film, a tungsten (W) silicide film and a cap isolation film 13 were deposited successively on semiconductor substrate 1 by CVD, and then these films were patterned by etching, using a photoresist as a mask thereby obtaining gate electrode 12 .
  • Cap isolation film 13 was made from a silicon oxide film or a silicon nitride film.
  • p-type well 10 was ion-implanted with n-type impurities such as P, etc. to form n-type semiconductor region (source, drain) 14 of n-channel type MISFET, and n-type well 11 was ion-implanted with p-type impurities such as B (boron) etc. to form p-type semiconductor region (source, drain) 15 of p-channel type MISFET, thereby obtaining an n-channel type MISFETQ n and p-channel type MIlSFETQ p .
  • n-type impurities such as P, etc.
  • p-type impurities such as B (boron) etc.
  • side wall spacer 16 was formed on the side wall of gate electrode 12 .
  • Side wall spacer 16 was formed by depositing a silicon oxide film or a silicon nitride film on semiconductor substrate 1 by CVD and patterning the film by anisotropic etching.
  • silicon oxide film 17 was deposited on semiconductor substrate 1 by CVD, and then, as shown in FIG. 32, contact holes 18 were formed through silicon oxide film 17 on n-type semiconductor region (source, drain) 14 of n-channel type MISFETQ n , and p-type semiconductor region (source, drain) of p-channel type MISFETQ n , respectively, and an aluminum (Al) alloy film deposited on silicon oxide film 17 by sputtering was patterned to form wiring 19 .
  • Al aluminum
  • a process for forming element isolation groove 4 according to a still further embodiment of the present invention will be explained below, referring to FIGS. 33 to 36 .
  • semiconductor substrate 1 was thermally oxidized at a temperature of 800° to 850° C. to form silicon oxide film (pad oxide film) 2 on the principal side (or surface) of semiconductor substrate 1 , and then silicon nitride film 3 was deposited on silicon oxide film 2 by CVD. Then, silicon nitride film 3 and silicon oxide film 2 in an element isolation region were removed by etching, using a photoresist as a mask.
  • semiconductor substrate 1 in the element isolation region was anisotropically etched by changing an etching gas composition, etc. to form groove 4 a on semiconductor substrate 1 in the element isolation region.
  • semiconductor substrate 1 was thermally oxidized, for example, at 950° C. to form silicon oxide film 5 on the inside wall of groove 4 a and round the shoulder edged groove 4 a at the same time.
  • the successive steps were carried out in the same manner as in Example 5.
  • undercut a was formed at the shoulder edge of groove 4 a prior to the step of forming silicon oxide film 5 on the inside wall of groove 4 a , whereby the shoulder edge of groove 4 a could be rounded. Formation of undercut a at the shoulder edge of groove 4 a according to this embodiment could be also carried out together with recessing of silicon oxide film 2 exposed to the inside wall of groove 4 a towards the active region according to Example 5.
  • silicon oxide film 5 was formed on the inside wall of groove 4 a and the shoulder edges of groove 4 a were rounded at the same time in the same manner as in Examples 1 to 3 , and then, as shown in FIG. 38, silicon nitride film 6 was thinly deposited on semiconductor substrate 1 by CVD. Silicon nitride film 6 was formed to suppress growth of silicon oxide film 5 on the inside wall of groove 4 a towards the active region during sintering of silicon oxide film 7 embedded in groove 4 a in a successive step.
  • silicon oxide film 7 was deposited on semiconductor substrate 1 by CVD to embed silicon oxide film 7 in groove 4 a , and then semiconductor substrate 1 was wet oxidized or annealed in the same temperature conditions as described before to sinter silicon oxide film 7 embedded in groove, thereby improving the quality of silicon oxide film 7 .
  • silicon oxide film 7 was polished by chemical mechanical polishing to leave silicon oxide film 7 only in groove 4 a , thereby forming an element isolation groove 4 .
  • silicon nitride film 3 covering the active region was to be etched with an etching solution such as hot phosphoric acid, etc.
  • silicon nitride film 6 on the inside wall of element isolation groove 4 was etched away at the same time, as shown in FIG. 41, thereby recessing silicon nitride film 6 inwardly into element isolation region 4 and forming a recess at the shoulder edge of element isolation groove 4 .
  • silicon oxide film 7 at the shoulder edge of element isolation groove 4 was reoxidized at a temperature of 850° to 900° C. to make the film thickness larger, thereby sealing the recess by silicon oxide film 7 .
  • silicon oxide film 7 it was necessary to make an increment of the film thickness at least twice as large as the thickness of silicon nitride film 6 .
  • the increment of the film thickness was too large, the active region was narrowed by grown silicon oxide film 5 .
  • an increment of the film thickness was made twice as large as the thickness of silicon nitride film 6 or slightly higher than the double thickness of silicon nitride film 6 by controlling oxidation time.
  • silicon oxide film 7 was polished by chemical mechanical polishing to leave silicon oxide film 7 only in groove 4 a , followed by sintering.
  • the surface of silicon nitride film 3 covering the active region and silicon nitride film 6 at the shoulder edge of element isolation groove 4 could be oxidized.
  • the oxide film on silicon nitride film 3 was removed by etching and successively silicon nitride film 3 was removed by etching, whereby formation of a recess at the shoulder edge of element isolation groove 4 could be prevented, as shown in FIG. 44.
  • silicon oxide film 5 was formed on the inside wall of groove 4 (i and the shoulder edge of groove 4 a was rounded at the same time in the same manner as in Examples 1 to 3 , and then, as shown in FIG. 46, the inside wall of groove 4 a was subjected to soft nitriding to segregate nitrogen in the region near the boundary between silicon oxide film 5 formed on the inside wall of groove 4 a and the side wall of the active region of semiconductor substrate 1 , thereby forming silicon nitride layer 20 .
  • semiconductor substrate 1 was heat-treated in a NO (nitrogen oxide) or N 2 O (dinitrogen oxide) atmosphere, where nitrogen released by thermal decomposition of NO or N 2 O was segregated in the region near the boundary between silicon oxide film 5 and the active region of semiconductor substrate 1 , and then silicon nitride layer 20 was formed by heat treatment.
  • NO nitrogen oxide
  • N 2 O dinitrogen oxide
  • silicon nitride layer 20 was formed in the region near the boundary between silicon oxide film 5 and the active region of semiconductor substrate 1 , whereby the region near the boundary was hard to oxidize during the sintering of silicon oxide film 7 later embedded in groove 4 a and thus growth of silicon oxide film 5 towards the active region could be suppressed.
  • silicon oxide film 5 was formed on the inside wall of groove 4 a and the shoulder edge of groove 4 a was rounded in the same manner as in Examples 1 to 3 , and then, as shown in FIG. 48, nitrogen was ion-implanted in the region near the boundary between silicon oxide film 5 and the active region of semiconductor substrate 1 , if necessary, followed by heat treatment.
  • groove 4 a was trenched on semiconductor substrate 1 in an element isolation region by etching, using silicon nitrogen film 3 as a mask, and then silicon oxide film 2 exposed to the inside wall of groove 4 a was removed with a hydrofluoric acid-based etching solution to recess silicon oxide film 2 towards the active region. Steps up to this stage were the same as in Examples 1 to 3.
  • semiconductor substrate 1 was subjected to soft nitriding to form silicon nitride film 21 on the inside wall of groove 4 a and round the shoulder edge of groove 4 a at the same time.
  • semiconductor substrate 1 was heat-treated in a mixed NO and N 2 atmosphere at a temperature of about 900° C. or in a mixed N 2 O and N 2 atmosphere at a temperature of 1,050° C.
  • silicon nitride film 21 was formed on the inside wall of groove 4 a , whereby the region near the above-mentioned boundary was hard to oxidize during the sintering of silicon oxide film 7 later embedded in groove 4 a and thus growth of silicon oxide film 5 towards the active region could be suppressed.
  • a process for forming element isolation groove 4 according to a still further embodiment of the present invention will be explained below, referring to FIGS. 51 to 54 .
  • groove 4 a was trenched on semiconductor substrate 1 in an element isolation region by etching, using silicon nitride film 3 as a mask, and then, as shown in FIG. 52, silicon oxide film 2 exposed to the inside wall of groove 4 a was removed by a hydrofluoric acid-based etching solution to recess silicon oxide film 2 towards the active region. Steps up to this stage were the same as in Examples 1 to 3.
  • silicon oxide film 7 was deposited on semiconductor substrate 1 by CVD to embed silicon oxide film 7 in groove 4 a .
  • semiconductor substrate 1 was wet oxidized or annealed to sinter silicon oxide film 7 .
  • silicon oxide film 5 was formed on the inside wall of groove 4 a and the shoulder edge of groove 4 a was rounded.
  • groove 4 a was trenched on semiconductor substrate 1 in an element isolation zone by etching, using silicon nitride film 3 as a mask, and then silicon oxide film 2 exposed to the inside wall of groove 4 a was removed by a hydrofluoric acid-based etching solution to recess silicon oxide film 2 towards the active region. Steps up to this stage were the same as in Examples 1 to 3.
  • silicon oxide film 7 was deposited on semiconductor substrate 1 by CVD to embed silicon oxide film 7 in groove 4 a , and then, as shown in FIG. 57, silicon oxide film 7 on silicon nitride film 3 was removed to leave silicon oxide film 7 only in groove 4 a , thereby forming element isolation groove 4 embedded with silicon oxide film 7 .
  • semiconductor substrate 1 was wet oxidized to sinter silicon oxide film 7 .
  • silicon oxide film was formed on the inside wall of groove 4 a and the shoulder edge of groove 4 a was rounded.
  • a process for forming element isolation groove 4 according to a still further embodiment of the present invention will be explained below, referring to FIGS. 59 to 64 .
  • groove 4 a was trenched on semiconductor substrate 1 in an element isolation region by etching, using silicon nitride film 3 as a mask, and then silicon oxide film 2 exposed to the inside wall of groove 4 a was removed by a hydrofluoric acid-based etching solution to recess silicon oxide film 2 towards the active region.
  • semiconductor substrate 1 was thermally oxidized to form silicon oxide film 5 on the inside wall of groove 4 a and round the shoulder edge of groove 4 a at the same time. Steps up to this stage were the same as in Examples 1 to 3.
  • polycrystalline silicon film 22 was shallowly deposited on semiconductor substrate 1 by CVD, and then, as shown in FIG. 62, silicon oxide film 7 was deposited on polycrystalline silicon film 22 by CVD to embed silicon oxide film 7 in groove 4 a.
  • semiconductor substrate 1 was wet oxidized to sinter silicon oxide film 7 embedded in groove 4 a .
  • at least a portion of polycrystalline silicon film 22 was oxidized and converted to silicon oxide film 23 .
  • oxidation of the region near the boundary between silicon oxide film 5 and the active region of semiconductor substrate 1 was suppressed, so that growth of silicon oxide film 5 towards the active region was inhibited.
  • polycrystalline silicon film 22 was oxidized to silicon oxide film 23 , its volume was increased to about twice as large as the original. That is, even when voids were formed in silicon oxide film 7 embedded in groove 4 a , the voids could be effectively constricted by the volume increase of silicon oxide film 23 .
  • silicon oxide film 7 and silicon oxide film 23 on silicon nitride film 3 were removed to leave silicon oxide films 7 and 23 only in groove 4 a , thereby forming element isolation groove 4 .
  • Sintering of silicon oxide film 7 and oxidation of polycrystalline silicon film 22 could be also carried out after formation of element isolation groove 4 .
  • an amorphous silicon film could be used in place of polycrystalline silicon film 22 .
  • groove 4 a was trenched on semiconductor substrate 1 in an element isolation region by etching, using silicon nitride film 3 as a mask, and then silicon oxide film 2 exposed to the inside wall of groove 4 a was removed by a hydrofluoric acid-based etching solution to recess silicon oxide film 2 towards the active region. Steps up to this stage were the same as in Examples 1 to 3.
  • semiconductor substrate 1 was heat-treated in a nitrogen atmosphere to form silicon nitride film 24 on the inside wall of groove 4 a and round the shoulder edge of groove 4 a at the same time.
  • silicon nitride film 24 was formed on the inside wall of groove 4 a , whereby oxidation of the active region of semiconductor substrate 1 could be inhibited during the sintering of silicon oxide film 7 later embedded in groove 4 a.
  • groove 4 a was trenched on semiconductor substrate 1 in an element isolation region by etching, using silicon nitride film 3 as a mask, and then silicon oxide film 2 exposed to the inside wall of groove 4 a was removed by a hydrofluoric acid-based solution to recess silicon oxide film 2 towards the active region. Steps up to this stage were the same as in Examples 1 to 3 . Then, semiconductor substrate 1 was thermally oxidized to form thin silicon oxide film 25 on the inside wall of groove 4 a .
  • semiconductor substrate 1 was heat-treated in a nitrogen atmosphere to convert silicon oxide film 25 on the inside wall of groove 4 a to silicon nitride film 26 .
  • silicon nitride film 26 was formed on the inside wall of groove 4 a , whereby oxidation of the active region of semiconductor substrate 1 could be inhibited during the sintering of silicon oxide film 7 later embedded in groove 4 a.
  • groove 4 a was trenched on semiconductor substrate 1 in an element isolation region by etching, using silicon nitride film 3 as a mask, and then silicon oxide film 2 exposed to the inside wall of groove 4 a was removed by a hydrofluoric acid-based etching solution to recess silicon oxide film 2 towards the active region. Steps up to this stage were the same as in Examples 1 to 3 . Then, thin polycrystalline silicon film 27 was deposited on semiconductor substrate 1 by CVD.
  • semiconductor substrate 1 was heat-treated in a nitrogen atmosphere to convert polycrystalline silicon film 27 to silicon nitride film 28 .
  • silicon nitride film 28 was formed on the inside wall of groove 4 a , whereby oxidation of the active region of semiconductor substrate 1 could be inhibited during the sintering of silicon oxide film 7 later embedded in the groove.
  • the shoulder edge of groove 4 a could be more preferably rounded by providing an undercut, as shown in FIG. 34, before trenching groove 4 a.
  • the shape of element isolation region by isolation groove of a semiconductor device can be optimized by low temperature heat treatment at not more than 1,000° C., and the devices can be made finer with improved electric characteristics thereof.

Abstract

A semiconductor device having a highly reliable groove isolation structure with a desired radius of curvature formed at the groove upper edge and without formation of any step, there is produced by reducing the stress generation around the groove upper edge of an element isolation groove on a semiconductor substrate, thereby optimizing the shape of an element isolation groove and making the device finer and improving the device electric characteristics.

Description

    TECHNICAL FIELD
  • The present invention relates to a semiconductor device having a highly reliable groove isolation structure and a process for producing the same. [0001]
    • BACKGROUND ART
  • A shallow groove isolation (SGI) structure is now available to make an electrical insulation or isolation between adjacent elements such as transistors, etc. on a semiconductor substrate. As shown in FIGS. 1A to [0002] 1D, the SGI structure typically comprises a shallow groove formed on a semiconductor substrate 31 of silicon and an oxide film 35 and the like embedded in the groove and is suitable for devices requiring processing dimensional precision of 0.25 μn or under, because its processing dimensional precision is higher than that of the structure so far by local oxidation of silicon (LOCOS). However the SGI structure sometimes suffers from formation of sharp protrusions 34 of semiconductor substrate 31 of silicon formed in the oxide film 35 formed by oxidation at the upper edge of the groove during the oxidation step, as shown in FIG. 1C. The presence of such sharp protrusions 34 of semiconductor substrate 31 of silicon causes concentration of electric fields around the protrusions during the circuit operation, sometimes deteriorating gate breakdown voltage or capacitance, as disclosed, for example, by A. Bryant et al (Technical Digest of IEDM '94, pp. 671-674). It is known from experiences that such deterioration of gate breakdown voltage occurs when the radius of curvature of the substrate is not more than 3 nm around the groove upper edge, even if the angle of substrate is not less than 90° around the groove upper edge. To overcome the deterioration, pad oxide film 32 of FIG. 1B is recessed backwards by about 0.1 μm as shown in FIG. 1B′ and oxidized with an oxidant, preferably steam at a temperature of about 1,000° C. to form a desired radius of curvature at the groove upper edges, as disclosed in JP-A-2-260660.
  • Even though the desired radius curvature can be obtained by the prior art procedure, step (or unevenness) [0003] 44 is formed on the upper surface of semiconductor substrate silicon 31 around the groove upper edge, as shown in FIG. 1C′. Such step 44 can be formed presumably due to the following mechanism. That is, semiconductor substrate 31 of silicon has a silicon-exposed region and a silicon-unexposed region in the recessed area at the edge of pad oxide film 32; the silicon-exposed region undergoes faster oxidant diffusion, i.e. faster oxidation, than the silicon-unexposed region resulting in formation of step 44 at the edge of pad oxide film 32 as a boundary. Gate oxide film 37, when formed in such a step region, has an uneven thickness, which leads to variations of electrical properties. Furthermore, stresses are liable to concentrate therein, resulting in a possible decrease in the electrical reliability of a transistors to be formed on step 44.
  • Further, the [0004] silicon oxide film 36 is deposited on the semiconductor substrate 31 by chemical vapor deposition (CVD) to embed the silicon oxide film 36 in the groove and then the semiconductor substrate 31 is heat treated to sinter the silicon oxide film 36 embedded in the groove. Sintering is carried out for improving the quality of the silicon oxide film 36 embedded in the groove. If the sintering is insufficient, voids are often generated in the groove in the subsequent steps.
  • Furthermore, it is said that wet or steam oxidation is effective for sintering the [0005] silicon oxide film 36 embedded in the groove, but the wet or steam oxidation is liable to oxidize the inside, particularly side wall, of the groove. Oxidation starts from the groove surface and thus the groove bottom is less oxidized. Once the groove side wall is oxidized, the active region is narrowed. This is another problem. Thicker oxide film will cause a larger stress on the boundary between the oxide film and the substrate and the once rounded shoulder edge will return to the original sharp one and crystal defects are also generated. This is a further problem. To overcome these problems, it was proposed to provide a silicon nitride film along the groove inside wall.
  • According to a process for forming a groove, disclosed in JP-A-[0006] 8-97277, a groove is trenched on a silicon substrate at first, and then an oxide film is formed on the groove inside surfaces (side wall and bottom surfaces) by heat oxidation, followed by further formation of a silicon nitride film thereon and still further formation of a silicon film such as anyone of amorphous, polycrystalline and monocrystalline silicon films on the silicon nitride film. Then, the groove is embedded with a silicon oxide film completely, followed by flattening of the groove top After the deposition of the silicon oxide film on the entire surface of substrate, but before the fattening, the silicon film is oxidized in an oxidizing atmosphere including steam at about 950° C. to convert it to a silicon oxide film. The silicon substrate is not oxidized during the oxidation, because the silicon substrate is protected by the silicon nitride film. According to the process, a film having a good compatibility with a silicon oxide film, i.e. a silicon film is formed as a thin film on the groove inside surfaces and thus the groove can be embedded with the silicon oxide film without any remaining voids in the groove. The silicon film in the groove must be then converted to a silicon oxide film by oxidation, but the silicon nitride film is provided between the silicon film and the silicon substrate, the silicon substrate is never oxidized during the oxidation of the silicon film. That is, no device characteristics are deteriorated at all.
  • In the above-mentioned prior art processes for forming a groove, heat treatment is carried out at a high temperature such as 1,000° C. or higher to round the shoulder edge of element isolation groove. However, large-dimension wafers are liable to undergo dislocation, which will serve as nuclei for defects, by heat treatment at a high temperature such as 1,000° C. or higher and thus a heat-treatment process at a dimension wafers. In the heat treatment at a low temperature such as less than 1,000° C., it is hard to round the shoulder edge of element isolation groove. [0007]
    • DISCLOSURE OF THE INVENTION
  • An object of the present invention is to provide a semiconductor device with a desired radius of curvature formed at the groove upper end and without formation of any step there, and also a process for producing the same. [0008]
  • The object of the present invention can be attained by reducing the stress generation around the groove upper end of an element isolation groove on a semiconductor substrate. [0009]
  • Another object of the present invention is to provide a novel technique of optimizing the shape of an element isolation groove, thereby making the device finer and improving the device electric characteristics. [0010]
  • Other object of the present invention is to provide a novel technique of reducing an adverse effect of stresses to an active region due to the sintering of a silicon oxide film embedded (or buried) in an element isolation groove on the device characteristics. present invention provides a process for producing a semiconductor device, which comprises the following steps: [0011]
  • (1) a step of forming a pad oxide film having a thickness of at least 5 nm, preferably at least 10 nm on a circuit-forming side of a semiconductor substrate (or a silicon substrate), [0012]
  • (2) a step of forming an anti-oxidation film on the pad oxide film, [0013]
  • (3) a step of trenching a groove to a desired depth at a desired position on the circuit-forming side of the semiconductor substrate, [0014]
  • (4) a step of recessing the pad oxide film to an [0015] extent 5 nm-40 nm from the inside wall of the groove,
  • (5) a step of oxidizing the inside wall of the groove trenched on the semiconductor surface, [0016]
  • (6) a step of embedding an isolation film in the oxidized groove, [0017]
  • (7) a step of removing the embedding isolation film formed on the anti-oxidation film, [0018]
  • (8) a step of removing the anti-oxidation film formed on the circuit-forming side of the semiconductor substrate, and [0019]
  • (9) a step of removing the pad oxide film formed on the circuit-forming side of the semiconductor substrate. [0020]
  • The present invention further provides a semiconductor device which comprises a semiconductor (or silicon) substrate and an element isolation oxide film having a groove isolation structure formed on the circuit-forming side of the semiconductor substrate, where the substrate has a monotonously convexed shape around the upper edge of the groove of the groove isolation structure; the oxide film is oxidized to have a thickness of 5 to 70 nm, preferably 30 to 70 nm at the inside wall of the groove at the intermediate level of the groove isolation structure; and the semiconductor substrate has a radius of curvature in a range of 3 to 35 nm at the upper edge of the groove thereof. [0021]
  • The present invention further provides a process for producing a semiconductor device, which comprises the following steps: [0022]
  • (a) a step of thermally oxidizing a semiconductor (or silicon) substrate, thereby forming a first silicon oxide film as a pad oxide film on the principal side (or surface) of the semiconductor substrate, then depositing a silicon nitride film as an anti-oxidation film on the first silicon oxide film, and then selectively etching the silicon nitride film, the first silicon oxide film and the semiconductor substrate residing in an element isolation region while masking an element region, thereby trenching a groove on the principal side (or surface) of the semiconductor substrate, [0023]
  • (b) a step of etching the first silicon oxide film exposed to inside wall of the groove, thereby recessing the first silicon oxide film from the inside wall of the groove towards an active region to an extent of 5 to 40 nm [0024]
  • (c) a step of thermally oxidizing the semiconductor substrate, thereby forming a second silicon oxide film the inside wall of the groove within the range for filling the second silicon oxide film in the recess space formed up to the edge of the recessed first silicon oxide film and rounding the shoulder edge of the groove at the same time, [0025]
  • (d) a step of depositing a third silicon oxide film on the principal side (or surface) of the semiconductor substrate, thereby embedding the third silicon oxide film in the groove, [0026]
  • (e) a step of heat-treating (or annealing) the semiconductor substrate, thereby sintering the third silicon oxide film embedded in the groove, [0027]
  • (f) a step of removing the third silicon oxide film on the silicon nitride film, while leaving the third silicon oxide film only in the groove, thereby forming an element isolation groove embedded with the third silicon oxide film, and [0028]
  • (g) a step of removing the silicon nitride film on the surface of the active region whose circumference is confined by the element isolation groove and then forming a semiconductor element in the active region. [0029]
  • The present invention further provides a process for producing a semiconductor device, which comprises the following steps: [0030]
  • (a) a step of thermally oxidizing a semiconductor substrate, thereby forming a first silicon oxide film on the principal side (or surface) of the semiconductor substrate, then depositing a silicon nitride film on the first silicon oxide film, and then selectively etching the silicon nitride film and the first silicon oxide film residing in an element isolation region while masking an element region, [0031]
  • (b) a step of isotropically and shallowly etching the surface of the semiconductor substrate in the element isolation region, thereby providing an undercut on the semiconductor substrate at the edge of the element isolation region, [0032]
  • (c) a step of selectively etching the semiconductor substrate in the element isolation region, thereby trenching a groove on the principal side (or surface) of the semiconductor substrate, [0033]
  • (d) a step of thermally oxidizing the semiconductor substrate, thereby forming a second silicon oxide film on the inside wall of the groove and rounding the shoulder edge of the groove at the same time, [0034]
  • (e) a step of depositing a third silicon oxide film on the principal side (or surface) of the semiconductor substrate, thereby embedding the third silicon oxide film in the groove, [0035]
  • (f) a step of heat-treating (or annealing) the semiconductor substrate, thereby sintering the third silicon oxide film embedded in the groove, [0036]
  • (g) a step of removing the third silicon oxide film on the silicon nitride film, while leaving the third silicon oxide film only in the groove, thereby forming an element isolation groove embedded with the third silicon oxide film, and [0037]
  • (h) a step of removing the silicon nitride film on the surface of an active region whose circumference is confined by the clement isolation groove and then forming a semiconductor element in the active region. [0038]
  • The present invention further provides numbers of variations of the above-mentioned processes.[0039]
    • BRIEF DESCRIPTION OF DRAWINGS
  • FIGS. 1A to [0040] 1D and 1B′ and 1C′ schematically show steps of producing a groove isolation structure by the conventional selective oxidation process.
  • FIGS. 2A to [0041] 2I schematically show steps of producing a groove isolation structure according to a first embodiment of the present invention.
  • FIG. 3 is a flow chart showing steps of producing a groove isolation structure according to the first embodiment of the present invention. [0042]
  • FIG. 4 is a diagram showing the working and effect of the first embodiment of the present invention. [0043]
  • FIGS. 5A and 5B show the working and effect of the first embodiment of the present invention. [0044]
  • FIG. 6 is a flowchart showing steps of producing a groove isolation structure according to a second embodiment of the present invention. [0045]
  • FIG. 7 is a diagram showing the working and effect of the second embodiment of the present invention. [0046]
  • FIG. 8 is a flowchart showing steps of producing a [0047] groove 1 isolation structure according to a third embodiment of the present invention.
  • FIG. 9 is a flowchart showing steps of producing a groove structure according to a fourth embodiment of the present invention. [0048]
  • FIG. 10 is a diagram showing the working and effect of the fourth embodiment of the present invention. [0049]
  • FIGS. [0050] 11 to 32 are cross-sectional elevation views of essential part of a semiconductor substrate showing a process for producing a semiconductor device according to Example 5 of the present invention.
  • FIGS. [0051] 33 to 36 are cross-sectional elevation views of essential part of a semiconductor device according to Example 6 of the present invention.
  • FIGS. [0052] 37 to 44 are cross-sectional elevation views of essential part of a semiconductor substrate showing a process for producing a semiconductor device according to Example 7 of the present invention.
  • FIGS. [0053] 45 to 48 are cross-sectional elevation view of essential part of a semiconductor substrate showing a process for producing a semiconductor device according to Example 8 of the present invention.
  • FIGS. [0054] 49 to 50 are cross-sectional elevation views of essential part of a semiconductor substrate showing a process for producing a semiconductor device according to Example 9 of the present invention.
  • FIGS. [0055] 51 to 54 are cross-sectional elevation views of part of a semiconductor substrate showing a process for producing a semiconductor device according to Example 10 of the present invention.
  • FIGS. [0056] 55 to 58 are cross-sectional elevation views of essential part of a semiconductor substrate showing a process for producing a semiconductor device according to Example 11 of the present invention.
  • FIGS. [0057] 59 to 64 are cross-sectional elevation views of essential part of a semiconductor substrate showing a process for producing a semiconductor device according to Example 12 of the present invention.
  • FIGS. 65 and 66 are cross-sectional elevation views of essential part of a semiconductor substrate showing a process for producing a semiconductor device according to Example 13 of the present invention. [0058]
  • FIGS. 67 and 68 are cross-sectional elevation views of essential part of a semiconductor substrate showing a process for producing a semiconductor device according to Example 14 of the present invention. [0059]
  • FIGS. 69 and 70 are cross-sectional elevation views of essential part of a semiconductor substrate showing a process for producing a semiconductor device according to Example 15 of the present invention.[0060]
    • BEST MODE FOR CARRYING OUT THE INVENTION
  • The present process for producing a semiconductor device comprises the following steps: [0061]
  • (1) a step of forming a pad oxide film such as a silicon oxide film to a thickness of at least 5 nm, preferably at least 10 nm, on a circuit-forming side of a semiconductor substrate, [0062]
  • (2) a step of forming an anti-oxidation film such as a silicon nitride film on the pad oxide film, [0063]
  • (3) a step of partially removing the anti-oxidation film and the pad oxide film from a desired position on the circuit-forming side of the semiconductor substrate and further trenching a groove to a desired depth at that position on the surface of the semiconductor substrate, [0064]
  • (4) a step of recessing (or partially removing) the pad oxide film from the edge side of the remaining antioxidation film on the basis of the surface of the semiconductor substrate to an extent of 5 to 40 nm by etching, [0065]
  • (5) a step of heat (or thermal) oxidizing the inside wall of the groove trenched on the semiconductor substrate preferably in an oxidative atmosphere having a gas ratio of H[0066] 2/O2 of less than 0.5 within the range for filling the resulting oxide in the recess space (clearance between the surface of the recess space (clearance oxidation film) formed up to the edge of the recessed pad oxide film,
  • (6) a step of embedding (or burying) an embedding isolation film in the oxidized groove, [0067]
  • (7) a step of removing the embedding isolation film formed on the anti-oxidation film, [0068]
  • (8) a step of removing the anti-oxidation film formed on the circuit-forming side of the semiconductor substrate, and [0069]
  • (9) a step of removing the pad oxide film formed on the circuit-forming side of the semiconductor substrate. [0070]
  • In the above-mentioned process, the shoulder edge of the groove can be more effectively improved by providing a partial undercut a below the [0071] pad oxide film 2, as shown in FIG. 34, before trenching the groove.
  • In the present semiconductor device comprising a semi-essential conductor substrate and an element isolation oxide film having a groove isolation structure formed on the circuit forming side of the semiconductor substrate, produced by the above-mentioned process, the substrate has no step on the upper surface, but a, monotonously convexed shape around the upper edge of the groove of the groove isolation structure; the oxide film is oxidized to have a thickness t of 5 to 70 nm, preferably 30 to 70 nm at the inside wall of the groove at the intermediate level of the groove isolation structure, as shown in FIG. 10; and the semiconductor substrate has a radius of curvature in a range of 3 to 35 nm at the upper edge of the groove thereof. [0072]
  • Typical processes of those to be disclosed herein will be briefly outlined below: [0073]
  • According to a first typical aspect of the present invention, a process for producing a semiconductor device comprises the following steps: [0074]
  • (a) a step of thermally oxidizing a semiconductor substrate, thereby forming a first silicon oxide film as a pad oxide film on the principal side (or surface) of the semiconductor substrate, then depositing a silicon nitride film as an anti-oxidation film on the first silicon oxide film, and then selectively etching the silicon nitride film, the first silicon oxide film and the semiconductor substrate residing in an element isolation region while masking an clement region, thereby trenching a groove on the principal side (or surface) of the semiconductor substrate, [0075]
  • (b) a step of etching the first silicon oxide film exposed to the inside wall of the groove, thereby recessing the first silicon oxide film to an extent of 5 to 40 nm from the groove inside wall towards an active region, [0076]
  • (c) a step of thermally oxidizing the semiconductor substrate, thereby forming a second silicon oxide film on the inside wall of the groove within the range for filling the second silicon oxide film in the recess space formed up to the edge of the recessed first silicon oxide film and rounding the shoulder edge of the groove at the same time, [0077]
  • (d) a step of depositing a third silicon oxide film on the principal side (or surface) of the semiconductor substrate, thereby embedding the third silicon oxide film in the groove, [0078]
  • (e) a step of heat-treating (or annealing) the semiconductor substrate, thereby sintering the third silicon oxide film embedded in the groove, [0079]
  • (f) a step of removing the third silicon oxide film on the silicon nitride film, while leaving the third silicon oxide film only in the groove, thereby forming an element isolation groove embedded with the third silicon oxide film, and [0080]
  • (g) a step of removing the silicon nitride film on the surface of the active region whose circumference is confined by the element isolation groove and then forming a semiconductor element in the active region. [0081]
  • In the first typical aspect of the present process, a thermally oxidizing temperature for forming the first silicon oxide film, a thermally oxidizing temperature for forming the second silicon oxide film and a heat-treating (or annealing) temperature for sintering the third silicon oxide film are all not more than 1,000° C. [0082]
  • In the first typical aspect of the present process, the thermally oxidizing temperature for forming the second silicon oxide film is from 800to 1,000° C. [0083]
  • In the first typical aspect of the present process for producing a semiconductor device, the groove has a taper angle θ of not more than 85°. [0084]
  • In the first typical aspect of the present process, the inside wall of the groove is subjected to an soft nitriding treatment after the step (c) but before the step (d), thereby forming a silicon nitride layer in an area near the boundary between the a second silicon oxide film formed on the inside wall of the groove and the active region of the semiconductor substrate. [0085]
  • In the first typical aspect of the present process, an area near the boundary between the second silicon oxide film formed on the inside wall of the groove and a clement isolation region of the semiconductor substrate is subjected to nitrogen ion implantation after the step (c) but before the step (d), thereby forming a silicon nitride layer in the area near the second silicon oxide film formed on the inside wall of the groove and the clement isolation region of the semiconductor substrate. [0086]
  • In the first typical aspect of the present process, the third silicon oxide film on the silicon nitride film is removed after the step (d), while leaving the third silicon oxide film only in the groove, thereby forming an element isolation groove embedded with the third silicon oxide film, and then heat-treating (or annealing) the semiconductor substrate, thereby sintering the third silicon oxide film embedded in the groove. [0087]
  • In the first typical aspect of the present process, the step [0088]
  • (c) is carried out in a nitrogen-containing atmosphere, thereby forming a second silicon nitride film on the inside wall of the groove just before fully tilling the space formed by recess of the pad oxide film, and rounding the shoulder edge of the groove at the same time. [0089]
  • In the first typical aspect of the present process, a second silicon nitride film is formed at least on the surface of the second silicon oxide film after the step (c) but before the step (d). [0090]
  • According to a second typical aspect of the present invention, a process for producing a semiconductor device comprises the following steps: [0091]
  • (a) a step of thermally oxidizing a semiconductor substrate, thereby forming a pad oxide film (a first silicon oxide film) on the principal side (or surface) of the semiconductor substrate, then depositing a silicon nitride film on the first silicon oxide film, and then selectively etching the silicon nitride film and the first silicon oxide film residing in an element isolation region while masking an element region, [0092]
  • (b) a step of isotropically and shallowly etching the semiconductor substrate in the element isolation region, thereby forming the undercut on the semiconductor substrate at the edge of the element isolation region, [0093]
  • (c) a step of selectively etching the semiconductor substrate in the element isolation region, thereby trenching a groove on the principal side (or surface) of the semiconductor substrate, [0094]
  • (d) a step of thermally oxidizing the semiconductor substrate, thereby forming a second silicon oxide film on the inside wall of the groove and rounding the shoulder edge of the groove at the same time, [0095]
  • (e) a step of depositing a third silicon oxide film on the principal side (or surface) of the semiconductor substrate, thereby embedding the third silicon oxide film in the groove, [0096]
  • (f) a step of heat-treating (or annealing) the semiconductor substrate, thereby sintering the third silicon oxide film embedded in the groove, [0097]
  • (g) a step of removing the third silicon oxide film on the silicon nitride film, while leaving the third silicon oxide film only in the groove, thereby forming an element isolation groove embedded with the third silicon oxide film, and [0098]
  • (h) a step of removing the silicon nitride film on the surface of an active region whose circumference is confined by the element isolation groove, and then forming a semiconductor element in the active region. [0099]
  • According to a third typical aspect of the present invention, a process for producing a semiconductor device comprises the following steps: [0100]
  • (a) a step of thermally oxidizing a semiconductor substrate, thereby forming a first silicon oxide film on the principal side (or surface) of the semiconductor substrate, then depositing a first silicon nitride film on the first silicon oxide film and then selectively etching the first silicon nitride film, the first silicon oxide film and the semiconductor substrate residing in an element isolation region while masking an element region, thereby trenching a groove on the principal side (or surface) of the semiconductor substrate. [0101]
  • (b) a step of etching the first silicon oxide film exposed to silicon oxide film from the inside wall of the groove to [0102]
  • (c) a step of thermally oxidizing the semiconductor device, thereby forming a second silicon oxide film on the inside wall of the groove in the range for filling the second silicon oxide film in the recess space formed up to the recessed first silicon oxide film, and rounding the shoulder edge of the groove at the same time, [0103]
  • (d) a step of depositing a second silicon nitride film on the semiconductor substrate including the inside of the groove by chemical vapor deposition, [0104]
  • (e) a step of depositing a third silicon oxide film on the principal side (or surface) of the semiconductor substrate, thereby embedding the third silicon oxide film in the groove, [0105]
  • (f) a step of heat-treating (or annealing) the semiconductor substrate, thereby sintering the third silicon oxide film embedded in the groove, [0106]
  • (g) a step of removing the third silicon oxide film and the second silicon nitride film on the first silicon nitride film, while leaving the third silicon oxide film and the second silicon nitride film only in the groove, thereby forming an element isolation groove embedded with the third silicon oxide film and the second silicon nitride film, [0107]
  • (h) a step of removing the first silicon nitride film on the surface of the active region whose circumference is confined by the element isolation groove by etching, [0108]
  • (i) a step of thermally oxidizing the third silicon oxide film in the element isolation groove, thereby increasing the thickness of the film and filling a recess formed by simultaneous removal of the second silicon nitride film at the shoulder edge of the element isolation groove during the removal of the first silicon nitride film by etching, and [0109]
  • (j) a step of forming a semiconductor element in the active region. [0110]
  • According to a fourth typical aspect of the present invention, a process for producing a semiconductor device comprises the following steps: [0111]
  • (a) a step of thermally oxidizing a semiconductor substrate, thereby forming a first silicon oxide film on the principal side (or surface) of the semiconductor substrate, then depositing a first silicon nitride film on the first silicon oxide film, and then selectively etching the first silicon nitride film, the first silicon oxide film and the semiconductor substrate residing in an element isolation zone while masking an element region, thereby trenching a groove on the principal side (or surface) of the semiconductor substrate, [0112]
  • (b) a step of etching the first silicon oxide film exposed to the inside wall of the groove, thereby recessing the first silicon oxide film from the inside wall of the groove towards an active region to an extent of 5 to 40 nm, [0113]
  • (c) a step of thermally oxidizing the semiconductor substrate, thereby forming a second silicon oxide film on the inside wall of the groove in the range for filling the second silicon oxide film in the recess space formed up to the recessed first silicon oxide film, and rounding the shoulder edge of the groove at the same time, [0114]
  • (d) a step of depositing a second silicon nitride film on the semiconductor substrate including the inside of the groove by chemical vapor deposition, [0115]
  • (e) a step of depositing a third silicon oxide film on the principal side (or surface) of the semiconductor substrate, thereby embedding the third silicon oxide in the groove, [0116]
  • (f) a step of removing the third silicon oxide film and the second silicon nitride film on the first silicon nitride film, while leaving the third silicon oxide film and the second silicon nitride film only in the groove, thereby forming an element isolation groove embedded with the third silicon oxide film and the second silicon nitride film, [0117]
  • (g) a step of heat-treating (or annealing) the semiconductor substrate, thereby sintering the third silicon oxide film embedded in the groove and oxidizing the surface of the first silicon nitride film and the surface of the second silicon nitride film on the shoulder edge of the element isolation groove, [0118]
  • (h) a step of removing the first silicon nitride film on the surface of the active region whose circumference is confined by the element isolation groove and the oxide film on the surface of the first silicon nitride film by etching, and [0119]
  • (i) a step of forming a semiconductor element in the active region. [0120]
  • According to the fifth typical aspect of the present invention, a process for producing a semiconductor device comprises the following steps: [0121]
  • (a) a step of thermally oxidizing a semiconductor substrate, thereby forming a first silicon oxide film (a pad oxide film) on the principal side (or surface) of the semiconductor substrate, then depositing a silicon nitride film on the first silicon oxide film, and then selectively etching the silicon nitride film, the first silicon oxide film and the semiconductor substrate residing in an element isolation region while masking an element region, thereby trenching a groove on the principal side (or surface) of the semiconductor substrate, [0122]
  • (b) a step of etching the first silicon oxide film exposed to the inside wall of the groove, thereby recessing the first silicon oxide film from the inside wall of the groove towards an active region to an extent of 5 to 40 nm, [0123]
  • (c) a step of depositing a second silicon oxide film (an embedded oxide film) on the principal side (or surface) of the semiconductor substrate, thereby embedding the second silicon oxide film in the groove, [0124]
  • (d) a step of thermally oxidizing the semiconductor substrate, thereby sintering the second silicon oxide film embedded in the groove, forming a third silicon oxide film (a heat oxide film) on the inside wall of the groove and rounding the shoulder edge of the groove at the same time, [0125]
  • (e) a step of removing the second silicon oxide film on the silicon nitride film, while leaving the second silicon oxide film only in the groove, thereby forming an element isolation groove embedded with the second silicon oxide film, and [0126]
  • (f) a step of removing the silicon nitride film on the surface of the active region whose circumference is confined by the element isolation groove, and then forming a semiconductor element in the active region. [0127]
  • According to a sixth typical aspect of the present invention, a process for producing a semiconductor device comprises the following steps: [0128]
  • (a) a step of thermally oxidizing a semiconductor substrate, thereby forming a first silicon oxide film (a pad oxide film) on the principal side (or surface) of the semiconductor substrate, then depositing a silicon nitride film on the first silicon oxide film, and then selectively etching the silicon nitride film, the first silicon oxide film and the semiconductor substrate residing in an element isolation region while masking an clement region, thereby trenching a groove on the principal side (or surface) of the semiconductor substrate, [0129]
  • (b) a step of etching the first silicon oxide film exposed to the inside wall of the groove, thereby recessing the first silicon oxide film from the inside wall of the groove towards an active region to an extent of 5 to 40 nm, [0130]
  • (c) a step of depositing a second silicon oxide film (an embedded oxide film) on the principal side (or surface) of the semiconductor substrate, thereby embedding the second silicon oxide film in the groove, [0131]
  • (d) a step of removing the second silicon oxide film on the silicon nitride film, while leaving the second silicon oxide film only in the groove, thereby forming an element isolation groove embedded with the second silicon oxide film, [0132]
  • (e) a step of thermally oxidizing the semiconductor substrate, thereby sintering the second silicon oxide film embedded in the groove, forming a third silicon oxide film (a heat oxide film) on the inside wall of the groove and rounding the shoulder edge of the groove at the same time, and [0133]
  • (f) a step of removing the silicon nitride film on the surface of the active region whose circumference is confined by the element isolation groove, and then forming a semiconductor element in the active region. [0134]
  • According to a seventh typical aspect of the present invention, a process for producing a semiconductor device comprises the following steps: [0135]
  • (a) a step of thermally oxidizing a semiconductor substrate, thereby forming a first silicon oxide film on the principal side (or surface) of the semiconductor substrate, then depositing a silicon nitride film on the first silicon oxide film, and then selectively etching the silicon nitride film, the first silicon oxide film and the semiconductor substrate residing in an element isolation region while masking an element region, thereby substrate, thereby trenching a groove on the principal side (or surface) of the semiconductor substrate, [0136]
  • (b) a step of etching the first silicon oxide film exposed to the inside wall of the groove, thereby recessing the first silicon oxide film from the inside wall of the groove towards an active region to an extent of 5 to 40 nm, [0137]
  • (c) a step of thermally oxidizing the semiconductor substrate, thereby forming a second silicon oxide film on the inside wall of the groove in the range for filling the second silicon oxide film in the recess space formed up to the edge of the recessed first silicon oxide film, and rounding the shoulder edge of the groove at the same time, [0138]
  • (d) a step of depositing a polycrystalline silicon film on the principal side (or surface) of the semiconductor substrate, [0139]
  • (e) a step of depositing a third silicon oxide film on the principal side (or surface) of the semiconductor substrate, thereby embedding the third silicon oxide film in the groove, [0140]
  • (f) a step of heat-treating (or annealing) tithe semiconductor substrate, thereby sintering the third silicon oxide film embedded in the groove and oxidizing the polycrystalline silicon film to convert at least a portion thereof to a silicon oxide film, [0141]
  • (g) a step of removing the third silicon oxide film and the silicon oxide film on the silicon nitride film, while leaving the third silicon oxide film and the silicon oxide film only in the groove, thereby forming an element isolation groove embedded with the third silicon oxide film and the silicon oxide film, and [0142]
  • (h) a step of removing the silicon nitride film on the surface of the active region whose circumference is confined by the element isolation groove, and then forming a semiconductor element in the active region. [0143]
  • According to an eighth typical aspect of the present invention, a process for producing a semiconductor device comprises the following steps: [0144]
  • (a) a step of thermally oxidizing a semiconductor substrate, thereby forming a first silicon oxide film on the principal side (or surface) of the semiconductor substrate, then depositing a silicon nitride film on the first silicon oxide film, and then selectively etching the silicon nitride film, the first silicon oxide film and the semiconductor substrate residing in an element isolation region while masking an element region, thereby trenching a groove on the principal side (or surface) of the semiconductor substrate, [0145]
  • (b) a step of etching the first silicon oxide film exposed to the inside wall of the groove, thereby recessing the first silicon oxide film from the inside wall of the groove towards an active region to an extent of 5 to 40 nm, [0146]
  • (c) a step of thermally oxidizing the semiconductor substrate, thereby forming a second silicon oxide film on the inside wall of the groove in the range for filling the second silicon oxide film in the recess space formed up to the edge of recessed first silicon oxide film and rounding the shoulder edge of the groove at the same time, [0147]
  • (d) a step of depositing a polycrystalline silicon film on the principal side (or surface) of the semiconductor substrate, [0148]
  • (e) a step of depositing a third silicon oxide film on the principal side (or surface) of the semiconductor substrate, thereby embedding the third silicon oxide film in the groove, [0149]
  • (f) a step of removing the third silicon oxide film and the polycrystalline silicon film on the silicon nitride film, while leaving the third silicon oxide film and the polycrystalline silicon film in the groove, thereby forming an element isolation groove embedded with the third silicon oxide film and the polycrystalline silicon film, [0150]
  • (g) a step of heat-treating (or annealing) the semiconductor substrate, thereby sintering the third silicon oxide film embedded in the groove and oxidizing the polycrystalline silicon film to convert at least a portion thereof to a silicon oxide film, and [0151]
  • (h) a step of removing the silicon nitride film on the surface of the active region whose circumference is confined by the element isolation groove, and then forming a semiconductor element in the active region. [0152]
  • According to a ninth typical aspect of the present invention, a process for producing a semiconductor device comprises the following steps: [0153]
  • (a) a step of oxidizing a semiconductor substrate, thereby forming a first silicon oxide film (a pad oxide film) on the principal side (or surface) of the semiconductor substrate, then depositing a silicon nitride film on the first silicon oxide film, and then selectively etching the silicon nitride film, the first silicon oxide film and the semiconductor substrate residing in an element isolation region while masking an element region, thereby trenching a groove on the principal side (or surface) of the semiconductor substrate, nitride film on the first silicon oxide film, and then [0154]
  • (b) a step of etching the first silicon oxide film exposed to the inside wall of the groove, thereby recessing the first silicon oxide film from the inside wall of the groove towards an active region in an extent of 5 to 40 nm, [0155]
  • (c) a step of heat-nitriding the semiconductor substrate, thereby forming a second silicon nitride on the inside wall of the groove, [0156]
  • (d) a step of depositing a second silicon oxide film (an embedded oxide film) on the principal side (or surface) of the semiconductor substrate, thereby embedding the second silicon oxide film in the groove, [0157]
  • (e) a step of heat-treating (or annealing) the semiconductor substrate, thereby sintering the second silicon oxide film embedded in the groove, [0158]
  • (f) a step of removing the second silicon oxide film on the first silicon nitride film, while leaving the second silicon oxide film only in the groove, thereby forming an element isolation groove embedded with the second silicon oxide film, and [0159]
  • (g) a step of removing the first silicon nitride film on the surface of the active region whose circumference is confined by the element isolation groove, and then forming a semiconductor element in the active region. [0160]
  • According to the tenth typical aspect of the present invention, a process for producing a semiconductor device comprises the following steps: [0161]
  • (a) a step of thermally oxidizing a semiconductor substrate, thereby forming a first silicon oxide film on the principal side (or surface) of the semiconductor substrate, then depositing a silicon nitride film on the first silicon oxide film, and then selectively etching the silicon nitride film, the first silicon oxide film and the semiconductor substrate residing in an element isolation region while masking an element region, thereby trenching a groove on the principal side (or surface) of the semiconductor substrate, [0162]
  • (b) a step of etching the first silicon oxide film exposed to the inside wall of the groove, thereby recessing the first silicon oxide film from the inside wall of the groove towards an active region in an extent of 5 to 40 nm, [0163]
  • (c) a step of thermally oxidizing the semiconductor substrate, thereby forming a second silicon oxide film on the inside wall of the groove, and then nitriding the second silicon oxide film, thereby converting at least a portion thereof to a silicon nitride film, [0164]
  • (d) a step of depositing a third silicon oxide film on the principal side (or surface) of the semiconductor substrate, thereby embedding the third silicon oxide film in the groove, [0165]
  • (f) a step of removing the third silicon oxide film on the first silicon nitride film, while leaving the third silicon oxide film only in the groove, thereby forming an element isolation groove embedded with the third silicon oxide film, and [0166]
  • (g) a step of removing the first silicon nitride film on the surface of the active region whose circumference is confined by the element isolation groove, and then forming a semiconductor element in the active region. [0167]
  • According to the eleventh typical aspect of the invention, a process for producing a semiconductor device comprises the following steps: [0168]
  • (a) a step of thermally oxidizing a semiconductor substrate, thereby forming a first silicon oxide film (a pad oxide film) on the principal side (or surface) of the semiconductor substrate, then depositing a silicon nitride film on the first silicon oxide film, and then selectively etching the silicon nitride film, the first silicon oxide film and the semiconductor substrate residing in an element isolation region while masking an element region, thereby trenching a groove on the principal side (or surface) of the semiconductor substrate, [0169]
  • (b) a step of etching the first silicon oxide film exposed to the inside wall of the groove, thereby recessing the first silicon oxide film from the inside wall of the groove towards an active region to an extent of 5 to 40 nm, [0170]
  • (c) a step of depositing a polycrystalline silicon film on the semiconductor substrate, and then nitriding the polycrystalline silicon film, thereby converting at least a portion thereof to a silicon nitride film, [0171]
  • (d) a step of depositing a second silicon oxide film (an embedded oxide film) on the principal side (or surface) of the semiconductor substrate, thereby embedding the second silicon oxide film in the groove, [0172]
  • (e) a step of heat-treating (or annealing) the semiconductor substrate, thereby sintering the second silicon oxide film embedded in the groove, [0173]
  • (f) a step of removing the second silicon oxide film on the first silicon nitride film, while leaving the second silicon oxide film only in the groove, thereby forming an element isolation groove embedded with the second silicon oxide film, and [0174]
  • (g) a step of removing the first silicon nitride film on the surface of the active region whose circumference is confined by the element isolation groove, and then forming a semiconductor element in the active region. [0175]
  • The embodiments of the present invention will be described in detail below, referring to drawings, where members having the same function will be identified with the same reference numerals throughout the drawings illustrating the embodiments of the present invention to omit repeat explanation. [0176]
    • EXAMPLE 1
  • Steps of producing a groove isolation structure of a semiconductor device according to the first embodiment of the present invention will be explained below, referring to FIGS. 2A to [0177] 2I and FIG. 3.
  • FIGS. 2A to [0178] 2I are cross-sectional structured elevation views of a semiconductor device according to the present process and FIG. 3 is a flow chart showing outlines of steps of the process. Steps will be explained, referring to FIGS. 2A to 2I according to the flow chart of FIG. 3.
  • (1) The surface of [0179] silicon substrate 31 was thermally oxidized to form a pad oxide film 32 having a thickness of about 10 nm (101 and 102 in FIG. 3).
  • (2) [0180] Silicon nitride film 42 was deposited to a thickness of about 200 nm on pad oxide film 32 and used as an anti-oxidation film when element isolation, thermally oxidized film 35 was formed (103 in FIG. 3).
  • (3) [0181] Photoresist 43 was formed on silicon nitride film 42 (104 in FIG. 3).
  • (4) [0182] Photoresist 43 at a desired position was removed by an ordinary light exposure procedure, and then parts of silicon nitride film 42, pat oxide film 32 and silicon substrate 31 were removed by etching, and a shallow groove was trenched at a predetermined angle of the inside wall of the groove to the surface of silicon substrate 31 (for example, at an angle of 95° to 110° shown by A in FIG. 2D) (105 to 107 in FIG. 3).
  • (5) [0183] Photoresist 43 was removed and then pad oxide film 32 was recessed (or partially removed) in an extent of to 40 nm by etching (108 and 109 in FIG. 3).
  • (6) Then, the surface of [0184] silicon substrate 31 was thermally oxidized to a thickness of about 30 nm, for example, in a dry oxidative atmosphere at 900° to 1,000° C. to form a heat (or thermal)-oxidized film 35 on the inside wall of the groove (110 in FIG. 3).
  • (7) An isolation film such as a silicon oxide film, etc. was deposited thereon by chemical vapor deposition (CVD), sputtering etc. to embed (or bury) the isolation film in the groove (the isolation film will be hereinafter referred to as embedding isolation film [0185] 36). The silicon oxide film, etc. deposited by chemical vapor deposition, sputtering, etc. are usually porous films, and thus after the deposition of embedding isolation film 36 silicon substrate 31 may be annealed at about 1,0000 C. or oxidized in an oxidative atmosphere at 1,000° C. to make the film compact (111 In FIG. 3)
  • (8) Embedding [0186] isolation film 36 was etched back by chemical mechanical polishing (CMP) or dry etching, where silicon nitride film 42 used as an anti-oxidation film served as an etching stopper to prevent silicon substrate 31 below silicon nitride film 42 from etching (112 in FIG. 3).
  • (9) [0187] Silicon nitride film 42 and pad oxide film 32 were removed, thereby the embedded groove structure was completed (113 in FIG. 3). Then, a semiconductor device was fabricated through necessary mounting procedures for producing a transistor structure, for example, by formation of gate oxide films and gate electrodes, doping with impurities, formation of wiring, interlayer insulating films, etc. formation of a surface protective film, etc.
  • Working and effects of the first embodiment of the present invention will be explained below, referring to FIG. 4 and FIGS. 5A and 5B. [0188]
  • Distinction of the first embodiment of the present invention from the prior art is that the extent of recessing [0189] pad oxide film 32 in the foregoing step
  • (5) is limited. FIG. 4 shows results of analyzing changes in radius of curvature of the [0190] silicon substrate 31 at the groove upper edge by changing the extent of recessing pad oxide film 32, where the extent of recessing pad oxide film 32 is given on the axis of abscissa and the radius at curvature of silicon substrate at the groove upper edge on the exist of ordinate. As is evident from FIG. 4, the radius of curvature of the substrate at the groove upper edge increases with increasing extent of recessing pad oxide film 32 from zero, reaches about 25 nm with a recessing extent of 5 nm and further increases to about 35 nm with a recess extent of 20 nm. However, when the recessing extent is increased beyond 40 nm, a step is formed on the upper side of the substrate at the groove upper edge, reducing the radius of curvature, for example, to 25 nm with a recessing extent of 60 nm.
  • It can be presumed that the dependency of the radius of curvature upon the extent of recessing the pad oxide film is due to the following grounds; [0191]
  • The oxide film starts to grow during the groove oxidation, while undergoing approximately 2-fold volumic expansion between [0192] silicon nitride film 42 and silicon substrate 31 (FIGS. 5A and 5B). When the extent of recessing pad oxide film 32 is zero, edge of silicon nitride film 42 is pushed upwards by the volumic expansion, deforming the silicon nitride film into a upwardly warped concave shape. A counterforce develops due to the warping deformation of silicon nitride film 42, resulting in development of compression stress both in the oxide film (including part of pad oxide film 32) below silicon nitride film 42 and in the silicon substrate (FIG. SA). Once the compression stress develops, diffusion of oxidative seeds, that is, progress of oxidation reaction, is suppressed, so that the rate of oxidation is considerably lowered at the groove upper edge. On the groove inside wall on the other hand, the growth direction (direction normal to the inside wall surface) of the oxide film is free from any restriction, that is, there is no inhibiting factor against the volumic expansion of the growing oxide film, and thus oxidation can process on the inside wall surface without any restriction in contrast to the oxidation of the groove upper edge. Thus, the substrate shape is sharpened at the groove upper edge of silicon substrate 31 with progress of oxidation, as shown by dotted lines in FIG. 5A.
  • When [0193] pad oxide film 32 is recessed, an exposed region of silicon substrate 31 at the groove upper edge and an unexposed region thereof are formed (FIG. 5B). In the exposed region, the growing oxide film is not in contact with upper layer silicon nitride film 42 at the initial stage of oxidation and thus no compression stress due to the warping deformation of silicon nitride film 42, as explained above, referring to FIG. 5A, develops substantially, and thus oxidation can proceed without any restriction. Furthermore, silicon substrate 31 is in two-side contact (i.e. in two oxygen supply directions) at the groove upper edge, and thus oxidation can proceed rapidly, resulting in rounding the groove upper edge, that is, increasing the radius of curvature.
  • In the unexposed region of [0194] silicon substrate 31, on the other hand, diffusion of oxidative seeds is inhibited by the presence of pad oxide film 32, that is, the oxidation is inhibited. Thus, a step is formed on the silicon substrate around the edge of pad oxide film 32, because of a difference in the rate of oxidation, as shown in FIG. 4. When the extent of recessing pad oxide film 32 is not more than 40 nm, the step is not formed, because of an approach to the readily oxidizable groove upper edge part (in two oxygen supply directions). Thus the radius of curvature is as large as 35 nm. On the other hand, when the recessing extent is more than 40 nm, a step is formed because of remoteness from the groove upper edge part, resulting in decreasing the radius of curvature. It should be noted that, when oxidation is further continued in the step
  • (6), the oxide film growing on the exposed part will be brought into contact with the silicon nitride film, followed by rapid development of a compression stress, as explained above. That is, the radius of curvature so far attained will be again decreased. [0195]
  • It is also possible to further round the shoulder edge of the groove by removing edge portions of upper edge portions of the groove after the recess of pad oxide film and before the oxidation in the groove. Thus, after recessing the pad oxide film, isotropic etching may be conducted at the shoulder edge of the groove (to remove the edges), followed by oxidation in the grooves. [0196]
  • In the first embodiment of the present invention, no step is formed any more on the substrate around the upper edge of groove isolation stricture and a much larger radius of curvature than 3 nm can be obtained by restricting an extent of recessing the pad oxide film to a range of 5 to 40 nm, and thus an increase in transistor leakage current or a decrease in gate breakdown voltage due to the field concentration around the edge of gate electrode film can be effectively prevented and also the transistor electric reliability can be be effectively improved. The shoulder edge of the groove can more preferably rounded by providing an undercut, as shown in FIG. 34, before trenching the groove. [0197]
    • EXAMPLE 2
  • Steps of producing a groove isolation structure of a semiconductor device according to a second embodiment of the present invention will be explained below, referring to FIGS. 2A to [0198] 2I and FIG. 6.
  • Process for producing an embedded groove structure of a semiconductor device according to the second embodiment of the present invention (flow chart) FIG. 6 is a modification of step [0199]
  • (6) of the process according to the first embodiment of the present invention. The embedded groove structure of the second embodiment is not largely different in structure, etc. from that of the first embodiment, and thus the steps of the second embodiment will be explained below, referring to the flow chart of FIG. 6, using the cross-sectional structural elevation views of the semiconductor device shown in FIGS. 2A to [0200] 2I.
  • (1) The surface of [0201] silicon substrate 31 was thermally oxidized to form a pad oxide film 32 having a thickness of about 10 nm (201 and 202 in FIG. 6).
  • (2) [0202] Silicon nitride film 42 was deposited on pad oxide film 32 to a thickness of about 200 nm, and used as an anti-oxidation film when element isolation, thermally oxidized film 35 was formed (203 in FIG. 6).
  • (3) [0203] Photoresist 43 was formed on silicon nitride film 42 (204 in FIG. 6).
  • (4) [0204] Photoresist 43 at a desired position was removed by an ordinary light exposure procedure, and then parts of silicon nitride film 42, pad oxide film 32 and silicon substrate 31 were removed by etching, and a shallow groove was trenched at a predetermined angle of the inside wall of the groove to the surface of silicon substrate 31 (for example, at an angle of 95° to 110° as shown by A in FIG. 2D) (205 to 207 in FIG. 6).
  • (5) [0205] Photoresist 43 was removed and then pad oxide film 32 was recessed in an extent of 5 to 40 nm by etching (208 and 209 in FIG. 6).
  • (6) The groove trenched on [0206] silicon substrate 31 was thermally oxidized to a depth of about 30 nm in an oxidative atmosphere of H2/O2 gas mixture in a gas flow rate ratio of H2/O2(O<r≦0.5) to form an element isolation, thermally oxidized film 35 (210 in FIG. 6).
  • (7) An isolation film such as a silicon oxide film, etc. was deposited thereon by chemical vapor deposition (CVD), sputtering, etc. to embed the isolation film in groove (the isolation film will be hereinafter referred to as embedding isolation film [0207] 36). The silicon oxide film, etc. deposited by chemical vapor deposition, sputtering, etc. are usually porous films and thus after the deposition of embedding isolation film 36 silicon substrate 31 may be annealed at about 1,000° C. or oxidized in an oxidative atmosphere at about 1,000° C. to make the film compact (211 in FIG. 6).
  • (8) Embedding [0208] isolation film 36 was etched back by chemical mechanical polishing (CMP) or dry etching, where silicon nitride film 42 used as an anti-oxidation film served as an etching stopper to prevent silicon substrate 31 below silicon nitride film 42 from etching (212 in FIG. 6).
  • (9) [0209] Silicon nitride film 42 and pad oxide film 32 were removed, whereby the embedded groove structure was completed (213 in FIG. 6). Then, a semiconductor device was fabricated through necessary mounting procedures for producing a transistor structure, for example, by formation of gate oxide films and gate electrodes, doping with impurities, formation of wirings, interlayer insulating films, etc., formation of a surface protective film, etc.
  • Working and effects of the second embodiment of the present invention will be explained below, referring to FIG. 7. [0210]
  • A gas flow rate ratio of H[0211] 2/O2 ofthe oxidative atmosphere can be changed in a range of 0<r≦2 but when r reaches 2 the reaction proceeds explosively. From the viewpoint of safety, the upper limit to r will be substantially about 1.8. When the oxidation temperature is presumed constant within the above-mentioned range of gas flow rate ratio, the rate of oxidation increases with increasing gas flow rate ratio, whereas the rate of oxidation decreases with decreasing gas flow rate ratio. Thus, an effect of the rate of oxidation upon the shape of upper edge of the groove of a semiconductor substrate was analyzed. The results are shown in FIG. 7, where a gas flow rate ratio of H2/O2 is shown on the axis of abscissa and a radius of curvature at the upper edge of the groove of a semiconductor substrate is shown on the axis of ordinate. As is evident from FIG. 7, the resulting radius of curvature drastically decreases with increasing gas flow rate ratio of hydrogen (H2) in the oxidative atmosphere. When a gas flow rate ratio r reaches 0.5, the radius of curvature is decreased to about 3 nm. When the gas flow rate ratio is made higher, the radius of curvature further decreases, though little by little.
  • Grounds for such phenomena can be explained as follows: [0212]
  • Oxidation develops a strain (stress) around the boundary between the silicon substrate and the silicon oxide film, as already mentioned above. On the other hand, the silicon oxide film shows a remarkable viscous behavior at a high temperature (900° C. or higher), and thus the developed stress is lessened at a high temperature with time. When the thickness of the oxide film is presumed constant, the time required for lessening the developed stress will be shorter with increasing rate of oxidation (larger gas flow rate ratio of H[0213] 2/O2), though the developed strain (stress) value is constant. Consequently, the residual stress will be increased. In case of lower rate of oxidation (smaller gas flow are ratio of H2/O2), the viscous effect of silicon oxide film can be brought about, so that the stress lessening proceeds relatively as compared under the conditions of constant oxide film thickness. The higher the stress induced by the oxidation, the more inhibited the oxidation in the region around the developed stress. Thus, the region of silicon substrate around the upper edge of the groove is a stress-concentrated site due to the growth of oxide film on the substrate upper side and the groove inside, and when the residual stress becomes higher, the oxidation around the stress concentrated site will be inhibited, so that the upper edge of the groove in silicon substrate will be sharpened. That is, oxidation of the semiconductor substrate around the upper edge of the groove can proceed in a low stress state by making a gas flow rate ratio of H2/O2 lower, so that the rounding of silicon substrate 31 can be attained around the upper edge of the groove.
  • From the foregoing grounds, the radius of curvature of the substrate around the upper edge of the groove in the groove isolation structure can be made much larger than 3 nm according to the second embodiment of the present invention Furthermore, the extent of recessing the pad oxide film is set in a range of 5 to 40 nm as given in the first embodiment of the present invention, the step development on the upper surface of the substrate at the upper edge of the groove can be prevented. That is, an increase in transistor leakage current or a decrease in gate breakdown voltage due to the field concentration around the edge of gate electrode film can be effectively prevented and also the transistor electric reliability can be effectively improved. The shoulder edge of the groove can be more preferably rounded by providing an undercut, as shown in FIG. 34, before trenching the groove. [0214]
  • It is also possible to further round the shoulder edge of the groove by removing edge portions of upper edge portions of the groove after the recess of pad oxide film and before the oxidation in the groove. Thus, after recessing the pad oxide film, isotropic etching may be conducted at the shoulder edge of the groove (to easily remove the edges), followed by oxidation in the groove. [0215]
    • EXAMPLE 3
  • Steps of producing an embedded groove structure of a semiconductor device according to a third embodiment of the present invention will be explained below, referring to FIGS. 2A to [0216] 2I and FIG. 8.
  • Process for producing an embedded groove structure of a semiconductor device according to the third embodiment of the present invention (flow chart) shown in FIG. 8 is a modification of step (6) of the process according to the first embodiment of the present invention. The embedded groove structure of the third embodiment is not largely different in structure, etc. from that of the first embodiment, and thus the steps of the third embodiment will be explained below, referring to the flow chart of FIG. 8, using the cross-sectional structural elevation views of the semiconductor device shown in FIGS. 2A to [0217] 2I.
  • (1) The surface of [0218] silicon substrate 31 was thermally oxidized to form a pad oxide film 32 having a thickness of about 10 nm (301 and 302 in FIG. 8)
  • (2) [0219] Silicon nitride film 42 was deposited on pad oxide film 32 to a thickness of about 200 nm, and used as an anti-oxidation (film when element isolation, thermally oxidized film 35 was formed (303 in FIG. 8).
  • (3) [0220] Photoresist 43 was formed on silicon nitride film 42 (304 in FIG. 5).
  • (4) [0221] Photoresist film 43 at a desired position was removed by an ordinary light exposure procedure, and then parts of silicon nitride film 42, pad oxide film 32 and silicon substrate 31 were removed by etching, a shallow groove was trenched at a predetermined angle of inside wall of the groove to the surface of silicon substrate 31 (for example, at an angle of 95° to 110° as shown by A in FIG. 2D) (305 to 307 in FIG. 8).
  • (5) [0222] Photoresist 43 was removed and then pad oxide film 32 was recessed in an extent of 5 to 40 nm by etching (308 and 309 in FIG. 8).
  • (6) T he groove trenched on [0223] silicon substrate 31 was thermally oxidized in an oxidative atmosphere of H2/O2 gas mixture in a gas flow rate ratio r of H2/O2 (o<r≦0.5) in the range wherein the recess space formed up to the edge of the recesses pad oxide film was filled (310 in FIG. 8).
  • (7) An isolation film such as a silicon oxide film, etc. was deposited thereon by chemical vapor deposition (CVD), sputtering, etc. to embed the isolation film in the groove (the isolation film will be hereinafter referred to as embedding isolation film [0224] 36). The silicon oxide film, etc., deposited by chemical vapor deposition, sputtering, etc are usually porous films and thus after the deposition of embedding isolation film 36 silicon substrate 31 may be annealed at about 1,000° C. or oxidized in an oxidative atmosphere at about 1,000° C. to make the film compact (311 in FIG. 8).
  • (8) Embedding [0225] isolation film 36 was etched back by chemical mechanical polishing (CMP) or dry etching, where silicon nitride film 42 used as an anti-oxidation film served as an etching stopper to prevent silicon substrate 31 below silicon nitride film 42 from etching (312 in FIG. 8)
  • (9) [0226] Silicon nitride film 42 and pad oxide film 32 were removed, whereby the embedded groove structure was completed (313 in FIG. 8). Then, a semiconductor device was fabricated through necessary mounting procedures for producing a transistor structure, for example, by formation of gate oxide films and gate electrodes, doping with impurities, formation of wirings, interlayer insulating film, etc., formation of a surface protective film, etc
  • Working and effects of the third embodiment of the FIG. 8. present invention will be explained below, referring to FIGS. 2A to [0227] 2I.
  • As explained already in the first embodiment of the present invention (FIG. 4), [0228] silicon nitride film 42 undergoes upward warping deformation when the recess space formed up to the edge of the pad oxide film is fully filled by oxidation, and a compression stress develops on pad oxide film 32 below silicon nitride film 43 and silicon substrate 31 by a compression force due to the bending of film 43, so that the oxidation is inhibited by the stress, sharpening the silicon substrate around the upper edge of the groove. However, when the oxidation is carried out just before the recess space formed up to the edge of pad oxide film 32 is fully filled, no compression stress due to the warping deformation develops any more, so that the oxidation smoothly proceeds at the upper corner end of silicon substrate 31, rounding silicon substrate 31 around the upper end of the groove. Furthermore, the extent of recessing the pad oxide film is limited to a range of 5 to 40 nm, as given in the first embodiment of the present invention, development of a step on the upper surface of the silicon substrate at the upper edge of the groove can be prevented.
  • For the foregoing grounds, the radius of curvature of the substrate around the upper edge of the groove in the groove isolation structure can be made much larger than 3 nm according to the third embodiment of the present invention. Furthermore, the step development on the upper surface of the substrate at the upper edge of the groove can be prevented, so that an increase in transistor leakage current or a decrease in gate breakdown voltage due to the field concentration around the end of gate electrode film can be effectively prevented and also the transistor electric reliability can be effectively improved. The shoulder edge of the groove can be more preferably rounded by providing an undercut, as shown in FIG. 34, before trenching the groove. [0229]
  • It is also possible to further round the shoulder edge of the groove by removing edge portions of upper end portions of the groove after the recess of pad oxide film and before the oxidation in the groove. Thus, after recessing the pad oxide film, isotropic etching may be conducted at the shoulder edge of the groove (to easily remove the edges), followed by oxidation in the groove. [0230]
    • EXAMPLE 4
  • Embedded groove structure of a semiconductor device according to a fourth embodiment of the present invention and steps of producing the embedded groove structure will be explained below, referring to FIGS. 2A to [0231] 2I and FIG. 9.
  • FIGS. 2A to [0232] 2I are cross-sectional structural elevation views of a semiconductor device according to the fourth embodiment of the present invention and FIG. 9 is a flow chart showing outlines of steps of producing the present semiconductor device. Steps of producing the present semiconductor device will be explained below along the flow chart of FIG. 9, referring to FIGS. 2A to 2I.
  • (1) The surface of [0233] silicon substrate 31 was thermally oxidized to form a pad oxide film 32 having a thickness of 5 to 50 nm (401 and 402 in FIG. 9).
  • (2) [0234] Silicon nitride film 42 was deposited on pad oxide film 32 to a thickness of 10 to 300 nm, and used as an anti-oxidation film when element isolation, thermally oxidized film 35 is formed (403 in FIG. 9).
  • (3) [0235] Photoresist 43 was formed on silicon nitride film (404 in FIG. 9).
  • (4) [0236] Photoresist film 43 at a desired position was removed by an ordinary light exposure procedure, and then parts of silicon nitride film 42, pad oxide film 32 and silicon substrate 31 were removed by etching, and a shallow groove was trenched at a predetermined angle of inside wall of the groove to the surface of silicon substrate 31 (for example, at an angle of 95° to 110° as shown by A in FIG. 2D) (405 to 407 in FIG. 9).
  • (5) [0237] Photoresist 43 was removed and then pad oxide film 32 was recessed in an extent of 5 to 40 nm by etching (408 and 409 in FIG. 9).
  • (6) Then, [0238] silicon substrate 31 was thermally oxidized at an oxidation temperature of 900° to 1,000° C. in an to form thermally oxidized film 35 in the range wherein the recess space formed up to the edge of the recessed pad oxide film is filled with the thermally oxidized film (410 in FIG. 9).
  • (7) An isolation film such as a silicon oxide film, etc. was deposited thereon by chemical vapor deposition (CVD), sputtering, etc. to embed the isolation film in the groove (the isolation film will be hereinafter referred to as embedding isolation film [0239] 36). The silicon oxide film, etc. deposited by chemical vapor deposition, sputtering, etc. are usually porous films and thus after the deposition of embedding isolation film 36 silicon substrate 31 may be annealed at about 1,000 C. or oxidized in an oxidative atmosphere at about 1,000° C. to make the film compact (411 in FIG. 9).
  • (8) Embedding [0240] isolation film 36 was etched back by chemical mechanical polishing (CMP) or dry etching, where silicon nitride film 42 used as an anti-oxidation film served as an etching stopper to prevent silicon substrate 31 below silicon nitride film 42 from etching (412 in FIG. 9).
  • (9) [0241] Silicon nitride film 42 and pad oxide film 32 were removed, whereby the embedded groove structure was completed (413 in FIG. 9). Then, a semiconductor device was fabricated through necessary mounting procedures for producing a transistor structure, for example, by formation of gate oxide films and gate electrodes, doping with impurities, formation of wirings, interlayer insulating films, etc., and formation of a surface protective film, etc. In the groove isolation structure of the semiconductor device according to the fourth embodiment of the present invention, the substrate has no step on the upper surface, and a nonotonously convexed shape around the upper edge of the groove, the oxide film thickness is in a range of 5 to 70 nm at the inside wall of the groove at the intermediate level of the groove isolation structure and the radius of curvature at the upper corner edge of semiconductor substrate is in a range of 3 to 35 nm.
  • Working and effects of the fourth embodiment of the present invention will be explained below, referring to FIG. 10. [0242]
  • FIG. 10 shows results of simulation of relations between the oxidized amount (thickness) of the element isolation, thermally oxidized film at the inside wall of the groove at the intermediate level and the radius of curvature at the upper corner edge of the substrate according to the fourth embodiment of the present invention, where “a” indicates a thickness of pad oxide film. As is evident from FIG. 10, the radius of curvature R at the upper corner edge of silicon substrate increases with increasing oxidized amount of inside wall of the groove, and reaches a maximum value. The maximum value depends upon the thickness a of pad oxide film, and increases with increasing thickness a, but reaches a constant value (about 35 mn) above a thickness a of 10 nm or more. The reason why the radius of curvature takes a maximum value is that the radius of curvature increase with progress of groove oxidation, and the recess space formed up to the edge of the recessed pad oxide film is gradually filled by the oxidation, resulting in development of upward warping deformation of the silicon nitride film (development of a compression stress on the silicon substrate and oxide film) with intrusion of oxidation therein, as shown in FIG. SA and consequent inhibition of oxidation by the compression stress, making the radius of curvature smaller. Further, with an increase of oxidation amount stress in the thermal oxide film at the upper edge portions of groove increases probably due to inhibition of the oxidation. [0243]
  • It has been found by experiments that the radius of curvature R gives no adverse effect on the transistor characteristics, so far as it is about 3 nm or more. The oxidized amount on the inside wall of the groove is 5 nm or more, which can ensure the necessary radius of curvature, as given in FIG. 10. Even by oxidation over an oxidized amount of 30 nm the radius of curvature no more increases. Thus, to maximize the radius of curvature, it is preferable to make the thickness of [0244] pad oxide film 10 nm or more and the oxidized amount of groove inside wall 30 nm or more.
  • Furthermore, no step is developed on the upper surface of the substrate at the upper edge of groove, because the extent of recessing the pad oxide film is set in a range of 5 to 40 nm according to the fourth embodiment of the present invention. Thus, the substrate at the upper edge ofthe groove can have a monotonously convexed surface. The shoulder edge of the groove can be more preferably rounded by providing an undercut, as shown in FIG. 34, before trenching the groove. [0245]
  • It is also possible to further round the shoulder edge of the groove by removing edge portions of tipper edge portions of the groove after the recess of pad oxide film and before the oxidation in the groove. Thus, after recessing the pad oxide film, isotropic etching may be conducted at the shoulder edge of the groove (to easily remove the edges), followed by oxidation in the groove. [0246]
  • In the fourth embodiment of the present invention, the radius of curvature of the substrate around the upper edge of the groove can be made as large as about 35 nm, and the substrate has no step on the upper surface at the upper edge of the groove, and thus an increase in transistor leakage current or gate breakdown voltage due to the field concentration around the end of gate electrode film can be effectively prevented and also the transistor electric reliability can be effectively improved. [0247]
  • As described above, the present invention can provide a semiconductor device having a groove isolation structure without deterioration of gate breakdown voltage of transistors, and also a process for producing the same. [0248]
    • EXAMPLE 5
  • A process for producing a complementary MISFET (CMOSFET) according to a further embodiment of the present invention will be explained below, referring to FIGS. [0249] 11 to 32.
  • As shown in FIG. 11, for example, [0250] semiconductor substrate 1 of p-type single crystal silicon having a resistivity of about 1 to 10 Ωcm was thermally oxidized at a temperature of 800° to 850° C. to form a silicon oxide film (pad oxide film) 2 destined to stress lessening and protection of an active region on the principal side (or surface) thereof, and then silicon nitride film 3 was deposited on silicon oxide film 2 by CVD.
  • Then, as shown in FIG. 12, [0251] silicon nitride film 3 and silicon oxide film 2 in an element isolation region were removed by etching, using a photoresist as a mask, and then, as shown in FIG. 13, groove 4 a was trenched to a depth of 350 to 400 nm on semiconductor substrate 1 in the element isolation zone by etching, using silicon nitride film 3 as a mask. In that case, the shoulder edge of the groove could be more preferably rounded by providing an undercut, as shown in FIG. 34, before trenching groove 4 a. Inside wall of groove 4 a was tapered, for example, at angles θ1 and θ2 of 85° or less at the lower and upper corner ends of the substrate, respectively, by adjusting a gas composition for etching semiconductor substrate 1. By taping the inside wall of groove 4 a, an isolation film can be easily embedded in groove 4 a.
  • [0252] Groove 4 a could be also trenched by successively etching silicon nitride film 3, silicon oxide film 2 and semiconductor substrate 1 residing in the element isolation region, using the photoresist as a mask. When semiconductor substrate 1 was etched, using the photoresist as a mask, a decrease in the thickness of silicon nitride film 3 serving as a mask for heat oxidation could be prevented. That is, the initial thickness of silicon nitride film 3 could be made smaller.
  • Then, the inside of [0253] groove 4 a was wet-washed to remove etching residues, and then, as shown in FIG. 14 and FIG. 15, which is an enlarged view of the essential part of FIG. 14, silicon oxide film exposed to the inside wall of groove 4 a was removed by a hydrofluoric acid-based etching solution to recess the silicon oxide film towards the active region. The extend d of recessing silicon oxide film 2 by the etching in a range of 5 to 40 nm.
  • By recessing [0254] silicon oxide film 2 exposed to the inside wall of groove 4 a in the above-mentioned extent range, rounding of the shoulder edge of groove 4 a could be made easier when silicon oxide film 5 was to be formed on the inside wall of groove 4 a in the successive heat oxidation step. When the extent of recessing silicon oxide film 2 was too large, the step is undesirably formed at the shoulder edge. Therefore, it was important to control the extent d of recessing silicon oxide film 2 from the inside wall of groove 4 a to a range of 5 to 40 nm.
  • Then, as shown in FIG. 16 and FIG. 17, which is an enlarged view of the essential part of FIG. 16, [0255] semiconductor substrate 1 was thermally oxidized, for example, at 950° C. to form silicon oxide film 5 on the inside wall of groove 4 a. Silicon oxide film 5 was formed to remedy etching damages on the inside wall of groove 4 a and also to lessen a stress on silicon oxide film 6 to be embedded in groove 4 a in a successive step. Thickness Tr of silicon oxide film 5 was made larger than thickness Tp of silicon oxide film (pad oxide film) 2 but three times as large as Tp, that is, in a range of Tp<Tr≦3Tp, by controlling the oxidation time, thereby rounding the shoulder edge of groove 4 a. When the oxidation temperature of semiconductor substrate 1 was below 800° C., silicon oxide film 5 was hard to grow, whereas above 1,000° C., a wafer of particularly large diameter was readily susceptible of dislocation. It was found that the oxidation was carried out in a temperature range of 800° to 1,000° C.
  • Then, as shown in FIG. 19, [0256] silicon oxide film 7 was deposited on the principal side (or surface) of semiconductor substrate 1 by CVD to embed silicon oxide film 7 in groove 4 a. Silicon oxide film 7 was made from a silicon oxide material having a good flowability as in a silicon oxide film formed from, for example, ozone (O3) and tetraethoxysilane ((C2H5)4Si). Prior to the step of depositing silicon oxide film 7, silicon nitride film 6 could be thinly deposited on the inside wall of groove by CVD, as shown in FIG. 18, where silicon nitride film 6 served to suppress growth of silicon oxide film 5 on the inside wall of groove 4 a towards the active region when sintering silicon oxide film 7 embedded in groove 4 a in a successive step and thus to suppress such an inconvenience as formation of leak path due to development of a stress on semiconductor substrate 1 in the active region by silicon oxide film 5.
  • Then, [0257] semiconductor substrate 1 was wet oxidized at a temperature of not more than 1,0000 C., for example, 850° C., to sinter silicon oxide film 7 embedded in groove 4 a, thereby improving the quality of silicon oxide film 7.
  • Then, as shown in FIG. 20, [0258] silicon oxide film 7 was polished, for example, by chemical mechanical polishing (CMP) to flatten the surface. Polishing was carried out with silicon nitride film 3 covering the active region as a stopper to leave silicon oxide film 7 only in groove 4 a, thereby an element isolation groove 4 embedded with silicon oxide film 7 was completed. Then, as shown in FIG. 2I, silicon nitride film 3 covering the active region was removed by an etching solution such as hot phosphoric acid, etc.
  • Sintering of [0259] silicon oxide film 7 embedded in groove 4 a could be carried out after silicon oxide film 7 was polished by CMP to leave silicon oxide film 7 only in groove 4 a. In that case, the thickness of silicon oxide film 7 to be sintered was smaller than that when the sintering was carried out before polishing silicon oxide film 7, and thus sintering time could be shortened.
  • When the size of [0260] groove 4 a was very small, voids could be sometimes formed in silicon oxide film 7, when embedded in groove 4 a during the step of depositing silicon oxide film 7 on semiconductor substrate 1. To avoid such formation of voids, silicon oxide film 7 having a thickness large enough to prevent formation of voids in the film was deposited, as shown in FIG. 22, and then polycrystalline silicon film 8 was deposited thereon by CVD, as shown in groove 4 a. Prior to the step of depositing silicon oxide film 7, silicon nitride film 6 could be thinly deposited on the inside wall of groove 4 a and silicon nitride film 3 by CVD to suppress growth of silicon oxide film 5 towards the active region during the sintering.
  • Then, as shown in FIG. 23, [0261] semiconductor substrate 1 was heat-treated (or annealed) under the above-mentioned conditions to sinter silicon oxide film 7. In that case, polycrystalline silicon film 8 on silicon oxide film 7 was thermally oxidized to and converted to silicon oxide film 8 a as shown in FIG. 24.
  • Then, as shown in FIG. 25, [0262] silicon oxide film 8 a and silicon oxide film 7 were polished to obtain an element isolation groove 4 free from voids.
  • A complementary MISFET was formed in the active region of [0263] semiconductor substrate 1 whose circumference was confined by element isolation groove 4 in the following manner:
  • At first, silicon oxide film Grad oxide film) [0264] 2 remaining on the surface of the active region was removed by a hydrofluoric acid solution, etc. and then, as shown in FIG. 26, semiconductor substrate 1 was thermally oxidized at a temperature of 800° to 850° C. to form a clean gate oxide film 9 on the surface of semiconductor substrate 1. In that case, the shoulder edge of element isolation groove 4 was rounded, thereby preventing such an inconvenience as thinning of gate oxide film 9 at the shoulder edge.
  • Then, as shown in FIG. 27, n-type impurities such as phosphorous (P), etc. were ion-implanted onto part of [0265] semiconductor substrate 1 and p-type impurities such as boron (B), etc. were ion-implanted on the other part thereof, and then semiconductor substrate 1 was heat-treated at a temperature of not more than 1,000° C., conduct extended diffusion of the two kinds of impurities, thereby forming p-type well 10 in n-channel type MISFET-forming region an d n-type well 11 on p-channel type MISFET-forming region. Gate oxide film 9 could be formed on the surfaces of p-type well 10 and n-type well 11, after their respective formation.
  • Then, as shown in FIG. 28, [0266] gate electrode 12 for the n-channel type MISFET was formed on p-type well 10 gate electrode 12 for p-channel type MISFET was formed on n-type well 11. To form gate electrode 12, for example, a p-doped polycrystalline silicon film, a tungsten (W) silicide film and a cap isolation film 13 were deposited successively on semiconductor substrate 1 by CVD, and then these films were patterned by etching, using a photoresist as a mask thereby obtaining gate electrode 12. Cap isolation film 13 was made from a silicon oxide film or a silicon nitride film.
  • Then, as shown in FIG. 29, p-type well [0267] 10 was ion-implanted with n-type impurities such as P, etc. to form n-type semiconductor region (source, drain) 14 of n-channel type MISFET, and n-type well 11 was ion-implanted with p-type impurities such as B (boron) etc. to form p-type semiconductor region (source, drain) 15 of p-channel type MISFET, thereby obtaining an n-channel type MISFETQn and p-channel type MIlSFETQp.
  • Then, as shown in FIG. 30, [0268] side wall spacer 16 was formed on the side wall of gate electrode 12. Side wall spacer 16 was formed by depositing a silicon oxide film or a silicon nitride film on semiconductor substrate 1 by CVD and patterning the film by anisotropic etching.
  • Then, as shown in FIG. 31, [0269] silicon oxide film 17 was deposited on semiconductor substrate 1 by CVD, and then, as shown in FIG. 32, contact holes 18 were formed through silicon oxide film 17 on n-type semiconductor region (source, drain) 14 of n-channel type MISFETQn, and p-type semiconductor region (source, drain) of p-channel type MISFETQn, respectively, and an aluminum (Al) alloy film deposited on silicon oxide film 17 by sputtering was patterned to form wiring 19.
  • It is also possible to further round the shoulder edge of the groove by removing edge portions of upper edge portions of the groove after the recess of pad oxide film and before the oxidation in the groove. Thus, after recessing the pad oxide film, isotropic etching may be conducted at the shoulder edge of the groove (to easily remove the edge), followed by oxidation in the groove. [0270]
    • EXAMPLE 6
  • A process for forming [0271] element isolation groove 4 according to a still further embodiment of the present invention will be explained below, referring to FIGS. 33 to 36.
  • At first, as shown in FIG. 33, [0272] semiconductor substrate 1 was thermally oxidized at a temperature of 800° to 850° C. to form silicon oxide film (pad oxide film) 2 on the principal side (or surface) of semiconductor substrate 1, and then silicon nitride film 3 was deposited on silicon oxide film 2 by CVD. Then, silicon nitride film 3 and silicon oxide film 2 in an element isolation region were removed by etching, using a photoresist as a mask.
  • Then, as shown in FIG. 34, the surface of [0273] semiconductor substrate 1 in the element isolation region was isotropically and shallowly etched to form an undercut a on semiconductor substrate 1 at the edges in the element isolation region.
  • Then, as shown in FIG. 35, [0274] semiconductor substrate 1 in the element isolation region was anisotropically etched by changing an etching gas composition, etc. to form groove 4 a on semiconductor substrate 1 in the element isolation region.
  • Then, as shown in FIG. 36, [0275] semiconductor substrate 1 was thermally oxidized, for example, at 950° C. to form silicon oxide film 5 on the inside wall of groove 4 a and round the shoulder edged groove 4 a at the same time. The successive steps were carried out in the same manner as in Example 5.
  • According to this embodiment, undercut a was formed at the shoulder edge of [0276] groove 4 a prior to the step of forming silicon oxide film 5 on the inside wall of groove 4 a, whereby the shoulder edge of groove 4 a could be rounded. Formation of undercut a at the shoulder edge of groove 4 a according to this embodiment could be also carried out together with recessing of silicon oxide film 2 exposed to the inside wall of groove 4 a towards the active region according to Example 5.
  • It is also possible to further round the shoulder edge of the groove by removing edge portions of upper edge portions of the groove after the recess of pad oxide film and before the oxidation in the groove. Thus, after recessing the pad oxide film, isotropic etching may be conducted at the shoulder edge of the groove (to easily remove the edges), followed by oxidation in the groove. [0277]
    • EXAMPLE 7
  • A process for forming [0278] element isolation groove 4 according to a further embodiment of the present invention will be explained below, referring to FIGS. 37 to 44.
  • At first, as shown in FIG. 37, [0279] silicon oxide film 5 was formed on the inside wall of groove 4 a and the shoulder edges of groove 4 a were rounded at the same time in the same manner as in Examples 1 to 3 , and then, as shown in FIG. 38, silicon nitride film 6 was thinly deposited on semiconductor substrate 1 by CVD. Silicon nitride film 6 was formed to suppress growth of silicon oxide film 5 on the inside wall of groove 4 a towards the active region during sintering of silicon oxide film 7 embedded in groove 4 a in a successive step.
  • Then, as shown in FIG. 39, [0280] silicon oxide film 7 was deposited on semiconductor substrate 1 by CVD to embed silicon oxide film 7 in groove 4 a, and then semiconductor substrate 1 was wet oxidized or annealed in the same temperature conditions as described before to sinter silicon oxide film 7 embedded in groove, thereby improving the quality of silicon oxide film 7.
  • Then, as shown in FIG. 40, [0281] silicon oxide film 7 was polished by chemical mechanical polishing to leave silicon oxide film 7 only in groove 4 a, thereby forming an element isolation groove 4. When silicon nitride film 3 covering the active region was to be etched with an etching solution such as hot phosphoric acid, etc. silicon nitride film 6 on the inside wall of element isolation groove 4 was etched away at the same time, as shown in FIG. 41, thereby recessing silicon nitride film 6 inwardly into element isolation region 4 and forming a recess at the shoulder edge of element isolation groove 4. Once such a recess was formed at the shoulder edge of element isolation groove 4, the surface of silicon oxide film 7 embedded in element isolation groove 4′ was sometimes fractured to make foreign fragments etching residues were left in the recess when gate electrode materials such as polycrystalline silicon, etc. deposited thereon in a later step were to be etched.
  • To overcome such an inconvenience as mentioned above, for example, as shown in FIG. 42, after removal of [0282] silicon nitride film 3, silicon oxide film 7 at the shoulder edge of element isolation groove 4 was reoxidized at a temperature of 850° to 900° C. to make the film thickness larger, thereby sealing the recess by silicon oxide film 7. To seal the recess by silicon oxide film 7, it was necessary to make an increment of the film thickness at least twice as large as the thickness of silicon nitride film 6. When the increment of the film thickness was too large, the active region was narrowed by grown silicon oxide film 5. Thus, an increment of the film thickness was made twice as large as the thickness of silicon nitride film 6 or slightly higher than the double thickness of silicon nitride film 6 by controlling oxidation time.
  • According to another procedure for preventing formation of a recess at the shoulder edge of [0283] element isolation groove 4, as shown in FIG. 43, silicon oxide film 7 was polished by chemical mechanical polishing to leave silicon oxide film 7 only in groove 4 a, followed by sintering. By setting a longer sintering time or a higher sintering temperature, the surface of silicon nitride film 3 covering the active region and silicon nitride film 6 at the shoulder edge of element isolation groove 4 could be oxidized. Then, the oxide film on silicon nitride film 3 was removed by etching and successively silicon nitride film 3 was removed by etching, whereby formation of a recess at the shoulder edge of element isolation groove 4 could be prevented, as shown in FIG. 44.
  • It is also possible to further round the shoulder edge of the groove by removing edge portions of upper edge portions of the groove after the recess of pad oxide film and before the oxidation in the groove. Thus, after recessing the pad oxide film, isotropic etching may be conducted at the shoulder edge of the groove (to easily remove the edges), followed by oxidation in the groove. [0284]
    • EXAMPLE 8
  • A process for forming [0285] element isolation groove 4 according to a further embodiment of the present invention will be explained below, referring to FIGS. 45 and 46.
  • At first, as shown in FIG. 45, [0286] silicon oxide film 5 was formed on the inside wall of groove 4(i and the shoulder edge of groove 4 a was rounded at the same time in the same manner as in Examples 1 to 3 , and then, as shown in FIG. 46, the inside wall of groove 4 a was subjected to soft nitriding to segregate nitrogen in the region near the boundary between silicon oxide film 5 formed on the inside wall of groove 4 a and the side wall of the active region of semiconductor substrate 1, thereby forming silicon nitride layer 20. To carry out a soft nitriding of the inside wall of groove 4 a, semiconductor substrate 1 was heat-treated in a NO (nitrogen oxide) or N2O (dinitrogen oxide) atmosphere, where nitrogen released by thermal decomposition of NO or N2O was segregated in the region near the boundary between silicon oxide film 5 and the active region of semiconductor substrate 1, and then silicon nitride layer 20 was formed by heat treatment.
  • According to this embodiment of the present invention, [0287] silicon nitride layer 20 was formed in the region near the boundary between silicon oxide film 5 and the active region of semiconductor substrate 1, whereby the region near the boundary was hard to oxidize during the sintering of silicon oxide film 7 later embedded in groove 4 a and thus growth of silicon oxide film 5 towards the active region could be suppressed.
  • According to another procedure for forming [0288] silicon nitride layer 20 in the region near the boundary between silicon oxide film 5 and the active region of semiconductor substrate 1, as shown in FIG. 47, silicon oxide film 5 was formed on the inside wall of groove 4 a and the shoulder edge of groove 4 a was rounded in the same manner as in Examples 1 to 3 , and then, as shown in FIG. 48, nitrogen was ion-implanted in the region near the boundary between silicon oxide film 5 and the active region of semiconductor substrate 1, if necessary, followed by heat treatment.
  • It is also possible to further round the shoulder edge of the groove by removing edge portions of upper edge portions of the groove after the recess of pad oxide film and before the oxidation in the groove. Thus, after recessing the pad oxide film, isotropic etching may be conducted at the shoulder edge of the groove (to easily remove the edges), followed by oxidation in the groove. [0289]
    • EXAMPLE 9
  • A process for forming [0290] element isolation groove 4 according to a still further embodiment of the present invention will be explained below, referring to FIGS. 49 and 50
  • At first, as shown in FIG. 49, [0291] groove 4 a was trenched on semiconductor substrate 1 in an element isolation region by etching, using silicon nitrogen film 3 as a mask, and then silicon oxide film 2 exposed to the inside wall of groove 4 a was removed with a hydrofluoric acid-based etching solution to recess silicon oxide film 2 towards the active region. Steps up to this stage were the same as in Examples 1 to 3.
  • Then, as shown in FIG. 50, [0292] semiconductor substrate 1 was subjected to soft nitriding to form silicon nitride film 21 on the inside wall of groove 4 a and round the shoulder edge of groove 4 a at the same time. To conduct soft nitriding of semiconductor substrate 1, semiconductor substrate 1 was heat-treated in a mixed NO and N2 atmosphere at a temperature of about 900° C. or in a mixed N2O and N2 atmosphere at a temperature of 1,050° C.
  • According to this embodiment, [0293] silicon nitride film 21 was formed on the inside wall of groove 4 a, whereby the region near the above-mentioned boundary was hard to oxidize during the sintering of silicon oxide film 7 later embedded in groove 4 a and thus growth of silicon oxide film 5 towards the active region could be suppressed.
  • It is also possible to further round the shoulder edge of the groove by removing edge portions of upper edge portions of the groove after the recess of pad oxide film and before the oxidation in the groove. Thus, after recessing the pad oxide film, isotropic etching may be conducted at the shoulder edge of the groove (to easily remove the edges), followed by oxidation in the groove. [0294]
    • EXAMPLE 10
  • A process for forming [0295] element isolation groove 4 according to a still further embodiment of the present invention will be explained below, referring to FIGS. 51 to 54.
  • At first, as shown in FIG. 51, [0296] groove 4 a was trenched on semiconductor substrate 1 in an element isolation region by etching, using silicon nitride film 3 as a mask, and then, as shown in FIG. 52, silicon oxide film 2 exposed to the inside wall of groove 4 a was removed by a hydrofluoric acid-based etching solution to recess silicon oxide film 2 towards the active region. Steps up to this stage were the same as in Examples 1 to 3.
  • Then, as shown in FIG. 53, [0297] silicon oxide film 7 was deposited on semiconductor substrate 1 by CVD to embed silicon oxide film 7 in groove 4 a. Then, as shown in FIG. 54, semiconductor substrate 1 was wet oxidized or annealed to sinter silicon oxide film 7. At the same time, silicon oxide film 5 was formed on the inside wall of groove 4 a and the shoulder edge of groove 4 a was rounded.
  • According to this embodiment, sintering of [0298] silicon oxide film 7, formation of silicon oxide film 5 on the inside wall of groove 4 a and rounding of the shoulder edge of groove 4 a were carried out at the same time, whereby the process for forming element isolation groove 4 could be simplified.
  • It is also possible to further round the shoulder edge of the groove by removing edge portions of upper edge portions of the groove after the recess of pad oxide film and before the oxidation in the groove. Thus, after recessing the pad oxide film, isotropic etching may be conducted at the shoulder edge of the groove (to easily remove the edges), followed by oxidation in the groove. [0299]
    • EXAMPLE 11
  • A process for forming [0300] element isolation groove 4 according to a still further embodiment of the present invention will be explained below, referring to FIGS. 55 to 58.
  • At first, as shown in FIG. 55, [0301] groove 4 a was trenched on semiconductor substrate 1 in an element isolation zone by etching, using silicon nitride film 3 as a mask, and then silicon oxide film 2 exposed to the inside wall of groove 4 a was removed by a hydrofluoric acid-based etching solution to recess silicon oxide film 2 towards the active region. Steps up to this stage were the same as in Examples 1 to 3.
  • Then, as shown in FIG. 56, [0302] silicon oxide film 7 was deposited on semiconductor substrate 1 by CVD to embed silicon oxide film 7 in groove 4 a, and then, as shown in FIG. 57, silicon oxide film 7 on silicon nitride film 3 was removed to leave silicon oxide film 7 only in groove 4 a, thereby forming element isolation groove 4 embedded with silicon oxide film 7. Then, as shown in FIG. 58, semiconductor substrate 1 was wet oxidized to sinter silicon oxide film 7. At the same time, silicon oxide film was formed on the inside wall of groove 4 a and the shoulder edge of groove 4 a was rounded.
  • According to this embodiment, sintering of [0303] silicon oxide film 7, formation of silicon oxide film 5 on the inside wall of groove 4 a and rounding of the shoulder edge of groove 4 a could be carried out at the same time, whereby the process for forming element isolation groove could be simplified.
  • It is also possible to further round the shoulder edge of the groove by removing edge portions of upper edge portions of the groove after the recess of pad oxide film and before the oxidation in the groove. Thus, after recessing the pad oxide film, isotropic etching may be conducted at the shoulder edge of the groove (to easily remove the edges), followed by oxidation in the groove. [0304]
    • EXAMPLE 12
  • A process for forming [0305] element isolation groove 4 according to a still further embodiment of the present invention will be explained below, referring to FIGS. 59 to 64.
  • At fist, as shown in FIG. 59, [0306] groove 4 a was trenched on semiconductor substrate 1 in an element isolation region by etching, using silicon nitride film 3 as a mask, and then silicon oxide film 2 exposed to the inside wall of groove 4 a was removed by a hydrofluoric acid-based etching solution to recess silicon oxide film 2 towards the active region.
  • Then, as shown in FIG. 60, [0307] semiconductor substrate 1 was thermally oxidized to form silicon oxide film 5 on the inside wall of groove 4 a and round the shoulder edge of groove 4 a at the same time. Steps up to this stage were the same as in Examples 1 to 3.
  • Then, as shown in FIG. 61, [0308] polycrystalline silicon film 22 was shallowly deposited on semiconductor substrate 1 by CVD, and then, as shown in FIG. 62, silicon oxide film 7 was deposited on polycrystalline silicon film 22 by CVD to embed silicon oxide film 7 in groove 4 a.
  • Then, as shown in FIG. 63, [0309] semiconductor substrate 1 was wet oxidized to sinter silicon oxide film 7 embedded in groove 4 a. At the same time, at least a portion of polycrystalline silicon film 22 was oxidized and converted to silicon oxide film 23. Thus, oxidation of the region near the boundary between silicon oxide film 5 and the active region of semiconductor substrate 1 was suppressed, so that growth of silicon oxide film 5 towards the active region was inhibited. When polycrystalline silicon film 22 was oxidized to silicon oxide film 23, its volume was increased to about twice as large as the original. That is, even when voids were formed in silicon oxide film 7 embedded in groove 4 a, the voids could be effectively constricted by the volume increase of silicon oxide film 23.
  • Then, as shown in FIG. 64, [0310] silicon oxide film 7 and silicon oxide film 23 on silicon nitride film 3 were removed to leave silicon oxide films 7 and 23 only in groove 4 a, thereby forming element isolation groove 4. Sintering of silicon oxide film 7 and oxidation of polycrystalline silicon film 22 could be also carried out after formation of element isolation groove 4. Furthermore, an amorphous silicon film could be used in place of polycrystalline silicon film 22.
  • It is also possible to further round the shoulder edge of the groove by removing edge portions of upper edge portions of the groove after the recess of pad oxide film and before oxidation in the groove. Thus, after recessing the pad oxide film, isotropic etching may be conducted at the shoulder edge of the groove (to easily remove the edges), followed by oxidation in the groove. [0311]
    • EXAMPLE 13
  • A process for forming [0312] element isolation groove 4 according to a still further embodiment of the present invention will be explained below, referring to FIGS. 65 and 66.
  • At first, as shown in FIG. 65, [0313] groove 4 a was trenched on semiconductor substrate 1 in an element isolation region by etching, using silicon nitride film 3 as a mask, and then silicon oxide film 2 exposed to the inside wall of groove 4 a was removed by a hydrofluoric acid-based etching solution to recess silicon oxide film 2 towards the active region. Steps up to this stage were the same as in Examples 1 to 3.
  • Then, as shown in FIG. 66, [0314] semiconductor substrate 1 was heat-treated in a nitrogen atmosphere to form silicon nitride film 24 on the inside wall of groove 4 a and round the shoulder edge of groove 4 a at the same time.
  • According to this embodiment, [0315] silicon nitride film 24 was formed on the inside wall of groove 4 a, whereby oxidation of the active region of semiconductor substrate 1 could be inhibited during the sintering of silicon oxide film 7 later embedded in groove 4 a.
  • It is also possible to further round the shoulder edge of the groove by removing edge portions of upper edge portions of the groove after the recess of pad oxide film and before the oxidation in the groove. Thus, after recessing the pad oxide film, isotropic etching may be conducted at the shoulder edge of the groove (to easily remove the edges), followed by oxidation in the groove. [0316]
    • EXAMPLE 14
  • A process for forming [0317] element isolation groove 4 according to a still further embodiment of the present invention will be explained below, referring to FIGS. 67 and 68.
  • At first, as shown in FIG. 67, [0318] groove 4 a was trenched on semiconductor substrate 1 in an element isolation region by etching, using silicon nitride film 3 as a mask, and then silicon oxide film 2 exposed to the inside wall of groove 4 a was removed by a hydrofluoric acid-based solution to recess silicon oxide film 2 towards the active region. Steps up to this stage were the same as in Examples 1 to 3 . Then, semiconductor substrate 1 was thermally oxidized to form thin silicon oxide film 25 on the inside wall of groove 4 a.
  • Then, as shown in FIG. 68, [0319] semiconductor substrate 1 was heat-treated in a nitrogen atmosphere to convert silicon oxide film 25 on the inside wall of groove 4 a to silicon nitride film 26.
  • According to this embodiment, [0320] silicon nitride film 26 was formed on the inside wall of groove 4 a, whereby oxidation of the active region of semiconductor substrate 1 could be inhibited during the sintering of silicon oxide film 7 later embedded in groove 4 a.
  • It is also possible to further round the shoulder edge of the groove by removing edge portions of upper edge portions of the groove after the recess of pad oxide film and before the oxidation in the groove. Thus, after recessing the pad oxide film, isotropic etching may be conducted at the shoulder edge of the groove (to easily remove the edges), followed by oxidation in the groove. [0321]
    • EXAMPLE 15
  • A process for forming [0322] element isolation groove 4 according to a still further embodiment of the present invention will be explained below, referring to FIGS. 69 and 70.
  • At first, as shown in FIG. 69, [0323] groove 4 a was trenched on semiconductor substrate 1 in an element isolation region by etching, using silicon nitride film 3 as a mask, and then silicon oxide film 2 exposed to the inside wall of groove 4 a was removed by a hydrofluoric acid-based etching solution to recess silicon oxide film 2 towards the active region. Steps up to this stage were the same as in Examples 1 to 3 . Then, thin polycrystalline silicon film 27 was deposited on semiconductor substrate 1 by CVD.
  • Then, as shown in FIG. 70, [0324] semiconductor substrate 1 was heat-treated in a nitrogen atmosphere to convert polycrystalline silicon film 27 to silicon nitride film 28.
  • According to this embodiment, [0325] silicon nitride film 28 was formed on the inside wall of groove 4 a, whereby oxidation of the active region of semiconductor substrate 1 could be inhibited during the sintering of silicon oxide film 7 later embedded in the groove.
  • In the foregoing Examples 6 to 15, the shoulder edge of [0326] groove 4 a could be more preferably rounded by providing an undercut, as shown in FIG. 34, before trenching groove 4 a.
  • It is also possible to further round the shoulder edge of the groove by removing edge portions of upper edge portions of the groove after the recess of pad oxide film and before the oxidation in the groove. Thus, after recessing the pad oxide film, isotropic etching may be conducted at the shoulder edge of the groove (to easily remove the edges), followed by oxidation in the groove. [0327]
  • In the foregoing, the present invention made by the present inventor has been explained according to specific embodiments of the present invention, but the present invention is not limited thereto and can be modified to various degrees within the scope of the present invention. [0328]
    • INDUSTRIAL APPLICABILITY
  • According to the present invention, the shape of element isolation region by isolation groove of a semiconductor device can be optimized by low temperature heat treatment at not more than 1,000° C., and the devices can be made finer with improved electric characteristics thereof. [0329]
  • Furthermore, according to the present invention, an adverse effect of a stress in the active region due to sintering of silicon oxide film embedded in the element isolation groove upon device characteristics can be reduced. Thus, a semiconductor device of high reliability can be produced.[0330]

Claims (23)

What is claimed is:
1. A process for producing a semiconductor device, which comprises the following steps:
(1) a step of forming a pad oxide film having a thickness of at least 5 nm on a circuit-forming side of a semiconductor substrate,
(2) a step of forming an anti-oxidation film on the pad oxide film,
(3) a step of trenching a groove to a desired depth at a desired position on the circuit-forming side of the semiconductor substrate,
(4) a step of recessing the pad oxide film to an extent of 5 to 40 nm from the inside wall of the groove,
(5) a step of oxidizing the inside wall of the groove trenched on the semiconductor surface,
(6) a step of embedding an isolation film in the oxidized groove,
(7) a step of removing the embedding isolation film formed on the anti-oxidation film,
(8) a step of removing the anti-oxidation film formed on the circuit-forming side of the semiconductor substrate, and
(9) a step of removing the pad oxide film formed on the circuit-forming side of the semiconductor substrate.
2. A process according to claim 1, wherein the inside wall of the groove is oxidized in an oxidative atmosphere of H2/O2 in a flow rate ratio of H2/O2 of not more than 0.5.
3. A process according to claim 1, wherein the inside wall of the groove is oxidized just before a recess space formed up to the edge of the recessed pad oxide film is fully filled by oxidation.
4. A process according to claim 1, wherein the inside wall of the groove is oxidized in an oxidative atmosphere of H2/O2 in a flow rate ratio of H2/O2 of not more than 0.5 in the range wherein a recess space formed up to the edge of the recessed pad oxide film is filled by oxidation.
5. A process for producing a semiconductor device, which comprises the following steps:
(a) a step of thermally oxidizing a semiconductor substrate, thereby forming a first silicon oxide film as a pad oxide film on the surface of the semiconductor substrate, then depositing a silicon nitride film as an anti-oxidation film on the first silicon oxide film, and then selectively etching the silicon nitride film, the first silicon oxide film and the semiconductor substrate residing in an element isolation region while masking an element region, thereby trenching a groove on the surface of the semiconductor substrate,
(b) a step of etching the first silicon oxide film exposed to the inside wall of the groove, thereby recessing the first silicon oxide film from the inside wall of the groove towards an active region to an extent of 5 to 40 nm,
(c) a step of thermally oxidizing the semiconductor substrate, thereby forming a second silicon oxide film on the inside wall of the groove just before fully filling the second silicon oxide film in the recess space formed up to the edge of the recessed first silicon oxide film and rounding the shoulder edge of the groove at the same time,
(d) a step of depositing a third silicon oxide film on the surface of the semiconductor substrate, thereby embedding the third silicon oxide film in the groove,
(e) a step of heat-treating (or annealing) the semiconductor substrate, thereby sintering the third silicon oxide film embedded in the groove,
(f) a step of removing the third silicon oxide film on the silicon nitride film, while leaving the third silicon oxide film only in the groove, thereby forming an element isolation groove embedded with the third silicon oxide film, and
(g) a step of removing the silicon nitride film on the surface o the active region whose circumference is confined by the element isolation groove and then forming a semiconductor element in the active region.
6. A process according to claim 5, wherein a thermally oxidizing temperature for forming the first silicon oxide film, a thermally oxidizing temperature for forming the second silicon oxide film and a heat-treating (or annealing) temperature for sintering the third silicon oxide film are all not more than 1,000° C.
7. A process according to claim 5, wherein the thermally oxidizing temperature for forming the second silicon oxide film is from 800° to 1,000° C.
8. A process according to claim 5, wherein the groove has a taper angle e of not more than 85°.
9. A process according to claim 5, wherein the inside wall of the groove is subjected to an soft nitriding treatment after the step (c) but before the step (d), thereby forming a silicon nitride layer in an area near the boundary between the second silicon oxide film formed on the inside wall of the groove and the active region of the semiconductor substrate.
10. A process according to claim 5, wherein an area near the boundary between the second silicon oxide film formed on the inside wall of the groove and an element isolation region of the semiconductor substrate is subjected to nitrogen ion implantation after the step (c) but before the step (d), thereby forming a silicon nitride layer in the area near the second silicon oxide film formed on the inside wall of the groove and the element isolation region of the semiconductor substrate.
11. A process according to claim 5, wherein the third silicon oxide film on the silicon nitride film is removed after the step (d), while leaving the third silicon oxide film only in the groove, thereby forming an element isolation groove embedded with the third silicon oxide film, and then heat-treating (or annealing) the semiconductor substrate, thereby sintering the third silicon oxide film embedded in the groove.
12. A process according to claim 5, wherein the step (c) is carried out in a nitrogen-containing atmosphere, thereby forming a second silicon nitride film on the inside wall of the groove and rounding the shoulder edge of the groove at the same time.
13. A process according to claim 5, wherein a second silicon nitride film is formed at least on the surface of the second silicon oxide film after the step (c) but before the step (d).
14. A process for producing a semiconductor device, which comprises the following steps:
(a) a step of thermally oxidizing a semiconductor substrate, thereby forming a first silicon oxide film on the surface of the semiconductor substrate, then depositing a silicon nitride film on the first silicon oxide film, up to the edge of the recessed first silicon oxide film and then selectively etching the silicon nitride film and and rounding the shoulder edge of the groove at the the first silicon oxide film residing in an element isolation region while masking an element region,
(b) a step of isotropically and shallowly etching the semiconductor substrate in the element isolation region, thereby forming an undercut on the semiconductor substrate at the edge of the element isolation region,
(c) a step of selectively etching the semiconductor substrate in the element isolation region, thereby trenching a groove on the surface of the semiconductor substrate,
(d) a step of thermally oxidizing the semiconductor substrate, thereby forming a second silicon oxide film on the inside wall of the groove and rounding the shoulder edge of the groove at the same time,
(e) a step of depositing a third silicon oxide film on the surface of the semiconductor substrate, thereby embedding the third silicon oxide film in the groove,
(f) a step of heat-treating (or annealing) the semiconductor substrate, thereby sintering the third silicon oxide film embedded in the groove,
(g) a step of removing the third silicon oxide film on the silicon nitride film, while leaving the third silicon oxide film only in the groove, thereby forming an element isolation groove embedded with the third silicon oxide film, and
(h) a step of removing the silicon nitride film on the surface of an active region whose circumference is confined by the element isolation groove, and then forming a semiconductor element in the active region.
15. A process for producing a semiconductor device, which comprises the following steps:
(a) a step of thermally oxidizing a semiconductor substrate, thereby forming a first silicon oxide film on the surface of the semiconductor substrate, then depositing a first silicon nitride film on the first silicon oxide film and then selectively etching the first silicon nitride film, the first silicon oxide film and the semiconductor substrate residing in an clement isolation region while masking an element region, thereby trenching a groove on the surface of the semiconductor substrate,
(b) a step of etching the first silicon oxide film exposed to the inside wall of the groove, thereby recessing the first silicon oxide film from the inside wall of the groove to an extent of 5 to 40 nm towards an active region,
(c) a step of thermally oxidizing the semiconductor device, thereby forming a second silicon oxide film on the inside wall of the groove just before fully filling the second silicon oxide film in the recess space formed up to the recessed first silicon oxide film, and rounding the shoulder edge of the groove at the same time,
(d) a step of depositing a second silicon nitride film on the semiconductor substrate including the inside of the groove by chemical vapor deposition,
(e) a step of depositing a third silicon oxide film on the surface of the semiconductor substrate, thereby embedding the third silicon oxide film in the groove,
(f) a step of heat treating (or annealing) the semiconductor substrate, thereby sintering the third silicon oxide film embedded in the groove,
(g) a step of removing the third silicon oxide film and the second silicon nitride film on the first silicon nitride film, while leaving the third silicon oxide film and the second silicon nitride film only in the groove, thereby forming an element isolation groove embedded with the third silicon oxide film and the second silicon nitride film,
(h) a step of removing the first silicon nitride film on the surface of the active region whose circumference is confined by the element isolation groove by etching,
(i) a step of thermally oxidizing the third silicon oxide film in the element isolation groove, thereby increasing the thickness of the film and filling a recess formed by simultaneous removal of the second silicon nitride film at the shoulder edge of the element isolation groove during the removal of the first silicon nitride film by etching, and
(j) a step of forming a semiconductor element in the active region.
16. A process for producing a semiconductor device, which comprises the following steps:
(a) a step of thermally oxidizing a semiconductor substrate, thereby forming a first silicon oxide film on the surface of the semiconductor substrate, then depositing a first silicon nitride film on the first silicon oxide film, and then selectively etching the first silicon nitride film, the first silicon oxide film and the semiconductor substrate residing in an element isolation zone while masking an element region, thereby trenching a groove on the surface of the semiconductor substrate,
(b) a step of etching the first silicon oxide film exposed to the inside wall of the groove, thereby recessing the first silicon oxide film from the inside wall of the groove towards an active region to an extent of 5 to 40 nm,
(c) a step of thermally oxidizing the semiconductor substrate, thereby forming a second silicon oxide film on the inside wall of the groove just before fully filling the second silicon oxide film in the recess space formed up to the recessed first silicon oxide film, and rounding the shoulder edge of the groove at the same time,
(d) a step of depositing a second silicon nitride film on the semiconductor substrate including the inside of the groove by chemical vapor deposition,
(e) a step of depositing a third silicon oxide film on the surface of the semiconductor substrate, thereby embedding the third silicon oxide in the groove,
(f) a step of removing the third silicon oxide film and the second silicon nitride film on the first silicon nitride film, while leaving the third silicon oxide film and the second silicon nitride film only in the groove, thereby forming an element isolation groove embedded with the third silicon oxide film and the second silicon nitride film,
(g) a step of heat-treating (or annealing) the semiconductor substrate, thereby sintering the third silicon oxide film embedded in the groove, and oxidizing the surface of the first silicon nitride film and the surface of the second silicon nitride film on the shoulder edge of the element isolation groove,
(h) a step of removing the first silicon nitride film on the surface of the active region whose circumference is confined by the element isolation groove by and the oxide film on the surface of the first silicon nitride film by etching, and
(i) a step of forming a semiconductor element in the active region.
17. A process for producing a semiconductor device, which comprises the following steps:
(a) a step of thermally oxidizing a semiconductor substrate, thereby forming a first silicon oxide film on the surface of the semiconductor substrate, then depositing a silicon nitride film on the first silicon oxide film, and then selectively etching the silicon nitride film, the first silicon oxide film and the semiconductor substrate residing in an element isolation region while masking an element region, thereby trenching a groove on the surface of the semiconductor substrate,
(b) a step of etching the first silicon oxide film exposed to the inside wall of the groove, thereby recessing the first silicon oxide film from the inside wall of the groove towards an active region to an extent of 5 to 40 nm,
(c) a step of depositing a second silicon oxide film on the surface of the semiconductor substrate, thereby embedding the second silicon oxide film in the groove.
(d) a step of thermally oxidizing the semiconductor substrate, thereby sintering the second silicon oxide film embedded in the groove, forming a third silicon film on oxide film on the inside wall of the groove and rounding the shoulder edge of the groove at the same time,
(e) a step of removing the second silicon oxide film on the silicon nitride film, while leaving the second silicon oxide film only in the groove, thereby forming an element isolation groove embedded with the second silicon oxide film, and
(f) a step of removing the silicon nitride film on the surface of the active region whose circumference is confined by the element isolation groove, and then forming a semiconductor element in the active region.
18. A process for producing a semiconductor device, which comprises the following steps:
(a) a step of thermally oxidizing a semiconductor substrate, thereby forming a first silicon oxide film on the surface of the semiconductor substrate, then depositing a silicon nitride film on the first silicon oxide film, and then selectively etching the silicon nitride film, the first silicon oxide film and the semiconductor substrate residing in an element isolation region, thereby trenching a groove on the surface of the semiconductor substrate,
(b) a step of etching the first silicon oxide film exposed to the inside wall of the groove, thereby recessing the first silicon oxide film from the inside wall of the groove towards an active region to an extent of 5 to 40 nm,
(c) A step of depositing a second silicon oxide film on the surface of the semiconductor substrate, thereby embedding the second silicon oxide film in the groove,
(d) a step of removing the second silicon oxide film on the silicon nitride film, while leaving the second silicon oxide film only in the groove, thereby forming an element isolation groove embedded with the second silicon oxide film,
(e) a step of thermally oxidizing the semiconductor substrate, thereby sintering the second silicon oxide film embedded in the groove, forming a third silicon oxide film on the inside wall of the groove and rounding the shoulder edge of the groove at the same time, and
(f) a step of removing the silicon nitride film on the surface of the active region whose circumference is confined by the element isolation groove, and then forming a semiconductor element in the active region.
19. A process producing a semiconductor device, which comprises the following steps:
(a) A step of thermally oxidizing a semiconductor substrate, thereby forming a first silicon oxide film on the surface of the semiconductor substrate, then depositing a silicon nitride film on the first silicon film, and then selectively etching the silicon nitride film, the first silicon oxide film and the semiconductor substrate residing in an element isolation region while masking an element region, thereby trenching a groove on the surface of the semiconductor substrate,
(b) a step of etching the first silicon oxide film exposed to the inside wall of the groove, thereby recessing the first silicon oxide film from the inside wall of the groove towards an active region to an extent of 5 to 40 nm,
(c) a step of thermally oxidizing the semiconductor substrate, thereby forming a second silicon oxide film on the inside wall of the groove just before fully filling the second silicon oxide film in the recess space formed up to the edge of the recessed first silicon oxide film, and rounding the shoulder edge of the groove at the same time,
(d) a step of depositing a polycrystalline silicon film on the surface of the semiconductor substrate,
(e) a step of depositing a third silicon oxide film on the surface of the semiconductor substrate, thereby embedding the third silicon oxide film in the groove,
(f) a step of heat-treating (or annealing) the semiconductor substrate, thereby sintering the third silicon oxide film embedded in the groove and oxidizing the polycrystalline silicon film to convert at least a portion thereof to a silicon oxide film,
(g) a step of removing the third silicon oxide film and the silicon oxide film o n the silicon nitride film, while leaving the third silicon oxide film and the silicon oxide film only in the groove, thereby forming an element isolation groove embedded with the third silicon oxide film and the silicon oxide film, and
(h) a step of removing the silicon nitride film on the surface of the active region whose circumference is confined by the element isolation groove, and then forming a semiconductor element in the active region.
20. A process for producing a semiconductor device, which comprises the following steps:
(a) a step of thermally oxidizing a semiconductor substrate, thereby forming a first silicon oxide film on the surface of the semiconductor substrate, then depositing a silicon nitride film on the first silicon oxide film, and then selectively etching the silicon nitride film, the first silicon oxide film and the semiconductor substrate residing in an clement isolation region while masking an element region, thereby trenching a groove on the surface of the semiconductor substrate,
(b) a step of etching the first silicon oxide film exposed to the inside wall of the groove, thereby recessing the first silicon oxide film from the inside wall of the groove towards an active region to an extent of 5 to 40 nm,
(c) a step of thermally oxidizing the semiconductor substrate, thereby forming a second silicon oxide film on the inside wall of the groove just before fully filling the second silicon oxide film in the recess space formed up to the edge of recessed first silicon oxide film and rounding the shoulder edge of the groove at the same time,
(d) a step of depositing a polycrystalline silicon film on the surface of the semiconductor substrate
(e) a step of depositing a third silicon oxide film on the surface of the semiconductor substrate, thereby embedding the third silicon oxide film in the groove,
(f) a step of removing the third silicon oxide film and the polycrystalline silicon film on the silicon nitride film, while leaving the third silicon oxide film and the polycrystalline silicon film in the groove, thereby forming an element isolation groove embedded with the third silicon oxide film and the polycrystalline silicon film,
(g) a step of heat-treating (or annealing) the semiconductor substrate, thereby sintering the third silicon oxide film embedded in the groove and oxidizing the polycrystalline silicon film to convert at least a portion thereof to a silicon oxide film, and
(h) a step of removing the silicon nitride film on the surface of the active region whose circumference is confined by the element isolation groove, and then forming a semiconductor element in the active region.
21. A process for producing a semiconductor device, same time, which comprises the following steps:
(a) a step of oxidizing a semiconductor substrate, thereby forming a first silicon oxide film on the surface of the semiconductor substrate, then depositing a silicon nitride film on the first silicon oxide film, and then selectively etching the silicon nitride film, the first silicon oxide film and the semiconductor substrate residing in an element isolation region while masking an element region, thereby trenching a groove on the surface of the semiconductor substrate,
(b) a step of etching the first silicon oxide film exposed to the inside wall of the groove, thereby recessing the first silicon oxide film from the inside wall of the groove towards an active region in an extent of 5 to 40 nm,
(c) a step of heat-nitriding the semiconductor substrate, thereby forming a second silicon nitride on the inside wall of the groove,
(d) a step of depositing a second silicon oxide film on the surface of the semiconductor substrate, thereby embedding the second silicon oxide film in the groove,
(e) a step of heat-treating (or annealing) the semiconductor substrate, thereby sintering the second silicon oxide film embedded in the groove,
(f) a step of removing the second silicon oxide film on the first silicon nitride film, while leaving the second silicon oxide film only in the groove, thereby forming an element isolation groove embedded with the second silicon oxide film, and
(g) a step of removing the first silicon nitride film on the surface of the active region whose circumference is confined by the element isolation groove, and then forming a semiconductor element in the active region.
22. A process for producing a semiconductor device, which comprises the following steps:
(a) a step of thermally oxidizing a semiconductor substrate, thereby forming a first silicon oxide film on the surface of the semiconductor substrate, then depositing a silicon nitride film on the first silicon oxide film and then selectively etching the silicon nitride film, the first silicon oxide film and the semiconductor substrate residing in an element isolation region while masking an element region, thereby trenching a groove on the surface of the semiconductor substrate,
(b) a step of etching the first silicon oxide exposed to the inside wall of the groove, thereby recessing the first silicon oxide film from the inside wall of the groove towards an active region in an extent of 5 to 40 nm,
(c) a step of thermally oxidizing the semiconductor substrate, thereby forming a second silicon oxide film on the inside wall of the groove, and then nitriding the second silicon oxide film, thereby converting at least a portion thereof to a silicon nitride film,
(d) a step of depositing a third silicon oxide film on the surface of the semiconductor substrate, thereby embedding the third silicon oxide film in the groove,
(f) a step of removing the third silicon oxide film on the first silicon nitride film, while leaving the third silicon oxide film only in the groove, thereby forming an element isolation groove embedded with the third silicon oxide film, and
(g) a step of removing the first silicon nitride film on the surface of the active region whose circumference is confined by the element isolation groove, and then forming a semiconductor element in the active region.
23. A process producing a semiconductor device, which comprises the following steps:
(a) a step of thermally oxidizing a semiconductor substrate, thereby forming a first silicon oxide film on the surface of the semiconductor substrate, then depositing a silicon nitride film on the first silicon oxide film, and then selectively etching the silicon nitride film, the first silicon oxide film and the semiconductor substrate residing in an element isolation region while masking an element region, thereby trenching a groove on the surface of the semiconductor substrate,
(b) a step of etching the first silicon oxide film exposed to the inside wall of the groove, thereby recessing the first silicon oxide film from the inside wall of the groove towards an active region to an extent of 5 to 40 nm,
(c) a step of depositing a polycrystalline silicon film on the semiconductor substrate, and then nitriding the polycrystalline silicon film, thereby converting at least a portion thereof to a silicon nitride film,
(d) a step of depositing a second silicon oxide film on the surface of the semiconductor substrate, thereby embedding the second silicon oxide film in the groove,
(e) a step of heat-treating (or annealing) the semiconductor substrate, thereby sintering the second silicon oxide film embedded in the groove,
(f) a step of removing the second silicon oxide film on the first silicon nitride film, while leaving the second silicon oxide film only in the groove, thereby forming an element isolation groove embedded with the second silicon oxide film, and
(g) a step of removing the first silicon nitride film on the surface of the active region whose circumference is confined by the element isolation groove, and then forming a semiconductor element in the active region.
US10/141,422 1998-07-31 2002-05-06 Semiconductor device and process for producing the same Abandoned US20030119276A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US10/141,422 US20030119276A1 (en) 1998-07-31 2002-05-06 Semiconductor device and process for producing the same

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
JP21683198A JP4592837B2 (en) 1998-07-31 1998-07-31 Manufacturing method of semiconductor device
JP10-216831 1998-07-31
US09/363,184 US6090684A (en) 1998-07-31 1999-07-29 Method for manufacturing semiconductor device
US09/536,447 US6403446B1 (en) 1998-07-31 2000-03-28 Method for manufacturing semiconductor device
US10/141,422 US20030119276A1 (en) 1998-07-31 2002-05-06 Semiconductor device and process for producing the same

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US09/536,447 Continuation US6403446B1 (en) 1998-07-31 2000-03-28 Method for manufacturing semiconductor device

Publications (1)

Publication Number Publication Date
US20030119276A1 true US20030119276A1 (en) 2003-06-26

Family

ID=16694586

Family Applications (3)

Application Number Title Priority Date Filing Date
US09/363,184 Expired - Fee Related US6090684A (en) 1998-07-31 1999-07-29 Method for manufacturing semiconductor device
US09/536,447 Expired - Fee Related US6403446B1 (en) 1998-07-31 2000-03-28 Method for manufacturing semiconductor device
US10/141,422 Abandoned US20030119276A1 (en) 1998-07-31 2002-05-06 Semiconductor device and process for producing the same

Family Applications Before (2)

Application Number Title Priority Date Filing Date
US09/363,184 Expired - Fee Related US6090684A (en) 1998-07-31 1999-07-29 Method for manufacturing semiconductor device
US09/536,447 Expired - Fee Related US6403446B1 (en) 1998-07-31 2000-03-28 Method for manufacturing semiconductor device

Country Status (2)

Country Link
US (3) US6090684A (en)
JP (1) JP4592837B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030001227A1 (en) * 2001-06-29 2003-01-02 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing a semiconductor device
WO2007089206A1 (en) 2006-02-01 2007-08-09 Silex Microsystems Ab Vias and method of making
US20220005690A1 (en) * 2018-10-15 2022-01-06 Tokyo Electron Limited Method of forming silicon film on substrate having fine pattern

Families Citing this family (102)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11284060A (en) * 1998-03-27 1999-10-15 Hitachi Ltd Semiconductor device and manufacturing method thereof
JP4592837B2 (en) * 1998-07-31 2010-12-08 ルネサスエレクトロニクス株式会社 Manufacturing method of semiconductor device
KR20000013397A (en) * 1998-08-07 2000-03-06 윤종용 Manufacturing method of trench isolation
US6274498B1 (en) * 1998-09-03 2001-08-14 Micron Technology, Inc. Methods of forming materials within openings, and method of forming isolation regions
US6372601B1 (en) * 1998-09-03 2002-04-16 Micron Technology, Inc. Isolation region forming methods
KR100292616B1 (en) * 1998-10-09 2001-07-12 윤종용 Manufacturing method of trench isolation
JP3571236B2 (en) * 1998-11-09 2004-09-29 株式会社ルネサステクノロジ Method for manufacturing semiconductor device
JP3955404B2 (en) * 1998-12-28 2007-08-08 株式会社ルネサステクノロジ Manufacturing method of semiconductor integrated circuit device
JP4649006B2 (en) * 1999-07-16 2011-03-09 ルネサスエレクトロニクス株式会社 Semiconductor device
KR100338767B1 (en) 1999-10-12 2002-05-30 윤종용 Trench Isolation structure and semiconductor device having the same, trench isolation method
WO2002023624A2 (en) * 2000-09-14 2002-03-21 Infineon Technologies North America Corp. Field effect transistor and method of fabrication
US6406976B1 (en) * 2000-09-18 2002-06-18 Motorola, Inc. Semiconductor device and process for forming the same
US6355538B1 (en) * 2000-09-18 2002-03-12 Vanguard International Semiconductor Corporation Method of forming isolation material with edge extension structure
JP3702162B2 (en) * 2000-09-25 2005-10-05 三洋電機株式会社 Manufacturing method of semiconductor device
US6368941B1 (en) * 2000-11-08 2002-04-09 United Microelectronics Corp. Fabrication of a shallow trench isolation by plasma oxidation
KR100392894B1 (en) * 2000-12-27 2003-07-28 동부전자 주식회사 Method for forming trench of semiconductor element
US6613635B2 (en) * 2000-12-28 2003-09-02 Sanyo Electric Co., Ltd. Method of fabricating semiconductor device having element isolation trench
JP2003017556A (en) * 2001-06-29 2003-01-17 Mitsubishi Electric Corp Semiconductor device and method of manufacturing same
US6890859B1 (en) 2001-08-10 2005-05-10 Cypress Semiconductor Corporation Methods of forming semiconductor structures having reduced defects, and articles and devices formed thereby
JP2004095886A (en) * 2002-08-30 2004-03-25 Fujitsu Ltd Semiconductor device and its manufacturing method
US7388259B2 (en) * 2002-11-25 2008-06-17 International Business Machines Corporation Strained finFET CMOS device structures
KR100474863B1 (en) * 2002-12-10 2005-03-10 매그나칩 반도체 유한회사 Method of forming an isolation layer in a semiconductor device
JP2004260102A (en) * 2003-02-27 2004-09-16 Rohm Co Ltd Process for fabricating semiconductor device
US6887798B2 (en) * 2003-05-30 2005-05-03 International Business Machines Corporation STI stress modification by nitrogen plasma treatment for improving performance in small width devices
US7329923B2 (en) * 2003-06-17 2008-02-12 International Business Machines Corporation High-performance CMOS devices on hybrid crystal oriented substrates
US7279746B2 (en) * 2003-06-30 2007-10-09 International Business Machines Corporation High performance CMOS device structures and method of manufacture
US7410846B2 (en) 2003-09-09 2008-08-12 International Business Machines Corporation Method for reduced N+ diffusion in strained Si on SiGe substrate
US6890808B2 (en) * 2003-09-10 2005-05-10 International Business Machines Corporation Method and structure for improved MOSFETs using poly/silicide gate height control
US6887751B2 (en) * 2003-09-12 2005-05-03 International Business Machines Corporation MOSFET performance improvement using deformation in SOI structure
US7170126B2 (en) * 2003-09-16 2007-01-30 International Business Machines Corporation Structure of vertical strained silicon devices
US6869866B1 (en) 2003-09-22 2005-03-22 International Business Machines Corporation Silicide proximity structures for CMOS device performance improvements
US7144767B2 (en) * 2003-09-23 2006-12-05 International Business Machines Corporation NFETs using gate induced stress modulation
US6872641B1 (en) * 2003-09-23 2005-03-29 International Business Machines Corporation Strained silicon on relaxed sige film with uniform misfit dislocation density
US7119403B2 (en) 2003-10-16 2006-10-10 International Business Machines Corporation High performance strained CMOS devices
US7303949B2 (en) * 2003-10-20 2007-12-04 International Business Machines Corporation High performance stress-enhanced MOSFETs using Si:C and SiGe epitaxial source/drain and method of manufacture
US7037770B2 (en) * 2003-10-20 2006-05-02 International Business Machines Corporation Method of manufacturing strained dislocation-free channels for CMOS
US7129126B2 (en) * 2003-11-05 2006-10-31 International Business Machines Corporation Method and structure for forming strained Si for CMOS devices
US7015082B2 (en) * 2003-11-06 2006-03-21 International Business Machines Corporation High mobility CMOS circuits
US7029964B2 (en) * 2003-11-13 2006-04-18 International Business Machines Corporation Method of manufacturing a strained silicon on a SiGe on SOI substrate
US7122849B2 (en) * 2003-11-14 2006-10-17 International Business Machines Corporation Stressed semiconductor device structures having granular semiconductor material
US7247534B2 (en) * 2003-11-19 2007-07-24 International Business Machines Corporation Silicon device on Si:C-OI and SGOI and method of manufacture
US7198995B2 (en) * 2003-12-12 2007-04-03 International Business Machines Corporation Strained finFETs and method of manufacture
US7247912B2 (en) * 2004-01-05 2007-07-24 International Business Machines Corporation Structures and methods for making strained MOSFETs
US7118999B2 (en) * 2004-01-16 2006-10-10 International Business Machines Corporation Method and apparatus to increase strain effect in a transistor channel
US7202132B2 (en) 2004-01-16 2007-04-10 International Business Machines Corporation Protecting silicon germanium sidewall with silicon for strained silicon/silicon germanium MOSFETs
US7381609B2 (en) 2004-01-16 2008-06-03 International Business Machines Corporation Method and structure for controlling stress in a transistor channel
US7923782B2 (en) 2004-02-27 2011-04-12 International Business Machines Corporation Hybrid SOI/bulk semiconductor transistors
US7205206B2 (en) * 2004-03-03 2007-04-17 International Business Machines Corporation Method of fabricating mobility enhanced CMOS devices
US7504693B2 (en) * 2004-04-23 2009-03-17 International Business Machines Corporation Dislocation free stressed channels in bulk silicon and SOI CMOS devices by gate stress engineering
US7223994B2 (en) * 2004-06-03 2007-05-29 International Business Machines Corporation Strained Si on multiple materials for bulk or SOI substrates
US7037794B2 (en) * 2004-06-09 2006-05-02 International Business Machines Corporation Raised STI process for multiple gate ox and sidewall protection on strained Si/SGOI structure with elevated source/drain
US7227205B2 (en) * 2004-06-24 2007-06-05 International Business Machines Corporation Strained-silicon CMOS device and method
TWI463526B (en) * 2004-06-24 2014-12-01 Ibm Improved strained-silicon cmos device and method
US7288443B2 (en) * 2004-06-29 2007-10-30 International Business Machines Corporation Structures and methods for manufacturing p-type MOSFET with graded embedded silicon-germanium source-drain and/or extension
US7217949B2 (en) * 2004-07-01 2007-05-15 International Business Machines Corporation Strained Si MOSFET on tensile-strained SiGe-on-insulator (SGOI)
US6991998B2 (en) * 2004-07-02 2006-01-31 International Business Machines Corporation Ultra-thin, high quality strained silicon-on-insulator formed by elastic strain transfer
US7384829B2 (en) 2004-07-23 2008-06-10 International Business Machines Corporation Patterned strained semiconductor substrate and device
US7193254B2 (en) * 2004-11-30 2007-03-20 International Business Machines Corporation Structure and method of applying stresses to PFET and NFET transistor channels for improved performance
US7238565B2 (en) 2004-12-08 2007-07-03 International Business Machines Corporation Methodology for recovery of hot carrier induced degradation in bipolar devices
US7262087B2 (en) * 2004-12-14 2007-08-28 International Business Machines Corporation Dual stressed SOI substrates
US7173312B2 (en) * 2004-12-15 2007-02-06 International Business Machines Corporation Structure and method to generate local mechanical gate stress for MOSFET channel mobility modification
US7274084B2 (en) * 2005-01-12 2007-09-25 International Business Machines Corporation Enhanced PFET using shear stress
US20060160317A1 (en) * 2005-01-18 2006-07-20 International Business Machines Corporation Structure and method to enhance stress in a channel of cmos devices using a thin gate
US7432553B2 (en) * 2005-01-19 2008-10-07 International Business Machines Corporation Structure and method to optimize strain in CMOSFETs
US7220626B2 (en) * 2005-01-28 2007-05-22 International Business Machines Corporation Structure and method for manufacturing planar strained Si/SiGe substrate with multiple orientations and different stress levels
US7256081B2 (en) * 2005-02-01 2007-08-14 International Business Machines Corporation Structure and method to induce strain in a semiconductor device channel with stressed film under the gate
US7224033B2 (en) * 2005-02-15 2007-05-29 International Business Machines Corporation Structure and method for manufacturing strained FINFET
US7545004B2 (en) * 2005-04-12 2009-06-09 International Business Machines Corporation Method and structure for forming strained devices
JP2006332404A (en) * 2005-05-27 2006-12-07 Seiko Epson Corp Semiconductor device and manufacturing method thereof
US7544577B2 (en) * 2005-08-26 2009-06-09 International Business Machines Corporation Mobility enhancement in SiGe heterojunction bipolar transistors
US7202513B1 (en) * 2005-09-29 2007-04-10 International Business Machines Corporation Stress engineering using dual pad nitride with selective SOI device architecture
US20070096170A1 (en) * 2005-11-02 2007-05-03 International Business Machines Corporation Low modulus spacers for channel stress enhancement
US20070099360A1 (en) * 2005-11-03 2007-05-03 International Business Machines Corporation Integrated circuits having strained channel field effect transistors and methods of making
US7655511B2 (en) 2005-11-03 2010-02-02 International Business Machines Corporation Gate electrode stress control for finFET performance enhancement
US7785950B2 (en) * 2005-11-10 2010-08-31 International Business Machines Corporation Dual stress memory technique method and related structure
US7709317B2 (en) * 2005-11-14 2010-05-04 International Business Machines Corporation Method to increase strain enhancement with spacerless FET and dual liner process
US7348638B2 (en) * 2005-11-14 2008-03-25 International Business Machines Corporation Rotational shear stress for charge carrier mobility modification
US7564081B2 (en) * 2005-11-30 2009-07-21 International Business Machines Corporation finFET structure with multiply stressed gate electrode
US7863197B2 (en) * 2006-01-09 2011-01-04 International Business Machines Corporation Method of forming a cross-section hourglass shaped channel region for charge carrier mobility modification
US7776695B2 (en) * 2006-01-09 2010-08-17 International Business Machines Corporation Semiconductor device structure having low and high performance devices of same conductive type on same substrate
US7635620B2 (en) * 2006-01-10 2009-12-22 International Business Machines Corporation Semiconductor device structure having enhanced performance FET device
US20070158743A1 (en) * 2006-01-11 2007-07-12 International Business Machines Corporation Thin silicon single diffusion field effect transistor for enhanced drive performance with stress film liners
US7691698B2 (en) * 2006-02-21 2010-04-06 International Business Machines Corporation Pseudomorphic Si/SiGe/Si body device with embedded SiGe source/drain
US8461009B2 (en) * 2006-02-28 2013-06-11 International Business Machines Corporation Spacer and process to enhance the strain in the channel with stress liner
US7521307B2 (en) * 2006-04-28 2009-04-21 International Business Machines Corporation CMOS structures and methods using self-aligned dual stressed layers
US7608489B2 (en) * 2006-04-28 2009-10-27 International Business Machines Corporation High performance stress-enhance MOSFET and method of manufacture
US7615418B2 (en) * 2006-04-28 2009-11-10 International Business Machines Corporation High performance stress-enhance MOSFET and method of manufacture
US7803690B2 (en) * 2006-06-23 2010-09-28 Taiwan Semiconductor Manufacturing Company, Ltd. Epitaxy silicon on insulator (ESOI)
US8853746B2 (en) * 2006-06-29 2014-10-07 International Business Machines Corporation CMOS devices with stressed channel regions, and methods for fabricating the same
US7790540B2 (en) 2006-08-25 2010-09-07 International Business Machines Corporation Structure and method to use low k stress liner to reduce parasitic capacitance
US7462522B2 (en) * 2006-08-30 2008-12-09 International Business Machines Corporation Method and structure for improving device performance variation in dual stress liner technology
US8754446B2 (en) * 2006-08-30 2014-06-17 International Business Machines Corporation Semiconductor structure having undercut-gate-oxide gate stack enclosed by protective barrier material
US8115254B2 (en) 2007-09-25 2012-02-14 International Business Machines Corporation Semiconductor-on-insulator structures including a trench containing an insulator stressor plug and method of fabricating same
US8492846B2 (en) 2007-11-15 2013-07-23 International Business Machines Corporation Stress-generating shallow trench isolation structure having dual composition
JP4920631B2 (en) * 2008-04-28 2012-04-18 シャープ株式会社 Manufacturing method of semiconductor device
CN101640182B (en) * 2008-07-31 2011-05-04 中芯国际集成电路制造(北京)有限公司 Method for forming shallow trench isolation structure and method for manufacturing semiconductor device
US8598006B2 (en) 2010-03-16 2013-12-03 International Business Machines Corporation Strain preserving ion implantation methods
CN102386132B (en) * 2010-08-27 2013-10-30 中芯国际集成电路制造(上海)有限公司 Method of reducing alignment tolerance and special equipment thereof applied in heat treatment process
CN102437084A (en) * 2011-08-17 2012-05-02 上海华力微电子有限公司 Method for adjusting thickness of oxide film on shallow trench isolation (STI) underlayer
US11569368B2 (en) * 2020-06-11 2023-01-31 Atomera Incorporated Method for making semiconductor device including a superlattice and providing reduced gate leakage
US11469302B2 (en) 2020-06-11 2022-10-11 Atomera Incorporated Semiconductor device including a superlattice and providing reduced gate leakage
CN112366205B (en) * 2020-11-09 2021-10-22 长江存储科技有限责任公司 Semiconductor device and preparation method thereof

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5863827A (en) * 1997-06-03 1999-01-26 Texas Instruments Incorporated Oxide deglaze before sidewall oxidation of mesa or trench
US5989975A (en) * 1997-10-04 1999-11-23 United Microelectronics Corp. Method for manufacturing shallow trench isolation
US6057241A (en) * 1997-04-30 2000-05-02 Hitachi, Ltd. Method of manufacturing a semiconductor integrated circuit device
US6090684A (en) * 1998-07-31 2000-07-18 Hitachi, Ltd. Method for manufacturing semiconductor device
US6261925B1 (en) * 1996-12-31 2001-07-17 Intel Corporation N2O Nitrided-oxide trench sidewalls to prevent boron outdiffusion and decrease stress
US6323102B1 (en) * 1998-01-27 2001-11-27 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing a semiconductor device
US6559027B2 (en) * 1997-02-18 2003-05-06 Hitachi, Ltd. Semiconductor device and process for producing the sme

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4580330A (en) * 1984-06-15 1986-04-08 Texas Instruments Incorporated Integrated circuit isolation
US5258332A (en) * 1987-08-28 1993-11-02 Kabushiki Kaisha Toshiba Method of manufacturing semiconductor devices including rounding of corner portions by etching
JPH02260660A (en) * 1989-03-31 1990-10-23 Toshiba Corp Manufacture of mos type semiconductor device
JPH0774164A (en) * 1993-07-02 1995-03-17 Hitachi Ltd Semiconductor memory and manufacture thereof
JP2955459B2 (en) * 1993-12-20 1999-10-04 株式会社東芝 Method for manufacturing semiconductor device
US5719085A (en) * 1995-09-29 1998-02-17 Intel Corporation Shallow trench isolation technique
TW444333B (en) * 1998-07-02 2001-07-01 United Microelectronics Corp Method for forming corner rounding of shallow trench isolation

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6261925B1 (en) * 1996-12-31 2001-07-17 Intel Corporation N2O Nitrided-oxide trench sidewalls to prevent boron outdiffusion and decrease stress
US6559027B2 (en) * 1997-02-18 2003-05-06 Hitachi, Ltd. Semiconductor device and process for producing the sme
US6057241A (en) * 1997-04-30 2000-05-02 Hitachi, Ltd. Method of manufacturing a semiconductor integrated circuit device
US5863827A (en) * 1997-06-03 1999-01-26 Texas Instruments Incorporated Oxide deglaze before sidewall oxidation of mesa or trench
US5989975A (en) * 1997-10-04 1999-11-23 United Microelectronics Corp. Method for manufacturing shallow trench isolation
US6323102B1 (en) * 1998-01-27 2001-11-27 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing a semiconductor device
US6090684A (en) * 1998-07-31 2000-07-18 Hitachi, Ltd. Method for manufacturing semiconductor device
US6403446B1 (en) * 1998-07-31 2002-06-11 Hitachi, Ltd. Method for manufacturing semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030001227A1 (en) * 2001-06-29 2003-01-02 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing a semiconductor device
US7095093B2 (en) 2001-06-29 2006-08-22 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing a semiconductor device
WO2007089206A1 (en) 2006-02-01 2007-08-09 Silex Microsystems Ab Vias and method of making
US20220005690A1 (en) * 2018-10-15 2022-01-06 Tokyo Electron Limited Method of forming silicon film on substrate having fine pattern

Also Published As

Publication number Publication date
US6403446B1 (en) 2002-06-11
US6090684A (en) 2000-07-18
JP2000049222A (en) 2000-02-18
JP4592837B2 (en) 2010-12-08

Similar Documents

Publication Publication Date Title
US6242323B1 (en) Semiconductor device and process for producing the same
US20030119276A1 (en) Semiconductor device and process for producing the same
US6221735B1 (en) Method for eliminating stress induced dislocations in CMOS devices
US6881631B2 (en) Method of manufacturing semiconductor device
KR0165457B1 (en) Method of trench isolation
KR970000703B1 (en) Manufacturing method of semiconductor device in which a silicon wafer is provided at its surface with filled oxide regions
JPH0513566A (en) Manufacture of semiconductor device
EP1164636B1 (en) Method to form self aligned, L-shaped sidewall spacers
US6441444B1 (en) Semiconductor device having a nitride barrier for preventing formation of structural defects
US6762459B2 (en) Method for fabricating MOS device with halo implanted region
JPH11145273A (en) Manufacture of semiconductor device
US5985737A (en) Method for forming an isolation region in an integrated circuit
JP3039978B2 (en) Method of forming an electric field isolation structure and a gate structure in an integrated MISFET device
JP3064994B2 (en) Semiconductor device and manufacturing method thereof
KR100246691B1 (en) Fabrication method of semiconductor device
US6110788A (en) Surface channel MOS transistors, methods for making the same, and semiconductor devices containing the same
US6344374B1 (en) Method of fabricating insulators for isolating electronic devices
US6309942B1 (en) STI punch-through defects and stress reduction by high temperature oxide reflow process
US5763316A (en) Substrate isolation process to minimize junction leakage
US7087508B2 (en) Method of improving short channel effect and gate oxide reliability by nitrogen plasma treatment before spacer deposition
US7135407B2 (en) Method of manufacturing a semiconductor device
JP2002057211A (en) Method for manufacturing semiconductor device having trench element isolation region
JP2001244324A (en) Method for manufacturing semiconductor device
JPH07201773A (en) Manufacture of semiconductor device
JP2000036535A (en) Trench isolation forming method

Legal Events

Date Code Title Description
STCB Information on status: application discontinuation

Free format text: EXPRESSLY ABANDONED -- DURING EXAMINATION