US20030128709A1 - Scalable, re-configurable crossbar switch architecture for multi-processor system interconnection networks - Google Patents
Scalable, re-configurable crossbar switch architecture for multi-processor system interconnection networks Download PDFInfo
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- US20030128709A1 US20030128709A1 US09/296,045 US29604599A US2003128709A1 US 20030128709 A1 US20030128709 A1 US 20030128709A1 US 29604599 A US29604599 A US 29604599A US 2003128709 A1 US2003128709 A1 US 2003128709A1
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q3/00—Selecting arrangements
- H04Q3/42—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
- H04Q3/54—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised
- H04Q3/545—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme
- H04Q3/54541—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme using multi-processor systems
- H04Q3/5455—Multi-processor, parallelism, distributed systems
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
- H04Q2213/1302—Relay switches
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
- H04Q2213/1304—Coordinate switches, crossbar, 4/2 with relays, coupling field
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
- H04Q2213/13296—Packet switching, X.25, frame relay
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
- H04Q2213/13322—Integrated circuits
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Abstract
Description
- The present application contains subject matter related to a concurrently filed U.S. Patent Application by Padmanabha I. Venkitakrishnan entitled “Backup Redundant Routing System Crossbar Switch Architecture for Multi-Processor System Interconnection Networks”. The related application is also assigned to Hewlett-Packard Company, is identified by docket number 10981858-1, and is hereby incorporated by reference.
- The present application also contains subject matter related to a concurrently filed U.S. Patent Application by Padmanabha I. Venkitakrishnan, Gopalakrishnan Janakiraman, Tsen-Gong Jim Hsu, and Rajendra Kumar entitled “Scalable System Control Unit for Distributed Shared Memory Multi-Processor Systems”. The related application is also assigned to Hewlett-Packard Company, is identified by docket number 10980275-1, and is hereby incorporated by reference.
- The present invention relates generally to multi-processor computer systems and more particularly to crossbar switch architecture.
- High performance, multi-processor systems with a large number of microprocessors are built by interconnecting a number of node structures, each node containing a small number of microprocessors. This necessitates an interconnection network that is efficient in carrying control information and data between the nodes of the multi-processor.
- In the past, crossbar switches, which route communications between the “nodes” of a network, included logic for determining a desired destination from message header, and for appropriately routing all of the parallel bits of a transmission; e.g., 64 bits in parallel for a 64 bit microprocessor. A configuration such as this presents inherent scalability problems, principally because its number of nodes or ports limits each crossbar switch. For example, a typical crossbar switch might service four nodes in parallel, and route 64 bits to one of the four nodes; if more nodes were desired, multiple crossbar switches would be cascaded to support the additional nodes. Such a configuration is not readily scalable either in terms of bandwidth; i.e., such a system could not readily be reconfigured to handle 128 bits in parallel to support higher-performance systems, or because the more cascaded structures, the greater the routing overhead and associated latency.
- Thus, a method or architecture has been long sought and long eluded those skilled in the art, which would be scalable and re-configurable while having low latency. The system would be packet switched and provide a high availability (HA) crossbar switch architecture.
- The present invention provides a new crossbar switch which is implemented by a plurality of parallel chips. Each chip is completely programmable to couple to every node in the system, e.g., from one node to about one thousand nodes (corresponding to present-day technology limits of about one thousand I/O pins) although conventional systems typically support no more than 32 nodes. The crossbar switch can be implemented to support only one node such that one chip can be used to route all 64 bits in parallel for 64 bit microprocessors or 128 bits in parallel for a 128 bit processor.
- The present invention provides a flexible structure that allows dynamic programming of its data routing, such that one commercial crossbar system can support many different network architectures. With dynamic scalability, if nodes are added to an existing system, then different programming may be used to reconfigure the crossbar switches.
- The present invention provides a multi-processor system interconnection network based on a scalable, re-configurable, low latency, packet switched and highly available crossbar switch architecture.
- The present invention further provides a scalable system by parallelizing the interconnection network into a number of identical crossbar switches. This enables implementation of the interconnection network function without pushing the limits of integrated circuit and system packaging technologies. At the same time, the invention provides a method to substantially increase the bandwidth of a multi-processor system.
- The present invention further provides a method to re-configure the ports of the crossbar switches so that a smaller number of crossbar switch circuits can provide the required bandwidth when the multi-processor system consists of a small number of node structures, thus reducing system hardware cost.
- The invention described also provides for a redundant interconnection network in parallel to the primary interconnection network, thus significantly enhancing the reliability and high-availability of the multi-processor system.
- The above and additional advantages of the present invention will become apparent to those skilled in the art from a reading of the following detailed description when taken in conjunction with the accompanying drawings.
- FIG. 1 (PRIOR ART) is a prior art Distributed Shared Memory (DSM) computer system;
- FIG. 2 is a functional block diagram of the interconnection network for a DSM computer system according to the present invention;
- FIG. 3 is an illustration of the interconnection network packet format according to the present invention;
- FIG. 4 is a micro-architectural diagram of the crossbar switch circuit according to the present invention; and
- FIG. 5 is a timing diagram of the crossbar switch.
- Referring now to FIG. 1, therein is shown a Distributed Shared Memory (DSM)
computer system 100. The DSMcomputer system 100 has a plurality ofnodes nodes crossbar switch 600. Thenodes crossbar switch 700. Thecrossbar switches communication switch 800. - In the DSM
computer system 100, thenodes respective memory units memory units coherence controllers - Further, in the DSM
computer system 100, each line of memory (typically a section of memory is tens of bytes in size) is assigned a “home node”, such as thenode 200, which maintains the sharing of that memory line and guarantees its coherence. The home node maintains a directory which identifies the nodes that possess a copy of that memory line. In thenodes coherence directories coherence controllers - The memory and
coherence controllers 220 are connected to a number of central processing units (CPUs), generally four or eight processors, such asprocessors coherence controllers 320 are shown connected to theprocessors coherence controllers 420 are shown connected toprocessors coherence controllers 520 are shown connected to theprocessors - Referring now to FIG. 2, therein is shown a functional block diagram of the interconnection network for a DSM
computer system 1000 according to the present invention. The DSMcomputer system 1000 has across bar switch 2000, which consists of a plurality of crossbar switch integrated circuits (XBS circuits) 2001 through 2016. A typical high-performance DSMcomputer system 1000 can potentially have 16 XBS circuits or more, whereas low and medium performance systems can conceivably have just 8 or even only 4 XBS circuits. The XBS circuits can all be packaged in the same integrated circuit chip or on separate integrated circuit chips. This arrangement meets the large bandwidth requirements of a high-performance DSMcomputer system 1000 in which the interconnection network is easily scalable. - Each of the
XBS circuits 2001 through 2016 has 16 ports which are respectively connected tonodes 3001 through 3016. Thenode 3009 is typical, and so each of the other nodes is somewhat similarly constructed and would have components which would be similarly numbered. In addition to the processors and memory, thenode 3009 also includes a system control unit (SCU) which includes the coherency controls and which is split into a system control unit address (SCUA)section 4009 and a system control unit data (SCUD) section 5009. The SCUD section 5009 is scalable in that additional SCUD sections may be added as required. In FIG. 2, fourSCUD sections 5009A through 5009D are shown. Each SCUD section, such asSCUD section 5009A, has four ports connected to the corresponding XBS circuits, such asXBS circuits 2001 through 2004 for theSCUD section 5009A. Similarly,SCUD section 5009B is connected to the XBS circuits 2005 through 2009. As would be evident to those skilled in the art, the four ports of subsequent SCUD sections would be respectively connected to subsequent ports of subsequent XBS circuits. This is represented by the phantom lines shown perpendicular to the arrows indicating output and input to the ports. - Since each port of the XBS circuit has the same functionality, the above arrangement not only allows the varying of the number of XBS circuits in the
interconnection network 1000, but allows bundling of several ports on an XBS circuit to derive ports with higher bandwidth. In other words, the architecture of the XBS circuit allows scaling in two dimensions, i.e., varying number of XBS circuits as well as varying the number of port on a single XBS circuit. This re-configurable and bundling feature of the ports of thecrossbar switch 2000 allows having a smaller number of XBS circuits to derive the required bandwidth when the multiprocessor system consists of a small number of nodes, thus reducing system hardware cost. - Further, building the
interconnection network 1000 with many of these parallelized XBS circuits as a plurality of integrated circuit chips helps in implementing these parts without pushing integrated circuit and part packaging technology limits. The scalable parallelized XBS circuits make packaging the interconnection network within the multiprocessor system cabinet very simple. - Referring now to FIG. 3, therein is shown an illustration of the interconnection network packet formats according to the present invention. The network packet (NP)6000 controls the control and data signal transversals through the
interconnection network 1000 between its source and destination nodes. Thenetwork packet 6000 is configured to providerouting information 6100, system control unit control packet (SCP)information 6200, and system control unit data packet (SDP)information 6300. - The
routing information 6100 provides the following information:destination 6110, source 6120, andoriginator 6130. - The
SCP information 6200 contains the following information:destination 6210,source 6220,originator 6230, thecommand 6240, theaddress 6250, and thelength 6260. - The
SDP information 6300 contains the following information:destination 6310,source 6320, theoriginator 6330, thedata 6340, and itslength 6350. - Referring now to FIG. 4, therein is shown a micro-architectural diagram of the
XBS circuit 2000 with 8ports port 2020 as typical, signals from the source node enter aninput buffer 2022 and then are input to the decode andsetup crossbar circuitry 2024. Thecircuitry 2024 is connected to a programmablecross-bar switch core 2026 which provides thenetwork packet 6000 tooutput drivers 2028 and then through theport 2050 to the destination node. - Referring now to FIG. 5, therein is shown the low latency transfer of the present invention in which the network packet from the source node is delivered to the destination node in four clock cycles.
- During the first clock cycle from T1 to T2, there is a latch of the
network packet 6000 into theinput buffer 2022. During the second clock cycle from T2 to T3, thenetwork packet 6000 is decoded, and thecrossbar switch core 2026 is setup. - During the third clock cycle from T3 to T4, the
network packet 6000 is propagated through the latch and switch. - During the fourth clock cycle from T4 to T5, the
network packet 6000 is driven out through thedestination port 2050. - In operation, the control and data signal traversals through the
interconnection network 1000 between its source and destination nodes, which could be fromnode 3001 tonode 3008, is accomplished by moving thenetwork packet 6000. Thedestination 6110 information and thesource 6130 information contain the information on the nodes involved for routing purposes. TheSCP 6200 information and theSDP 6300 information are generated and used by the source and destination nodes by providing control information and data. - To meet the large bandwidth requirements of high performance DSM computer systems, the
DSM computer system 1000 can have 16 XBS circuits, 2001 through 2016, which can all be integrated into the same integrated circuit or be separate circuits in order to simplify the making of the integrated circuits or packaging the integrated circuits. - For an
XBS circuit 2001 having 16 ports operating at 400 MHz the bandwidth could be 1.6 GB/s per part. At the same time, only 608 signal pins would be required. From the above, it will be evident that it is possible in low and medium performance systems to have a smaller number of XBS circuits when there are a smaller number of node structures and still be able to retain the required bandwidth. This would substantially reduce system hardware cost, while at the same time providing a great deal of flexibility. - In accordance with the present invention, a new crossbar switch is implemented by a plurality of parallel chips. Each chip is completely programmable to couple to every node in the system, e.g., from one node to about one thousand nodes (corresponding to present-day technology limits of about one thousand I/O pins) although conventional systems typically support no more than 32 nodes. For example, if each chip is configured to route up to 64 bits, 32 chips could be provided as part of a crossbar system. If the system as implemented only supported one node, then one chip could be used to route all 64 bits in parallel. On the other hand, if there were 32 nodes, each chip could be connected to all 32 nodes and could be configured by software to each route two bits to attached nodes. Each particular node determines whether a message is intended for it. Thus, the structure provided by the invention reduces latency and promotes scalability. As can be seen from this description, the present invention is a flexible structure that allows dynamic programming of its data routing, such that one commercial crossbar system can support many different network architectures. An advantage of this system is dynamic scalability; if one adds nodes to an existing system, then a different driver may be used to reconfigure the crossbar switches.
- While the invention has been described in conjunction with a specific best mode, it is to be understood that many alternatives, modifications, and variations will be apparent to those skilled in the art in light of the aforegoing description. Accordingly, it is intended to embrace all such alternatives, modifications, and variations which fall within the spirit and scope of the included claims. All matters set forth herein or shown in the accompanying drawings are to be interpreted in an illustrative and non-limiting sense.
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US09/296,045 US6597692B1 (en) | 1999-04-21 | 1999-04-21 | Scalable, re-configurable crossbar switch architecture for multi-processor system interconnection networks |
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US09/296,045 US6597692B1 (en) | 1999-04-21 | 1999-04-21 | Scalable, re-configurable crossbar switch architecture for multi-processor system interconnection networks |
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Cited By (3)
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US20050083921A1 (en) * | 2000-10-31 | 2005-04-21 | Chiaro Networks Ltd. | Router switch fabric protection using forward error correction |
US20150208076A1 (en) * | 2014-01-21 | 2015-07-23 | Lsi Corporation | Multi-core architecture for low latency video decoder |
US20170060786A1 (en) * | 2015-08-28 | 2017-03-02 | Freescale Semiconductor, Inc. | Multiple request notification network for global ordering in a coherent mesh interconnect |
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US20060174052A1 (en) * | 2005-02-02 | 2006-08-03 | Nobukazu Kondo | Integrated circuit and information processing device |
KR100546546B1 (en) * | 1999-02-23 | 2006-01-26 | 가부시키가이샤 히타치세이사쿠쇼 | Integrated circuit and information processing device |
US7343622B1 (en) * | 2000-04-27 | 2008-03-11 | Raytheon Company | Multi-level secure multi-processor computer architecture |
US6950893B2 (en) * | 2001-03-22 | 2005-09-27 | I-Bus Corporation | Hybrid switching architecture |
EP1280374A1 (en) * | 2001-07-27 | 2003-01-29 | Alcatel | Network element with redundant switching matrix |
US7376811B2 (en) * | 2001-11-06 | 2008-05-20 | Netxen, Inc. | Method and apparatus for performing computations and operations on data using data steering |
US6820167B2 (en) * | 2002-05-16 | 2004-11-16 | Hewlett-Packard Development Company, L.P. | Configurable crossbar and related methods |
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US20150208076A1 (en) * | 2014-01-21 | 2015-07-23 | Lsi Corporation | Multi-core architecture for low latency video decoder |
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US20170060786A1 (en) * | 2015-08-28 | 2017-03-02 | Freescale Semiconductor, Inc. | Multiple request notification network for global ordering in a coherent mesh interconnect |
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