US20030147199A1 - Cylinder-type capacitor for a semiconductor device - Google Patents
Cylinder-type capacitor for a semiconductor device Download PDFInfo
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- US20030147199A1 US20030147199A1 US10/375,385 US37538503A US2003147199A1 US 20030147199 A1 US20030147199 A1 US 20030147199A1 US 37538503 A US37538503 A US 37538503A US 2003147199 A1 US2003147199 A1 US 2003147199A1
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- layer
- cylinder
- insulating layer
- etch stop
- pattern
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/84—Electrodes with an enlarged surface, e.g. formed by texturisation being a rough surface, e.g. using hemispherical grains
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
- H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
- H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
Definitions
- the present invention relates to a method for fabricating a capacitor for a semiconductor device, and more particularly, to a method for fabricating a cylinder-type capacitor for a semiconductor device.
- DRAM dynamic random access memory
- a number of techniques have been suggested for accomplishing capacitor integration. These include forming the capacitor dielectric layer into a thin film, using a material having a high dielectric constant as the dielectric layer, and increasing the effective area of a capacitor electrode by making a cylinder-type electrode or a fin-type electrode or by growing hemispherical grains (HSGs) on the surface of the electrode.
- HSGs hemispherical grains
- FIGS. 1 through 5 a conventional method for fabricating a cylinder-type capacitor for a semiconductor device will be described.
- Like reference numerals refer to like elements throughout the drawings.
- a first insulating layer 120 is formed on a semiconductor substrate 100 on which a conductive region 110 is formed.
- a first photoresist pattern 122 having a first opening A at the position corresponding to the conductive region 110 is formed on the first insulating layer 120 .
- the exposed portion of the first insulating layer 120 is etched, using the first photoresist pattern 122 as a mask, and thereby forming a first insulating layer pattern 120 a having a contact hole 125 for exposing the conductive region 110 .
- a first conductive layer 130 for filling the contact hole 125 is formed.
- the upper surface of a resultant structure shown in FIG. 2 is planarized to expose the upper surface of the first insulating layer pattern 120 a , and thereby forming a contact plug 130 a .
- a etch stop layer 140 and a second insulating layer 150 are formed in sequence on the surface of the top of the first insulating layer pattern 120 a and the contact plug 130 a .
- a second photoresist pattern 152 having a second opening B at a position above the contact plug 130 a is formed on the second insulating layer 150 .
- the second insulating layer 150 and the etch stop layer 140 are etched by using the second photoresist pattern 152 as a mask, and thereby forming a second insulating layer pattern 150 a and an etch stop layer pattern 140 a having a storage node hole 155 for exposing the surface of the top of the contact plug 130 a .
- a second conductive layer 160 is formed at a thickness such that the storage node hole 155 is not completely filled.
- the top of the second conductive layer 160 and the second insulating layer pattern 150 a are removed to form a separated storage node 160 a .
- a dielectric layer 180 and an upper electrode 190 are formed on the storage node 160 a.
- the photolithography process is performed twice, as described with reference to FIGS. 1 and 3.
- the process for forming a conductive layer is performed twice.
- the photolithography process is limited in that it requires the use of expensive exposure equipment having high resolution capabilities, and is a process that influences productivity due to high production cost. Also, since the polysilicon layer is formed by diffusion in the process for forming the conductive layer, the process takes a relatively long time to complete.
- a method for fabricating a cylinder-type capacitor for a semiconductor device includes the steps of forming in sequence a first insulating layer, a first etch stop layer, a second insulating layer, and a second etch stop layer on a semiconductor substrate including a conductive region, forming a second etch stop layer pattern, a second insulating layer pattern, and a first etch stop layer pattern by etching a part of the second etch stop layer, the second insulating layer, and the first etch stop layer so that a storage node hole for exposing the surface of a part of the first insulating layer may be formed, forming a spacer on an inner wall of the storage node hole, forming a first insulating layer pattern by etching the first insulating layer exposed using the second etch stop layer pattern and the spacer as a mask so that a node contact hole for exposing the conductive region may be formed, removing the second etch stop
- the conductive region may be an active region on the surface of the semiconductor substrate, or a contact pad on the top of the semiconductor substrate.
- the method further includes the step of forming a contact pad self-aligned by two neighboring gate electrodes formed on the semiconductor substrate, and the conductive region may be the contact pad.
- the step of forming a contact pad includes the steps of forming an interdielectric layer which fills a space between the two gate electrodes, forming a contact hole for exposing the surface of the semiconductor substrate between the two neighboring gate electrodes by patterning the interdielectric layer, and filling a conductive material in the contact hole.
- the gate electrodes may be formed of the structure of a polycide in which a silicide layer is formed on a polysilicon layer.
- the interdielectric layer may be formed of a boron phosphorus silicate glass (BPSG) layer, a spin on glass (SOG) layer, an undoped silicate glass (USG) layer, a silicon oxide layer formed by using a high density plasma-chemical vapor deposition (HDP-CVD) method, or a tetraethylorthosilicate (TEOS) layer formed by using a plasma enhanced-CVD (PE-CVD) method.
- BPSG boron phosphorus silicate glass
- SOG spin on glass
- USG undoped silicate glass
- silicon oxide layer formed by using a high density plasma-chemical vapor deposition (HDP-CVD) method
- TEOS tetraethylorthosilicate
- PE-CVD plasma enhanced-CVD
- the method further includes the steps of forming a silicon oxide layer on the second etch stop layer, forming a silicon oxide layer pattern by etching a part of the silicon oxide layer so that the storage node hole may be formed, and removing the silicon oxide layer pattern during the formation of the node contact hole.
- the silicon oxide layer is preferably a silicon oxide layer formed by using a PE-CVD method, or a high temperature oxide layer.
- the first insulating layer may be a silicon oxide layer formed by a HDP-CVD method
- the second insulating layer may be a TEOS layer formed by a PE-CVD method
- the first etch stop layer and the second etch stop layer may be silicon nitride layers, respectively, formed by a low pressure-CVD (LP-CVD) method.
- LP-CVD low pressure-CVD
- the thickness of the first insulating layer may be between 8000 and 12000 ⁇ , and the thickness of the second insulating layer may be between 5000 and 20000 ⁇ , and the thickness of the first etch stop layer and the second etch stop layer may be between 300 and 500 ⁇ , respectively.
- the step of forming a spacer includes the steps of forming a third insulating layer to have a thickness with which the storage node hole may not be completely filled, and etching-back the third insulating layer.
- the third insulating layer may be a silicon nitride layer or a silicon oxynitride layer formed by a PE-CVD method.
- the step of removing the second etch stop layer pattern and the spacer is performed by removing the spacer after the removal of the second etch stop layer pattern, or by simultaneously removing the second etch stop layer pattern and the spacer.
- the step of removing the second etch stop layer pattern and the spacer is performed by a wet etching method using a mixed solution of hydrogen peroxide, water (H 2 O), and hydrofluoric acid (HF).
- the step of forming a lower electrode includes the steps of forming a conductive layer having the thickness with which the storage node hole and the node contact hole may not be completely filled, on the entire surface of a resultant on which the node contact hole is formed, and forming a plurality of separated storage nodes by removing the top of the conductive layer and the second insulating layer pattern.
- the conductive layer may be formed of a polysilicon layer by diffusion.
- the step of forming a plurality of plurality storage nodes includes the steps of forming an oxide layer which fills the storage node hole and the node contact hole, on the conductive layer, removing a part of the oxide layer and the top of the conductive layer so that the second insulating layer pattern may be exposed, and removing the oxide layer which fills the storage node hole and the node contact hole, and the second insulating layer pattern by a wet-etching method.
- the oxide layer is formed of a USG layer, a BPSG layer, a double layer of a silicon oxide layer and a USG layer, or a double layer of a silicon oxide layer and a BPSG layer.
- the step of forming a lower electrode may further includes the step of forming hemispherical grains (HSGs) on the surface of the storage node.
- HSGs hemispherical grains
- the dielectric layer may be formed of a Al 2 O 3 layer, a Ta 2 O 5 layer, a SrTiO 3 (STO) layer, (Ba, Sr) TiO 3 (BST) layer, a PbTiO 3 layer, Pb(Zr, Ti)O 3 (PZT) layer, a SrBi 2 Ta 2 O 9 (SBT) layer, (Pb,La)(Zr,Ti)O 3 layer, or BaTiO 3 (BTO) layer.
- the dielectric layer may be formed of a triple layer of a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer, or a double layer of a silicon nitride layer and a silicon oxide layer.
- the upper electrode may be formed by using a polysilicon layer by diffusion.
- the present invention is further directed to a cylinder-type capacitor of a semiconductor device.
- a lower electrode is formed of a conductive layer which directly contacts a conductive region on a semiconductor substrate.
- the lower electrode comprises a first cylinder in contact with the conductive region and a second cylinder on and in contact with the first cylinder, the second cylinder being larger in width than the first cylinder.
- a dielectric layer is on the lower electrode.
- An upper electrode is on the dielectric layer. The upper electrode extends into the first and second cylinders.
- the conductive region comprises an active region on the surface of the semiconductor substrate or a contact pad above the semiconductor substrate.
- the capacitor may further comprise a contact pad that is self-aligned by two neighboring gate electrodes formed on the semiconductor substrate.
- the gate electrodes may comprise a polycide structure in which a silicide layer is formed on a polysilicon layer.
- the lower conductive layer may comprise a polysilicon layer.
- the lower electrode may include hemispherical grains (HSGs) on the surface thereof.
- the dielectric layer is, for example, formed of one of a Al 2 O 3 layer, a Ta 2 O 5 layer, a SrTiO 3 (STO) layer, a (Ba, Sr)TiO 3 (BST) layer, a PbTiO 3 layer, Pb(Zr, Ti)O 3 (PZT) layer, a SrBi 2 Ta 2 O 9 (SBT) layer, a (Pb,La)(Zr,Ti)O 3 layer, and a BaTiO 3 (BTO) layer.
- STO SrTiO 3
- BST SrTiO 3
- PbTiO 3 layer Pb(Zr, Ti)O 3
- SBT SrBi 2 Ta 2 O 9
- BaTiO 3 (BTO) layer BaTiO 3
- the dielectric layer may optionally be formed of one of a triple layer comprising a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer, and a double layer comprising a silicon nitride layer and a silicon oxide layer.
- the upper electrode may, for example, comprise a polysilicon layer.
- a photolithography process and a process for forming a conductive layer are each performed once, respectively.
- the overall fabrication process is simplified, and productivity is improved and production cost reduced.
- FIGS. 1 through 5 are sectional views illustrating a conventional method for fabricating a cylinder-type capacitor for a semiconductor device
- FIGS. 6 through 14 are sectional views illustrating a method for fabricating a cylinder-type capacitor for a semiconductor device according to a first embodiment of the present invention
- FIG. 15 is a sectional view illustrating a method for fabricating a cylinder-type capacitor for a semiconductor device according to a second embodiment of the present invention.
- FIGS. 16 through 18 are sectional views illustrating a method for fabricating a cylinder-type capacitor for a semiconductor device according to a third embodiment of the present invention.
- FIG. 19 is a sectional view illustrating a method for fabricating a cylinder-type capacitor for a semiconductor device according to a fourth embodiment of the present invention.
- FIGS. 20 through 24 are sectional views illustrating a method for fabricating a cylinder-type capacitor for a semiconductor device according to a fifth embodiment of the present invention.
- FIGS. 6 through 14 are sectional views illustrating a method for fabricating a cylinder-type capacitor of a semiconductor device according to a first embodiment of the present invention.
- a gate insulating layer 201 is interposed between a semiconductor substrate 200 and a gate electrode 205 .
- a capping layer 203 is formed on the top of the gate electrode 205 , and a spacer for gate 204 is formed on the sidewall of the gate electrode 205 .
- Impurity ions are implanted onto the semiconductor substrate 200 on which the gate electrode 205 is formed, and active regions 210 and 210 ′ are formed on the surface of the semiconductor substrate 200 .
- a first insulating layer 220 , a first etch stop layer 230 , a second insulating layer 240 , and a second etch stop layer 250 are formed in sequence on the resultant structure on which the active regions 210 and 210 ′ are formed.
- the first insulating layer 220 and the second insulating layer 240 may be formed of the same layer, but, in this case, the second insulating layer 240 is formed of a material having a higher etching selectivity than that of the first insulating layer 220 , so as to be easily removed during separation of storage nodes.
- the first insulating layer 220 may be formed of a silicon oxide layer by a HDP-CVD method
- the second insulating layer 240 may be formed of a TEOS layer by a PE-CVD method.
- the thickness of the first insulating layer 220 is decided by considering a lay-out of a device to be formed and, for example, may be between 8000 and 12000 ⁇ .
- the thickness of the second insulating layer 240 may be equal to or greater than the height of the storage node, considering the height of the storage node to be formed, or between 5000 and 20000 ⁇ .
- the first etch stop layer 230 and the second etch stop layer 250 are formed of silicon nitride layers, respectively, by a LP-CVD method.
- Each thickness of the first etch stop layer 230 and the second etch stop layer 250 may be a thickness with which etching of the second insulating layer 240 and the first insulating layer 220 can be prevented.
- the thickness of the first etch stop layer 230 and the second etch stop layer 250 can be between 300 and 500 ⁇ , respectively.
- a photoresist pattern 252 having an opening of a width W 21 at the position corresponding to one of the active regions 210 is formed on the second etch stop layer 250 .
- the second etch stop layer 250 , the second insulating layer 240 , and the first etch stop layer 230 are etched by using the photoresist pattern 252 as a mask, and thereby, a second etch stop layer pattern 250 a , a second insulating layer pattern 240 a , and a first etch stop layer pattern 230 a are formed so that a storage node hole 255 exposing the surface of a portion of the first insulating layer 220 is formed.
- a third insulating layer 260 is formed at a thickness such that the storage node hole 255 is not completely filled.
- the third insulating layer 260 is formed of a silicon nitride layer or a silicon oxynitride layer by a PE-CVD method.
- the thickness of the third insulating layer 260 is decided by considering the width of a node contact hole to be formed in the first insulating layer 220 .
- a spacer 260 a is formed on an inner wall of the storage node hole 255 by etching-back the third insulating layer 260 .
- the surface of the top of the first insulating layer 220 is exposed to the width W 22 (W 22 ⁇ W 21 ).
- the exposed first insulating layer 220 is etched by using the second etch stop layer pattern 250 a and the spacer 260 a as a mask, and a first insulating layer pattern 220 a is formed, having a node contact hole 265 in which a surface of a portion of the active region 210 is exposed.
- the second etch stop layer pattern 250 a and the spacer 260 a are removed.
- the second etch stop layer pattern 250 a may be removed during the process described with reference to FIGS. 9 and 10. If a portion, or all, of the second etch stop layer pattern 250 a remains, even following the process described in FIGS. 9 and 10, then the second etch stop layer pattern 250 a is removed with the spacer 260 a . That is, an additional removal step is performed, for removing the second etch stop layer pattern 250 a and the spacer 260 a .
- This removal step can be performed by removing the spacer 260 a after removal of the second etch stop layer pattern 250 a , or by simultaneously removing the second etch stop layer pattern 250 a and the spacer 260 a .
- An etching solution or etching gas having a high etching selectivity with respect to the spacer 260 a , as compared to the first insulating layer pattern 220 a , the second insulating layer pattern 240 a , and the semiconductor substrate 200 is preferably used in the step of removing the second etch stop layer pattern 250 a and the spacer 260 a .
- the step of removing the second etch stop layer pattern 250 a and the spacer 260 a may be performed by a wet etching method using an etching solution containing hydrogen peroxide, water, and hydrofluoric acid.
- etching solution or etching gas A high degree of etching selectivity of the etching solution or etching gas is preferred for avoiding deterioration of the second insulator layer pattern 240 , and thereby maintaining adequate height in the storage node, and avoiding a reduction in capacitance.
- a conductive layer 270 having appropriate thickness so as to avoid completely filling the storage node hole 255 and the node contact hole 265 is formed on the entire surface of a resultant structure shown in FIG. 11.
- the conductive layer 270 is formed of a polysilicon layer by diffusion.
- An oxide layer 280 which fills the storage node hole 255 and the node contact hole 265 is formed on the conductive layer 270 .
- the oxide layer 280 is preferably formed of a USG layer, a BPSG layer, a double layer of a silicon oxide layer and a USG layer, or a double layer of a silicon oxide layer and a BPSG layer.
- the active region 210 can be prevented from being etched.
- a part of the oxide layer 280 and the top of the conductive layer 270 are removed by etching-back or, chemical mechanical polishing (CMP), the upper surface of the resultant structure shown in FIG. 12 so that the second insulating layer pattern 240 a may be exposed.
- a separated storage node 270 a is formed by removing the oxide layer 280 filling the storage node hole 255 and the node contact hole 265 , and removing the second insulating layer pattern 240 a , by wet etching.
- the storage node 270 a forms a lower electrode of a cylinder-type capacitor.
- a dielectric layer 280 and an upper electrode 290 are formed on the storage node 270 a .
- the dielectric layer 280 is, for example, formed of a Al 2 O 3 layer, a Ta 2 O 5 layer, a STO layer, a BST layer, a PbTiO 3 layer, a PZT layer, a SBT layer, a (Pb,La)(Zr,Ti)O 3 layer, or a BTO layer.
- the dielectric layer 280 may be formed of a triple layer of a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer, or a double layer of a silicon nitride layer and a silicon oxide layer.
- the upper layer 290 is preferably formed of a polysilicon layer by diffusion.
- FIG. 15 is a sectional view illustrating the method for fabricating a cylinder-type capacitor of a semiconductor device according to a second embodiment of the present invention.
- a gate insulating layer 301 is interposed between a semiconductor substrate 300 and a gate electrode 305 .
- a capping layer 303 is formed on the top of the gate electrode 305
- a spacer for gate 304 is formed on the sidewall of the gate electrode 305 .
- Active regions 310 and 310 ′ are formed on the surface of the semiconductor substrate 300 on which the gate electrode 305 is formed.
- a first insulating layer pattern 320 a , and a first etch stop layer pattern 330 a are formed on the resultant structure on which the active regions 310 and 310 ′ are formed.
- a storage node interfacing with the first etch stop layer pattern 330 a , the first insulating layer pattern 320 a , and the active region 310 is formed.
- HSGs are formed on the surface of the storage node, and thereby completing a lower electrode 370 b .
- a dielectric layer 380 and an upper electrode 390 are formed on the lower electrode 370 b .
- Other processes beyond the process for forming HSGs are the same as those in the first embodiment, so a description thereof will be omitted.
- FIGS. 16 through 18 are sectional views illustrating a method for fabricating a cylinder-type capacitor of a semiconductor device according to a third embodiment of the present invention.
- a plurality of gate electrodes 405 are formed on a semiconductor substrate 400 .
- a gate insulating layer 401 is interposed under the gate electrodes 405 .
- a capping layer 403 is formed on the top of the gate electrodes 405 , and a spacer for gate 404 is formed on sidewalls of the gate electrodes 405 .
- the gate electrodes 405 may be formed of the structures of a polycide in which polysilicon layers 405 a and silicide layers 405 b , for example, tungsten silicide layers, are formed in sequence.
- the interdielectric layer 407 which fills a space between the plurality of gate electrodes 405 is formed.
- the interdielectric layer 407 may be formed of a BPSG layer, a SOG layer, a USG layer, a silicon oxide layer formed by using a HDP-CVD method, or a TEOS layer formed by using a PE-CVD method.
- a photoresist pattern (not shown) is formed on the interdielectric layer 407 , and the interdielectric layer 407 is patterned by using the photoresist pattern as a mask.
- an interdielectric layer pattern 407 a having a contact hole H for exposing the surface of the semiconductor substrate 400 between the two neighboring gate electrodes 405 is formed.
- a contact pad 410 is formed by filling a conductive material in the contact hole H.
- a first insulating layer pattern 420 a and a first etch stop layer pattern 430 a are formed on the resultant structure on which the contact pad 410 is formed.
- a storage node 470 a interfacing with the first etch stop layer pattern 430 a , the first insulating layer pattern 420 a , and the contact pad 410 is formed.
- a dielectric layer 480 and an upper electrode 490 are formed on the storage node 470 a .
- Other processes are the same as those in the first embodiment, so a description thereof will be omitted.
- FIG. 19 is a sectional view illustrating the method for fabricating a cylinder-type capacitor of a semiconductor device according to a fourth embodiment of the present invention.
- a gate insulating layer 501 is interposed between a semiconductor substrate 500 and a gate electrode 505 .
- a capping layer 503 is formed on the top of the gate electrode 505
- a spacer for gate 504 is formed on the sidewall of the gate electrode 505 .
- the gate electrodes 505 are formed of a polysilicon layer 505 a and a silicide layer 505 b , in sequence, for example, of the structure of a polycide in which a tungsten silicide layer is formed.
- a first insulating layer pattern 507 a and a contact pad 510 are formed on the resultant structure on which the gate electrodes 505 are formed.
- a first insulating layer pattern 520 a and a first etch stop layer pattern 530 a are formed on the resultant structure on which the contact pad 510 is formed.
- a storage node interfacing with the first etch stop layer pattern 530 a , the first insulating layer pattern 520 a , and the contact pad 510 is formed.
- HSGs are formed on the surface of the storage node, and thereby completing a lower electrode 570 b .
- a dielectric layer 580 and an upper electrode 590 are formed on the lower electrode 570 b . Processes beyond the formation of HSGs are the same as those in the third embodiment, so a description thereof will be omitted.
- FIGS. 20 through 24 are sectional views illustrating a method for fabricating a cylinder-type capacitor of a semiconductor device according to a fifth embodiment of the present invention.
- a gate insulating layer 601 is interposed between a semiconductor substrate 600 and a gate electrode 605 .
- a capping layer 603 is formed on the top of the gate electrode 605
- a spacer for gate 604 is formed on the sidewall of the gate electrode 605 .
- Active regions 610 and 610 ′ are formed on the surface of the semiconductor substrate 600 on which the gate electrode 605 is formed.
- a first insulating layer 620 , a first etch stop layer 630 , a second insulating layer 640 , and a second etch stop layer 650 are formed in sequence on the resulting structure on which the active regions 610 and 610 ′ are formed.
- a silicon oxide layer 651 is formed on the second etch stop layer 650 .
- the silicon oxide layer 651 may comprise a silicon oxide layer formed by using a PE-CVD method, or a high temperature oxide layer.
- a photoresist pattern 652 having an opening of width W 31 is formed at a position corresponding to active region 610 on the silicon oxide layer 651 .
- the silicon oxide layer 651 , the second etch stop layer 650 , the second insulating layer 640 , and the first etch stop layer 630 are etched by using the photoresist pattern 652 as a mask, and thereby, a silicon oxide layer pattern 651 a , a second etch stop layer pattern 650 a , a second insulating layer pattern 640 a , and a first etch stop layer pattern 630 a having a storage node hole 655 for exposing the surface of a part of the first insulating layer 620 are formed.
- a third insulating layer 660 having a suitable thickness such that the storage node hole 655 is not completely filled is formed.
- the third insulating layer 660 is preferably formed of a silicon nitride layer or a silicon oxynitride layer by a PE-CVD method.
- a spacer 660 a is formed on an inner wall of the storage node hole 655 by etching-back the third insulating layer 660 .
- the first insulating layer 620 is exposed across width W 32 .
- a process for treating a residue having no selectivity is performed.
- the silicon oxide layer pattern 651 a protects the second etch stop layer pattern 650 a .
- the second etch stop layer pattern 650 a is removed, the second insulating layer pattern 640 a is etched in the subsequent process for forming a node contact hole, and the height of the storage node is reduced. This causes the capacitance of the resulting capacitor to be reduced.
- the silicon oxide layer pattern 651 a prevents this problem.
- the silicon oxide layer pattern 651 a can optionally be removed during the process for treating a residue, or alternatively remain on the structure.
- the exposed first insulating layer 620 is etched by using the second etch stop layer pattern 650 a and the spacer 660 a as a mask, and a first insulating layer pattern 620 a is formed, having a node contact hole 665 in which the surface of a part of the active region 610 is exposed.
- the silicon oxide layer pattern 651 a remaining after the process for treating a residue, and the first insulating layer 620 are the same material layers, so the silicon oxide layer pattern 651 a is completely removed during this step. After that, processes described with reference to FIGS. 11 through 14, or processes for obtaining a resultant of FIG. 15 will be performed.
- a storage node hole is formed under a single photolithography process, and a single process for forming a conductive layer is performed following formation of a node contact hole using a spacer.
- This is in contrast with the conventional approach illustrated above, which requires dual photolithography processes and dual processes for forming a conductive layer.
- the overall fabrication process is simplified, and thereby productivity is improved and production cost reduced. Since a contact plug of a cylinder-type capacitor according to the prior art can be used as a lower electrode of a capacitor, the effective area of the capacitor electrode increases, thereby improving the capacitance of the capacitor.
Abstract
A cylinder-type capacitor of a semiconductor device includes a lower electrode that is formed of a conductive layer which directly contacts a conductive region on a semiconductor substrate. The lower electrode comprises a first cylinder in contact with the conductive region and a second cylinder on and in contact with the first cylinder, the second cylinder being larger in width than the first cylinder. A dielectric layer is on the lower electrode. An upper electrode is on the dielectric layer. The upper electrode extends into the first and second cylinders. According to the present invention, a semiconductor cylinder-type capacitor is provided at a relatively low production cost using simplified fabrication processes.
Description
- This application is a divisional application of U.S. Ser. No. 09/886,066, filed Jun. 21, 2001, the content of which is incorporated herein by reference.
- 1. Field of the Invention
- The present invention relates to a method for fabricating a capacitor for a semiconductor device, and more particularly, to a method for fabricating a cylinder-type capacitor for a semiconductor device.
- 2. Description of the Related Art
- The performance characteristics of a memory cell such as a dynamic random access memory (DRAM) among semiconductor devices share an direct connection with the capacitance of the memory cell capacitor. For example, as the capacitance of the cell capacitor increases, the low voltage characteristics and soft error characteristics of the memory cell are improved.
- As semiconductor devices continue to become more highly-integrated, the available area of a unit cell in which a capacitor is formed decreases. Thus, methods for increasing the capacitance of a capacitor within the limited area are necessary.
- A number of techniques have been suggested for accomplishing capacitor integration. These include forming the capacitor dielectric layer into a thin film, using a material having a high dielectric constant as the dielectric layer, and increasing the effective area of a capacitor electrode by making a cylinder-type electrode or a fin-type electrode or by growing hemispherical grains (HSGs) on the surface of the electrode.
- Hereinafter, referring to FIGS. 1 through 5, a conventional method for fabricating a cylinder-type capacitor for a semiconductor device will be described. Like reference numerals refer to like elements throughout the drawings.
- Referring to FIG. 1, a first
insulating layer 120 is formed on asemiconductor substrate 100 on which aconductive region 110 is formed. Afirst photoresist pattern 122 having a first opening A at the position corresponding to theconductive region 110 is formed on the firstinsulating layer 120. - Referring to FIG. 2, the exposed portion of the first
insulating layer 120 is etched, using the firstphotoresist pattern 122 as a mask, and thereby forming a firstinsulating layer pattern 120 a having acontact hole 125 for exposing theconductive region 110. After the firstphotoresist pattern 122 is removed, a firstconductive layer 130 for filling thecontact hole 125 is formed. - Referring to FIG. 3, the upper surface of a resultant structure shown in FIG. 2 is planarized to expose the upper surface of the first
insulating layer pattern 120 a, and thereby forming acontact plug 130 a. Aetch stop layer 140 and a secondinsulating layer 150 are formed in sequence on the surface of the top of the firstinsulating layer pattern 120 a and thecontact plug 130 a. Asecond photoresist pattern 152 having a second opening B at a position above thecontact plug 130 a is formed on the secondinsulating layer 150. - Referring to FIG. 4, the second
insulating layer 150 and theetch stop layer 140 are etched by using the secondphotoresist pattern 152 as a mask, and thereby forming a secondinsulating layer pattern 150 a and an etchstop layer pattern 140 a having astorage node hole 155 for exposing the surface of the top of thecontact plug 130 a. After the secondphotoresist pattern 152 is removed, a secondconductive layer 160 is formed at a thickness such that thestorage node hole 155 is not completely filled. - Referring to FIG. 5, the top of the second
conductive layer 160 and the secondinsulating layer pattern 150 a are removed to form aseparated storage node 160 a. Adielectric layer 180 and anupper electrode 190 are formed on thestorage node 160 a. - According to the conventional method described above, in order to form a contact plug and a storage node, the photolithography process is performed twice, as described with reference to FIGS. 1 and 3. As described with reference to FIGS. 2 and 4, the process for forming a conductive layer is performed twice. The photolithography process is limited in that it requires the use of expensive exposure equipment having high resolution capabilities, and is a process that influences productivity due to high production cost. Also, since the polysilicon layer is formed by diffusion in the process for forming the conductive layer, the process takes a relatively long time to complete.
- Thus, in the above conventional method for fabricating a cylinder-type capacitor of a semiconductor device, the number of processes is large, and the production cost is high.
- To address the above limitations, it is an object of the present invention to provide a method for fabricating a cylinder-type capacitor for a semiconductor device, while reducing production cost and simplifying the process.
- Accordingly, to achieve the above object, there is provided a method for fabricating a cylinder-type capacitor for a semiconductor device. The method includes the steps of forming in sequence a first insulating layer, a first etch stop layer, a second insulating layer, and a second etch stop layer on a semiconductor substrate including a conductive region, forming a second etch stop layer pattern, a second insulating layer pattern, and a first etch stop layer pattern by etching a part of the second etch stop layer, the second insulating layer, and the first etch stop layer so that a storage node hole for exposing the surface of a part of the first insulating layer may be formed, forming a spacer on an inner wall of the storage node hole, forming a first insulating layer pattern by etching the first insulating layer exposed using the second etch stop layer pattern and the spacer as a mask so that a node contact hole for exposing the conductive region may be formed, removing the second etch stop layer pattern and the spacer, forming a lower electrode on exposed surfaces of the storage node hole and the node contact hole, and forming a dielectric layer and an upper electrode on the lower electrode.
- The conductive region may be an active region on the surface of the semiconductor substrate, or a contact pad on the top of the semiconductor substrate.
- The method further includes the step of forming a contact pad self-aligned by two neighboring gate electrodes formed on the semiconductor substrate, and the conductive region may be the contact pad. Here, the step of forming a contact pad includes the steps of forming an interdielectric layer which fills a space between the two gate electrodes, forming a contact hole for exposing the surface of the semiconductor substrate between the two neighboring gate electrodes by patterning the interdielectric layer, and filling a conductive material in the contact hole. The gate electrodes may be formed of the structure of a polycide in which a silicide layer is formed on a polysilicon layer. The interdielectric layer may be formed of a boron phosphorus silicate glass (BPSG) layer, a spin on glass (SOG) layer, an undoped silicate glass (USG) layer, a silicon oxide layer formed by using a high density plasma-chemical vapor deposition (HDP-CVD) method, or a tetraethylorthosilicate (TEOS) layer formed by using a plasma enhanced-CVD (PE-CVD) method.
- The method further includes the steps of forming a silicon oxide layer on the second etch stop layer, forming a silicon oxide layer pattern by etching a part of the silicon oxide layer so that the storage node hole may be formed, and removing the silicon oxide layer pattern during the formation of the node contact hole. The silicon oxide layer is preferably a silicon oxide layer formed by using a PE-CVD method, or a high temperature oxide layer.
- The first insulating layer may be a silicon oxide layer formed by a HDP-CVD method, and the second insulating layer may be a TEOS layer formed by a PE-CVD method. The first etch stop layer and the second etch stop layer may be silicon nitride layers, respectively, formed by a low pressure-CVD (LP-CVD) method.
- The thickness of the first insulating layer may be between 8000 and 12000 Å, and the thickness of the second insulating layer may be between 5000 and 20000 Å, and the thickness of the first etch stop layer and the second etch stop layer may be between 300 and 500 Å, respectively.
- The step of forming a spacer includes the steps of forming a third insulating layer to have a thickness with which the storage node hole may not be completely filled, and etching-back the third insulating layer. The third insulating layer may be a silicon nitride layer or a silicon oxynitride layer formed by a PE-CVD method.
- The step of removing the second etch stop layer pattern and the spacer is performed by removing the spacer after the removal of the second etch stop layer pattern, or by simultaneously removing the second etch stop layer pattern and the spacer.
- The step of removing the second etch stop layer pattern and the spacer is performed by a wet etching method using a mixed solution of hydrogen peroxide, water (H2O), and hydrofluoric acid (HF).
- The step of forming a lower electrode includes the steps of forming a conductive layer having the thickness with which the storage node hole and the node contact hole may not be completely filled, on the entire surface of a resultant on which the node contact hole is formed, and forming a plurality of separated storage nodes by removing the top of the conductive layer and the second insulating layer pattern. The conductive layer may be formed of a polysilicon layer by diffusion. The step of forming a plurality of plurality storage nodes includes the steps of forming an oxide layer which fills the storage node hole and the node contact hole, on the conductive layer, removing a part of the oxide layer and the top of the conductive layer so that the second insulating layer pattern may be exposed, and removing the oxide layer which fills the storage node hole and the node contact hole, and the second insulating layer pattern by a wet-etching method. Preferably, the oxide layer is formed of a USG layer, a BPSG layer, a double layer of a silicon oxide layer and a USG layer, or a double layer of a silicon oxide layer and a BPSG layer.
- The step of forming a lower electrode may further includes the step of forming hemispherical grains (HSGs) on the surface of the storage node.
- The dielectric layer may be formed of a Al2O3 layer, a Ta2O5 layer, a SrTiO3(STO) layer, (Ba, Sr) TiO3(BST) layer, a PbTiO3 layer, Pb(Zr, Ti)O3(PZT) layer, a SrBi2Ta2O9(SBT) layer, (Pb,La)(Zr,Ti)O3 layer, or BaTiO3(BTO) layer. Alternatively, the dielectric layer may be formed of a triple layer of a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer, or a double layer of a silicon nitride layer and a silicon oxide layer.
- The upper electrode may be formed by using a polysilicon layer by diffusion.
- The present invention is further directed to a cylinder-type capacitor of a semiconductor device. A lower electrode is formed of a conductive layer which directly contacts a conductive region on a semiconductor substrate. The lower electrode comprises a first cylinder in contact with the conductive region and a second cylinder on and in contact with the first cylinder, the second cylinder being larger in width than the first cylinder. A dielectric layer is on the lower electrode. An upper electrode is on the dielectric layer. The upper electrode extends into the first and second cylinders.
- The conductive region comprises an active region on the surface of the semiconductor substrate or a contact pad above the semiconductor substrate. The capacitor may further comprise a contact pad that is self-aligned by two neighboring gate electrodes formed on the semiconductor substrate.
- The gate electrodes may comprise a polycide structure in which a silicide layer is formed on a polysilicon layer. The lower conductive layer may comprise a polysilicon layer. The lower electrode may include hemispherical grains (HSGs) on the surface thereof.
- The dielectric layer is, for example, formed of one of a Al2O3 layer, a Ta2O5 layer, a SrTiO3 (STO) layer, a (Ba, Sr)TiO3 (BST) layer, a PbTiO3 layer, Pb(Zr, Ti)O3(PZT) layer, a SrBi2Ta2O9(SBT) layer, a (Pb,La)(Zr,Ti)O3 layer, and a BaTiO3(BTO) layer. The dielectric layer may optionally be formed of one of a triple layer comprising a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer, and a double layer comprising a silicon nitride layer and a silicon oxide layer.
- The upper electrode may, for example, comprise a polysilicon layer.
- According to the present invention, a photolithography process and a process for forming a conductive layer are each performed once, respectively. Thus, the overall fabrication process is simplified, and productivity is improved and production cost reduced.
- The above object and advantages of the present invention will become more apparent by describing in detail preferred embodiments thereof with reference to the attached drawings in which:
- FIGS. 1 through 5 are sectional views illustrating a conventional method for fabricating a cylinder-type capacitor for a semiconductor device;
- FIGS. 6 through 14 are sectional views illustrating a method for fabricating a cylinder-type capacitor for a semiconductor device according to a first embodiment of the present invention;
- FIG. 15 is a sectional view illustrating a method for fabricating a cylinder-type capacitor for a semiconductor device according to a second embodiment of the present invention;
- FIGS. 16 through 18 are sectional views illustrating a method for fabricating a cylinder-type capacitor for a semiconductor device according to a third embodiment of the present invention;
- FIG. 19 is a sectional view illustrating a method for fabricating a cylinder-type capacitor for a semiconductor device according to a fourth embodiment of the present invention; and
- FIGS. 20 through 24 are sectional views illustrating a method for fabricating a cylinder-type capacitor for a semiconductor device according to a fifth embodiment of the present invention.
- The present invention will be described more fully hereinafter with reference to the accompanying drawings in which preferred embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the thickness of layers and regions are exaggerated for clarity. It will be understood that when an element such as a layer is referred to as being “on” another element or substrate, it can be directly on another element or substrate, or intervening elements may also be present. Like reference numerals refer to like elements throughout the drawings.
- Embodiment 1
- FIGS. 6 through 14 are sectional views illustrating a method for fabricating a cylinder-type capacitor of a semiconductor device according to a first embodiment of the present invention. Referring to FIG. 6, a
gate insulating layer 201 is interposed between asemiconductor substrate 200 and agate electrode 205. Acapping layer 203 is formed on the top of thegate electrode 205, and a spacer forgate 204 is formed on the sidewall of thegate electrode 205. Impurity ions are implanted onto thesemiconductor substrate 200 on which thegate electrode 205 is formed, andactive regions semiconductor substrate 200. A first insulatinglayer 220, a firstetch stop layer 230, a second insulatinglayer 240, and a secondetch stop layer 250 are formed in sequence on the resultant structure on which theactive regions - The first insulating
layer 220 and the second insulatinglayer 240 may be formed of the same layer, but, in this case, the second insulatinglayer 240 is formed of a material having a higher etching selectivity than that of the first insulatinglayer 220, so as to be easily removed during separation of storage nodes. For example, the first insulatinglayer 220 may be formed of a silicon oxide layer by a HDP-CVD method, and the second insulatinglayer 240 may be formed of a TEOS layer by a PE-CVD method. - The thickness of the first insulating
layer 220 is decided by considering a lay-out of a device to be formed and, for example, may be between 8000 and 12000 Å. The thickness of the second insulatinglayer 240, for example, may be equal to or greater than the height of the storage node, considering the height of the storage node to be formed, or between 5000 and 20000 Å. - Preferably, the first
etch stop layer 230 and the secondetch stop layer 250 are formed of silicon nitride layers, respectively, by a LP-CVD method. Each thickness of the firstetch stop layer 230 and the secondetch stop layer 250 may be a thickness with which etching of the second insulatinglayer 240 and the first insulatinglayer 220 can be prevented. For example, the thickness of the firstetch stop layer 230 and the secondetch stop layer 250 can be between 300 and 500 Å, respectively. - Referring to FIG. 7, a
photoresist pattern 252 having an opening of a width W21 at the position corresponding to one of theactive regions 210 is formed on the secondetch stop layer 250. The secondetch stop layer 250, the second insulatinglayer 240, and the firstetch stop layer 230 are etched by using thephotoresist pattern 252 as a mask, and thereby, a second etchstop layer pattern 250 a, a second insulatinglayer pattern 240 a, and a first etchstop layer pattern 230 a are formed so that astorage node hole 255 exposing the surface of a portion of the first insulatinglayer 220 is formed. - Referring to FIG. 8, after the
photoresist pattern 252 is removed, a thirdinsulating layer 260 is formed at a thickness such that thestorage node hole 255 is not completely filled. Here, the third insulatinglayer 260 is formed of a silicon nitride layer or a silicon oxynitride layer by a PE-CVD method. The thickness of the third insulatinglayer 260 is decided by considering the width of a node contact hole to be formed in the first insulatinglayer 220. - Referring to FIG. 9, a
spacer 260 a is formed on an inner wall of thestorage node hole 255 by etching-back the third insulatinglayer 260. Here, the surface of the top of the first insulatinglayer 220 is exposed to the width W22 (W22<W21). - Referring to FIG. 10, the exposed first insulating
layer 220 is etched by using the second etchstop layer pattern 250 a and thespacer 260 a as a mask, and a first insulatinglayer pattern 220 a is formed, having anode contact hole 265 in which a surface of a portion of theactive region 210 is exposed. - Referring to FIG. 11, the second etch
stop layer pattern 250 a and thespacer 260 a are removed. The second etchstop layer pattern 250 a may be removed during the process described with reference to FIGS. 9 and 10. If a portion, or all, of the second etchstop layer pattern 250 a remains, even following the process described in FIGS. 9 and 10, then the second etchstop layer pattern 250 a is removed with thespacer 260 a. That is, an additional removal step is performed, for removing the second etchstop layer pattern 250 a and thespacer 260 a. This removal step can be performed by removing thespacer 260 a after removal of the second etchstop layer pattern 250 a, or by simultaneously removing the second etchstop layer pattern 250 a and thespacer 260 a. An etching solution or etching gas having a high etching selectivity with respect to thespacer 260 a, as compared to the first insulatinglayer pattern 220 a, the second insulatinglayer pattern 240 a, and thesemiconductor substrate 200, is preferably used in the step of removing the second etchstop layer pattern 250 a and thespacer 260 a. For example, the step of removing the second etchstop layer pattern 250 a and thespacer 260 a may be performed by a wet etching method using an etching solution containing hydrogen peroxide, water, and hydrofluoric acid. A high degree of etching selectivity of the etching solution or etching gas is preferred for avoiding deterioration of the secondinsulator layer pattern 240, and thereby maintaining adequate height in the storage node, and avoiding a reduction in capacitance. - Referring to FIG. 12, a
conductive layer 270 having appropriate thickness so as to avoid completely filling thestorage node hole 255 and thenode contact hole 265, is formed on the entire surface of a resultant structure shown in FIG. 11. Preferably, theconductive layer 270 is formed of a polysilicon layer by diffusion. Anoxide layer 280 which fills thestorage node hole 255 and thenode contact hole 265 is formed on theconductive layer 270. Here, theoxide layer 280 is preferably formed of a USG layer, a BPSG layer, a double layer of a silicon oxide layer and a USG layer, or a double layer of a silicon oxide layer and a BPSG layer. If a silicon oxide layer having a high etching durability is formed before forming the USG layer or the BPSG layer, and theoxide layer 280 is formed of a double layer of a silicon oxide layer and a USG layer, or a double layer of a silicon oxide layer and a BPSG layer, theactive region 210 can be prevented from being etched. - Referring to FIG. 13, a part of the
oxide layer 280 and the top of theconductive layer 270 are removed by etching-back or, chemical mechanical polishing (CMP), the upper surface of the resultant structure shown in FIG. 12 so that the second insulatinglayer pattern 240 a may be exposed. A separatedstorage node 270 a is formed by removing theoxide layer 280 filling thestorage node hole 255 and thenode contact hole 265, and removing the second insulatinglayer pattern 240 a, by wet etching. Thestorage node 270 a forms a lower electrode of a cylinder-type capacitor. - Referring to FIG. 14, a
dielectric layer 280 and anupper electrode 290 are formed on thestorage node 270 a. Thedielectric layer 280 is, for example, formed of a Al2O3 layer, a Ta2O5 layer, a STO layer, a BST layer, a PbTiO3 layer, a PZT layer, a SBT layer, a (Pb,La)(Zr,Ti)O3 layer, or a BTO layer. Alternatively, thedielectric layer 280 may be formed of a triple layer of a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer, or a double layer of a silicon nitride layer and a silicon oxide layer. Theupper layer 290 is preferably formed of a polysilicon layer by diffusion. - According to the embodiment described above, a photolithography process and a process for forming a conductive layer are performed once, respectively, and then processes are simplified. Comparing the resulting structure of FIG. 14 with the conventional structure of FIG. 5, in FIG. 14, the effective surface area of the capacitor electrode increases. Thus, a capacitor having improved capacitance can be fabricated.
- Embodiment 2
- FIG. 15 is a sectional view illustrating the method for fabricating a cylinder-type capacitor of a semiconductor device according to a second embodiment of the present invention. Referring to FIG. 15, a
gate insulating layer 301 is interposed between asemiconductor substrate 300 and agate electrode 305. Acapping layer 303 is formed on the top of thegate electrode 305, and a spacer forgate 304 is formed on the sidewall of thegate electrode 305.Active regions semiconductor substrate 300 on which thegate electrode 305 is formed. A first insulatinglayer pattern 320 a, and a first etchstop layer pattern 330 a are formed on the resultant structure on which theactive regions stop layer pattern 330 a, the first insulatinglayer pattern 320 a, and theactive region 310, is formed. In order to improve capacitance, HSGs are formed on the surface of the storage node, and thereby completing alower electrode 370 b. Adielectric layer 380 and anupper electrode 390 are formed on thelower electrode 370 b. Other processes beyond the process for forming HSGs are the same as those in the first embodiment, so a description thereof will be omitted. - Embodiment 3
- FIGS. 16 through 18 are sectional views illustrating a method for fabricating a cylinder-type capacitor of a semiconductor device according to a third embodiment of the present invention. Referring to FIG. 16, a plurality of
gate electrodes 405 are formed on asemiconductor substrate 400. Agate insulating layer 401 is interposed under thegate electrodes 405. Acapping layer 403 is formed on the top of thegate electrodes 405, and a spacer forgate 404 is formed on sidewalls of thegate electrodes 405. Thegate electrodes 405 may be formed of the structures of a polycide in which polysilicon layers 405 a andsilicide layers 405 b, for example, tungsten silicide layers, are formed in sequence. Aninterdielectric layer 407 which fills a space between the plurality ofgate electrodes 405 is formed. Theinterdielectric layer 407 may be formed of a BPSG layer, a SOG layer, a USG layer, a silicon oxide layer formed by using a HDP-CVD method, or a TEOS layer formed by using a PE-CVD method. - Referring to FIG. 17, a photoresist pattern (not shown) is formed on the
interdielectric layer 407, and theinterdielectric layer 407 is patterned by using the photoresist pattern as a mask. As a result, aninterdielectric layer pattern 407 a having a contact hole H for exposing the surface of thesemiconductor substrate 400 between the two neighboringgate electrodes 405 is formed. Acontact pad 410 is formed by filling a conductive material in the contact hole H. - Referring to FIG. 18, a first insulating
layer pattern 420 a and a first etchstop layer pattern 430 a are formed on the resultant structure on which thecontact pad 410 is formed. Astorage node 470 a interfacing with the first etchstop layer pattern 430 a, the first insulatinglayer pattern 420 a, and thecontact pad 410 is formed. Adielectric layer 480 and anupper electrode 490 are formed on thestorage node 470 a. Other processes are the same as those in the first embodiment, so a description thereof will be omitted. - Embodiment 4
- FIG. 19 is a sectional view illustrating the method for fabricating a cylinder-type capacitor of a semiconductor device according to a fourth embodiment of the present invention. Referring to FIG. 19, a
gate insulating layer 501 is interposed between asemiconductor substrate 500 and agate electrode 505. Acapping layer 503 is formed on the top of thegate electrode 505, and a spacer forgate 504 is formed on the sidewall of thegate electrode 505. Thegate electrodes 505 are formed of apolysilicon layer 505 a and asilicide layer 505 b, in sequence, for example, of the structure of a polycide in which a tungsten silicide layer is formed. A first insulatinglayer pattern 507 a and acontact pad 510 are formed on the resultant structure on which thegate electrodes 505 are formed. A first insulatinglayer pattern 520 a and a first etchstop layer pattern 530 a are formed on the resultant structure on which thecontact pad 510 is formed. A storage node interfacing with the first etchstop layer pattern 530 a, the first insulatinglayer pattern 520 a, and thecontact pad 510 is formed. In order to improve capacitance, HSGs are formed on the surface of the storage node, and thereby completing alower electrode 570 b. Adielectric layer 580 and anupper electrode 590 are formed on thelower electrode 570 b. Processes beyond the formation of HSGs are the same as those in the third embodiment, so a description thereof will be omitted. - Embodiment 5
- FIGS. 20 through 24 are sectional views illustrating a method for fabricating a cylinder-type capacitor of a semiconductor device according to a fifth embodiment of the present invention. Referring to FIG. 20, a
gate insulating layer 601 is interposed between asemiconductor substrate 600 and agate electrode 605. Acapping layer 603 is formed on the top of thegate electrode 605, and a spacer forgate 604 is formed on the sidewall of thegate electrode 605.Active regions semiconductor substrate 600 on which thegate electrode 605 is formed. A first insulatinglayer 620, a firstetch stop layer 630, a second insulatinglayer 640, and a secondetch stop layer 650 are formed in sequence on the resulting structure on which theactive regions silicon oxide layer 651 is formed on the secondetch stop layer 650. Here, thesilicon oxide layer 651 may comprise a silicon oxide layer formed by using a PE-CVD method, or a high temperature oxide layer. - Referring to FIG. 21, a
photoresist pattern 652 having an opening of width W31 is formed at a position corresponding toactive region 610 on thesilicon oxide layer 651. Thesilicon oxide layer 651, the secondetch stop layer 650, the second insulatinglayer 640, and the firstetch stop layer 630 are etched by using thephotoresist pattern 652 as a mask, and thereby, a siliconoxide layer pattern 651 a, a second etchstop layer pattern 650 a, a second insulatinglayer pattern 640 a, and a first etchstop layer pattern 630 a having astorage node hole 655 for exposing the surface of a part of the first insulatinglayer 620 are formed. - Referring to FIG. 22, after the
photoresist pattern 652 is removed, a thirdinsulating layer 660 having a suitable thickness such that thestorage node hole 655 is not completely filled is formed. Here, the third insulatinglayer 660 is preferably formed of a silicon nitride layer or a silicon oxynitride layer by a PE-CVD method. - Referring to FIG. 23, a
spacer 660 a is formed on an inner wall of thestorage node hole 655 by etching-back the third insulatinglayer 660. Here, the first insulatinglayer 620 is exposed across width W32. In a case where it is necessary to remove a silicon nitride layer or silicon oxynitride layer on the exposed surface of the first insulatinglayer 620, a process for treating a residue having no selectivity is performed. Here, the siliconoxide layer pattern 651 a protects the second etchstop layer pattern 650 a. If the second etchstop layer pattern 650 a is removed, the second insulatinglayer pattern 640 a is etched in the subsequent process for forming a node contact hole, and the height of the storage node is reduced. This causes the capacitance of the resulting capacitor to be reduced. The siliconoxide layer pattern 651 a prevents this problem. The siliconoxide layer pattern 651 a can optionally be removed during the process for treating a residue, or alternatively remain on the structure. - Referring to FIG. 24, the exposed first insulating
layer 620 is etched by using the second etchstop layer pattern 650 a and thespacer 660 a as a mask, and a first insulatinglayer pattern 620 a is formed, having a node contact hole 665 in which the surface of a part of theactive region 610 is exposed. The siliconoxide layer pattern 651 a remaining after the process for treating a residue, and the first insulatinglayer 620, are the same material layers, so the siliconoxide layer pattern 651 a is completely removed during this step. After that, processes described with reference to FIGS. 11 through 14, or processes for obtaining a resultant of FIG. 15 will be performed. - According to the present invention, a storage node hole is formed under a single photolithography process, and a single process for forming a conductive layer is performed following formation of a node contact hole using a spacer. This is in contrast with the conventional approach illustrated above, which requires dual photolithography processes and dual processes for forming a conductive layer. Thus, the overall fabrication process is simplified, and thereby productivity is improved and production cost reduced. Since a contact plug of a cylinder-type capacitor according to the prior art can be used as a lower electrode of a capacitor, the effective area of the capacitor electrode increases, thereby improving the capacitance of the capacitor.
- While this invention has been particularly shown and described with reference to preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (9)
1. A cylinder-type capacitor of a semiconductor device comprising:
a lower electrode formed of a conductive layer which directly contacts a conductive region on a semiconductor substrate, wherein the lower electrode comprises a first cylinder in contact with the conductive region and a second cylinder on, and in contact with, the first cylinder, the second cylinder being larger in width than the first cylinder;
a dielectric layer on the lower electrode; and
an upper electrode on the dielectric layer, wherein the upper electrode extends into the first and second cylinders.
2. The capacitor according to claim 1 , wherein the conductive region comprises an active region on the surface of the semiconductor substrate or a contact pad above the semiconductor substrate.
3. The capacitor according to claim 1 , wherein the conductive region comprises a contact pad that is self-aligned by two neighboring gate electrodes formed on the semiconductor substrate.
4. The capacitor according to claim 3 , wherein the gate electrodes comprise a polycide structure in which a silicide layer is formed on a polysilicon layer.
5. The capacitor according to claim 1 , wherein the conductive layer comprises a polysilicon layer.
6. The capacitor according to claim 1 , wherein the lower electrode includes hemispherical grains (HSGs) on the surface thereof.
7. The capacitor according to claim 1 , wherein the dielectric layer is formed of one of a Al2O3 layer, a Ta2O5 layer, a SrTiO3 (STO) layer, a (Ba, Sr)TiO3 (BST) layer, a PbTiO3 layer, Pb(Zr, Ti)O3(PZT) layer, a SrBi2Ta2O9(SBT) layer, a (Pb,La)(Zr,Ti)O3 layer, and a BaTiO3(BTO) layer.
8. The capacitor according to claim 1 , wherein the dielectric layer is formed of one of a triple layer comprising a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer, and a double layer comprising a silicon nitride layer and a silicon oxide layer.
9. The capacitor according to claim 1 , wherein the upper electrode comprises a polysilicon layer.
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US10/375,385 US20030147199A1 (en) | 2001-01-10 | 2003-02-27 | Cylinder-type capacitor for a semiconductor device |
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US09/886,066 US6548349B2 (en) | 2001-01-10 | 2001-06-21 | Method for fabricating a cylinder-type capacitor for a semiconductor device |
US10/375,385 US20030147199A1 (en) | 2001-01-10 | 2003-02-27 | Cylinder-type capacitor for a semiconductor device |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101740104A (en) * | 2008-11-04 | 2010-06-16 | 海力士半导体有限公司 | Circuit and method for outputing data |
Families Citing this family (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6538274B2 (en) * | 2000-12-20 | 2003-03-25 | Micron Technology, Inc. | Reduction of damage in semiconductor container capacitors |
KR100382732B1 (en) * | 2001-01-10 | 2003-05-09 | 삼성전자주식회사 | Method for fabricating cylinder-type capacitor of semiconductor device |
KR100405134B1 (en) * | 2001-06-25 | 2003-11-12 | 대한민국 | A manufacturing process electro luminescence device |
KR100406581B1 (en) * | 2001-12-15 | 2003-11-20 | 주식회사 하이닉스반도체 | method of manufacturing semiconductor device |
KR100505656B1 (en) * | 2002-12-10 | 2005-08-04 | 삼성전자주식회사 | Method for manufacturing semiconductor device including contact body expanded along bit line direction to obtain more contacting area with storage node |
US6806208B2 (en) * | 2003-03-11 | 2004-10-19 | Oki Electric Industry Co., Ltd. | Semiconductor device structured to prevent oxide damage during HDP CVD |
KR100780611B1 (en) * | 2004-12-28 | 2007-11-29 | 주식회사 하이닉스반도체 | Method for manufacturing capacitor of semiconductor memory device using amorphous carbon |
JP4916168B2 (en) | 2004-12-28 | 2012-04-11 | 株式会社ハイニックスセミコンダクター | Manufacturing method of semiconductor memory device having capacitor of cylinder structure |
KR100670396B1 (en) * | 2004-12-30 | 2007-01-16 | 동부일렉트로닉스 주식회사 | Method for fabricating cylindric type capacitor using side lobe phenomenon |
KR100665852B1 (en) * | 2005-08-03 | 2007-01-09 | 삼성전자주식회사 | Method for manufacturing semiconductor device |
KR100925031B1 (en) * | 2007-06-11 | 2009-11-03 | 주식회사 하이닉스반도체 | Method for manufacturing semiconductor device with cylinder type capacitor |
CN101673619B (en) * | 2009-08-21 | 2012-10-03 | 上海宏力半导体制造有限公司 | Columnar capacitor, stacking-type coaxial columnar capacitor and preparation method thereof |
US8685778B2 (en) * | 2010-06-25 | 2014-04-01 | International Business Machines Corporation | Planar cavity MEMS and related structures, methods of manufacture and design structures |
CN102456738A (en) * | 2010-10-29 | 2012-05-16 | 上海宏力半导体制造有限公司 | VDMOS (Vertical Double-diffused Metal Oxide Semiconductor) transistor |
CN103151244B (en) * | 2011-12-07 | 2017-04-26 | 华邦电子股份有限公司 | Stackable capacitor and manufacturing method thereof |
CN109728088A (en) * | 2017-10-30 | 2019-05-07 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
KR20200010913A (en) | 2018-07-23 | 2020-01-31 | 삼성전자주식회사 | A semiconductor device |
CN113402161A (en) * | 2021-07-16 | 2021-09-17 | 上海大学 | Ultra-wideband fluorescent quantum dot doped quartz amplifying optical fiber and preparation method thereof |
Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5324679A (en) * | 1991-03-23 | 1994-06-28 | Samsung Electronics Co., Ltd. | Method for manufacturing a semiconductor device having increased surface area conductive layer |
US5656531A (en) * | 1993-12-10 | 1997-08-12 | Micron Technology, Inc. | Method to form hemi-spherical grain (HSG) silicon from amorphous silicon |
US5807777A (en) * | 1997-11-03 | 1998-09-15 | Texas Instruments - Acer Incorporated | Method of making a double stair-like capacitor for a high density DRAM cell |
US5817555A (en) * | 1996-05-02 | 1998-10-06 | Lg Semicon Co., Ltd. | Method for fabricating capacitor of semiconductor device using hemispherical grain (HSG) polysilicon |
US6162680A (en) * | 1999-05-24 | 2000-12-19 | Worldwide Semiconductor Manufacturing Corp. | Method for forming a DRAM capacitor |
US6303430B1 (en) * | 1998-11-04 | 2001-10-16 | United Microelectronics Corp. | Method of manufacturing DRAM capacitor |
US6376874B1 (en) * | 1998-06-24 | 2002-04-23 | Samsung Electronics Co., Ltd. | Method for fabricating a capacitor of a semiconductor memory device |
US6459116B1 (en) * | 1997-08-04 | 2002-10-01 | Micron Technology, Inc. | Capacitor structure |
US6489195B1 (en) * | 1999-11-05 | 2002-12-03 | Samsung Electronics Co., Ltd. | Method for fabricating DRAM cell using a protection layer |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR970011759A (en) * | 1995-08-31 | 1997-03-27 | 배순훈 | Shelf Position Adjuster |
KR19990004603A (en) * | 1997-06-28 | 1999-01-15 | 김영환 | Capacitor Formation Method of Semiconductor Device |
KR100256059B1 (en) * | 1997-10-14 | 2000-05-01 | 윤종용 | Method of forming dram cell capacitor |
TW427014B (en) * | 1997-12-24 | 2001-03-21 | United Microelectronics Corp | The manufacturing method of the capacitors of DRAM |
US6190962B1 (en) * | 1999-12-20 | 2001-02-20 | United Microelectronics Corp. | Method of fabricating capacitor |
KR100382732B1 (en) * | 2001-01-10 | 2003-05-09 | 삼성전자주식회사 | Method for fabricating cylinder-type capacitor of semiconductor device |
-
2001
- 2001-01-10 KR KR10-2001-0001353A patent/KR100382732B1/en active IP Right Grant
- 2001-06-21 US US09/886,066 patent/US6548349B2/en not_active Expired - Lifetime
- 2001-09-10 TW TW090122321A patent/TW523913B/en not_active IP Right Cessation
- 2001-09-28 CN CNB011409894A patent/CN1222029C/en not_active Expired - Lifetime
- 2001-11-26 JP JP2001359842A patent/JP3977633B2/en not_active Expired - Fee Related
-
2003
- 2003-02-27 US US10/375,385 patent/US20030147199A1/en not_active Abandoned
Patent Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5324679A (en) * | 1991-03-23 | 1994-06-28 | Samsung Electronics Co., Ltd. | Method for manufacturing a semiconductor device having increased surface area conductive layer |
US5656531A (en) * | 1993-12-10 | 1997-08-12 | Micron Technology, Inc. | Method to form hemi-spherical grain (HSG) silicon from amorphous silicon |
US5817555A (en) * | 1996-05-02 | 1998-10-06 | Lg Semicon Co., Ltd. | Method for fabricating capacitor of semiconductor device using hemispherical grain (HSG) polysilicon |
US6459116B1 (en) * | 1997-08-04 | 2002-10-01 | Micron Technology, Inc. | Capacitor structure |
US5807777A (en) * | 1997-11-03 | 1998-09-15 | Texas Instruments - Acer Incorporated | Method of making a double stair-like capacitor for a high density DRAM cell |
US6376874B1 (en) * | 1998-06-24 | 2002-04-23 | Samsung Electronics Co., Ltd. | Method for fabricating a capacitor of a semiconductor memory device |
US6303430B1 (en) * | 1998-11-04 | 2001-10-16 | United Microelectronics Corp. | Method of manufacturing DRAM capacitor |
US6162680A (en) * | 1999-05-24 | 2000-12-19 | Worldwide Semiconductor Manufacturing Corp. | Method for forming a DRAM capacitor |
US6489195B1 (en) * | 1999-11-05 | 2002-12-03 | Samsung Electronics Co., Ltd. | Method for fabricating DRAM cell using a protection layer |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101740104A (en) * | 2008-11-04 | 2010-06-16 | 海力士半导体有限公司 | Circuit and method for outputing data |
Also Published As
Publication number | Publication date |
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US20020090778A1 (en) | 2002-07-11 |
KR20020060333A (en) | 2002-07-18 |
JP3977633B2 (en) | 2007-09-19 |
US6548349B2 (en) | 2003-04-15 |
CN1365142A (en) | 2002-08-21 |
KR100382732B1 (en) | 2003-05-09 |
CN1222029C (en) | 2005-10-05 |
TW523913B (en) | 2003-03-11 |
JP2002222872A (en) | 2002-08-09 |
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