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Publication numberUS20030179593 A1
Publication typeApplication
Application numberUS 10/233,966
Publication dateSep 25, 2003
Filing dateSep 3, 2002
Priority dateMar 20, 2002
Also published asUS6794923
Publication number10233966, 233966, US 2003/0179593 A1, US 2003/179593 A1, US 20030179593 A1, US 20030179593A1, US 2003179593 A1, US 2003179593A1, US-A1-20030179593, US-A1-2003179593, US2003/0179593A1, US2003/179593A1, US20030179593 A1, US20030179593A1, US2003179593 A1, US2003179593A1
InventorsRodney Burt, Haoran Zhang, Thomas Botker, Vadium Ivanov
Original AssigneeTexas Instruments Incorporated
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Low ripple charge pump
US 20030179593 A1
Abstract
A charge pump circuit is configured for charging of parasitic capacitances associated with charge pump capacitors in a manner that minimizes voltage ripple. The charge pump circuit is suitably configured with an independent charging circuit configured for supplying the current needed to charge the parasitic capacitances, rather than utilizing the reservoir capacitor to supply the needed current. The independent charging circuit can be implemented with various configurations of charge pump circuits, such as single phase or dual phase charge pumps, and/or doubler, tripler or inverter configurations. The independent charging circuit comprises a parasitic charging capacitor or other voltage source configured with one or more switch devices configured to facilitate charging of the parasitics during any phases of operation of the charge pump circuit. In addition, the independent charging circuit comprises an independent cell, and is local to charge pump circuit for supplying the current for charging the parasitic capacitances, instead of having the current supplied through external bussing or wire bonds.
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Claims(20)
What is claimed is:
1. A charge pump circuit configured for minimizing voltage ripple, said charge pump circuit comprising:
a charge pump comprising at least a first pump capacitor;
a regulation loop configured for regulation of low speed inaccuracies of said charge pump circuit, said regulation loop coupled to said first pump capacitor; and
an independent charging circuit configured for charging of parasitic capacitances associated with said first pump capacitor during phase changes of said charge pump.
2. The charge pump circuit according to claim 1, wherein said independent charging circuit comprises a first switch device and a voltage source, said first switch device configured for providing a charge from said voltage source to said parasitic capacitances.
3. The charge pump circuit according to claim 2, wherein said voltage source comprises a charging capacitor.
4. The charge pump circuit according to claim 3, wherein said charging capacitor has a capacitance between approximately 4 to 20 times the size of said parasitic capacitances.
5. The charge pump circuit according to claim 1, wherein said independent charging circuit is configured apart from any external source and any external bussing.
6. The charge pump circuit according to claim 1, wherein said independent charging circuit comprises an independent cell.
7. The charge pump circuit according to claim 2, wherein said charge pump circuit comprises a dual phase charge pump doubler, said dual phase charge pump doubler further comprising a second pump capacitor, and said independent charging circuit further comprising a second switch device, said second switch device configured for providing a charge from said voltage source to said parasitic capacitances of said second charge pump capacitor.
8. The charge pump circuit according to claim 1, said independent charging circuit configured for charging said parasitic capacitances only during an initial phase of a discharging phase of said first pump capacitor.
9. A charge pump circuit configured for dual phase operation, said charge pump circuit comprising:
an input supply voltage terminal;
a pump voltage terminal;
a dual phase charge pump doubler comprising a first charge pump capacitor and a second charge pump capacitor, and a plurality of switches;
a regulation loop configured for regulation of low speed inaccuracies of said charge pump circuit, said regulation loop comprising an amplifier and a regulated voltage, said amplifier having a positive input terminal coupled to said input supply voltage terminal, and a negative input terminal coupled through said regulated voltage to said pump voltage terminal, and being configured to regulate internal nodes coupled to said first charge pump capacitor and said second charge pump capacitor; and
an independent charging circuit comprising a voltage source configured for regulation of high speed inaccuracies caused by parasitic capacitances at said first charge pump capacitor and said second charge pump capacitor, said independent charging circuit configured for charging said parasitic capacitances during phase changes of said dual phase charge pump doubler.
10. The charge pump circuit according to claim 9, wherein said independent charging circuit further comprises a first switch device and a second switch device, said first switch device configured to facilitate charging of parasitic capacitances associated with said first pump capacitor, and said second switch device configured to facilitate charging of parasitic capacitances associated with said second pump capacitor.
11. The charge pump circuit according to claim 10, wherein said charge pump circuit further comprises a clock circuit for controlling operation of said first switch device and said second switch device.
12. The charge pump circuit according to claim 11, wherein said independent charging circuit is configured to charge parasitic capacitances associated with said first pump capacitor during an initial phase within a discharging phase of said first pump capacitor.
13. The charge pump circuit according to claim 12, wherein said initial phase comprises between approximately 1% to 20% of said discharging phase.
14. The charge pump circuit according to claim 9, wherein said voltage source comprises a charging capacitor.
15. The charge pump circuit according to claim 9, wherein said independent charging circuit is configured separate from any external source and any external bussing.
16. A method for minimizing voltage ripple in a dual phase charge pump circuit, said method comprising the steps of:
charging a first pump capacitor during a first charging phase;
charging parasitic capacitances associated with said first pump capacitor with an independent charging circuit during an initial phase of a first discharging phase of said first pump capacitor;
charging a second pump capacitor during a second charging phase; and
charging parasitic capacitances associated with said second pump capacitor with said independent charging circuit during an initial phase of a second discharging phase of said second pump capacitor, wherein said steps of charging said parasitic capacitances minimizes utilization of a reservoir capacitor of said dual phase charge pump circuit to charge said parasitic capacitances.
17. The method according to claim 16, said step of charging parasitic capacitances associated with said first pump capacitor comprising the switching of charge from a voltage source of said independent charging circuit to said parasitic capacitances associated with said first pump capacitor.
18. The method according to claim 17, said step of charging parasitic capacitances associated with said second pump capacitor comprising the switching of charge from said voltage source of said independent charging circuit to said parasitic capacitances associated with said second pump capacitor.
19. The method according to claim 16, wherein said steps of charging said parasitic capacitances with said independent charging circuit occurs through local supply of a charge from a voltage source separate from any external bussing.
20. A charge pump circuit configured for minimizing voltage ripple, said charge pump circuit comprising:
a charge pump comprising at least a first pump capacitor;
a regulation loop configured for regulation of low speed inaccuracies of said charge pump circuit, said regulation loop coupled to said first pump capacitor; and
an independent charging circuit configured for charging of parasitic capacitances associated with said first pump capacitor during phase changes of said charge pump, said independent charging circuit configured separate from any external source and any external bussing, and said independent charging circuit comprising a first switch device and a voltage source, said first switch device configured for providing a charge from said voltage source to said parasitic capacitances.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority of U.S. Provisional Application Serial No. 60/365,905, filed Mar. 20, 2002, entitled “CHARGE PUMPS WITH CONTROLLED CHARGE CURRENT.”

FIELD OF INVENTION

[0002] The present invention relates to charge pumps for use in integrated circuits. More particularly, the present invention relates to a charge pump having a low voltage ripple.

BACKGROUND OF THE INVENTION

[0003] The demand for less expensive, and yet more reliable integrated circuit components for use in communication, imaging and high-quality video applications continues to increase rapidly. As a result, integrated circuit manufacturers are requiring improved performance in the voltage supplies and references for such components and devices to meet the design requirements of such emerging applications.

[0004] One device utilized for providing a regulated voltage supply is a charge pump circuit. Charge pumps are DC/DC converters that utilize a capacitor instead of an inductor or transformer for energy storage, and are configured for generating positive or negative voltages from the input voltage. Charge pumps can be configured in various manners, including a charge pump voltage doubler circuit, i.e., a charge pump circuit configured for doubling the input voltage, as well as tripler and inverter configurations. Charge pump circuits can be configured for single phase operation, with a single charge pump capacitor used to charge current during one phase of operation and discharge current during another phase of operation. For example, with reference to FIG. 1, a basic charge pump doubler 100 is illustrated, having a pump capacitor CPUMP, as well as switches S1, S2, S3 and S4 that are configured for single phase operation. In addition, charge pump circuit 100 comprises a reservoir capacitor CRES for maintaining charge to a load device. Basic charge pump doublers exhibit undesirable output voltage ripple due to uncontrolled inrush and charging currents, among other reasons.

[0005] To improve voltage ripple, charge pump circuits can also be configured for dual phase regulation, in which two charge pump capacitors are configured to operate during both phases of operation, i.e., one of the capacitors is charging current and the other capacitor is discharging current during each phase of operation. For example, with reference to FIG. 2, a charge pump circuit 200 configured for dual phase voltage operation is illustrated. Charge pump circuit 200 includes a charge pump control circuit comprising four switches S1, S2, S3 and S4 for use with a first pump capacitor CPUMP1 configured to discharge and supply current to a load device during a first phase while a second pump capacitor CPUMP2 is being charged, and four switches S5, S6, S7 and S8 for use with second pump capacitor CPUMP2 configured to discharge and supply current to the load device during a second phase while first pump capacitor CPUMP1 is being charged.

[0006] Other approaches to charge pump circuits include the implementation of a latch triggered upper switch drive. For example, with reference to FIG. 3, a charge pump circuit 300 configured as a dual phase doubler comprises a latch triggered upper drive 360 for driving upper switches S3, S4 and S7, S8 in phase with lower switches S1, S2, and S5, S6, wherein nodes 310 and 320 are pulled down to ground on one cycle and up to supply voltage VS + during the second cycle. Such dual phase charge pump doublers as 200 and 300 have improved output voltage ripple as compared to single phase doublers, but still have significant ripple due to current drawn by charge pump capacitors CPUMP1 and CPUMP2, as well as reservoir capacitor CRES.

[0007] Another approach to improve ripple performance includes the use of regulated charge pump circuits having a regulation loop. For example, a dual phase charge pump regulator can comprise a latch triggered upper drive and a regulation loop comprising a regulated voltage VREG and an amplifier. The amplifier is configured to sense the difference in voltage from pump voltage VPUMP and supply voltage VS +, i.e., a difference voltage VREG, to regulate charging of the pump capacitors. Thus, for example, through operation of the regulated feedback loop of the amplifier, a regulated voltage VREG, e.g., 2 volts, is forced between pump voltage VPUMP and supply voltage VS +. Accordingly, regulated charge pump circuits can regulate not only DC, but also during the discharge phase from which ripple occurs.

[0008] One problem inherent in any charge pump circuit is the presence of parasitics on the pump capacitors. For example, for charge pump circuit 300, charge pump capacitors CPUMP1 and CPUMP2 include parasitic capacitors 330 and 350 and parasitic capacitors 370 and 390, respectively. Parasitic capacitors 330, 350, 370 and 390 can often have a capacitance between approximately 1% to 10% or more of the capacitance of charge pump capacitors CPUMP1 and CPUMP2, e.g., for 50 pF of capacitance for pump capacitors CPUMP1 and CPUMP2, parasitic capacitors 330, 350, 370 and 390 can comprise approximately 0.5 pF to 5 pF of capacitance. During the phase changes, which occur very rapidly, parasitic capacitors 330, 350, 370 and 390 must also be charged in a very short amount of time. Even with the addition of an amplifier and a regulator loop that is capable of supplying small currents, such a regulator loop will not sufficiently respond to fast transient requirements.

[0009] Thus, reservoir capacitor CRES must supply the glitch current, e.g., up to 4 mA or more, required to recharge parasitic capacitors 330, 350, 370 and 390. However, when reservoir capacitor CRES supplies the glitch current di/dt, a voltage drop of up to approximately 150 mV or more can occur at the output of charge pump circuit 300, resulting in undesirable voltage ripple.

[0010] Accordingly, a need exists for an improved charge pump regulator that can suitably charge the parasitics of the charge pump capacitors, thus improving voltage ripple performance.

SUMMARY OF THE INVENTION

[0011] A charge pump circuit is configured for charging of parasitic capacitances associated with charge pump capacitors in a manner that minimizes voltage ripple. In accordance with one aspect of the present invention, the charge pump circuit is suitably configured with an independent charging circuit configured for supplying the current needed to charge the parasitic capacitances, rather than utilizing the reservoir capacitor to supply the needed current. As a result, the total voltage ripple can be reduced, e.g., by a factor of up to ten times or more, during operation of the charge pump circuit. The independent charging circuit can be implemented with various configurations of charge pump circuits, such as single phase or dual phase charge pumps, and/or doubler, tripler or inverter configurations.

[0012] The independent charging circuit is configured to minimize introduction of noise to charge pump circuit. In accordance with an exemplary embodiment of the present invention, the independent charging circuit is local to the charge pump circuit for supplying the current for charging the parasitic capacitances, instead of having the current supplied through external bussing or wire bonds.

[0013] The independent charging circuit can be configured in various manners for supplying the current required for charging the parasitic capacitances. In accordance with an exemplary embodiment comprising a dual phase charge pump doubler, the independent charging circuit comprises a parasitic charging capacitor configured with a pair of switch devices configured to facilitate charging of the parasitics during both phases of operation of dual phase charge pump circuit. However, the independent charging circuit can comprise any voltage source for providing a charge, as well as fewer or additional switch devices based on the number of pump capacitors.

BRIEF DESCRIPTION OF THE DRAWINGS

[0014] A more complete understanding of the present invention may be derived by referring to the detailed description and claims when considered in connection with the Figures, where like reference numbers refer to similar elements throughout the Figures, and:

[0015]FIG. 1 illustrates a schematic diagram of a prior art charge pump doubler circuit;

[0016]FIG. 2 illustrates a schematic diagram of a prior art dual phase charge pump doubler circuit;

[0017]FIG. 3 illustrates a schematic diagram of a prior art dual phase charge pump doubler circuit with a latch triggered upper switch drive;

[0018]FIG. 4 illustrates a block diagram of an exemplary charge pump circuit with an independent charging circuit in accordance with an exemplary embodiment of the present invention;

[0019]FIG. 6 illustrates a schematic diagram of an exemplary charge pump circuit with an independent charging circuit in accordance with an exemplary embodiment of the present invention; and

[0020]FIG. 7 illustrates a schematic diagram of an exemplary charge pump circuit with an independent charging circuit in accordance with another exemplary embodiment of the present invention.

DETAILED DESCRIPTION

[0021] The present invention may be described herein in terms of various functional components. It should be appreciated that such functional components may be realized by any number of hardware or structural devices configured to perform the specified functions. For example, the present invention may employ various integrated components, e.g., buffers, supply rail references, current mirrors, logic devices and the like, which are comprised of various electrical devices, e.g., resistors, transistors, capacitors, diodes and the like whose values may be suitably configured for various intended purposes. In addition, the present invention may be practiced in any integrated circuit application where regulated voltage supplies are desired. However for purposes of illustration only, exemplary embodiments of the present invention will be described herein in connection with a dual phase charge pump circuit. Further, it should be noted that while various components may be suitably coupled or connected to other components within exemplary circuits, such connections and couplings can be realized either by direct connection between components, or by connection through other components and devices located thereinbetween.

[0022] As discussed above, previous approaches for solving the problems of charge pump circuits have difficulty in limiting ripple performance due to the glitch current di/dt required to charge the parasistics of the pump capacitors. However, in accordance with various aspects of the present invention, a charge pump circuit is configured for charging of parasitic capacitances associated with charge pump capacitors in a manner that minimizes voltage ripple. In accordance with one aspect of the present invention, the charge pump circuit is suitably configured with an independent charging circuit configured for supplying the current needed to charge the parasitic capacitances, rather than utilizing the reservoir capacitor to supply the needed current. As a result, the total voltage ripple can be reduced, e.g., by a factor of up to ten times or more, during operation of the charge pump circuit.

[0023] In accordance with an exemplary embodiment, a block diagram of an exemplary charge pump circuit 400 is illustrated in FIG. 4. Charge pump circuit 400 comprises a charge pump doubler 402, a regulation loop 404, and an independent charging circuit 406. Charge pump doubler 402 comprises a dual phase charge pump, and can be configured with a clock signal for driving both lower and upper switches, such as provided through a clock circuit 408, or a latched triggered drive for the upper switches. However, charge pump doubler 402 can also be replaced by a single phase charge pump, as well as a tripler or an inverter configuration.

[0024] Regulation loop 404 comprises an amplifier 405 and is configured to sense the difference in voltages VS + and VPUMP, voltage difference VREG, to regulate the charging of the pump capacitors. Amplifier 405 can be configured to provide a voltage output or a current output. During operation, regulation loop 404 is configured to provide regulation of the slower requirements for charging current within charge pump circuit 400, i.e., to drive the pump capacitors, but not the parasitic capacitances.

[0025] Independent charging circuit 406 is configured for supplying the current for charging parasitic capacitances during discharging of the pump capacitors, for example, during an initial phase of the discharging of the pump capacitors. In accordance with an exemplary embodiment, independent charging circuit 406 is local to charge pump circuit 400 for supplying the current for charging the parasitic capacitances, instead of having the current supplied through external bussing or wire bonds, or through reservoir capacitor CRES. In addition, independent charging circuit 406 can also comprise an independent cell, enabling independent charging circuit 406 to be suitably “tacked on” to various charge pump circuit configurations. Operation of independent charging circuit 406 can be facilitated through clock circuit 408, which can comprise various logic configurations for providing controlled clock signals.

[0026] Independent charging circuit 406 is configured to address the high speed inaccuracies caused by glitch current requirements by suitably recharging the parasitic capacitances. Thus, rather than utilizing the reservoir capacitor to supply the needed current, the current required for charging parasitic capacitances during charging of the pump capacitors can be supplied by independent charging circuit 406. Accordingly, the total voltage ripple can be significantly reduced.

[0027] With reference to FIG. 5, in accordance with an exemplary embodiment of the present invention, a schematic diagram of an exemplary charge pump circuit 500 is illustrated. Charge pump circuit 500 comprises a dual phase charge pump doubler 502 configured with a regulation loop 504 and an independent charging circuit 506. In accordance with this embodiment, dual phase charge pump doubler 502 comprises four switches S5, S6, S7 and S8 and a second pump capacitor CPUMP2 configured for supplying current to drive a load device, i.e., discharging, during a first phase, e.g., when CLOCK1 signal is high and CLOCK2 signal is low, four switches S1, S2, S3 and S4 and a first pump capacitor CPUMP1 configured for supplying or discharging current to the load device during a second phase, e.g., when CLOCK2 signal is high and CLOCK1 signal is low, and a reservoir capacitor CRES for maintaining a substantially constant output voltage at the load device. Although switches S3, S4, S7 and S8 are latch triggered, i.e., the gates of switches S3 and S4 are driven by the drains of switches S7 and S8, while the gates of switches S7 and S8 are driven by the drains of switches S3 and S4, switches S3, S4, S7 and S8 can also be suitably driven by level-shifted clock signals in phase with CLOCK1 and CLOCK2.

[0028] Pump capacitors CPUMP1 and CPUMP2 include parasitic capacitances CPAR1 and CPAR2 and parasitic capacitances CPAR3 and CPAR4, respectively. Parasitic capacitances CPAR1, CPAR2, CPAR3 and CPAR4 can be configured with different capacitance values, for example, with parasitic capacitances CPAR1 and CPAR3 configured as the dominant parasitics, e.g., approximately 10% of the capacitance of pump capacitors CPUMP1 and CPUMP2, and parasitic capacitances CPAR2 and CPAR4 comprising smaller parasitics, e.g., approximately 1% of the capacitance of pump capacitors CPUMP1 and CPUMP2. Thus, for an exemplary embodiment of charge pump circuit 500 comprising pump capacitors CPUMP1 and CPUMP2 having capacitances of approximately 50 pF, parasitic capacitances CPAR1 and CPAR3 can have a capacitance of approximately 5 pF, while parasitic capacitances CPAR2 and CPAR4 can have a capacitance of approximately 0.5 pF. Further, selection of the dominant parasitic can be made based on the layout of the parasitics on the substrate, i.e., by selecting the parasitic on the side of pump capacitors CPUMP1 and CPUMP2 closest to the substrate.

[0029] Regulation loop 504 comprises an amplifier 505 and a regulated voltage VREG, which comprises the difference voltage forced between pump voltage VPUMP and supply voltage VSUPPLY. Amplifier 505 is configured to provide regulation of the slower requirements for charging current within charge pump circuit 500, regulating for example within approximately 3-5 MHz, or about 4 MHz of bandwidth, or about 125 nanoseconds for each phase. Amplifier 505 can be configured to provide a voltage output or a current output. Although regulation loop 504 is provided for regulation of slow speed inaccuracies, regulation loop 504 can be suitably modified or replaced by any circuit or device for addressing slow speed inaccuracies. As discussed above, for high speed inaccuracies caused by glitch current requirements of parasitic capacitances CPAR1, CPAR2, CPAR3 and CPAR4, regulation loop 504 is insufficient alone. However, independent charging circuit 506 is configured to address the high speed inaccuracies caused by glitch current requirements by suitably recharging parasitic capacitances CPAR1, CPAR2, CPAR3 and CPAR4, rather than requiring reservoir capacitor CRES to provide the glitch current.

[0030] Independent charging circuit 506 is configured local to charge pump circuit 500 for supplying the current for charging parasitic capacitances CPAR1, CPAR2, CPAR3 and CPAR4 during discharging of current by the respective pump capacitor, CPUMP1 or CPUMP2. Accordingly, the current for charging parasitic capacitances CPAR1, CPAR2, CPAR3 and CPAR4 can be locally supplied, rather from an external source through bussing or wire bonds that can introduce other sources of noise to charge pump circuit 500. In addition, independent charging circuit 506 can also comprise an independent cell, enabling independent charging circuit 506 to be suitably “tacked on” to various charge pump circuit configurations.

[0031] Independent charging circuit 506 is configured for supplying the current for charging parasitic capacitances CPAR1, CPAR2, CPAR3 and CPAR4 during the discharging of pump capacitors CPUMP1 and CPUMP2. For example, when charge pump doubler 502 operates to discharge pump capacitor CPUMP1, independent charging circuit 506 suitably provides the charging current required by parasitic capacitances CPAR1 and CPAR2, for a period such as approximately 10 nanoseconds. Once parasitic capacitances CPAR1 and CPAR2 are suitably charged, regulation loop 504, in addition to supplying current needed for maintaining regulation node 510, suitably recharges independent charging circuit 506 for the remainder of the approximately 125 nanoseconds of the first phase to prepare for the next phase. For the next phase, once charge pump doubler 502 operates to discharge pump capacitor CPUMP2, independent charging circuit 506 suitably provides the charging current required by parasitic capacitances CPAR3 and CPAR4, e.g., for approximately 10 nanoseconds. Once parasitic capacitances CPAR3 and CPAR4 are suitably charged during the initial phase of the discharge cycle of pump capacitor CPUMP2, regulation loop 504 suitably recharges independent charging circuit 506 for the remainder of the approximately 125 nanoseconds of the second phase to prepare again for the next phase.

[0032] Accordingly, by suitably charging parasitic capacitances CPAR1, CPAR2, CPAR3 and CPAR4 with independent charging circuit 506, regulation loop 504 can suitably drive pump capacitors CPUMP1 and CPUMP2 without requiring reservoir capacitor CRES to provide additional charge for the parasitics.

[0033] Independent charging circuit 506 can be configured in various manners for providing a charging current for parasitic capacitances CPAR1, CPAR2, CPAR3 and CPAR4. In accordance with an exemplary embodiment, independent charging circuit 506 comprises a parasitic charging capacitor CCHG configured with a pair of switch devices S9 and S10 to facilitate charging of the parasitics during both phases of operation of dual phase charge pump circuit 500.

[0034] Switch devices S9 and S10 can be controlled by clock signals CLOCK1 and CLOCK2, or by other clock signals configured to facilitate charging of parasitic capacitances CPAR1, CPAR2, CPAR3 and CPAR4 during discharging of pump capacitors CPUMP1 and CPUMP2. While switch devices S9 and S10 can comprise p-channel transistor devices, switch devices S9 and S10 can also comprise any other switch configuration. In addition, fewer or additional switch devices can be provided, based on the number of pump capacitors implemented within charge pump circuit 500.

[0035] Charging capacitor CCHG comprises a capacitor significantly larger than the largest parasitic capacitance. For example, charging capacitor CCHG can include a capacitance between approximately 2 to 40 times than that of the dominant parasitic capacitance, preferably from approximately 4 to 20 times larger. In accordance with an exemplary embodiment, charging capacitor CCHG comprises a 40 pF capacitor, as compared to an approximate 5 pF of dominant parasitic capacitances CPAR1 and CPAR3.

[0036] While independent charging circuit 506 comprises a pair of switch devices S9 and S10 configured for switching to charging capacitor CCHG, independent charging circuit 506 could also be configured for switching to a voltage source for charging parasitic capacitances CPAR1, CPAR2, CPAR3 and CPAR4. For example, rather than charging capacitor CCHG, a voltage follower could be suitably included within independent charging circuit 506 to charge parasitic capacitances CPAR1, CPAR2, CPAR3 and CPAR4. Moreover, any other device or circuit for providing a charge through switch devices S9 and S10 can be provided.

[0037] With reference to FIG. 6, in accordance with another exemplary embodiment, a schematic diagram of an exemplary dual phase charge pump circuit 600 is illustrated. Charge pump circuit 600 comprises a dual phase charge pump doubler 602 configured with a regulation loop 604, an independent charging circuit 606, a clock circuit 608. In accordance with this exemplary embodiment, dual phase charge pump doubler 602 comprises four switches S5, S6, S7 and S8 and a second pump capacitor CPUMP2 configured for supplying current during a first phase, four switches S1, S2, S3 and S4 and a first pump capacitor CPUMP1 configured for supplying current during a second phase, and a reservoir capacitor CRES for maintaining a substantially constant output voltage at the load device. Upper switches S3, S4, S7 and S8 are suitably driven by a latch triggered drive. Pump capacitors CPUMP1 and CPUMP2 include parasitic capacitances CPAR1 and CPAR2 and parasitic capacitances CPAR3 and CPAR 4, respectively.

[0038] Regulation loop 604 comprises an amplifier 605 and a regulated voltage VREG. Amplifier 605 is configured to provide regulation of the slower requirements for charging current within charge pump circuit 600. In accordance with this exemplary embodiment, amplifier 605 comprises transistor devices M6 and M7, and is configured for sensing differences in voltages VPUMP and VS +. However, amplifier 605 can comprise any amplifier configuration. Regulated voltage VREG is generated through transistors M0, M3 and M4, and provides a voltage forced between pump voltage VPUMP and supply voltage VS + during operation of regulation loop 604. A current source IBIAS is provided to generate regulated voltage VREG, and can comprise any current source configuration.

[0039] Independent charging circuit 606 comprises a parasitic charging capacitor CCHG configured with a pair of switch devices S9 and S10 to facilitate charging of the parasitics during both discharging phases of operation of dual phase charge pump circuit 600. However, independent charging circuit 606 can comprise any other configuration for supplying a charging current to parasitic capacitances parasitic capacitances CPAR1, CPAR2, CPAR3 and CPAR4.

[0040] Clock circuit 608 is configured to provide clock signals to drive switch devices S1, S2, S5, S6 and switch devices S9 and S10 during both phases of operation. In the exemplary embodiment, clock circuit 608 comprises a plurality of inverter devices, e.g., inverters 610, 612 and 614, configured to provide dual phase logic signals. However, any logic configuration can be implemented.

[0041] The present invention has been described above with reference to an exemplary embodiment. However, those skilled in the art will recognize that changes and modifications may be made to the exemplary embodiment without departing from the scope of the present invention. For example, the various components may be implemented in alternate ways, such as, for example, the changing of transistor devices from PMOS to NMOS transistors and the changing of the polarity of the charge pump circuits. In addition, various of the transistor devices can be suitably configured as bipolar devices. These alternatives can be suitably selected depending upon the particular application or in consideration of any number of factors associated with the operation of the circuit. In addition, the techniques described herein may be extended or modified for use with other integrated circuits separate from a charge pump circuit. These and other changes or modifications are intended to be included within the scope of the present invention, as expressed in the following claims.

Referenced by
Citing PatentFiling datePublication dateApplicantTitle
EP2544344A1Jul 4, 2011Jan 9, 2013Dialog Semiconductor GmbHTriple mode charge-pump.
Classifications
U.S. Classification363/59
International ClassificationH02M3/07
Cooperative ClassificationH02M3/07
European ClassificationH02M3/07
Legal Events
DateCodeEventDescription
Feb 24, 2012FPAYFee payment
Year of fee payment: 8
Feb 21, 2008FPAYFee payment
Year of fee payment: 4
May 10, 2005CCCertificate of correction
Sep 3, 2002ASAssignment
Owner name: TEXAS INSTRUMENTS INCORPORATED, TEXAS
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:BURT, RODNEY T.;ZHANG, HAORAN;BOTKER, THOMAS L.;AND OTHERS;REEL/FRAME:013260/0222
Effective date: 20020829
Owner name: TEXAS INSTRUMENTS INCORPORATED 13500 NORTH CENTRAL
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:BURT, RODNEY T. /AR;REEL/FRAME:013260/0222