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Publication numberUS20030182641 A1
Publication typeApplication
Application numberUS 10/312,419
PCT numberPCT/KR2001/001092
Publication dateSep 25, 2003
Filing dateJun 26, 2001
Priority dateJun 26, 1999
Also published asUS6701491, WO2001001245A1
Publication number10312419, 312419, PCT/2001/1092, PCT/KR/1/001092, PCT/KR/1/01092, PCT/KR/2001/001092, PCT/KR/2001/01092, PCT/KR1/001092, PCT/KR1/01092, PCT/KR1001092, PCT/KR101092, PCT/KR2001/001092, PCT/KR2001/01092, PCT/KR2001001092, PCT/KR200101092, US 2003/0182641 A1, US 2003/182641 A1, US 20030182641 A1, US 20030182641A1, US 2003182641 A1, US 2003182641A1, US-A1-20030182641, US-A1-2003182641, US2003/0182641A1, US2003/182641A1, US20030182641 A1, US20030182641A1, US2003182641 A1, US2003182641A1
InventorsSei-Yang Yang
Original AssigneeSei-Yang Yang
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Rapid input/output probing apparatus and input/output probing method using the same, and mixed emulation/simulation method based on it
US 20030182641 A1
Abstract
An input and output probe system software according to the present invention, which is performed in an arbitrary computer for server, adds an additional circuit for probe capable of the input/output prove, to the design verification and examination object circuit so as to generate an extended circuit capable of the input/output probe in an automatic system. Interface module of the input/output probe connects a hardware board, wherein the extended circuit capable of the input/output prove is embodied in a hardware chip and a computer for server. Said interface module controls the performance of the hardware board, performs the input/output prove against the hardware chip on the hardware board under the specific situation or condition, thereby enabling the exchange of information on the performance results in respect to the design verification and the examination object circuit between the computer for server and the hardware chip.
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Claims(34)
What is claimed is:
1. An input/output probing apparatus, comprising:
an input/output probing system software; and
an input/output probing interface module for connecting a circuit for its design verification,
wherein said input/output probing system software generates, for the circuit for its design verification to be embodied in at least one semiconductor chip mounted on an arbitrary prototyping board or an arbitrary PCB, a HDL code for representing an additional circuit for IOP-probe or the behavior of said additional circuit for IOP-probe, and adds said HDL code for representing said additional circuit for IOP-probe or the behavior of said additional circuit for IOP-probe to said circuit for its design verification or the HDL code,
thereby making it possible to embody said circuit for its design verification capable of doing the input/output probe in said semiconductor chip and to perform said input/output probe by using HDL code for representing said additional circuit for IOP-probe or the behavior of the additional circuit for IOP-probe.
2. The input/output probing apparatus according to claim 1,
wherein said HDL code for representing said additional circuit for IOP-probe or the behavior of the additional circuit for IOP-probe is automatically generated by performing said input/output probing system software.
3. The input/output probing apparatus according to claim 2,
wherein before automatically generating said HDL code said input/output probing system software, the circuit for its design verification or said HDL code for its design verification is examined by the input/output probing system software; and
wherein a new circuit for its design verification or a new HDL code for its design verification, which is functionally equivalent to the original circuit or the original HDL code and which is completely synchronized with a single clock and converted to, is automatically generated to perform the input/output probe.
4. The input/output probing apparatus according to claim 2 or claim 3,
wherein said input/output probing system software additionally generates a event detector for detecting the conversion condition into a probe mode for the input/output probe to realize the event detector in the inside of said semiconductor chip.
5. The input/output probing apparatus according to claim 4, further comprising an extended circuit for its design verification which is completed by adding the additional circuit for IOP-probe to the circuit for its design verification,
wherein in an output probe mode, said extended circuit becomes a shift register structure capable of parallel-loading a storage element for its output probe to carry out the shifting operation synchronized with a probe clock, so that the logical values of said shift register can have the logical values of the storage elements for its output probe by parallel-loading just before said shifting operation, and thus the content of a corresponding region of the memory for its output probe can be read with a reading operation;
wherein in an input probe mode, said extended circuit becomes the shift register structure capable of serial-loading a storage element for its input probe to carry out the shifting operation, and wherein a synchronous set or reset operation, or the synchronous set or reset operation subsequent to an asynchronous set or reset operation, or a synchronous disable operation subsequent to the asynchronous set or reset operation is selectively applied to each of the storage elements for its input probe by such shifting operation, thus making the logical values of the storage elements for its input probe the input probe values, and thus a corresponding region of the memory for its input probe can be written by a writing operation when necessary; and
wherein in a normal mode, a circuit, which does not change the functional logical properties of the circuit for its design verification even if the additional circuit for IOP-probe is added thereto is constructed.
6. The input/output probing apparatus according to claim 4, further comprising an extended HDL code for its design verification which is completed by adding an additional HDL code for representing the behavior of the additional circuit for IOP-probe to the HDL code for its design verification when the circuit for its design verification object is dictated as the HDL code,
wherein in an output probe mode, said extended HDL code represents the behavior of the shift register, which is capable of parallel-loading the storage element for its output probe, to carry out the shifting operation synchronized with the probe clock, so that signal values of signal lines of a register HDL code can have the signal values for output probe by parallel-loading in the HDL code for representing the behavior of the shift register just before said shifting operation, and thus a specific region of the memory for its output probe can be read by a reading operation;
wherein in an input probe mode, said extended HDL code becomes the shift register structure, which is capable of serial-loading with the storage element for its input probe, to carry out the shifting operation synchronized with the probe clock, wherein the synchronous set or reset operation, or the synchronous set or reset operation subsequent to the asynchronous set or reset operation, or the synchronous disable operation subsequent to the asynchronous set or reset operation is applied to the signals of the HDL code by such shifting operation, the HDL code representing the behavior of storage elements of the HDL code for its input probe, thus making the logic values of signals for input probe the input probe values, and thus a corresponding region of the memory for its input probe can be written by the writing operation when necessary; and
wherein in the normal mode, a HDL code, which does not change the behavior of the HDL code for its design verification changed even if the additional circuit for IOP-probe is added to the HDL code for its design verification, is constructed.
7. The input/output probing apparatus according to claim 5 or 6,
wherein in the output probe mode, the extended circuit for its design verification added with the additional circuit for IOP-probe become at least one shift register array structure capable of parallel-loading the storage elements for output probe by the signals for output probe and the double input flip-flops together with the circuit for its design verification assigned to the RFPD for output probe, while one input by said each of the double input flip-flops is connected to the signal lines for probe in order that each of the signal lines for probe can be loaded in parallel into said double input flip-flop; the output of a single flip-flop existing in each one of at least one shift register array structure is logically connected, respectively, to one of at least one output probe line of said RFPD at the time of the output probe; additionally when necessary, for the memory for output probe, the output of a single flip-flop existing in the respective shift register array structures which store the contents read by the reading operation of the corresponding region by the finite state machine for memory probe embedded in the corresponding RFPD, is appeared on at least one output probe line of said RFPD by the shift operation;
wherein in the input probe mode, the input of a single flip-flop existing in each one of at least one shift register array structure capable of parallel-loading the storage elements for input probe is logically connected, respectively, to one of at least one input probe line of said RFPD in order that the input probe values can be loaded in series into the shift register by the shifting operation synchronized with the probe clock; in case that a user clock is connected to clock input of the respective storage elements driving each of the signals for input probe, the output of the respective flip-flops constructing at least one shift register array capable of said parallel-load is connected to a single input of each of the double input storage elements replaced for each of the corresponding storage elements, or a combination circuit is added to a data input terminal of said storage element in order that each of the corresponding storage elements becomes a synchronous set or synchronous reset by the output value of the respective flip-flops constructing at least one shift register array capable of said parallel-load; in case where the user clock is not physically connected to the clock input of the corresponding storage element for each of the storage elements deriving each of the signal lines for input probe, the corresponding storage element is constituted as a storage element having an asynchronous set and asynchronous reset, and the combination circuit for controlling the asynchronous set input and asynchronous reset input of said storage element is added, so that the logical value of said storage element can be established as a specific input probe value desired through a process including the asynchronous set or asynchronous reset operation for said storage element; additionally when necessary, for the memory for input probe, the logical values are assigned from at least one input probe line of said RFPD to each of the inputs of the first terminal flip-flop existing in each of the shift register array structures in the memory data input terminal by the shifting operation, in order that after the shifting operation of the shift register in said memory data input terminal is completed, the input probe for the memory can be performed in the writing operation to said specific address of the memory by the subsequent finite state machine for memory probe, the memory having the contents to be written in the specific address by the writing operation of the corresponding region.
8. The input/output probing apparatus according to claim 5 or 6,
wherein the shift register array of the additional circuit for IOP-probe is constructed by connecting double input flip-flops in series, or the HDL code corresponding to the behavior of shift register array of the HDL code representing the behavior of the additional circuit for IOP-probe is constructed as the HDL code representing the behavior of double input flip-flops in series.
9. The input/output probing apparatus according to claim 8, wherein a physically identical probe clock is assigned to all clock inputs of the double input flip-flops of the shift register array of the additional circuit for IOP-probe, and the control over the probe clock and at least one user's clock is performed by an interface module for its input/output probe and the input/output probing system software.
10. The input/output probing apparatus according to claim 7, wherein the output probe line and the input probe line exist as individually independent unidirectional probe lines.
11. The input/output probing apparatus according to claim 7, wherein the output probe line and the input probe line exist as bi-directional probe lines in which the output probe line and the input probe line are mutually combined.
12. A combined verification apparatus of emulation and simulation, comprising an input/output probing system software capable of automatically generating an additional circuit for IOP-probe and an interface module of the input/output probe, wherein the emulation and simulation are alternately performed.
13. The input/output probing apparatus according to claim 12, wherein the input/output probing system software can automatically generate a detector of the input/output probe point.
14. An input/output probing method using an input probe method,
wherein in a circuit for its design verification for input probe, for the input probe of at least one flip-flop, in which a user clock is not directly assigned to a clock input of at least one flip-flop existing in the circuit for its design verification; rather, a locally generated local clock or gated clock is inputted thereto, there is generated the extended circuit for its design verification by adding a finite state machine, which generates a shift register array structure capable of serial-load and asynchronous set/reset enabling signals at a specific point of time and then outputs them, and the additional circuit for input probe having a control circuit to the circuit for its design verification;
wherein in input probe mode, after loading input probe values to said shift register array structure from the outside in order via the serial-loading synchronized with the probe clock, there are generated an input probe value of flip-flops to be an corresponding input probe object among the input probe values loaded to the respective flip-flops of said shift register array; an asynchronous set/reset enabling output value for the flip-flop to be said input probe object, the asynchronous set/reset enabling output value being generated from said finite state machine; and signal values for controlling the asynchronous set and reset of the flip-flop, so that the input probe is accomplished by said signal values in the input probe mode through a process including the operation for controlling the asynchronous set and reset inputs of the flip-flop for input probe; and
wherein in normal operation mode, the extended circuit for its design verification generated by adding said additional circuit for input probe to the original circuit for its design verification can perform the operation functionally equivalent to the original circuit for its design verification.
15. A combined verification method of emulation and simulation, wherein an emulation method for verifying the extended circuit for its design verification realized by adding an additional circuit for IOP probe to a circuit for its design verification by at least one semiconductor chip, and a simulation method for verifying the circuit for its design verification by a simulator are alternately performed at least once when necessary, through the exchange of the state information in an automatic method between an arbitrary prototyping board or an arbitrary PCB and an arbitrary simulator, by performing the input/output probe for at least one semiconductor chip.
16. The combined verification method of emulation and simulation according to claim 15, wherein the exchange of the complete state information in the automatic method between the arbitrary prototyping board or PCB and the arbitrary simulator is used by the input/output probe based on the additional circuit for IOP-probe.
17. The combined verification method of emulation and simulation according to claim 15, wherein the exchange of the partial state information in the automatic method between the arbitrary prototyping board or PCB and the arbitrary simulator is used by the input/output probe based on the additional circuit for IOP-probe.
18. A combined verification method of emulation and simulation, comprising the steps of:
preparing the performance of simulation of a circuit for its design verification using an arbitrary simulator in a server computer, where the circuit for its design verification and the name of ASIC vendor library used at the time of the design are inputted by the server computer, and then, the extended circuit for its design verification added with an additional circuit for IOP-probe capable of input/output probe is generated in an automatic method by an input/output probing system software, thereby realizing said extended design verification object circuit in a prototyping board on which at least one semiconductor chip is equipped;
determining the present execution mode, where the initial state information of the circuit for its design verification to be a combined verification object is inputted by the server computer in order that the present state information of a simulation circuit for said arbitrary simulator and an emulation circuit in said arbitrary prototyping board or arbitrary PCB would be the same as the initial state information of the circuit for its design verification, thereby determining whether the first performance is carried out by simulation or emulation; and determining the execution mode switching conditions between simulation and emulation under the execution process and storing the determined execution mode switching condition in the execution mode switching condition queue in time order, and then, making the first queue the conversion point and the conversion condition of the present verification method;
proceeding with the design verification by either of the emulation or simulation, which should be suitable for the present execution mode;
performing the design verification which is different from the conventional design verification method but subsequent to the conventional design verification method, through the exchange of the present state information, by an input/output probing method using the additional circuit for IOP-probe realized in at least one semiconductor chip equipped on said arbitrary prototyping board or arbitrary PCB and an input/output probing apparatus, where the performance of the present design verification method is stopped at the point when the conversion point or conversion condition of the present verification method is satisfied; new conversion point and conversion condition of the present verification method are established in the execution mode switching queue; the present execution mode is converted to different execution mode to execute the emulation; and
continuing to alternately perform at least once the design verification method as above between emulation and simulation till the execution mode switching queue is vacant.
19. A combined verification method of emulation and simulation, comprising the steps of:
preparing the performance of simulation of a circuit for its design verification using an arbitrary simulator in a server computer, where the circuit for its design verification and the name of ASIC vendor library used at the time of the design are inputted by the server computer, and then, the extended circuit for its design verification added with an additional circuit for IOP-probe capable of input/output probe is generated in an automatic method by an input/output probing system software, thereby realizing said extended design verification object circuit in a prototyping board on which at least one semiconductor chip is equipped;
determining the present execution mode, wherein the initial state information of the circuit for its design verification to be a combined verification object is inputted by the server computer in order that the present state information of a simulation circuit for said arbitrary simulator and an emulation circuit in said arbitrary prototyping board or arbitrary PCB would be the same as the initial state information of the circuit for its design verification, thereby determining whether the first performance is carried out by simulation or emulation; and determining the execution mode switching conditions between simulation and emulation under the execution process and storing the determined execution mode switching condition in the execution mode switching condition queue in time order, and then, making the first queue the conversion point and the conversion condition of the present verification method;
proceeding with the design verification by either of the emulation or simulation, which should be suitable for the present execution mode;
performing the design verification which is different from the conventional design verification method but subsequent to the conventional design verification method, through the exchange of the present state information, by an input/output probing method using the additional circuit for IOP-probe realized in at least one semiconductor chip equipped on said arbitrary prototyping board or arbitrary PCB and an input/output probing apparatus, where the performance of the present design verification method is stopped at the point when the conversion point or conversion condition of the present verification method is satisfied; new conversion point and conversion condition of the present verification method are established in the execution mode switching queue; the present execution mode is converted to different execution mode to execute the emulation; and
continuing to alternately perform at least once the design verification method as above between emulation and simulation till the execution mode switching queue is vacant.
20. A combined verification method of emulation and simulation, comprising the steps of:
preparing the performance of simulation of a HDL code for its design verification by an arbitrary simulator in a server computer, where the HDL code for its design verification is inputted by the server computer, and then, an extended HDL code for its design verification added with an additional HDL code for IOP-probe capable of input/output probe is generated in an automatic method by an input/output probing system software, thereby realizing said extended HDL code for its design verification in a prototyping board on which at least one semiconductor chip is equipped;
determining the present execution mode, where the initial state information of the HDL code for its design verification to be a combined verification object is inputted by the server computer in order that the present state information of a simulation HDL code for said arbitrary simulator and an emulation HDL code in said arbitrary prototyping board or arbitrary PCB would be the same as the initial state information of the HDL code for its design verification, thereby determining whether the first execution is carried out by simulation or emulation; and determining the execution mode switching conditions between simulation and emulation under the execution process and storing the determined execution mode switching condition in the execution mode switching condition queue in time order, and then, making the first queue the conversion point and the conversion condition of the present verification method;
proceeding with the design verification by either of the emulation or simulation, which should be suitable for the present execution mode;
performing the design verification which is different from the conventional design verification method but subsequent to the conventional design verification method, through the exchange of the present state information, by an input/output probing method using the additional HDL code for IOP-probe realized in at least one semiconductor chip equipped on said arbitrary prototyping board or arbitrary PCB and an input/output probing apparatus, where the performance of the present design verification method is stopped at the point when the conversion point or conversion condition of the present verification method is satisfied; new conversion point and conversion condition of the present verification method are established in the execution mode switching queue; the present execution mode is converted to different execution mode to execute the emulation; and
continuing to alternately perform at least once the design verification method as above between emulation and simulation till the execution mode switching queue is vacant.
21. Input/output probing method, comprising the steps of:
inputting a name of ASIC vendor library and a circuit for its design verification, or a HDL code for its design verification;
inputting a signal line for its input/output probe;
generating an extended circuit for its design verification by adding an additional circuit for IOP-probe to the circuit for its design verification after the additional circuit for IOP-probe is generated according to its corresponding semiconductor chip on a prototyping board, or generating an extended HDL code for its design verification by adding an additional HDL code for IOP-probe to the HDL code for its design verification after the additional HDL code for IOP-probe is generated;
embodying the extended circuit for its design verification or the extended HDL code for its design verification in their corresponding semiconductor chips on the prototyping board;
performing a circuit verification process in a normal mode;
examining the necessity of the probe performance and whether said probe performance is an output probe;
performing an input probe by assigning data for input probe to an input probe line, via an input/output probing interface module in a server computer after converting the data for input probe generated in the server computer to the input probe mode; and
completing the output probe by transmitting a value appeared on an output probe line, the value being generated by performing the output probe after conversion of the value to the output probe mode, to the server computer via the input/output probing interface module.
22. The input/output probing apparatus according to claim 1, wherein a semiconductor chip is FPGA, CPLD or a ASIC chip.
23. The combined verification method of emulation and simulation according to any one of claims 15 to 20, which said simulator is a simulation accelerator.
24. The combined verification method of emulation and simulation according to any one of claims 15 to 20, wherein said method is carried out by an input/output probing apparatus comprising:
an input/output probe server computer for performing a input/pout probe system software which performs the input/output probe on the prototyping board connected to the input/output probing interface module;
a simulation server computer for performing the simulation; and
a simulation accelerator server computer;
wherein the input/output probe server computer and the simulation server computer, or the input/output probe server computer and the simulation accelerator server computer are connected to each other, through a short/long-distance computer network or inter-network, so that they are performed in a remote method based on the input/output probing method using the input/output probing apparatus under a network environment where emulation and simulation are distributed.
25.
26.
27. A combined verification method of emulation and simulation, wherein the input/output probe is made by embodying an extended circuit for its design verification added with an additional circuit for IOP-probe in at least one RFPD equipped on an arbitrary at least one prototyping board or an arbitrary PCB,
wherein the simulation subsequent to the emulation is possible by transmitting complete state information or partial state information, which is extracted from the extended circuit for design verification in said at least one RFPD at the time of the output probe, to a server computer via an interface module, and
wherein the emulation of the circuit for its design verification is possible subsequent to the simulation by transmitting the complete state information or the partial state information extracted from an arbitrary simulator, in which a software model of the circuit for its design verification is performed at the time of the input probe, to said at least one RFPD via the interface module.
28. The combined verification method of emulation and simulation according to claim 27, wherein the emulation and simulation are alternately performed at least once, and at least one RFPD equipped on said at least one arbitrary prototyping board or arbitrary PCB is temporally and spatially shared among two or more variously different circuits for their design verification,
29. The combined verification method of emulation and simulation according to claim 27 or 28, wherein the extended circuit for its design verification added with the additional circuit for IOP-probe is realized in at least one RFPD mounted on the arbitrary prototyping board or arbitrary PCB so as to make the input/output probe possible; wherein the complete state information or the partial state information is extracted in real time from the extended circuit for its design verification performed on said at least one RFPD whenever at least one output probe is periodically or non-periodically performed during the emulation, operating the circuit for its design verification included in the extended circuit for its design verification throughout the entire emulation process without stopping, and then, the extracted information is transmitted to the server computer through the interface module so as to establish at least one roll-back point; simultaneously, wherein an input sequence is sampled in real time in memory during the emulation so as to replay the emulation when necessary; wherein during a certain period of time desired by a user after the emulation is completed, some signals values for output-probing among all signals existing in the circuit for its design verification or the HDL code for its design verification is obtained by performing both the emulation using the input sequence stored in said memory and the simulation using the arbitrary simulator when necessary, through the input probe using said extracted state information as to said at least one RFPD, after making the state of the circuit for its design verification realized in said at least one RFPD the same as one of the state of said at least one roll-back point.
30. The combined verification method of emulation and simulation according to claim 27 or 28,
wherein the extended circuit for its design verification added with the additional circuit for IOP-probe is realized in at least one RFPD equipped on the arbitrary prototyping board or arbitrary PCB so as to make the input/probe probe possible;
wherein the complete state information or the partial state information is extracted from the extended circuit for its design verification performed on said at least one RFPD whenever at least one output probe is periodically or non-periodically performed during the emulation, temporarily stopping the circuit for its design verification included in the extended circuit for its design verification only during a certain period of time of the output probe process, and then, the extracted information is transmitted to the server computer through the interface module so as to establish at least one roll-back point; simultaneously, the input sequence is sampled in real time per every clock during the emulation when necessary, without stopping the circuit for its design verification, through the output probe of the input signals inside said RFPD, and then, the sampled input sequence is temporarily stored in the embedded memory existing inside said RFPD;
wherein the circuit for its design verification is temporarily stopped to read data stored in said embedded memory, and then, the data as read is transmitted to the server computer through very small numbers of at least one output probe line provided in said RFPD via the interface module in order and then stored in the memory so as to replay the emulation; simultaneously, in case where DRAM or SDRAM is used together with RFPD in said arbitrary prototyping board or arbitrary PCB, for specific control signal lines connected to DRAM or SDRAM in RFPD, a specific single value or a transition value is assigned during such transmission process of the probe data so that refresh or auto-refresh of DRAM or SDRAM is made possible and the data loss of DRAM or SDRAM during the transmission process is prevented;
wherein during a certain period of time desired by a user after the emulation is completed, the probe of signals for probe, the signals existing in the circuit for its design verification or the HDL code for its design verification, is obtained by performing both the emulation using the input sequence stored in said memory and the simulation using the arbitrary simulator when necessary, through the input probe using said extracted state information as to said at least one RFPD, after making the state of the circuit for its design verification realized in said at least one RFPD the same as the state of said at least one roll-back point.
31. The combined verification method of emulation and simulation according to claim 27, wherein the emulation of the circuit for its design verification having a circuit portion needed for a design correction is performed with high speed in at least one RFPD on the arbitrary rapid prototyping board or arbitrary PCB which realizes the entire circuit for its design verification, for which the design correction is not made, as the extended circuit for its design verification added with the additional circuit for IOP-probe, thereafter, the simulation of a partial portion of the circuit for its design verification, the design of the partial portion being corrected by the output probe using the result of such emulation, is performed in the server computer, and the results of said circuit portion which is not corrected in design, being performed by the emulation through the input probe using the result of such simulation, are corrected, thereby enabling the right emulation of the entire circuit for its design verification.
32. The combined verification method of emulation and simulation according to claim 30, wherein in case that a memory existing in a user circuit for its design verification is realized by an on-chip memory in RFPD, for the output probe of the memory existing in said user circuit, the contents of said on-chip memory are copied in real time as a separate probe data storage memory, without temporarily stopping the user clocks or slowing them than the original user clocks by using said separate probe data storage memory, thereafter, the contents stored in the probe data storage memory are read.
33. The combined verification method of emulation and simulation according to claim 30, wherein in case that the memory existing in the user clock for its design verification is embodied by an off-chip memory on the arbitrary prototyping board, for the output probe of the memory existing in said user circuit, the contents of said off-chip memory are copied in real time as a separate probe data storage memory, without temporarily stopping the user clocks or slowing them than the original user clocks by using said separate probe data storage memory, thereafter, the contents stored in the probe data storage memory are read.
34. The combined verification method of emulation and simulation according to claim 32 or 33, wherein for the output probe of the memory existing in the user circuit, a tag is maintained in said separate probe data storage memory, for read/write at a specific address of the user circuit memory the read is performed with either said specific address or the predetermined address in pre-determined order of the user circuit memory at a first period of a system clock, which is two times faster than a user clock, so as to store the read data at the same address in the probe data storage memory and to modify said corresponding tag, and then, the original reading/writing at said specific address in the user circuit memory is performed at the second period of the system clock.
Description
BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a technology of the design verification and the test of a designed digital circuit, particularly to input/output probing apparatus and input/output probing method using the same capable of realizing the designed digital circuit as a programmable chip or semiconductor chip in an actual hardware manner and rapidly facilitating a process of the design verification and the test based on emulation. Furthermore, the present invention relates to a combined verification method of emulation and simulation and a combined verification device for the above that realizes the designed digital circuit by a programmable chip or application specific semiconductor chip in an actual hardware manner and that performs the verification followed by the automatic conversion during the verification process based on emulation as a simulator executed on the computer based on simulation, or to the contrary that performs the verification followed by the automatic conversion during the verification process based on simulation as a simulator executed on the computer based on emulation, and that can verify by alternately more than once repeating the above emulation and simulation.

[0003] 2. Description of Prior Art

[0004] Recently as the design of an integrated circuit and the processing technology of a semiconductor have rapidly improved, it is a tendency that the scale of a digital circuit design has increased as well as the constitution thereof has been complicated. Along with this, since competition in the market becomes still fiercer, a superior product should be developed in a short time. Therefore, there has been a great need for an effective method to efficiently verify and test a designed circuit in a short time.

[0005] Up to now, a simulator, an access in the form of software, is mainly used for the design verification of the designed digital circuit. Since the verification method based on simulation using a simulator is able to use various delay models for the circuit, it has the advantages that the timing verification as well as the functional verification are possible, a perfect visibility to all signal lines existing within the circuit during the debugging process is provided, etc.

[0006] However, since the simulator should sequentially perform a software code comprising a sequential instruction sequence modeling a design verification circuit in a software manner on the computer, there are limits that the verification takes very long time and due to the combination with other peripheral hardware environment the verification (referred to as ICE, In-Circuit Emulation) of the entire system is not possible. Moreover, since the capacity of a computer depending on the simulation software and the single processor is not able to compete with the complexity of a digital circuit with tens of millions of gate-level which is rapidly on the increase, recently for a general design verification the verification based on simulation needs a long time beyond imagination of only the simulation.

[0007] Meanwhile, the design verification method based on emulation in a hardware manner that realizes the designed circuit as an actual chip and uses the realized chip verifies a digital circuit in the situation that all constituents of the designed digital circuit are virtually operated in parallel on the chip as realized. Hence, the emulation-basis design verification is possible at the maximum speed of about a million times as fast as the simulation-basis design verification and the ICE environment is formed with other peripheral hardware environment, which make it possible the combined verification.

[0008] However, compared to the simulation, the emulation has a disadvantage to be very inconvenient in performing the debugging. Its major reason is that the visibility which tells the logic values of many signal lines existing in the circuit realized in programmable chips or application specific semiconductor chips excessively gets worse compared to the simulation.

[0009] As a core device for the design verification based on emulation, programmable chips, Reusable Field Programmable Devices (hereinafter, referred to as ‘RFPD’) is used. There are Field Programmable Gate Array (FPGA) and Complex Programmable Logic Device (CPLD) in such RFPD. Since recently the degree of integration of RFPD becomes very high owing to the development of the semiconductor technology, the prototyping of the very complex digital circuit has been possible just by using single RFPD or very small numbers of RFPD. Contrary to the realization of circuit using an application specific semiconductor chip, there are advantages that the realization of circuit using such RFPD is possible with small costs on the spot and can considerably reduce the time and costs rendered for correction of bug as found.

[0010] The present invention, due to the realization of a design verification circuit, is a method applicable to the case of using an application specific semiconductor chips using the art of a standard cell or gate array as well as RFPD chips. The Embodiment thereof will be explained supposing, for convenience, that RFPD is used.

[0011] The highly integrated semiconductor art has resulted in economical prototyping. However, most of the numerous signal lines existing on the digital circuit for its design verification exist within the RFPD when prototyping, thereby making probe of the signal lines very difficult and bringing out a very serious problem that its visibility for the debugging gets worse. Such will be emerged a major problem even in the future RFPD with the higher degree of integration is used.

[0012] In order to solve such problem, a method capable of probing effectively and rapidly even in the case the signal lines existing in the circuit exist within the chips is necessary so that an effective and rapid debugging is possible for the circuit realized in RFPD to be a design verification object.

[0013] Furthermore, for the design verification of the digital circuit, to properly use emulation method and simulation method alternately during the process of the design verification is a method to maximize the effectiveness of the verification. That is, the design verification is based on emulation and functional verification at high speed is performed at a specific point or situation requiring very detailed verification. And at this time the verification method is automatically converted from emulation-basis to simulation-basis, thereby either functional verification or timing verification is performed with the 100% perfect visibility for the circuit to be verified. Further, if necessary, performance of the verification by repeating such conversion between emulation and simulation more than once is a method to maximize the effectiveness of the verification.

[0014] However, in case of the design verification of a hardware board arbitrarily realized by installing a number of programmable chips, RFPD, or a general application specific semiconductor chips the digital circuit designed by a designer in the emulation-basis environment, up to now there is no input/output device and input/output method using the same with an open architecture that is not confined to a specific hardware board or specific emulation equipment and that is able to perform the debugging rapidly and effectively regarding all arbitrary hardware prototyping or emulation boards. Further, because of some reasons (for example, in order to minimize the consumption of electricity), in the digital circuit design it is very usual for designers to design a circuit using gated clocks or locally generated clocks rather than a synchronized clock. Hence, such asynchronous factors make an input/output probe, particularly input probe, for a circuit very difficult and there does not exist an input/output method applicable to all situations with no restriction to any design methods.

[0015] In addition, there has been no combined verification method and combined verification device by using emulation and simulation together as described above, clearing up disadvantages of the verification method based on emulation by combining the verification method based on simulation and the verification method based on emulation. In particular, in case emulation should be performed subsequently to the performance of simulation, it is necessarily required that storage elements and memory existing in the circuit realized in the RFPD performing emulation have the logical values of storage element (flip-flop or latch) and memory (RAM or ROM) of the circuit for its design verification at the present point which are obtained after the performance of simulation, before the start of emulation

[0016] However, there has also been no method that is free to exchange the logical values of the storage elements existing in the circuit realized in RFPD for the specific logical values obtained as a result of simulation in the asynchronous situation that gated clocks or locally generated clock signal is assigned in the clock input of the storage elements existing in the circuit for its design verification. In particular, in the ICE environment, it is impossible to usually control (for example, to temporarily discontinue or proceed more than eleven user clocks) a user circuit and at least one user clock that inflicts to target environment as it planned. Under such circumstances, an input/output probing method becomes more difficult and further any counter methods are not suggested.

[0017] Recently owing to the development of internet technology, it is usual that at least one designer performing the design of a digital circuit, at least one software for design, at least one arbitrary simulator, at least one arbitrary hardware board for emulation, at least one server computer are connected through network as they are geographically distributed rather than crowded in a single place. Simulator or hardware board or emulator constituting such environment is not a specific product but one of various products providing many vendors. For example, simulators are ModelSim of Model Tech company, VCS of Synopsys company, Nsim of Cadence company, Riviera of Aldec company, etc. and emulators are Mercury-plus of Cadence company, Celaro of Mentor Graphics Corp., V-Station of IKOS company, MP of Aptix company, etc. and hardware boards are products realized by various technologies such as prototyping board manufactured by itself. As such, the characteristic of each environment is very heterogeneous. Under such distributed environment that an arbitrary simulator and an arbitrary hardware board exist far apart geographically, there is no method of performing emulation and simulation for one circuit for its design verification alternately at high speed by using the time division method through short- and long-distance network or inter-network. Time division method can provide many users with a method of effectively sharing an arbitrary hardware-basis verification apparatus over the network, whereas there has been no method of providing an arbitrary prototyping board or an arbitrary PCB with such function.

[0018] Further, a field applicable to such art can be applied to the step of testing a circuit after its manufacture as well as the step of the design verification of a circuit. There is a scan method widely used for such circuit verification. However, there is a fatal problem that the scan does not provide any methods controllable for the storage element that uses gated clocks or locally generated clocks mentioned above. The input/output probing method according to the present invention that will be specifically described later basically provides a perfect controllability and observability regarding all storage elements existing in a circuit and thus could be also superior to the scan method in view of the circuit verification.

[0019] The method capable of performing emulation and simulation alternately suggested in U.S. Pat. No. 5,937,179 which was filed by Texas Instrument (TI) uses the scan chain mentioned above, a generally known art in the circuit verification. It is uncontrollable for the input probe for the storage elements regarding the circuit having even one storage element that uses gated clocks or locally generated clocks indicated in the above patent.

[0020] Therefore, a perfect input probe control regarding storage elements is possible in the method suggested in the present invention, whereas the combined emulation/simulation verification can not be applied to a circuit with an asynchronous factor but only to 100% synchronous circuits wherein the same clock is assigned to all storage elements existing in the circuit. Further, there is a very serious problem that it cannot be applied to an arbitrary hardware board since it has no open architecture.

[0021] Further, in case RAM or ROM exists in a user circuit and such memory is realized by using on-chip memory (specifically, Distributed RAM or BlockRAM of Xilinx FPGA, Embedded Array Block of Altera FPGA, etc.) or off-chip memory existing within the RFPD, the method suggested in the above TI patent can not probe in real time the contents of such on-chip memory or off-chip memory unless a user clock is temporarily discontinued or slowed down by at least tens times during the process of output probe. Thus, there is a fatal problem that is cannot be applied to the ICE environment

SUMMARY OF THE INVENTION

[0022] Accordingly, it is an object of the present invention, for an effective design verification and test of a digital circuit, that an input/output probing system software adds an additional circuit for the input/output probe to a circuit and thus automatically generating an extended circuit capable of input/output probe thereby realized, and the input/output probe for any arbitrary prototyping board or arbitrary PCB can be performed using an interface module of the input/output probe, thereby enabling a rapid and effective debugging.

[0023] It is another object of the present invention to perfectly provide a method capable of the combined performance of simulation using an arbitrary simulator and emulation using an arbitrary prototyping board or an arbitrary PCB (Printed Circuit Board) manufactured by mounting semiconductor chips wherein a circuit is realized by using the above input/output probing apparatus and input/output probing method even in an extremely difficult situation, the ICE environment requiring a real-time operation, in the case of using on-chip memory or off-chip memory within the RFPD.

[0024] Herein below, referring to the drawings attached a rapid input/output probing apparatus and input/output probing method using the same and combined emulation/simulation method based on the above according to the present invention are more specifically explained.

BRIEF DESCRIPTION OF THE DRAWINGS

[0025]FIG. 1 illustrates schematically an input/output probing apparatus according to the present invention.

[0026]FIG. 2A illustrates schematically an example of realization of an additional circuit for memory probe by a finite state machine for probing memory.

[0027]FIG. 2B illustrates schematically another example of realization of an additional circuit for memory probe by a finite state machine for probing memory.

[0028]FIG. 3 illustrates an example of an asynchronous circuit and a 4-bit asynchronous binary counter

[0029]FIG. 4A and FIG. 4B illustrate schematically symbol and function of single input D-type flip-flop having one data input (D).

[0030]FIG. 4C and FIG. 4D illustrate schematically symbol and function of single input D-type flip-flop having one data input (D) and asynchronous set/reset input (AR/AS).

[0031]FIG. 4E and FIG. 4F illustrate schematically symbol and function of double input D-type flip-flop having two data inputs (D1, D2).

[0032]FIG. 4G and FIG. 4H illustrate schematically symbol and function of double input D-type flip-flop having two data inputs (D1, D2) and enable (EN) input.

[0033]FIG. 4I and FIG. 4J illustrate schematically symbol and function of D-type flip-flop having data input (D) and asynchronous set (AS) and asynchronous reset (AR), and synchronous enable (EN) input.

[0034]FIG. 5 illustrates schematically an example of a shift register array structure wherein parallel-load and serial-load are possible according to input/output mode that indicates an additional circuit for IOP-probe relating to the present invention.

[0035]FIG. 6 illustrates schematically another example of a shift register array structure wherein parallel-load and serial-load are possible according to input/output mode as shown in FIG. 5.

[0036]FIG. 7 illustrates schematically an example of realizing the double input D-type flip-flop as shown in FIG. 4A.

[0037]FIG. 8A illustrates schematically a situation that an additional circuit for IOP-probe is added to the circuit for its design verification as shown in FIG. 3.

[0038]FIG. 8B illustrates schematically a control circuit used in the situation that an additional circuit for IOP-probe is added to the circuit for its design verification as shown in FIG. 3 and defines it by a truth table.

[0039]FIG. 8C illustrates schematically another situation that an additional circuit for IOP-probe is added to the circuit for its design verification as shown in FIG. 3.

[0040]FIG. 8D illustrates schematically a control circuit used in another situation that an additional circuit for IOP-probe is added to the circuit for its design verification as shown in FIG. 3 and defines it by a truth table.

[0041]FIG. 8E illustrates schematically another situation that an additional circuit for IOP-probe is added to the circuit for its design verification as shown in FIG. 3.

[0042]FIG. 8F illustrates schematically a control circuit used in another situation that an additional circuit for IOP-probe is added to the circuit for its design verification as shown in FIG. 3 and defines it by a truth table.

[0043]FIG. 8G illustrates schematically another situation that an additional circuit for IOP-probe is added to the circuit for its design verification as shown in FIG. 3.

[0044]FIG. 8H illustrates schematically a control circuit used in another situation that an additional circuit for IOP-probe is added to the circuit for its design verification as shown in FIG. 3 and defines it by a truth table.

[0045]FIG. 9A illustrates schematically a situation that an arbitrary flip-flop of the circuit for its design verification has an asynchronous set and asynchronous reset.

[0046]FIG. 9B illustrates schematically a situation that flip-flop of FIG. 9A is converted in an extended circuit for its design verification.

[0047]FIG. 9C illustrates defining the truth table of control circuit used in FIG. 9B.

[0048]FIG. 9D illustrates schematically a situation that an arbitrary flip-flop of the circuit for its design verification has an asynchronous set and asynchronous reset.

[0049]FIG. 9E illustrates schematically a situation that flip-flop of FIG. 9D is converted in an extended circuit for its design verification.

[0050]FIG. 9F illustrates defining the truth table of control circuit used in FIG. 9E.

[0051]FIG. 10 illustrates the constitution of a circuit functionally equivalent to a latch by a flip-flop and a multiplexer.

[0052]FIG. 11 is a flow chart explaining an embodiment of the input/output probe using FIG. 1.

[0053]FIG. 12 illustrates schematically a combined verification environment of emulation and simulation.

[0054]FIG. 13 illustrates schematically the constitution of a combined verification environment of emulation and simulation by a distribution method using short- and long-distance network.

[0055]FIG. 14 illustrates schematically the constitution of a combined verification environment of emulation and simulation in the distributive environment using internetwork.

[0056]FIG. 15 is a flow chart explaining a design verification method according to an embodiment of the combined verification of emulation and simulation using FIG. 12 or FIG. 13 or FIG. 14.

[0057]FIG. 16 is a flow chart explaining a method of the design verification according to another embodiment of the combined verification of emulation and simulation using FIG. 12 or FIG. 13 or FIG. 14.

[0058]FIG. 17 illustrates an example that an additional circuit for input probe for performing the input probe for combinational signal lines is added.

[0059]FIG. 18 illustrates schematically a situation of real time probe for RFPD input signals using on-chip memory of the RFPD inside of the RFPD.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0060]FIG. 1 illustrates schematically an input/output probing apparatus relating to the present invention comprising an input/output probing system software and an input/output probing interface module which are operated in a server computer.

[0061] As shown in FIG. 1, the input/output probing apparatus comprises an input/output probing system software and an input/output probing interface module (26). Input/output probing interface module (26) can be comprised of interface module (27) and interface cable (28). Input/output probing system software is performed in a server computer (20), which has an arbitrary simulator (for example, HDL simulator or logic simulator, or a cycle-basis simulator) or is connected to other computer having an arbitrary simulator through short-and long-distance network or inter-network.

[0062] Input/output probing interface module (27) connects a server computer (20) having input/output probing system software to an arbitrary hardware board (44) (hereinafter referred to as an arbitrary prototyping board or an arbitrary PCB) which mounts at least one semiconductor chip (for example, FPGA, CPLD, or ASIC) wherein the designed digital circuit is realized. Input/output probing interface module (27) generates a system clock necessary for the input/output probe, at least one user clock and probe clock generated from the above system clock, control signals of operation mode, control signals of probe mode, a reading/writing signal of memory for probe, and etc under the control of input/output probing system software and, if necessary, supplies them to an arbitrary prototyping board or arbitrary PCB, thereby controlling the operation of an arbitrary prototyping board or an arbitrary PCB.

[0063] To this effect, input/output probing interface module (27) by itself has FPGA or CPLD, or microprocessor or microcontroller, or exclusive ASIC chip built-in. Specifically, it is general that input/output probing interface module (27) is mounted in a PCI slot so as to be connected to a PCI (Peripheral Computer Interface) bus of server computer (20) or is connected to other secondary system bus (for example, S-bus of SUN Workstation, etc.) having the same function as above. Absolutely, in the case of requiring high speed, it is connected to a main bus, a primary system bus of the server computer, and if it is also possible at low speed, it is connected to a USB (Universal Serial Bus) or parallel port or serial port, etc., thereby an arbitrary server computer connects to an arbitrary prototyping board or an arbitrary PCB.

[0064] Input/output probing system software (32) can read complete state information or partial state information of the circuit for its design verification realized on an arbitrary prototyping board or an arbitrary PCB at an arbitrary point or situation desired by a user during the process of the design verification from the prototyping board, or on the contrary write it as a specific state information value at the above arbitrary point or situation through the input/output probing interface module(27). Herein, state information is a term indicating value of storage elements (flip-flop or latch) and content of memory (RAM or ROM) of a digital circuit in that the complete state information indicates values of all storage elements and contents of all memory of the circuit for its design verification, and the partial state information indicates value of partial storage element and (or) content of partial memory of the circuit for its design verification. Further, a storage element is different from a memory in that a storage element indicates flip-flop or latch, meanwhile a memory indicates RAM (Random Access Memory) or ROM (Read Only Memory).

[0065] To begin with, the input/output probing method according to the present invention is explained on the supposition that memory does not exist in the circuit for its design verification, and it will be explained later in case memory exists.

[0066] Input/output probing system software (32) includes an input/output probing circuit compiler that converts the circuit for its design verification so as to enable the input/output probe in an automated method. Such input/output probing circuit compiler generates a circuit (hereinafter referred to as extended circuit for its design verification) in an automatic method that is accomplished by adding an additional circuit (will be explained below) for IOP-probe to the circuit for its design verification.

[0067] The function of the additional circuit for IOP-probe which is included in the extended circuit for its design verification is that, in output probe mode, the circuit portion formed by adding an additional circuit becomes the shift register structure to do the shifting operation synchronized with a probe clock, and just before the shifting operation, logical values of the shift register have logical values of all or partial storage elements within the circuit to be output-probed. In input probe mode, the circuit portion formed by adding an additional circuit becomes the shift register structure to do the shifting operation and, by using such shifting operation, logical values of storage elements to be input-probed have input probe values by a synchronous set or reset operation, or a synchronous set or reset operation subsequent to an asynchronous set or reset operation or a synchronous disable operation subsequent to an asynchronous set or reset operation regarding all or partial storage elements within the circuit to be input-probed. In normal mode, even if an additional circuit is added, a circuit in which functional logical behavior of the circuit for its design verification is not altered is produced.

[0068] Or, in case that an object of the design verification is dictated by hardware description language (hereinafter referred to as the HDL) code, the HDL code completed by adding a HDL additional code expressing the behavior of the additional circuit for IOP-probe to the HDL code for its design verification expresses a shift register behavior in the HDL portion formed by adding the HDL code in output probe mode to do the shifting operation synchronized with a probe clock, and just before the shifting operation, signal values that the signal lines of a register HDL code have output signal values of all or partial storage elements to be output-probed, in the HDL code expressing the behavior of a shift register.

[0069] In input probe mode, the HDL code portion formed by adding the HDL code becomes the shift register structure to do the shifting operation synchronized with a probe clock and, by using such shifting operation, logical values of signals to be input probed become input probe values in a synchronous set or reset operation, or a synchronous set or reset operation subsequent to an asynchronous set or reset operation or a synchronous disable operation subsequent to an asynchronous set or reset operation regarding signals of the HDL code expressing the behavior of storage elements of HDL code to be input-probed. Further, in normal mode, even if the additional circuit for IOP-probe is added, the HDL code that does not alter behavior of the design verification HDL code is also called the additional circuit for IOP-probe.

[0070] An example of a specific method of realizing the function of the additional circuit for IOP-probe is explained supposing that the chip used in realizing a circuit is RFPD. The additional circuit for IOP-probe enables at least one shift register array structure wherein both parallel-load and serial-load are possible according to the change in mode with the signal lines of storage element to be probed and double input flip-flops within at least one said RFPD chip where the circuit for its design verification is realized. In output probe mode, each input of the double input flip-flops is connected to the output signal lines of storage element to be output-probed, thereby parallel-loading is possible from each logical value on the signal lines to be output-probed to each of the above double input flip-flops. Next, the output of one flip-flop existing in each of at least one said shift register array structure is logically connected to one input/output pin (I/O pin) which functions at least one output probe line of the corresponding RFPD and according to the shifting operation synchronized with the probe clock of the shift register, logical values of all flip-flops of the shift register are sequentially appeared on the above said input/output pin which functions output probe line. In such output probe, signal line to be output-probed could be output line of the storage element, however would be output of combinational gate.

[0071] However, input probe is performed only for the output line of storage element so as to store the input probe value in the storage element. In input probe mode, input of one flip-flop existing in each of at least one shift register array structure capable of serial-loading is connected to logically one input/output pin which functions at least one output probe line of the corresponding RFPD, thereby enabling serial-loading the input probe values sequentially supplied from outside to the shift register over the input/output pin which functions input probe line by the shifting operation synchronized with the probe clock. In case user clocks provided from the input/output probing interface module are directly connected to the clock input of the corresponding storage element to be input-probed, each output of flip-flops constituting at least one shift register array capable of serial-loading is connected to one data input of each of double input flip-flops replaced for each of the corresponding storage elements driving each of the corresponding signal lines to be input-probed.

[0072] Or, in case a user clock is not directly connected to a clock input of the storage element to be input-probed (in case a gated clock or locally generated clock is used, etc.), each storage element driving each of signal lines to be an input probe object is replaced by double input flip-flop having asynchronous set and asynchronous reset, and asynchronous set input and asynchronous reset input of such flip-flop are controlled by the control line of operation mode and the output line of the flip-flop having input probe value for the storage element to be input-probed in the flip-flops of the above shift register array and by the output line of a finite state machine for storage element to be probed.

[0073] As such, a storage element to be input-probed enables asynchronous set or reset at a specific point and further an output line of the flip-flop having the input probe value for a storage element is connected to one data input of the double input flip-flop replaced for a storage element of the user circuit to be input-probed, thereby setting output of the storage element to be input-probed to either 0 or 1, the logical value of a flip-flop having the input probe value for storage element through synchronous set or reset subsequent to asynchronous set or reset, thereby realized.

[0074] Further, in case a user clock is not directly connected to a clock input of the storage element to be input-probed, as a different method from the above, each storage element driving each of the signal lines to be input-probed is replaced by the double input flip-flop having asynchronous set and asynchronous reset, and synchronous enable, and the asynchronous set and asynchronous reset of such flip-flop are controlled by the output line of a finite state machine for the storage element to be probed and the control line of operation mode and the output line of the flip-flop having the input probe value for the storage element to be input-probed in the flip-flops of the shift register array.

[0075] As such, a storage element to be input-probed enables the asynchronous set or reset at a specific point and further another output line of the finite state machine for probe is connected to a synchronous enable of the flip-flop replaced for a storage element of the user circuit to be input-probed, thereby setting an output of the above storage element to be input-probed to either 0 or 1, the logical value of a flip-flop having the input probe value for storage element.

[0076] To this effect, the finite state machine (90) for the storage element to be probed as mentioned above is additionally necessary. The function of the finite state machine is to generate a set/reset enable signal to be provided so that asynchronous set or asynchronous rest occurs in a storage element to be input-probed by the signal values supplied from the shift register array only at the point when asynchronous set and asynchronous rest of storage element to be input-probed are necessary. Besides, its function supplies double input flip-flop with the select signal of input data of double input flip-flop that enables synchronous set or synchronous reset subsequent to asynchronous set or asynchronous rest to be occurred as the logical value of flip-flop having the input probe value for storage element, or to generate a set/reset enable signal to be supplied so that asynchronous set or asynchronous rest occurs in a storage element to be input-probed by the signal values supplied from the shift register array only at the point when asynchronous set and asynchronous reset of a storage element to be input-probed are necessary as well as to generate synchronous enable signal to be supplied and to supply control signal and data signal necessary for performing the output probe for memory.

[0077] To this effect, the asynchronous set and asynchronous reset of storage element to be input-probed should be controlled as it planned by using output line of flip-flop having the input probe value for storage element to be probed in the flip-flops of the shift register array, set/reset enable signal line from the finite state machine for probing storage element, and control signal lines of operation mode (normal-mode/probe-mode), which can be defined and realized by using a simple combined function. The functional behavior and role of the finite state machine for probing storage elements is explained later referring to an example thereof.

[0078] Partial or all storage elements used in the circuit for its design verification have already asynchronous set and asynchronous reset and, in case a user clock is not directly connected to the clock input of the above storage elements, it should be considered so as not to transform the original functional logical behavior of the circuit for its design verification in normal mode, by changing the corresponding storage element to be input-probed to the double input flip-flop having asynchronous set and asynchronous reset or to the single input flip-flop having asynchronous set and asynchronous reset and synchronous enable, while trying to convert a circuit as mentioned above by an additional circuit for IOP-probe added by including a control circuit portion driving asynchronous set input and asynchronous reset input. Such is not a difficult matter and will be also specifically explained later referring to an example thereof.

[0079] An example of another method for realizing such function of the additional circuit for IOP-probe is that in case there is a storage element using a gated clock input or a storage element using a locally generated signal as a clock input after an input/output probing system software examines the circuit for its design verification, the input/output probing system software combines the original circuit for its design verification with the circuit functionally equivalent and fully synchronous with the system clock in an automated method and regards the circuit fully synchronous with the system clock as a new circuit for its design verification, instead of the original circuit for its design verification.

[0080] Additional circuit for IOP-probe enables at least one shift register array structure wherein both parallel-load and serial-load according to a change in mode are possible by signal lines for storage element to be a probe object and double input flip-flops within at least one RFPD wherein the circuit for its design verification is realized. In output probe mode, after connecting input of each double input flip-flop to output signal lines of storage element to be output-probed and thus enabling parallel-loading from each logical value on the signal lines to be output-probed to each double input flip-flop, output of one flip-flop existing in each of the at least one shift register array structure is logically connected to one input/output pin functioning at least one output probe line in the corresponding RFPD, respectively, and according to the shifting operation synchronized with the probe clock of the shift register, logical values of all flip-flops of the shift register are sequentially appeared on the input/output pin functioning an output probe line.

[0081] In input probe mode, input of one flip-flop existing in each of the at least one shift register array structure wherein both parallel-load and serial-load according to a change in mode are possible is logically connected to one input/output pin functioning at least one input probe line in the corresponding RFPD, respectively, thereby enabling serial-loading the input probe value sequentially supplied from outside to the shift register over the input/output pin functioning input probe line by the shifting operation synchronized with the probe clock. Since all storage elements to be input-probed are directly connected to a user clock, each output of the flip-flops constituting at least one shift register array capable of parallel-loading is connected to one input of each double input flip-flop replaced for each of the corresponding storage elements driving each of the corresponding signal lines to be input-probed, thereby realized. However, it will be explained later in case a storage element used in the circuit for its design verification is latch.

[0082] Additionally, in case memory such as RAM or ROM is included in the circuit for its design verification and such memory is realized by using on-chip memory (for specific example, Distributed RAM or BlockRAM of Xilinx FPGA, Embedded Array Block of Altera FPGA) provided to be embedded in the RFPD, additional circuit for memory reading/writing is further included in the additional circuit for IOP-probe.

[0083] Additional circuit for memory reading/writing, under the control of input/output probing system software, in output probe mode, reads the content of the entire region or specific region of memory existing in the circuit for its design verification realized within the RFPD in determined order and enables it to be read by the input/output probing system software in an automated method via interface module and interface cable through the output probe line, and in input probe mode, performs writing the data the input/output probing system software has in the entire region or specific region of writable memory existing in the circuit for its design verification realized within the RFPD in an automated method in determined order through the input probe line of RFPD via interface module and interface cable.

[0084] An example of the specific realization of such additional circuit for memory reading/writing, first of all, generates reading/writing control signal of memory and address sequence regarding the entire memory region to be read/written, and constitutes by using flip-flop, multiplexer, and, if necessary, in the case of a clocked memory, finite state machine for memory probe which generates even the clock signal. FIG. 2A illustrates schematically an example of such constitution. A specific explanation of the operation of the additional circuit for memory reading/writing is as follows:

[0085] In output probe mode, the finite state machine (90) for memory probe generates control signal line of operation mode (normal mode/probe mode), control signal line of probe mode (input probe/output probe), signal of memory reading/writing (non-existence/existence) for probe, by inputting a probe clock, reading/writing control signal (81) of memory, address signal (82) of specific address, selection input signal (84) of multiplexer 1 at memory input terminal (83), and if necessary, even memory clock signal (85), and thus making reading/writing control signal (81) of memory (101), address signal (82) of specific address, and if necessary even the memory clock signal (85) appeared on the output portion of memory input terminal multiplexer 1 (83), thereby the present content in the specific address being appeared on the memory output terminal (86).

[0086] Thereafter, the finite state machine generates enable signal regarding flip-flops (87) of the memory output terminal thus storing value of the memory output terminal (86) in flip-flops (87) of the memory output terminal and generating input select signal regarding the flip-flops (87) of the memory output terminal thus the flip-flops (87) of the memory output terminal becoming the shift register structure synchronized with the probe clock thereby the present content in the specific address being sequentially appeared on the output probe line through the shifting operation. As such, the present content in the specific address of memory can be read. The finite state machine (90) for memory probe performs such reading of the specific address of memory regarding all memory addresses to be a reading object in an automated method in order.

[0087] In input probe mode, the finite state machine (90) for memory probe makes control signal line of operation mode (normal mode/probe mode), control signal line of probe mode (input probe/output probe), memory reading/writing (nonexistence/existence) signal lines for probe, by inputting a probe clock, reading/writing control signal (81) of memory, address signal (82) of specific address, selection input signal (84) of memory input terminal multiplexer 1 (83) appeared on the output portion of memory input terminal multiplexer 1 (83), thereby accessing to the specific address to be a memory writing object by a writing.

[0088] Further, the shift register (88) of data input terminal, by inputting a probe clock, makes the content of data to be written in the specific address to be a memory writing object stored in the shift register (88) of data input terminal by the shifting operation synchronized with the probe clock as the logical value sequentially input via the input probe line at the point when the shifting operation is completed, and generates selection signal for the signal line of selection input of the multiplexer 2 (89) of data input terminal of memory. The content of data stored in the shift register of the above data input terminal should be written in the specific address to be a memory writing object, if necessary, by generating memory clock signal (85). The finite state machine (90) for memory probe performs such writing of the specific address of memory regarding all memory addresses to be a reading object in an automated method in order.

[0089] For memory reading/writing, an address generator regarding memory address region to be a reading/writing object can be embedded inside the finite state machine (90) for memory probe, and such additional circuit for memory reading/writing can be similarly applied to even the case of memory being a two-port memory.

[0090] However, such reading/writing of on-chip memory can not be applied to the ICE environment incapable of arbitrarily controlling (free to go or stop) a user circuit and at least one clock assigned to the target environment, unless clocks are slowed down at least several tens times. The reading process of on-chip memory is necessarily required for the iPOD-basis verification (will be explained later) providing very strong function of the debugging that the clocks are performed without being slowed down. Therefore, a method of performing the reading process of on-chip memory without slowing down the clocks is explained referring to FIG. 2B.

[0091] To this effect, there is a need for on-chip memory OM2 (104) having the same amount as on-chip memory OM1 (102) used for realizing memory existing in the user circuit and additionally realizing another tag bit. The difficulty in performing the output probe for on-chip memory OM1 (102) realizing memory existing in the user circuit is that after output probe for flip-flops existing in the user circuit performs the loading of different content of the above flip-flops in parallel by using different flip-flops for output probe, it can proceed the operation of reading the different content of flip-flops for output probe via the sequential shifting simultaneously with the executing the user circuit at full speed. Meanwhile, it is impossible to read at a time the entire content in all addresses of on-chip memory OM1 (102) that realizes memory existing in the user circuit.

[0092] The solution thereof is to perform in parallel the output probe process of sequentially reading the content of on-chip memory OM1 (102) that realizes memory existing in the user circuit under the control of the finite state machine (90) for memory probe along with the operation of user circuit at full speed. In such process, in case of trying to write at the specific address A of the corresponding on-chip memory OM1 (102), which has not been probed out, by the operation of user circuit up to now, the finite state machine (90) for memory probe perceives that the corresponding tag output of probe data storage memory OM2 (104) of the corresponding specific address A is 0 and generates control signals and thus reading the content of the corresponding specific address A and then storing it in the above on-chip memory OM2 (104) with the same address first. And then, after changing the corresponding tag to 1, it proceeds with writing of the specific address A of on-chip memory OM1 (102) by a user circuit.

[0093] Cases different from the above are as follows:

[0094] First, during the process of performing in parallel the output probe process of sequentially reading the content of on-chip memory OM1 (102) that realizes memory existing in the user circuit along with the operation of user circuit, the tries to repeatedly write the specific address of on-chip memory OM1 (102) which was already read and stored in the corresponding address of OM2 (104) by the operation of a user circuit in advance (if the tag output from OM2 is 1, it can tell it is not the initial writing after starting memory probe at a specific point).

[0095] Second, in case of trying to read at the specific address of the corresponding on-chip memory OM1 (102), differently from normal address generated in the user circuit, it performs reading OM1 (102) with the address generated in pre-determined address generated in the address generator embedded in the finite state machine (90) for memory probe and thus storing the content in OM2 (104) and setting the corresponding tag to 1. And the memory operation of reading for memory OM1 (102) to be intended by a user circuit is performed. To this effect, memory probe occurs at a specific point by using the system clock twice faster than the user clock. In the first period of the system clock, specific address data of OM1 (102) is stored at the same address of OM2 (104) simultaneously setting the corresponding tag to 1 and, in the second period of the system clock, the memory operation of user circuit for OM1 (102) is performed. To this effect, all tags of OM2 (104) are initialized to 0 regarding all addresses at the first time, and when the content of specific address is read from OM1 (102) in memory output probe at a specific point and thus initially stored in OM2 (104), tag of the corresponding address is set to 1. When such setting of tag to 1 is performed as the number of times as all address of memory to be probed, the entire content of memory OM1 (102) for probe is copied in probe data storage memory OM2 (104) without stopping the execution of the user circuit. After such copying is completed, the output probe for memory can be completed by reading the content of the probe data storage memory OM2 (104) (consequently, after the output probe for the corresponding on-chip memory OM1 (102) is completed) and the tag is initialized to 0 for an additional output probe that may be carried out in the future.

[0096] It is also possible to proceed the above processes in parallel without stopping the execution of the user circuit. Consequently, when realizing, by such method, a memory existent in the user circuit with use of an on-chip memory of inside the RFPD, it is also possible to execute a real-time output probe without slowing down the user clock which is used very important in the ICE environment.

[0097] Moreover, an on-chip memory OM2 (104) can be realized together with the user circuit on at least one RFPD of the arbitrary prototyping board or the arbitrary PCB. With such realization, it is possible to minimize the probe data transmission bandwidth to interface module (26) (transmission of probe data only with the minimum of 1 bit is possible without discontinuing the user circuit). Yet, the resource of RFPD should be used. For such use of resource, the output probe flip-flops (87) such as those added to the data output section of the memory for probe (101) of FIG. 2A should be added to outputs (100) of probe data storage memory OM2 (104), and the pertinent control signals should be generated from a finite state machine (90) for memory probe and supplied them.

[0098] Other method involves a realization of an on-chip memory OM2(104) at the is interface module (26). Such method requires to secure a transmission bandwidth as much as data bus of the memory used in said user circuit between at least one RFPD of the arbitrary prototyping board in which the user circuit is realized or the arbitrary PCB and interface module (26).

[0099] To emphasize once more, when the memory is included in the above circuit for its design verification, the input/output probing system software adds an additional circuit for IOP-probe to the circuit for its design verification, generates the extended circuit for its design verification, and realizes to at least one RFPD in order to perform an input/output probe. An additional circuit for IOP-probe is a circuit added with an additional circuit not only to perform an input/output probe with regard to the storage element of the circuit for its design verification but also to perform reading/writing of the memory.

[0100] The output probe line and the input probe line of the present invention may exist as an individually independent and single direction probe line or exist as a bidirectional probe line in which the output probe line and the input probe line are combined. Further, the probe clocks used in the present invention may be clocks different from the user clocks used in the circuit for its design verification which are generated from the system clock and be used or may be one of the user clocks (for instance, the fastest clock).

[0101] The input/output probing system software includes a step of receiving input of the signal lines for probe and memory existent in the circuit for its design verification, or signals for probe and memory block existent in the HDL code for its design verification. In order to realize the circuit for its design verification to at least one RFPD equipped on the arbitrary prototyping board or on the arbitrary PCB, the signal lines for output probe or logic values at a specific period of time in the memory region for reading or at the point specific situations occur should appear at the output probe lines successively only during certain period of time.

[0102] In order for the signal lines for input probe or memory region for writing to have logic values added to the input probe line at the specific period of time, a step of generating an extended circuit for its design verification from addition of an additional circuit for IOP-probe to the circuit for its design verification allocated to at least one RFPD equipped on the arbitrary prototyping board or on the arbitrary PCB is further comprised. Moreover, with regard to signal lines for output probe and the memory region for reading, the logic values at a specific period of time on the signal lines for output probe and the content of memory are to appear on the output probe line of the pertinent RFPD by using an additional circuit for IOP-probe, and the values appeared on the output probe line are transmitted to server computer via the input/output probing interface module.

[0103] With regard to the signal lines for input probe and the memory region for reading, after generation of data for input probe from the state information acquired from server computer, said data are either synchronous only with probe clocks in the signal lines for input probe of the pertinent RFPD and assigned via input/output probing interface module, or together with the synchronization with the probe clocks, the probe data are appropriately transformed into between input probe mode and output probe mode via probe mode control signal line and assigned so that as the logic values of the signal lines for input probe and the content of the memory region for writing would have the logic values transmitted through input probe line, a step for establishing the state information of the circuit for its design verification the same as the state information acquired from said server computer is comprised.

[0104] The use of such input/output probing apparatus and input/output probing method allows the design verification in combination of emulation and simulation by using an arbitrary prototyping board or an arbitrary PCB equipped with at least one semiconductor chip realized with the extended circuit for its design verification added with an additional circuit for IOP-probe at the circuit for its design verification and the arbitrary simulator.

[0105] In other words, as for such design verification in combination of emulation and simulation, an input/output probing system software comprises a step for receiving input of signal lines for probe and the memory existent in the circuit for its design verification, or signals for probe and memory blocks existent in the HDL code for its design verification. In order to realize a circuit for its design verification to at least one RFPD equipped on the arbitrary prototyping board or the arbitrary PCB, the signal lines for output probe or the logic values at the specific period of time in the memory region for reading or at the point specific situations occur should appear at the output probe line successively only during certain period of time. A step for generating the extended circuit for its design verification from addition of an additional circuit for IOP-probe added to the circuit for its design verification allocated to at least one RFPD equipped on the arbitrary prototyping board or the arbitrary PCB is further comprised in order for signals for input probe or memory regions for writing to bear the logic values added to a specific period of time in the input probe line.

[0106] Moreover, with regard to the signal lines for output probe and the memory region for reading, logic values at a specific period of time on the signal lines for output probe and the content of memory are to appear on the output probe line of the pertinent RFPD by using an additional circuit for IOP-probe, and the values appeared on the output probe line are transmitted to server computer via the input/output probing interface module. Accordingly, the current state information of the circuit for its design verification will have the initial state value for the simulation with simulator.

[0107] With regard to the signal lines for input probe and the memory region for writing, data for input probe are generated from the state information acquired through simulation from server computer. Said data are either synchronous only with probe clocks in the signal lines for input probe of the pertinent RFPD and assigned via input/output probing interface module and the interface cable, or together with the synchronization with the probe clocks, the probe mode are appropriately transformed into between input probe mode and output probe mode via probe mode control signal line and assigned so that the logic values of the signal lines for input probe and the content of the memory region for writing would have the logic values transmitted through input probe line.

[0108] A step for establishing the state information of the circuit for its design verification implemented on RFPD as above the same as the state information generated through simulation during a certain period of time at the simulator is comprised. Should Foreign Language Interface (FLI) or Programming Language Interface (PLI) prepared in the simulator be used, it is possible to obtain such exchange of the state information between at least one RFPD equipped on the arbitrary prototyping board or on the arbitrary PCB and the arbitrary simulator at the level of the Application Program Interface (API). Thus, such exchange is possible while minimizing the overhead.

[0109] As shown above, in order to perform a combined verification with an automated method between emulation and simulation using said input/output probing apparatus and said input/output probing method of the present invention, the execution transformation between emulation and simulation should be automatically accomplished. Such accomplishment is called execution mode switching, and said execution mode switching is possible when specific requirement is fulfilled (for instance, the point wherein specific value is stored twice in a specific register within the circuit). Such requirement is called an execution mode switching requirement.

[0110] The execution mode switching requirement can be at least two having a before/after time sequence relationship during the entire verification process. In such case, the execution mode switching from emulation to simulation or from simulation to logic emulation occurs when the requirement is satisfactorily met under the condition that the requirement previously established is arranged first followed by the requirement established later according to the time sequence. For such matter, it is necessary to store the execution mode switching requirement in a queue, and this is called an execution mode switching requirement queue which is maintained within the input/output probing system software as in a data structure.

[0111] The combined verification process of emulation and simulation according to the input/output probing apparatus and input/output probing method of the present invention comprises: a step for inputting the names of circuit for its design verification and ASIC bender library by server computer; a step for designating signal lines for probe on the circuit for its design verification necessary for the combined verification and an additional memory region if necessary; a step for generating an extended circuit for its design verification from an additional addition of an additional circuit for IOP-probe to the circuit for its design verification realized on at least one RFPD in order for signal lines for output probe and logic values of the specific period of time in the memory region to appear at the output probe line for a certain period of time, and for the signal lines for input probe and memory region to have the logic values added to the specific period of time in the input probe line; a step for making the logic values of the specific period of time in the storage elements for output probe and the content of the memory region to appear at the output probe line of at least one of said RFPD by using an additional circuit for IOP-probe from executing the output probe with regard to at least one of said RFPD under the control of input/output probing system software at the point of an arbitrary time the user has established or at point an arbitrary situation occurs when said circuit for its design verification is realized on at least one RFPD and during the operation of said realized circuit for its design verification; a step for automatically establishing values appeared as in the above as a simulation initial state value for executing simulation by a simulator by transmitting to server computer via input/output probing interface module; and a step for enabling the automatic execution of emulation following the simulation by letting the storage element and the memory region which are the objects of the input probe have the state information of the circuit for its design verification acquired through simulation at an arbitrary point the user has established or an arbitrary situation during simulation by a simulator by using input probing method employing an additional circuit for IOP-probe through an input probe line of at least one RFPD equipped on the arbitrary prototyping board or the arbitrary PCB via input/output probing interface module from server computer.

[0112] The combined verification process of emulation and simulation according to the input/output probing apparatus and input/output probing method of the present invention comprises: a step for inputting the names of HDL code for its design verification and ASIC bender library by server computer; a step for designating signal lines for probe on the HDL code for its design verification necessary for the combined verification and an additional memory region if necessary; a step for generating an extended HDL code for its design verification from an additional addition of an additional HDL code for IOP-probe to the HDL code for its design verification realized on at least one RFPD in order for signal lines for output probe and logic values of the specific period of time in the memory region to appear at the output probe line for a certain period of time, and for the signal lines for input probe and memory region to have the logic values added to the specific period of time in the input probe line; a step for making the logic values of the specific period of time in the storage elements for output probe and the content of the memory region to appear at the output probe line of at least one of said RFPD by using an additional circuit for IOP-probe from performing the output probe with regard to at least one of said RFPD at the point of an arbitrary time the user has established or at point an arbitrary situation occurs when said HDL code for its design verification is realized on at least one RFPD and during the operation of said realized HDL code for its design verification and a circuit functionally equivalent thereof; a step for automatically establishing values appeared as in the above as a simulation initial state value for executing simulation by a simulator by transmitting to server computer via input/output probing interface module; and a step for enabling the automatic execution of emulation following the simulation by letting the storage element and the memory region which are the objects of the input probe have the state information of the HDL code for its design verification acquired through simulation at an arbitrary point the user has established or an arbitrary situation during simulation by a simulator by using input probe method employing an additional circuit for IOP-probe through an input probe line of at least one RFPD equipped on the arbitrary prototyping board or the arbitrary PCB via input/output probing interface module from server computer.

[0113] In accordance with such input/output probe, the emulation employing an arbitrary prototyping board or an arbitrary PCB and simulation executed at the server computer are performed alternately for at least once. Particularly, the emulation followed by simulation can be continuously proceeded by transmitting the logic values of the output probe signal lines to simulator in the server computer if the signal lines for output probe are output lines of all storage elements (flip-flop or latch) existent in the circuit for its design verification (values of all storage elements output probed at such point are called ‘complete state information’) when combinational feedback loop is not existent in the circuit for its design verification, or if all values of the remaining storage elements are determined by proceeding at least one clock cycle from the output line values of the partial storage elements (values of the partial storage elements output probed at such point are called ‘possible complete partial state information’) even when the signal lines for output probe are the output lines of partial storage elements existent in the circuit for its design verification.

[0114] Should at least one combinational feedback loop is included in the circuit for its design verification, each of the combinational signal lines existent in the combinational circuit in which each combinational feedback loops can cut said feedback loops should be included in the signal lines for output probe. When it is possible to perform such emulation and simulation alternately at least once, there are many advantages as presented below at the stage the design verification is performed by employing an arbitrary prototyping board or an arbitrary PCB.

[0115] First of all, it is possible to perform 100% visibility without a re-compile process of RFPD with regard to not only the signal lines which can be probed through the output probe from the circuit for its design verification realized to at least one RFPD on the arbitrary prototyping board or the arbitrary PCB but also the rest of the signal lines. The reason of canceling such re-compile process to the maximum being extremely important in the debugging process is the necessity of time consumed for compiling RFPD of the millions of the recent gate levels which can take few minutes at least to several hours at most.

[0116] Accordingly, one of the most important matter in the debugging process with regard to a circuit realized on RFPD is to enable a prompt debugging by restraining the re-compile regarding said RFPD at the maximum. Should the design verification is performed employing both simulation and emulation together, a 100% visibility with regard to all signal lines existent in the circuit for its design verification indispensable for debugging process is perfectly prepared even during emulation without the recompile process regarding such RFPD. Not only such 100% visibility is possible but it is possible to perform simulation subsequently to emulation with signal line values that have been output probed at each of the output points regardless of said user's request by at least one output probe being performed regardless of user's request at regular intervals (for example, once for every 10,000 clock cycles) or at irregular intervals without performing a probe based on unnecessary presumption in the debugging process while performing first of all the circuit for its design verification realized on at least one RFPD of said arbitrary prototyping board or arbitrary PCB on said arbitrary prototyping board or arbitrary PCB. Thus, simulation soon after [subsequently of] emulation can be performed with signal line values which were output probed from each of output probe points (each of these points is called ‘Roll-back Point’) regardless of said user's request.

[0117] If employing the above process, for debugging, it is possible to perform an instant probe at the desired moment (this is called, “Instant Probe On Demand”, hereinafter, ‘iPOD’) for the output probe desired by user during his/her desired period of time (the beginning of this period of time is indicated as t_s and the end of this period of time is indicated as t_e.) with regard to the certain desired signal lines without prior presumption. Such iPOD is possible for all signal lines existent in the circuit for its design verification from the initial beginning point to the last point. This is done by bring the state of the circuit for its design verification to the nearest, but behind in time, roll-back point from the time t_s, from when output probing is desired, with input-probing the state of the circuit for its design verification, and performing the emulation from said roll-back point to t_s, and transferring the state information of the circuit for its design verification to a simulator in a server computer by output-probing at t_s, and performing the simulation from t_s to the. Throughout this procedure, user can get a complete visibility to all signal lines in the circuit for its design verification to be output-probed during this period of time, i.e. t_s to t_e.

[0118] For such emulation reply, storing the input pattern is required. The input pattern stored in the server computer beforehand will not cause any problem, but at in-circuit situation, the input pattern is generated at the peripheral hardware in real-time basis and assigned so that storing of such input pattern should be conducted on real-time basis. Accordingly, input sampling method for the above using memory should be provided.

[0119] Meanwhile, when bugs existent in the circuit for its design verification or the HDL code for its design verification are found by undergoing such process, a correction thereof is required, and a process for confirming whether such correction is soundly conducted should be provided. Yet, such confirmation process will require a recompile process in order to reflect the pertinent design correction with regard to at least one of said RFPD wherein the circuit for its design verification is realized should a prompt execution via emulation is intended.

[0120] Nevertheless, it is desirable to furnish a method promptly confirming whether such correction is sound prior to the re-compile process which consumes quite a few hours. A new method for such involving emulation and simulation conducted not only temporally but also spatially together can be employed. In other words, the portion which does not contain design correction uses realization made on at least one of RFPD on said arbitrary prototyping board or the arbitrary PCB, and the portion containing design correction uses a software model which was modeled at the simulator on the server computer.

[0121] If such method is used, the portion containing design correction is generally limited to the local compared to the entire design to be verified, and is a very small area (for instance, one entity of VHDL). Thus, as such small area can be promptly processed without taking much time even via execution by simulation, the present invention has an advantage of increasing the speed of the entire verification. In order for such temporal and spatial combined verification to be possible, a design correction should be made so that the input probe is possible for all output lines of the sub module, which needs simulation, and output probe is possible for all input lines of the sub module.

[0122] For example, when the design correction is made and the portion the simulation will be performed is 1-bit full adder, the output probe is required with regard to the input lines thereof, i.e., a, b and carry_in, and the input probe is required with regard to the output lines thereof, i.e., sum and carry_out. In such case, the input probe with regard to the output probe and the output of the storage element may use the aforementioned method, but the input probe with regard to the output of the combinational logic gate uses flip-flops and multiplexer for each signal lines which are for input for probe in order to be executed as FIG. 17.

[0123] If using such input/output probing methods and a hierarchial design method in adding an additional circuit for probe to enable input/output probe with regard to the input/output signal lines of each sub module in the design is added, the entire circuit for its design verification not containing the design correction as to the circuit for its design verification containing a circuit portion in requisition of the design correction is performed in a high speed by emulation on at least one of RFPD of said arbitrary prototyping board or the arbitrary PCB. Then, the portion of the circuit for its design verification in completion of design correction as the output probe to the inputs of specific sub modules in completion of design correction using the result of such emulation is performed simulation at the server computer.

[0124] The accurate/proper emulation of the entire circuit for its design verification can be executed without re-compile by correcting the result of said circuit portion not in completion of design correction which was executed by emulation via input probe with regard to the output of specific sub modules in completion of design correction using result of such simulation. Moreover, through such input/output probe, it is possible for several users to share temporally and spatially and to use an arbitrary prototyping system comprised with at least one RFPD.

[0125] In other words, each user in his own embeds the simulator in his server computer, respectively, and not only it is possible to convert the verification method to emulation using said prototyping system from simulation through input probe when necessary, but also it is possible to convert from emulation to simulation at any time. Thus, a very effective share of the arbitrary prototyping system as the above becomes possible.

[0126] Meanwhile, such simulation can be performed in the server computer in substitution to a separate evaluation process, and when necessary, a partial modeling of the circuit for its design verification and execution by including thereof to the prototyping system software in order to increase the execution speed of the simulation or evaluation process instead of designing all of the entire circuit for its design verification and executing thereof is possible.

[0127] When either executing the design verification with regard to the digital circuit realized on at least one of said RFPD using the arbitrary prototyping board equipped with at least one RFPD in the ICE environment or executing the design verification with regard to the digital circuit realized on at least one of said RFPD operating the arbitrary PCB equipped with at least one RFPD, the following difficulties arise.

[0128] First, when said arbitrary prototyping board or said arbitrary PCB are operated in the ICE environment or in the real operation environment, the execution thereof is generally done in very high speed (for example, at least several tens of MHz). In such situation, in order to able to use the iPOD function, all input values should be sampled and stored at every clock with regard to all inputs assigned to at least one RFPD. A method for such involves storing all input values through physical contact from outside the RFPD with regard to all inputs assigned to at least one of said RFPD. For such, a separate logic analyzer or a signal sampler performing similar function thereof can be used.

[0129] However, a problem in such method requires a consideration for enabling the arbitrary prototyping board or the arbitrary PCB to be in physical contact with regard to input trace lines wherein said logic analyzer or signal sampler is connected to RFPD. The making of arbitrary prototyping board and arbitrary PCB in consideration of such situation is not realizable. Also, even if such making is done in consideration of the above situation, the current package technique of semiconductor chip (for example, BGA, uBGA, Flip chip, etc.) makes the contact of such numerous pins extremely difficult.

[0130] In this respect, the second method having taking into account of such situation includes storage of all inputs inside the RFPD by output probe instead of obtaining all input values through physical contact of outside the RFPD with regard to all inputs assigned to at least one of said RFPD. Thus, for such purpose, a separate logic analyzer or a signal sampler performing such similar function is not required. Input values output probed through such process can be transmitted to the server computer via interface module.

[0131] Yet, in order to maximize the advantage of such second method, input values of all inputs (for example, 240 inputs) output probed inside the RFPD should be transmitted to the server computer using the least possible numbers of RFPD pins (for example, 6 pins or less). In such situation, it is impossible to sample inputs for every clock of the original user clock and to transmit to server computer using the output probe clock at the same speed. The user clock should be lowered proportionately to output probe clock. For instance, if number of inputs assigned to RFPD is 240 and the output probe data line is 1 bit, the user clock should be lowered to 1/240 compared to the output probe clock. Such use of the lowered user clock is not refreshed within the determined time when there is a dynamic logic requiring refresh such as Dynamic Random Access Memory (DRAM) or Synchronous Dynamic Random Access Memory (SDRAM) in the peripheral circuit. Thus, a serious problem such as data loss can be raised.

[0132] In this respect, the following method can be used to effectively solve the problem. That is, many RFPD use on-chip memory inside of the chips and such examples are: BlockRAM of Xilinx FPGA or Embedded Array Block (EAB) of Altera FPGA, etc. If such on chip memory is used, it is possible to use an identical high clock for both user clock and probe clock as much as the capacity of on chip memory, to output probe all inputs assigned to RFPD inside the chip, and to store them in on-chip memory in real-time.

[0133] Next, through the above process, the input values stored in the on-chip memory are read, and through said least number of output probe data line, said values are consecutively transmitted to the server computer via interface module. During such transmission process, if the user clock is discontinued, only the probe clocks are operated at high speed. Such generation of user clock and probe clock is generated and provided from the interface module. During the period the user clock is discontinued, DRAM or SDRAM enters self refresh mode and independently executes refresh in order to prevent data loss.

[0134] For such purpose, a constant single value (for example, Clock Enable (CLE)) of the specific inputs assigned to DRAM or SDRAM is 0 during this period of time, and Write Enable (/WE) is 1). However, as variation value, constant (for example, Chip Select (/CS)) and Row Address Strobe (/RAS) and Column Address Strobe (CAS) are required to be 0 during a first one clock period of the initiation of the self refresh and to be 1) at the remaining period. For such purpose, an additional circuit for IOP-probe should perform such control with regard to inputs. It is possible to simply realize the above by using multiplexer for each input.

[0135] If such second method is used, a very important advantage is obtained which provides a very powerful debugging function when satisfying the extremely minimum requirement condition even in a “certain” environment (for example, ICE environment wherein SDRAM, processor, etc. are operating together) with regard to a “certain” arbitrary board equipped on at least one RFPD, The inputs assigned to RFPD collected through such process can be used as test bench in simulation afterwards. FIG. 18 is a drawing presenting schematically a real-time method with regard to the input signals inside of the RFPD by using on-chip memory of such RFPD.

[0136] The content described in the above is examined as below in more details in reference to the drawings.

[0137]FIG. 2A and FIG. 2B illustrate schematically as an example of a concrete realization of the additional circuit for memory reading/writing, a finite state machine for memory probe generating, most of all, read/write control signals with regard to the memory and address sequence with regard to all memory region which are the objects of reading/writing and even generating the clock signals in case of clocked memory according to the needs, a multiplexer, and a flip-flop are schematically illustrated.

[0138] The input/output probing method according to the present invention comprises a step for making an extended circuit for its design verification wherein an additional circuit for IOP-probe is generated with a method in which input/output system software is automated and is added to the circuit for its design verification. First of all, when the circuit for its design verification does not contain a memory and flip-flops are used for a storage element, such flip-flops are assumed as all D-type flip-flops and an exception to such case will be explained immediately below.

[0139] In such step, the extended circuit for its design verification which is a circuit made by adding an additional circuit for IOP-probe to the circuit for its design verification forms a circuit portion by adding an additional circuit in the output probe mode. Such circuit portion becomes a shift register structure and does a shifting operation synchronous at the probe clock. Prior to such shifting operation, the logic values which the shift register have will have the logic values of signal lines which are the objects of the output probe.

[0140] The circuit portion formed by addition of an additional circuit in the input probe mode becomes a shift register structure, and does a shifting operation By using such shifting operation, the logic values of the flip-flops which are the objects for input probe become the input probe values by synchronous set or the synchronous reset operation, or asynchronous set or asynchronous reset operation followed by the synchronous set or the synchronous re-set operation, or the asynchronous set or the asynchronous reset operation followed by the synchronous disable operation.

[0141] In the normal mode, even if the additional circuit for IOP-probe is added, the functional logical behavior of the circuit for its design verification is not to contain a non-transformed performance. In order to explain such matter in more detail, FIG. 3 explains the example of an asynchronous circuit.

[0142] The user clock of the circuit is not physically connected (in contrast of ‘logically connected’) due to clock input of all flip-flops in the circuit illustrated in FIG. 3 and such clock is called ‘gated clock’. The circuit according to FIG. 3 is a 4-bit asynchronous binary counter wherein the user clock of the circuit is not physically connected due to clock input of the remaining three flip-flops excluding the flip-flop of the lowest bit.

[0143]FIG. 4 depicts schematically the symbols of the various D-type flip-flops and the functional skill. FIG. 5 and FIG. 6 illustrate an example of shift register array structure wherein a parallel load representing the additional circuit for IOP-probe regarding the present invention, and other examples. FIG. 7 illustrates schematically an example of realization of double input D-type flip-flops of FIG. 4. An extended circuit for its design verification added with an additional circuit for IOP-probe for enabling input/output probe with regard to all 4-bit output lines of 4-bit asynchronous binary counter such as that in FIG. 3 is illustrated in FIG. 8A.

[0144] The circuit of FIG. 8A in the output probe mode together with the circuit for its design verification is constituted to have a shift register array structure enabling a parallel load by signal lines for probe and double input flip-flops (PFF0, PFF1, PFF2, PFF3). Concurrently, each one input of the double input flip-flops is connected to signal lines for probe, respectively. Thus, it is possible to load in parallel the logic values of the signal lines for probe to the double input flip-flops. At output probe, the output (in this case, the far most right output, PFF3) of one flip-flop existent in the shift register array structure can be logically connected to the input/output probe line. In the input probe mode, an input (in this case, the far most left input, PFF0) of one flip-flop existent in each shift register array structure wherein the parallel load is possible is logically connected to the input probe line. The outputs (p0, p1, p2, p3) of each flip-flop constituting the shift register array wherein the parallel load is possible are connected to an input of the double input flip-flop (FF0) substituted among each of flip-flops (FF0, FF1, FF2, FF3 in FIG. 3) driving each of the signal lines for input probe (I this case, y0, y1, y2, y3) (This is related to a case when the user clock is connected to the clock input of the pertinent flip-flop. Thus, only FF0 is the pertinent object). Or each of the flip-flops is substituted with the double input flip-flop concurrently having both asynchronous set and asynchronous reset. By controlling the inputs of the asynchronous set and asynchronous reset of such flip-flops, the values of the flip-flops become the desired input probe values. Afterwards, the output of such flip-flops can be arranged to 0 or 1 by the final synchronous set or synchronous reset through an input of a datum of the double input flip-flop connected to the output of the pertinent flip-flop among the flip-flops constituting the shift register array (This is related to a case when user clock is not connected to the clock input of the pertinent flip-flop. Thus, FF1, FF2, FF3 are the pertinent objects) and be realized. For such realization, a finite state machine for probing a storage element is additionally required.

[0145] The role of the finite state machine for probing a storage element used in the above is to control in order to let the asynchronous set and asynchronous reset occur from the signal values supplied from the shift register array only at the point asynchronous set and asynchronous reset of the flip-flops which are the objects of the input probe are required. Moreover, by the logic values of the pertinent flip-flop among the flip-flops constituting the shift register array, the final synchronous set or synchronous reset of the double input flip-flop should be controlled for their occurrence.

[0146] For such purpose, it is necessary to have a combinational circuit function such as FIG. 8B in order to control the asynchronous set and asynchronous reset of the flip-flops which are the objects of the input probe by using signal lines from the shift register array for probing a storage element, signal lines of the storage element probe finite state machine, and operation mode control (normal mode/probe mode) signal lines.

[0147] When coding the meaning differently regarding the inputs and outputs of the combination circuit in FIG. 8B (for instance, interpreting the meaning of 0 and 1 of FSMOut differently, etc.), the truth table of FIG. 8(b) naturally becomes different.

[0148] Another extended circuit for its design verification is illustrated in FIG. 8C wherein the additional circuit for IOP-probe enabling the input/output probe regarding all 4-bit output lines of 4-bit asynchronous binary counter such as FIG. 3 is added. The difference between FIG. 8C and FIG. 8A is the performance of input probe through asynchronous set or asynchronous reset followed by synchronous disable by using a single input flip-flop having asynchronous set/reset and synchronous enable instead of execution of input probe with asynchronous set or asynchronous reset followed by synchronous set or synchronous reset as shown in FIG. 8A by using the double input flip-flop having asynchronous set/reset with regard to flip-flops (FF1, FF2, FF3) using clock generated locally.

[0149] Examples illustrated in FIG. 8A and FIG. 8C newly constituted and used the whole flip-flops used in the shift register array wherein parallel load and serial load are all possible in accordance with the mode conversion completely separate from the flip-flops existent in the circuit for its design verification. The advantage thereof is in minimization of interference with regard to the circuit for its design verification such as the operation of the circuit for its design verification while performing input/output probe, a possible execution of output probe in parallel and etc. Nevertheless, a disadvantage of the overhead being large may arise.

[0150] Examples such as FIG. 8E and FIG. 8G can minimize the overhead for input/output probe by using the transformed flip-flops (FF0 in this case) selected from flip-flops partially existent in the circuit for its design verification among the flip-flops used in said shift register array.

[0151] For a case of 4-bit asynchronous binary counter, there is one flip-flop as a very small circuit wherein a user clock is directly connected to the clock of the flip-flop. However, for the ordinary circuit having a large sized circuit, mostly there are so many numbers of flip-flops wherein the user clock is directly connect to the flip-flop. Accordingly, a method using such flip-flops partially existent in the circuit for its design verification among the flip-flops used in said shift register array is a very desirable method since the overhead for input/output probe can be lowered much. Yet, it entails a disadvantage of not being able to use in ICE environment because the performance of the user circuit cannot be proceeded during the output probe.

[0152]FIG. 9A depicts a situation wherein at least one arbitrary flip-flop in the circuit for its design verification already has asynchronous set and asynchronous reset, the user clock is not directly connected to the clock input of such flip-flop, and either a local clock generated locally or a clock that has been gated is connected. In such situation, the first method involves, as already explained, a substitution of the pertinent flip-flops which are the objects of input probe to a double input flip-flop, inclusion of a combinational control circuit driving the asynchronous set and asynchronous reset inputs, and circuit conversion to the additionally added additional circuit for IOP-probe, as previously explained for preventing transformation of the functional logic characteristics of the original circuit for its design verification at the normal mode. FIG. 9B illustrates such situation and the truth table of the combinational control circuit used therein is represented in FIG. 9C.

[0153] The role of the finite state machine for probing a storage element which is synchronous to the probe clock and driven is to generate asynchronous set/reset activation signals in order to let the input probe immediately occur only at a specific-th of the cycle of said probe clock by controlling asynchronous set input and asynchronous reset input of the double input flip-flap substituting the flip-flop which is the object of the input probe with input probe value stored in the specific flip-flop of the shift register array constituting an additional circuit for IOP-probe (in this case, activation occurs). The cycles excluding the specific-th cycle of the double input probe clock at the input probe mode generate asynchronous set/reset activation signals disabling the asynchronous set and asynchronous reset of said double input flip-flop substituting the specific flip-flop which is the object of the input probe (in this case, inactivation occurs).

[0154] The asynchronous set/reset activation signals are generated (in this case, inactivation occurs) at the normal operation mode in order for the extended circuit for its design verification to be functionally equivalent to the original circuit for its design verification. Thus, the control circuit section connected to asynchronous set input and asynchronous reset input of said double input flip-flops substituting the flip-flop for input probe which is the object for input probe is driven. Such is controlled to let the final synchronous set or synchronous reset of said double input flip-flop occurs with the logic values of the pertinent flip-flop among the flip-flops constituting the shift register array.

[0155] For such instance, the second method involves, as already explained, a substitution of the pertinent flip-flop which is the object of input probe to a single input flip-flop having synchronous enable, inclusion of a combinational control circuit driving the asynchronous set and asynchronous reset inputs, and circuit transformation to the additionally added additional circuit for IOP-probe, as previously explained for preventing transformation of the functional logic characteristics of the original circuit for its design verification at the normal mode. FIG. 9E illustrates such instance and the truth table of the combinational control circuit used therein is represented in FIG. 9F.

[0156] The role of the finite state machine for probing a storage element which is synchronous to the probe clock and driven is to generate asynchronous set/reset activation signals in order to let the input probe immediately occur only at a specific-th of the cycle of said probe clock by controlling asynchronous set input and asynchronous reset input of the single input flip-flap having synchronous enable substituting the flip-flop which is the object of the input probe with input probe value stored in the specific flip-flop of the shift register array constituting an additional circuit for IOP-probe (in this case, activation occurs).

[0157] The cycles excluding said specific-th cycle of said double input probe clock at the input probe mode generate asynchronous set/reset activation signals disabling the asynchronous set and asynchronous reset of said single input flip-flop substituting the specific flip-flop which is the object of the input probe (in this case, inactivation occurs).

[0158] The asynchronous set/reset activation signals are generated (in this case, inactivation occurs) at the normal operation mode in order for the extended circuit for its design verification to be functionally equivalent to the original circuit for its design verification. Thus, the control circuit section connected to asynchronous set input and asynchronous reset input of said single input flip-flops substituting the flip-flop for input probe that is the object for input probe is driven. Furthermore, after the input probe is performed with asynchronous set or asynchronous reset, the control to maintain the current values of the pertinent flip-flop at the specific point by using synchronous enable signals generated at the finite state machine is rendered.

[0159] Such extended circuit for its design verification generated from the addition of an additional circuit for IOP-probe to the circuit for its design verification is realized on at least one RFPD of the arbitrary prototyping board or the arbitrary PCB. When conversion to simulation at a specific point or at a point a specific situation occurred during the process of performing the verification based on the emulation by executing the prototyping board, the logic values at the signal lines which are the objects for probe are transmitted to server computer through input/output probing interface module via at least one output probe line connected to the output of one flip-flop existent in each of at least one shift register array structure when the probe clock is added to RFPD after a detection for such need of conversion by input/out probe system software, discontinuation of emulation performance, and an addition of probe clock to RFPD.

[0160] Nevertheless, the point of the input/output probe can be statically determined prior to the emulation performance, and dynamically determined at the same point a specific situation develops during the emulation performance. In order to determine the point of input/output probe dependent on the situation of emulation such as the point of time a specific situation develops, the input/output probe point can be determined by using external apparatus such as a logic analyzer and observing thereof. Or by additionally adding an input/output probe point detector detecting the operation situation of inside the RFPD, a situation of input/output probe can be initiated when input/output probe state is outputted, and such state is perceived by input/output probing system software. In a situation of an additional addition of said input/output probe point detector together with an additional circuit for IOP-probe to a circuit for its design verification inside the RFPD, the input/output probing system software will also be responsible for the automatic generation and addition thereof.

[0161] In case of an input probe, after the input/output probing system software generates input probe data regarding at least one pertinent RFPD of the prototyping board, and converts the operation mode under control of input/output probing system software to the input probe mode, the data for input probe which were transmitted as the probe clock is added to RFPD via at least one input probe line logically connected to an input of one flip-flop existent in each of at least one shift register array structure via input/output probing interface module from the server computer are stored in the flip-flops existent in each of at least one shift register array structure.

[0162] As input probe data stored in the above manner, the input probe regarding flip-flops for final input probe will be accomplished on at least one RFPD equipped on the arbitrary prototyping board or arbitrary PCB by synchronous set or reset operation, or asynchronous set or reset operation followed by synchronous set or reset, or asynchronous set or reset operation followed by synchronous disable operation.

[0163] In a case wherein the flip-flops used in the circuit design are not D-type but RS-type, JK-type and T-type, etc., an equivalent circuit is realized after constituting a circuit functionally equivalent to D-type flip-flops and a simple combinational circuit by using said two. Accordingly, a method for producing an additional circuit for probe from said probe method in the present invention is a method that can even be applied to a case using whatever kind of flip-flops to the circuit.

[0164] Also, if the storage element used in the circuit for its design verification is a latch, first, after each of latches prior to using the above methods is converted to FIG. 10 by using flip-flops and the combinational circuit, and a circuit functionally equivalent to the original latch is obtained, the above methods are applied.

[0165]FIG. 11 is a flow chart explaining an input/output probing method in accordance with one example of the present invention that is performed by server computer (20) illustrated in FIG. 1.

[0166] First of all, the name of ASIC vender library and the circuit for its design verification input or the HDL code for its design verification are inputted (Step S50). Afterwards, the signal lines for input/output probe are inputted (Step S52). When basic data such as the above are inputted, either after generation of an additional circuit for IOP-probe for the pertinent semiconductor chip on the prototyping board, an extended circuit for its design verification is generated by being added to the circuit for its design verification or after generation of an additional HDL code for IOP-probe, an extended HDL code for its design verification is generated by being added to the HDL code for its design verification (Step S54).

[0167] The extended circuit for its design verification or the extended HDL code for its design verification generated in the above is realized on the pertinent semiconductor chip on the prototyping board. (Step S56). After realization at Step S56, a circuit verification process is performed at the normal mode (Step S70). In accordance with the performance result of the circuit verification process, whether it is necessary to perform probe is examined. In other words, in a case it is necessary to examine, progress to Step S74 is made and in a case it is not necessary, progress to Step S82 is made (Step S72).

[0168] When it is necessary to examine, progress to Step S74 is made to examine whether the subject matter is the output probe. If found to be the output probe, progress to Step S80 is made, and if found to be the input probe, progress to Step S76 is made. At Step S76, the data for input probe are generated from the server computer, and progress to Step S78 is made. At Step S78, after conversion to input probe mode, the data for input probe are assigned to input probe line via input/output probing interface module at server computer. Thus, the input probe is performed and progress to Step S82 is made. At Step S80, after conversion to output probe mode, the output probe is performed. The values appeared in the output probe line are transmitted to the server computer through input/output probing interface module. Thus, the output probe is completed and progress to Step S82 is made. At Step S82, the completion of the design verification is examined. If completed, the whole process is terminated, and if not, progress to Step S70 is made.

[0169] With the input/output probing apparatus and input/output probing method of the present invention as above, it is possible for a circuit for its design verification to be fully verified in its design by alternate performance of the emulation and simulation with no limitation in their conversion numbers.

[0170]FIG. 12 schematically illustrates an example, in which the combined verification environment using the emulation and simulation is constructed in standalone mode.

[0171] However, it is desirable for a prototyping board performing the emulation and a simulator performing the simulation to be performed under the environment that the prototyping board and the simulator are distributed through a network. Considering such environment, FIG. 13 schematically illustrates an example, in which the combined verification environment using the simulation and simulation is constructed through a short/long-distance network.

[0172]FIG. 14 schematically illustrates an enlarged example of such environment that the emulation and simulation can be performed under the distributed environment on the inter-network (for example, internet).

[0173]FIG. 15 is a flow chart illustrating the steps of the combined verification method of emulation and simulation according to an embodiment of the present invention, which is performed by a server computer (20) shown in FIG. 12 or FIG. 13 or FIG. 13.

[0174] In the step S100, a circuit for its design verification and the name of ASIC vendor library used at the time of the design are inputted by the server computer. Thereafter, the extended design verification object circuit added with the additional circuit for IOP-probe is generated in an automatic method, by performing the input/output probing system software, in at least one RFPD of the arbitrary prototyping board or the arbitrary PCB capable of input/output probe. Then, said generated extended circuit for its design verification is realized in at least one RFPD on the arbitrary prototyping board or the arbitrary PCB, and the simulation using an arbitrary simulator for the circuit for its design verification is prepared in the server computer.

[0175] In the step S102, the initial state information (state information: values of all storage elements (flip-flop or latch) in a circuit) on the circuit for its design verification to be a combined verification object of emulation and simulation is inputted by the server computer (20). Then, after making the present state information of a simulation circuit for the arbitrary simulator and an emulation circuit for the arbitrary prototyping board or arbitrary PCB the same as the initial state information, the conversion point or conversion condition sequence of the verification method is determined. The determined conversion point or conversion condition sequence is stored in an execution mode switching condition queue, and then, the first queue is determined as the conversion point and conversion condition of the present verification method.

[0176] In the step S104, it is determined whether the present state information is verified by emulation or by simulation. In case that the verification by emulation is determined, it proceeds to the step S106 where the verification by emulation is proceeded by said arbitrary prototyping board or arbitrary PCB till the present verification stop point or stop condition is satisfied. In the step S108, it is examined whether an additional verification process is necessary. As a result of the examination, if such a process is not necessary, the entire process is ended; however, if necessary, it proceeds to the step S109.

[0177] In the step S109, it is examined whether the execution mode switching condition queue is vacant. If it is not vacant, it proceeds to the step S115; however, if vacant, to the step S111. In the step S111, it is examined whether the conversion point or conversion condition sequence of a new verification method should be stored in the execution mode switching condition queue. If its storage is not necessary, it proceeds to the step S108; however, if necessary, to the step S113.

[0178] In the step S113, the conversion point or conversion condition sequence of the new verification method is stored in the execution mode switching condition queue and then it proceeds to the step S115. In the step S115, the conversion point and conversion condition of the present verification method are newly established as the execution switching condition queue and then it proceeds to the step S117. In the step S117, it is examined whether the present verification method is performed by the emulation or by the simulation. If the method is by the emulation, it proceeds to the step S134; however, if by simulation, to the step S132.

[0179] In the step 132, the input probe of the present invention for RFPDs is performed. By such input probe, the extended circuit for its design verification realized in at least one RFPD on the arbitrary prototyping board or arbitrary PCB has exactly the same present state information as that of the circuit for its design verification of at the present verification stop point. Such present state information is obtained through the simulation on the server computer. Then, it proceeds to the step S106. In the step S134, the output probe of the present invention for at least one RFPDs on the arbitrary prototyping board is performed. By such output probe, the circuit for its design verification performed by the arbitrary simulator on the server computer has the same present state information as that of the circuit for its design verification of at the present verification stop point. Then, it proceeds to the step S120.

[0180] In the step S120, the verification by simulation is proceeded till the conversion point or conversion condition of the present verification method is satisfied, by the arbitrary simulator on the sever computer. Then, it proceeds to the step S108.

[0181]FIG. 16 is a flowchart illustrating the steps of the combined verification method of simulation and emulation according to another embodiment of the present invention, which is performed by the server computer (20) displayed in FIG. 12 or FIG. 13 or FIG. 14.

[0182] In the step S300, the HDL code for its design verification and the name of ASIC vender library used at the time of the design are inputted by the server computer. Then, the extended HDL code for its design verification added with the additional HDL code for IOP probe is generated in an automatic method by the input/output probing system software in at least one RFPD on the arbitrary prototyping board or the arbitrary PCB capable of the input/output probe according to the present invention. The generated extended HDL code for its design verification is realized in at least one RFPD on the arbitrary prototyping board or arbitrary PCB. Then, the simulation using the arbitrary simulator for the HDL code for its design verification is prepared on the server computer.

[0183] In the step S302, the initial state information (state information: values of all storage elements (flip-flop or latch) in a circuit) on the HDL code for its design verification to be a combined verification object of emulation and simulation is inputted by the server computer (20). Then, after making the present state information of a simulation HDL code for the arbitrary simulator and an emulation HDL code for the arbitrary prototyping board or arbitrary PCB the same as the initial state information, the conversion point or conversion condition sequence of the verification method is determined. The determined conversion point or conversion condition sequence is stored in an execution mode switching condition queue, and then, the first queue is determined as the conversion point and conversion condition of the present verification method.

[0184] In the step S304, it is determined whether the present state information is verified by emulation or by simulation. In case that the verification by emulation is determined, it proceeds to the step S306, where the verification by emulation is proceeded by said arbitrary prototyping board or arbitrary PCB till the present verification stop point or stop condition is satisfied. In the step S308, it is examined whether an additional verification process is necessary. As a result of the examination, if such a process is not necessary, the entire process is ended; however, if necessary, it proceeds to the step S309.

[0185] In the step S309, it is examined whether the execution mode switching condition queue is vacant. If it is not vacant, it proceeds to the step S315; however, if vacant, to the step S311. In the step S311, it is examined whether the conversion point or conversion condition sequence of a new verification method should be stored in the execution mode switching condition queue. If its storage is not necessary, it proceeds to the step S308; however, if necessary, to the step S313. In the step S313, the conversion point or conversion condition sequence of the new verification method is stored in the execution mode switching condition queue and then it proceeds to the step S315.

[0186] In the step S315, the conversion point and conversion condition of the present verification method are newly established as the execution switching condition queue and then it proceeds to the step S317. In the step S317, it is examined whether the present verification method is performed by the emulation or by the simulation. If the method is by the emulation, it proceeds to the step S334; however, if by simulation, to the step S332. In the step 332, the input probe of the present invention for RFPDs is performed. By such input probe, the extended HDL code for its design verification realized in at least one RFPD on the arbitrary prototyping board or arbitrary PCB has exactly the same present state information as that of the HDL code for its design verification of at the present verification stop point. Such present state information is obtained through the simulation on the server computer. Then, it proceeds to the step S306.

[0187] In the step S334, the output probe of the present invention for at least one RFPDs on the arbitrary prototyping board is performed. By such output probe, the HDL code for its design verification performed by the arbitrary simulator on the server computer has the same present state information as that of the HDL code for its design verification of at the present verification stop point. Then, it proceeds to the step S320. In the step S320, the verification by simulation is proceeded till the conversion point or conversion condition of the present verification method is satisfied, by the arbitrary simulator on the sever computer. Then, it proceeds to the step S308.

INDUSTRIAL APPLICABILITY

[0188] As mentioned above, according to the present invention directed to an input/output probing apparatus and an input/output probing method using the same, it is possible to rapidly and effectively debug, with 100% perfect signal visibility, a circuit for its design verification which is realized in at least one semiconductor chip equipped on an arbitrary prototyping board or arbitrary PCB and then emulated. Also, said apparatus and method enable the state information exchange with a circuit for its design verification simulated on an arbitrary simulator in a complete automatic method, thereby making the alternate high-speed functional verification and accurate timing verification possible so that the performance of very effective verification is possible. Such advantages are perfectly supported both under the ICE environment and when using on-chip memory in RFPD.

[0189] From the aforementioned description, it will be understood to those skilled in the art that various modifications and conversion are possible within the scope of the technical idea of the present invention. Accordingly, the technical scope of the present invention shall be limited solely by the scope of the claims appended hereto not by the contents described in the embodiments.

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Classifications
U.S. Classification714/725, 716/106, 716/117
International ClassificationG01R31/3183, G01R31/28, G01R31/317, G06F17/50, G01R31/3185
Cooperative ClassificationG06F17/5022, G01R31/318357, G01R31/31715, G06F17/5027
European ClassificationG01R31/317K3, G06F17/50C3E, G06F17/50C3, G01R31/3183F3
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