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Publication numberUS20030194842 A1
Publication typeApplication
Application numberUS 10/128,742
Publication dateOct 16, 2003
Filing dateApr 23, 2002
Priority dateApr 12, 2002
Also published asUS6642113, US6812507, US20040026732
Publication number10128742, 128742, US 2003/0194842 A1, US 2003/194842 A1, US 20030194842 A1, US 20030194842A1, US 2003194842 A1, US 2003194842A1, US-A1-20030194842, US-A1-2003194842, US2003/0194842A1, US2003/194842A1, US20030194842 A1, US20030194842A1, US2003194842 A1, US2003194842A1
InventorsShou-Wei Huang, Tung-Cheng Kuo, Chien-Hung Liu, Shyi-Shuh Pan
Original AssigneeTung-Cheng Kuo, Chien-Hung Liu, Shyi-Shuh Pan, Shou-Wei Huang
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Non-volatile memory capable of preventing antenna effect and fabrication thereof
US 20030194842 A1
Abstract
A non-volatile memory capable of preventing the antenna effect and the fabrication thereof are described. The non-volatile memory includes a word-line having a high resistance portion and a memory cell portion on a substrate and a charge trapping layer located between the word-line and the substrate. The high resistance portion is electrically connected with a grounding doped region in the substrate and the memory cell portion is electrically connected with a metal interconnect over the substrate.
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Claims(19)
What is claimed is:
1. A non-volatile memory capable of preventing an antenna effect, comprising:
a word-line disposed on a substrate, wherein the word-line comprises a metal silicide layer and a polysilicon layer and is divided into a high resistance portion and a memory cell portion, wherein the high resistance portion is electrically connected with a grounding doped region in the substrate;
a charge trapping layer located between the word-line and the substrate; and
a metal interconnect electrically connecting with the memory cell portion of the word-line via a first contact.
2. The non-volatile memory of claim 1, wherein the high resistance portion of the word-line is narrower than the memory cell portion of the word-line.
3. The non-volatile memory of claim 1, wherein the high resistance portion of the word-line is electrically connected with the grounding doped region via a second contact.
4. The non-volatile memory of claim 1, wherein the charge trapping layer comprises a silicon oxide/silicon nitride/silicon oxide (ONO) composite layer.
5. The non-volatile memory of claim 1, wherein the metal silicide layer comprises tungsten silicide.
6. A method for fabricating a non-volatile memory capable of preventing an antenna effect, comprising the steps of:
forming a charge trapping layer on a substrate;
forming a word-line on the charge trapping layer, the word-line having a memory cell portion and a high resistance portion;
forming a grounding doped region in the substrate;
electrically connecting the grounding doped region and the high resistance portion of the word-line; and
forming a metal interconnect over the substrate to electrically connect with the memory cell portion of the word-line.
7. The method of claim 6, wherein the high resistance portion the word-line is electrically connected with the grounding doped region via a contact.
8. The method of claim 6, wherein the metal interconnect is electrically connected with the memory cell portion of the word-line via a contact.
9. The method of claim 6, further comprising applying a large current to blow the high resistance portion of the word-line.
10. The method of claim 6, wherein the charge trapping layer comprises a silicon oxide/silicon nitride/silicon oxide (ONO) composite layer.
11. The method of claim 6, further comprising forming a dielectric layer over the substrate covering the word-line after the grounding doped region is formed in the substrate.
12. The method of claim 11, wherein the dielectric layer comprises borophosphosilicate glass (BPSG).
13. A method for fabricating a non-volatile memory capable of preventing an antenna effect, comprising the steps of:
providing a substrate;
forming sequentially a charge trapping layer, a polysilicon layer and a metal silicide layer on the substrate;
patterning the metal silicide layer, the polysilicon layer and the charge trapping layer to form a word-line having a memory cell portion and a high resistance portion;
forming a grounding doped region in the substrate;
forming a first contact on the substrate to electrically connect the grounding doped region and the high resistance portion of the word-line; and
forming a second contact over the substrate to electrically connect with the memory cell portion of the word-line.
14. The method of claim 13, further comprising forming a metal interconnect over the substrate to electrically connect with the second contact.
15. The method of claim 13, further comprising applying a large current to blow the high resistance portion of the word-line.
16. The method of claim 13, wherein the charge trapping layer comprises a silicon oxide/silicon nitride/silicon oxide (ONO) composite layer.
17. The method of claim 13, wherein the metal silicide layer comprises tungsten silicide.
18. The method of claim 13, further comprising forming a dielectric layer over the substrate covering the word-line after the grounding doped region is formed in the substrate.
19. The method of claim 18, wherein the dielectric layer comprises borophosphosilicate glass (BPSG).
Description
CROSS-REFERENCE TO RELATED APPLICATION

[0001] This application claims the priority benefit of Taiwan application serial no. 91107421, filed Apr. 12, 2002.

BACKGROUND OF THE INVENTION

[0002] 1. Field of Invention

[0003] The present invention relates to a structure of a semiconductor device and the fabrication thereof. More particularly, the present invention relates to a structure of a non-volatile memory capable of preventing the antenna effect and the fabrication thereof.

[0004] 2. Description of Related Art

[0005] In a method for fabricating a non-volatile memory, a charge trapping layer and a polysilicon gate are formed sequentially on a substrate and then a source/drain region is formed in the substrate beside the polysilicon gate. When the charge trapping layer is a silicon nitride-based layer, the non-volatile memory can be called a “nitride read-only memory (NROM)”.

[0006] In a process of fabricating a non-volatile memory with a charge trapping layer, plasma techniques are frequently used. However, when a transient charge unbalance occurs in the plasma, charges will move along the conductive portions on the target wafer. Such an effect is called the “antenna effect”. Consequently, some charges are injected into the charge trapping layers of the non-volatile memory to unevenly raise the threshold voltages (VT) of the memory cells, i.e., to produce a programming effect. Therefore, the VT distribution of the non-volatile memory is much broadened, being usually from 0.3V to 0.9V.

[0007] In order to prevent the programming effect caused by the antenna effect, a diode is formed in the substrate to electrically connect with the word-line in the prior art. When the charges accumulated on the word-line reach a certain amount to produce a voltage higher than the breakdown voltage of the diode, the charges are released in a breakdown manner. However, the programming effect cannot be completely eliminated with this method since there may still be some charges injected into the charge trapping layer even if the voltage produced is lower than the breakdown voltage of the diode. Moreover, by using this method, the input voltage of the non-volatile memory is lowered by the diode to adversely decrease the operating speed of the memory device.

SUMMARY OF THE INVENTION

[0008] Accordingly, this invention provides a non-volatile memory and the fabrication thereof to prevent the charge trapping layer of a non-volatile memory from being damaged in a plasma process.

[0009] This invention also provides a non-volatile memory and the fabrication thereof to prevent the non-volatile memory from being programmed in a plasma process, so that the threshold voltages (VT) of the memory cells are not raised and the VT distribution is not broadened.

[0010] This invention also provides a non-volatile memory and the fabrication thereof to avoid the input voltage of the memory device from being lowered, so that the operating speed is not decreased.

[0011] The non-volatile memory of this invention includes a word-line having a high resistance portion and a memory cell portion on a substrate and a charge trapping layer located between the word-line and the substrate. The high resistance portion of the word-line is electrically connected with a grounding doped region in the substrate and the memory cell portion is electrically connected with a metal interconnect over the substrate. The high resistance portion of the word-line is, for example, narrower than the other portions of the word-line in order to have a higher resistance.

[0012] This invention also provides a method for fabricating a non-volatile memory capable of preventing the antenna effect. In this method, a charge trapping layer is formed on a substrate and then a word-line having a high resistance portion and a memory cell portion is formed on the substrate. A grounding doped region is formed in the substrate and then the high resistance portion of the word-line is electrically connected with the grounding doped region. Thereafter, a metal interconnect is formed over the substrate to electrically connect with the memory cell portion of the word-line. When the process is completed, a large current is applied to blow the high resistance portion of the word-line.

[0013] This invention provides another method for fabricating a non-volatile memory capable of preventing the antenna effect. A charge trapping layer, a polysilicon layer and a metal silicide layer are formed sequentially on a substrate and then patterned to form a word-line having a memory cell portion and a high resistance portion. A grounding doped region is formed in the substrate and then a first contact is formed on the substrate to electrically connect the grounding doped region and the high resistance portion of the word-line. A second contact is formed over the substrate to electrically connect with the memory cell portion of the word-line. When the process is completed, a large current is applied to blow the high resistance portion of the word-line.

[0014] Because this invention uses a high resistance portion of the word-line to conduct the charges accumulated on the word-line into the substrate in a plasma process, the charge trapping layer of the non-volatile memory is not damaged and the memory cells are not programmed at random. Moreover, since the high resistance portion of the word-line has a high resistance, applying a large current can easily blow the high resistance portion to disconnect the word-line from the grounding doped region after the manufacturing process. Consequently, the input voltage of the memory device is not lowered and the operating speed of the memory device is not decreased.

[0015] It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0021] First Embodiment

[0022] Refer to FIG. 1, FIG. 1 illustrates a top view of a non-volatile memory structure capable of preventing the antenna effect according to the first embodiment of this invention.

[0023] As that shown in FIG. 1, a word-line 102 having a high resistance portion 104 and a memory cell portion 106 is located on a substrate 100. The high resistance portion 104 of the word-line 102 is narrower than the memory cell portion 106 in order to have a higher resistance and is electrically connected with a grounding doped region 108 formed in the substrate 100 via a contact 112. The memory cell portion 106 of the word-line 102 is electrically connected with a metal interconnect 110 via a contact 114.

[0024] Refer to FIG. 2 to further understand the non-volatile memory structure according to the first embodiment of this invention. FIG. 2 illustrates a cross-sectional view of the non-volatile memory structure shown in FIG. 1 along the line II-II.

[0025] As that shown in FIG. 2, a word-line 102 comprising a polysilicon layer 103 and a metal silicide layer 105 is disposed on the substrate 100, wherein the metal silicide layer 105 comprises, for example, tungsten silicide (WSix). A charge trapping layer 101, which may comprise a silicon oxide/silicon nitride/silicon oxide (ONO) composite layer, is located between the word-line 102 and the substrate 100. When the charge trapping layer 101 is based on a silicon nitride layer, the non-volatile memory being fabricated can be called a “nitride read-only memory (NROM)”. The two contacts 112 and 114 are located in a dielectric layer 116 that comprises a material such as borophosphosilicate glass (BPSG). When the process is completed, a large current is applied to blow the high resistance portion 104 of the word-line 102.

[0026] Second Embodiment

[0027] Refer to FIG. 3A˜3C, FIG. 3A˜3C illustrate a process flow of fabricating a non-volatile memory capable of preventing the antenna effect according to the second embodiment of this invention in a cross-sectional view

[0028] Refer to FIG. 3A, a charge trapping layer 302, a polysilicon layer 306 and a metal silicide layer 308 are formed sequentially on a substrate 300 and then patterned to form a word-line 304 that has a high resistance portion 310 and a memory cell portion 312. The high resistance portion 310 of the word-line 304 is, for example, narrower than the memory cell portion 312 in order to have a higher resistance.

[0029] Refer to FIG. 3B, a grounding doped region 314 is formed in the substrate 300 overlapping a portion of the high resistance portion 310 of the word-line 304.

[0030] Refer to FIG. 3C, a dielectric layer 316 is formed over the substrate 300. A contact 318 is formed in the dielectric layer 316 to electrically connect the grounding doped region 314 and the high resistance portion 310 of the word-line 304. Another contact 320 is formed simultaneously in the dielectric layer 316 to electrically connect with the memory cell portion 312 of the word-line 304. Thereafter, a metal interconnect 322 is formed over the substrate 300 to electrically connect with the memory cell portion 312 of the word-line 304 via the contact 320.

[0031] Refer to FIG. 4A and 4B to further understand the structure of the high resistance portion 310 of the word-line 304. FIG. 4A and FIG. 4B illustrate a magnified cross-sectional view and a magnified top view, respectively, of the high resistance portion 310 shown in FIG. 3C.

[0032] As that shown in FIG. 4B, the high resistance portion 310 of the word-line 304 is narrower than the other portions of the word-line 304 to have a higher resistance. Therefore, when the manufacturing process is completed, a large current can be applied to blow the high resistance portion 310 of the word-line 304 to disconnect the memory cell portion 312 of the word-line 304 from the grounding doped region 314.

[0033] Since this invention uses a high resistance portion of the word-line to electrically connect the substrate and the word-line, the charges accumulated on the word-line can be conducted into the substrate in a plasma process. It is noted that the charges are produced in a small amount despite that the plasma environment has a relative high voltage level, so that the current formed from the charges is weak and the high resistance portion of the word-line is not blown. Therefore, the charge trapping layer of the non-volatile memory is not damaged and the memory cells are not programmed at random.

[0034] Moreover, since the high resistance portion of the word-line has a high resistance, applying a large current can easily blow the high resistance portion to disconnect the word-line from the grounding doped region when the manufacturing process is completed. Consequently, the input voltage of the memory device is not lowered and the operating speed of the memory device is not decreased.

[0035] It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention covers modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.

BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawings,

[0017]FIG. 1 illustrates a top view of a non-volatile memory structure capable of preventing the antenna effect according to a first embodiment of this invention;

[0018]FIG. 2 illustrates a cross-sectional view of the non-volatile memory structure shown in FIG. 1 along the line II-II;

[0019]FIG. 3A˜3C illustrate a process flow of fabricating a non-volatile memory capable of preventing the antenna effect according to a second embodiment of this invention in a cross-sectional view; and

[0020]FIG. 4A and FIG. 4B illustrate a magnified cross-sectional view and a magnified top view, respectively, of the high resistance portion shown in FIG. 3C.

Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US6869844 *Nov 5, 2003Mar 22, 2005Advanced Micro Device, Inc.Method and structure for protecting NROM devices from induced charge damage during device fabrication
US7675173Oct 18, 2006Mar 9, 2010Infineon Technologies AgManufacturing semiconductor circuit, corresponding semiconductor circuit, and associated design process
DE102005049793B3 *Oct 18, 2005Jul 5, 2007Infineon Technologies AgVerfahren zur Herstellung einer Halbleiterschaltung, entsprechend hergestellte Halbleiterschaltung sowie zugehöriges Entwurfsverfahren
Classifications
U.S. Classification438/258, 257/E21.423, 438/261, 257/E21.21
International ClassificationH01L21/28, H01L21/336
Cooperative ClassificationY10S438/954, H01L21/28282, H01L29/66833
European ClassificationH01L29/66M6T6F18, H01L21/28G
Legal Events
DateCodeEventDescription
Feb 21, 2011FPAYFee payment
Year of fee payment: 8
Jan 31, 2007FPAYFee payment
Year of fee payment: 4
Apr 23, 2002ASAssignment
Owner name: MACRONIX INTERNATIONAL CO., LTD., TAIWAN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:KUO, TUNG-CHENG;LIU, CHIEN-HUNG;PAN, SHYI-SHUH;AND OTHERS;REEL/FRAME:012836/0034
Effective date: 20020410
Owner name: MACRONIX INTERNATIONAL CO., LTD. SCIENCE-BASED IND
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:KUO, TUNG-CHENG /AR;REEL/FRAME:012836/0034