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Publication numberUS20030199112 A1
Publication typeApplication
Application numberUS 10/393,531
Publication dateOct 23, 2003
Filing dateMar 21, 2003
Priority dateMar 22, 2002
Also published asUS8005634, US20070122921
Publication number10393531, 393531, US 2003/0199112 A1, US 2003/199112 A1, US 20030199112 A1, US 20030199112A1, US 2003199112 A1, US 2003199112A1, US-A1-20030199112, US-A1-2003199112, US2003/0199112A1, US2003/199112A1, US20030199112 A1, US20030199112A1, US2003199112 A1, US2003199112A1
InventorsArulkumar Shanmugasundram, Suketu Parikh
Original AssigneeApplied Materials, Inc.
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Copper wiring module control
US 20030199112 A1
Abstract
Techniques for controlling an output property during wafer processing include forwarding feedforward and feedback information between functional units in a wafer manufacturing facility. At least some embodiments of the invention envision implementing such techniques in a copper wiring module to optimize a sheet resistance or an interconnect line resistance. Initially, a first wafer property is measured during or after processing by a plating process. Subsequently, the wafer is forwarded to a polishing process. A second wafer property is then measured during or after processing by the second process. At least one of these first and second wafer properties are used to optimize the second process. Specifically, one or more target parameters of a second process recipe are adjusted in a manner that obtains a desired final output property on the wafer by using these first and second wafer properties. Examples of the wafer properties that may be measured at the first process include thickness profile, edge exclusion information, sheet resistance profile, reflectance, resistivity drop, and reflectivity. Examples of the wafer properties that may be measured at the second process include copper clearing time, reflectance, thickness, and an electrical property.
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Claims(57)
We claim:
1. A method for controlling an output property during wafer processing in a copper wiring module, said method comprising the steps of:
(1) measuring plating wafer property information during or after processing by a plating process;
(2) feeding said plating wafer property information to a polishing process, said polishing process comprising at least one copper removal step;
(3) measuring polishing wafer property information during or after processing by said polishing process; and
(4) optimizing said polishing process by using at least one of said plating wafer property information and said polishing wafer property information to modify one or more target parameters of said at least one copper removal process of said polishing process to obtain a desired output property on said wafer.
2. The method of claim 1, wherein the output property comprises at least one of a sheet resistance or an interconnect line resistance.
3. The method of claim 1, further comprising:
measuring wafer property information during or after processing by one or more upstream wafer processing processes; and
further optimizing said polishing process by using said wafer property information from said one or more upstream processing processes to modify one or more target parameters of said at least one copper removal process of said polishing process.
4. The method of claim 3, wherein said one or more upstream wafer processing processes comprises at least one of an etch or dielectric deposition process.
5. The method of claim 3, wherein said wafer property information measured at said one or more upstream wafer processing processes comprises at least one of a dielectric deposition thickness, dielectric deposition uniformity, critical depth, critical width, or trench depth.
6. The method of claim 1, wherein said one or more target parameters of said polishing process comprises a removal rate parameter.
7. The method of claim 1, wherein said one or more target parameters of said polishing process comprises a removal rate parameter and a bulk polish time.
8. The method of claim 1, said plating wafer property information comprises at least one of a thickness profile, edge exclusion information, sheet resistance profile, reflectance, resistivity drop, and reflectivity.
9. The method of claim 1, said polishing wafer property information comprises copper clearing time, reflectance, thickness, and an electrical property.
10. The method of claim 1, wherein said polishing process comprises a bulk polish process, an endpoint process, and a barrier polish process.
11. The method of claim 10, wherein said polishing wafer property information comprises thickness profile information collected during or after said bulk polish process.
12. The method of claim 10, wherein said polishing wafer property information comprises copper clearing information collected during or after said endpoint process.
13. The method of claim 10, wherein said polishing wafer property information comprises an electrical property collected during or after said barrier polish process.
14. The method of claim 1, wherein said polishing process comprises a chemical mechanical polishing process and said plating process comprises an electro chemical plating process.
15. A copper wiring module for processes wafers, said copper wiring module comprising:
a plating tool for applying a plating to a wafer;
a first metrology device for measuring plating wafer property information during or after processing by the plating tool;
a polishing tool for polishing the wafer via at least one copper removal step;
a second metrology device for measuring plating wafer property information during or after processing by the polishing tool; and
a controller for optimizing processing of the polishing tool by using at least one of said plating wafer property information received from said first metrology device and said polishing wafer property information received from said second metrology device to modify one or more target parameters of said at least one copper removal process of said polishing process to obtain a desired output property on said wafer.
16. The system of claim 15, wherein the output property comprises at least one of a sheet resistance or an interconnect line resistance.
17. The system of claim 15, further comprising:
one or more upstream wafer processing tools;
a third metrology device for measuring wafer property information during or after processing by said one or more upstream wafer processing tools; and
wherein said controller further optimizes processing of said polishing tool by using said wafer property information from said one or more upstream processing processes to modify one or more target parameters of said at least one copper removal process of said polishing tool.
18. The system of claim 17, wherein said one or more upstream wafer processing tools comprises at least one of an etch or dielectric deposition tool.
19. The system of claim 17, wherein said wafer property information measured at said one or more upstream wafer processing processes comprises at least one of a dielectric deposition thickness, dielectric deposition uniformity, critical depth, critical width, or trench depth.
20. The system of claim 15, wherein said one or more target parameters of said polishing tool comprises a removal rate parameter.
21. The system of claim 15, wherein said one or more target parameters of said polishing tool comprises a removal rate parameter and a bulk polish time.
22. The system of claim 15, said plating wafer property information comprises at least one of a thickness profile, edge exclusion information, sheet resistance profile, reflectance, resistivity drop, and reflectivity.
23. The system of claim 15, wherein said polishing tool further comprises a bulk polish chamber, an endpoint chamber, and a barrier polish chamber.
24. The system of claim 23, wherein said polishing wafer property information comprises thickness profile information collected at said bulk polish chamber.
25. The system of claim 23, wherein said polishing wafer property information comprises copper clearing information collected at said endpoint chamber.
26. The system of claim 23, wherein said polishing wafer property information comprises an electrical property collected at said barrier polish chamber.
27. The system of claim 15, wherein said plating tool comprises an electro chemical plating tool and said polishing tool comprises a chemical mechanical polishing tool.
28. An optimizer for optimizing processing of a copper wiring module, said optimizer comprising:
a communications port for receiving plating wafer property information received from a first metrology device associated with a plating tool and polishing wafer property information received from a second metrology device associated with a polishing tool;
a memory for storing tool recipes used to control operation of said plating tool and said polishing tool; and
a controller for optimizing processing of said polishing tool by using at least one of said plating wafer property information and said polishing wafer property information to modify one or more target parameters of a polishing tool recipe to obtain a desired output property on a wafer.
29. A system for controlling an output property during wafer processing in a copper wiring module, said system comprising:
means for measuring plating wafer property information during or after processing by a plating process;
means for feeding said plating wafer property information to a polishing process, said polishing process comprising at least one copper removal step;
means for measuring polishing wafer property information during or after processing by said polishing process; and
means for optimizing said polishing process by using at least one of said plating wafer property information and said polishing wafer property information to modify one or more target parameters of said at least one copper removal process of said polishing process to obtain a desired output property on said wafer.
30. The system of claim 29, wherein the output property comprises at least one of a sheet resistance or an interconnect line resistance.
31. The system of claim 29, further comprising:
means for measuring wafer property information during or after processing by one or more upstream wafer processing processes; and
means for further optimizing said polishing process by using said wafer property information from said one or more upstream processing processes to modify one or more target parameters of said at least one copper removal process of said polishing process.
32. The system of claim 31, wherein said one or more upstream wafer processing processes comprises at least one of an etch or dielectric deposition process.
33. The system of claim 31, wherein said wafer property information measured at said one or more upstream wafer processing processes comprises at least one of a dielectric deposition thickness, dielectric deposition uniformity, critical depth, critical width, or trench depth.
34. The system of claim 29, wherein said one or more target parameters of said polishing process comprises a removal rate parameter.
35. The system of claim 29, wherein said one or more target parameters of said polishing process comprises a removal rate parameter and a bulk polish time.
36. The system of claim 29, said plating wafer property information comprises at least one of a thickness profile, edge exclusion information, sheet resistance profile, reflectance, resistivity drop, and reflectivity.
37. The system of claim 29, said polishing wafer property information comprises copper clearing time, reflectance, thickness, and an electrical property.
38. The system of claim 29, wherein said polishing process comprises a bulk polish process, an endpoint process, and a barrier polish process.
39. The system of claim 38, wherein said polishing wafer property information comprises thickness profile information collected during or after said bulk polish process.
40. The system of claim 38, wherein said polishing wafer property information comprises copper clearing information collected during or after said endpoint process.
41. The system of claim 38, wherein said polishing wafer property information comprises an electrical property collected during or after said barrier polish process.
42. The system of claim 39, wherein said plating process comprises an electro chemical plating process and said polishing process comprises a chemical mechanical polishing process.
43. An optimizer for optimizing processing of a copper wiring module, said optimizer comprising:
means for receiving plating wafer property information received from a first metrology device associated with a plating tool and polishing wafer property information received from a second metrology device associated with a polishing tool;
means for storing tool recipes used to control operation of said plating tool and said polishing tool; and
means for optimizing processing of said polishing tool by using at least one of said plating wafer property information and said polishing wafer property information to modify one or more target parameters of a polishing tool recipe to obtain a desired output property on a wafer.
44. A computer readable medium for controlling an output property during wafer processing in a copper wiring module, said computer readable medium comprising:
computer readable instructions for measuring plating wafer property information during or after processing by a plating process;
computer readable instructions for feeding said plating wafer property information to a polishing process, said polishing process comprising at least one copper removal step;
computer readable instructions for measuring polishing wafer property information during or after processing by said polishing process; and
computer readable instructions for optimizing said polishing process by using at least one of said plating wafer property information and said polishing wafer property information to modify one or more target parameters of said at least one copper removal process of said polishing process to obtain a desired output property on said wafer.
45. The computer readable medium of claim 44, wherein the output property comprises at least one of a sheet resistance or an interconnect line resistance.
46. The computer readable medium of claim 44, further comprising:
computer readable instructions for measuring wafer property information during or after processing by one or more upstream wafer processing processes; and
computer readable instructions for further optimizing said polishing process by using said wafer property information from said one or more upstream processing processes to modify one or more target parameters of said at least one copper removal process of said polishing process.
47. The computer readable medium of claim 46, wherein said one or more upstream wafer processing processes comprises at least one of an etch or dielectric deposition process.
48. The computer readable medium of claim 46, wherein said wafer property information measured at said one or more upstream wafer processing processes comprises at least one of a dielectric deposition thickness, dielectric deposition uniformity, critical depth, critical width, or trench depth.
49. The computer readable medium of claim 46, wherein said one or more target parameters of said polishing process comprises a removal rate parameter.
50. The computer readable medium of claim 46, wherein said one or more target parameters of said polishing process comprises a removal rate parameter and a bulk polish time.
51. The computer readable medium of claim 46, said plating wafer property information comprises at least one of a thickness profile, edge exclusion information, sheet resistance profile, reflectance, resistivity drop, and reflectivity.
52. The computer readable medium of claim 46, said polishing wafer property information comprises copper clearing time, reflectance, thickness, and an electrical property.
53. The computer readable medium of claim 46, wherein said polishing process comprises a bulk polish process, an endpoint process, and a barrier polish process.
54. The computer readable medium of claim 53, wherein said polishing wafer property information comprises thickness profile information collected during or after said bulk polish process.
55. The computer readable medium of claim 53, wherein said polishing wafer property information comprises copper clearing information collected during or after said endpoint process.
56. The computer readable medium of claim 53, wherein said polishing wafer property information comprises an electrical property collected during or after said barrier polish process.
57. The computer readable medium of claim 44, wherein said plating process comprises an electro chemical plating process and said polishing process comprises a chemical mechanical polishing process.
Description
CROSS REFERENCE TO RELATED APPLICATION

[0001] This application claims the benefit of U.S. Provisional Application 60/366,270, filed on Mar. 22, 2002, which is incorporated herein by reference.

FIELD OF THE INVENTION

[0002] The present invention relates generally to semiconductor wafer manufacturing systems and processes. More particularly, the present invention relates to techniques for optimizing semiconductor manufacturing processes at, for example, the fab, tool, and/or module levels using feedback and/or feedforward information. Even more particularly, the present invention relates to techniques for optimizing semiconductor manufacturing processes at, for example, a copper wiring module using feedback and/or feedforward information from the various tools within the module.

BACKGROUND OF THE INVENTION

[0003] Present-day semiconductor wafer fabrication factories (or ‘fabs’) are extremely complex environments that require an extraordinary amount of coordination. A typical fab may consist of hundreds of wafer processing functional units. Examples of these functional units include modules, submodules, tools, cluster tools, chambers, and any other entities responsible for performing one or more of a variety of operations or processes on a semiconductor wafer. The subject of processing by these functional units includes semiconductor wafers, which may be processed into a wide variety of items such as logic (e.g., central processing units) or memory (e.g., DRAMs). Each tool in the fab is responsible for performing one or more operations or series of operations that result in the final product. After a tool performs its operation, the wafer may be forwarded to a downstream tool where additional operations or series of operations may be performed. Each tool may process wafers according to hundreds of distinct processes, with each having hundreds of individual steps. Ultimately, the sum of the operations performed by these tools (e.g., the functional units in the fab) on the wafer results in the final product or the final state of the wafer.

[0004] In typical situations, the tools may be grouped, either logically or physically, into modules (which constitute a higher level functional unit relative to the tools) to produce a module level product (e.g., a product at the module level). For example, a number of tools may be grouped together in a copper wiring module to produce intricate copper geometric circuit patterns on the substrate of a wafer. These modules may include, at one or more portions thereof, any number of tools such as, for example, electro chemical plating (ECP) tools, chemical mechanical polishing (CMP) tools, and other similar tools. In a typical processing scheme, wafers are initially moved into a chamber of the ECP tool where an electroplating or plating process takes place. The result of the plating process is the application of, for example, a thin layer of copper on the wafer substrate. From there, the wafer may be moved downstream to a CMP tool. The CMP tool polishes the wafer to remove any excess metallization (i.e., the plating or plated material). Afterwards, the wafer may be moved to the next tool in the module, which may include, for example, a barrier polishing or other similar tool. The end result or final product of the module includes the remaining copper material, which forms the desired copper geometric circuit pattern.

[0005] In addition to the above-described processes performed by the functional units on a wafer (e.g., the application and subsequent polishing of metallization by tools in a copper wiring module), a number of quality control operations may be implemented within the functional units to improve the overall quality of the fab. In typical situations, any number of wafer attributes or properties may be measured during or after processing by a functional unit. These measured properties may then be compared against the expected results or target parameters. If a measured property deviates too greatly from an expected result, a modification or adjustment may be made to the processing operation or procedure of the functional unit in an attempt to address the deficiency.

[0006] Thus, with the copper wiring module described above, after plating by an ECP tool, the thickness of a layer applied to a wafer may be measured to generate a thickness profile. If the plated layer is too thick, the ECP tool recipe may be modified to decrease a plating time (i.e., the amount of time plating material is applied to the wafer). In a similar manner, after polishing at a CMP tool, the thickness of the polished layer may be similarly measured. If the layer is too thick, the CMP tool recipe may be modified to increase a polishing time (i.e., the amount of time the wafer is polished). In this manner, the control processes of the individual functional units within a fab may be modified to increase effectiveness and efficiency.

[0007] To implement these quality control measures, conventional wafer manufacturing systems contemplate, for example, that an engineer may inspect the product of a process after each step and manually update the recipe of that particular functional unit to address any unsatisfactory results. These products are monitored by using, for example, sensors or metrology devices after each processing step. More particularly, a wafer may be physically removed from the processing line, where any number of wafer properties may be measured, and subsequently returned to the line. For example, in the copper wiring module described above, a wafer may be removed after processing from a chamber in an ECP tool to allow measuring of a copper thickness. From there, the measured properties (e.g., the copper thickness) may be compared against the expected results or target parameters. When a less than satisfactory property or condition is identified, a modification may be made to the functional unit recipe to address the deficiency.

[0008] While these techniques addressed some of the problems faced with certain types of individual functional units (e.g., situations where the results of processing by a lone tool have drifted outside an acceptable range), they failed to consider the dramatic impact a wafer property at one functional unit could have on the processing effectiveness of another functional unit. Instead of sharing information between the functional units (e.g., between the ECP and CMP tools of a copper wiring module), the conventional approach was to address each functional unit and each problem individually.

[0009] One reason for this approach was the limited connectivity capability of the functional units. For example, the ECP tools and CMP tools of a copper wiring module were not capable of communicating easily with each other. Other reasons stemmed from the inability of the metrology devices of those functional units to collect data at a wafer level basis.

[0010] As a result, these conventional quality control processes had no way of addressing a deficient property measured at one functional unit anywhere but at that functional unit. Similarly, these processes did not share or transfer information upstream, downstream, or between runs to optimize processing. Thus, information measured at a CMP tool was not fed back to an ECP tool for purposes of optimizing processing of the CMP tool. This led to situations where one deficiency or problem may have been compounded by the existence of other problems at other functional units. In some cases, the remedies to a problem at one functional unit produced a result that may have been satisfactory to the first functional unit, but resulted in a condition or deficiency that was impossible to resolve at a downstream functional unit. As an example, to address the problem of a thicker than desirable plated layer, an ECP tool might decrease a plating time. While this modification may have resulted in a satisfactory result at the ECP tool, it may have also left a layer so thin that downstream CMP tools could not adequately process the wafer.

[0011] In the above and other cases, processing at one functional unit may be more effective if information could be utilized at other functional units to produce results that increase the effectiveness of processing of the first functional unit. For example, a CMP tool may process wafers more effectively if it could forward optimal processing information to an ECP tool. In this manner, the CMP tool may instruct the ECP tool to, for example, decrease a plating thickness.

[0012] What is therefore needed is a technique for optimizing semiconductor wafer manufacturing processes within a copper wiring module. Specifically, what is needed is a technique that transfers information from one tool within the copper wiring module to another for purpose of optimizing a copper wiring module output property. What is also needed is a technique that allows information or data to be transmitted between copper wiring module tools and/or processing runs. As a result, a tool may direct or request another tool to produce a result that provides optimal processing conditions for the requesting tool.

SUMMARY OF THE INVENTION

[0013] The present invention addresses the needs and the problems described above by using feedback and feedforward information to optimize manufacturing processes in a fab. For example, the invention may be implemented in a copper wiring module to optimize a copper wiring module output property such as a sheet resistance or an interconnect line resistance. Specifically, a first wafer property is initially measured during or after processing by a first process. One example of the first process includes an electro chemical plating process. Examples of the wafer properties that may be measured at the first process include thickness profile, edge exclusion information, sheet resistance profile, reflectance, resistivity drop, and reflectivity. Subsequently, the wafer is forwarded to a second process. An example of the second process includes a chemical mechanical polishing process. A second wafer property is then measured during or after processing by the second process. Examples of the wafer properties that may be measured at the second process include copper clearing time, reflectance, thickness, and an electrical property. Subsequently, at least one of these first and second wafer properties is used to optimize the second process. Specifically, one or more target parameters of a second process recipe are adjusted in a manner that obtains a desired final output property on the wafer (e.g., a sheet resistance or an interconnect line resistance) by using these first and second wafer properties.

[0014] In one or more parallel and at least somewhat overlapping embodiments, the second process (e.g., the CMP process) includes a bulk polish process, an endpoint process, and a barrier polish process. In these embodiments, information may be measured at any combination of these processes for optimization of the second process. Examples include thickness profile information collected during or after the bulk polish process, copper clearing information collected during or after the endpoint process, and/or electrical property information collected during or after the barrier polish process.

BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Various objects, features, and advantages of the present invention can be more fully appreciated as the same become better understood with reference to the following detailed description of the present invention when considered in connection with the accompanying drawings, in which:

[0016]FIG. 1 depicts one example of a block diagram representation of a semiconductor manufacturing facility or fab utilizable for implementing one or more aspects of the present invention;

[0017]FIG. 2 depicts one example of a block diagram representation of a semiconductor manufacturing tool utilizable for producing a tool product in the fab of FIG. 1;

[0018]FIG. 3 depicts one example of a process implementable for using feedback and feedforward information to optimize functional unit processing;

[0019]FIG. 4 depicts one example of a flow diagram of a process sequence for optimizing functional unit processing of one or more of the embodiments of the present invention;

[0020]FIG. 5 depicts one example of a process utilizable for forwarding feedback and/or feedforward information;

[0021]FIG. 6 depicts one example of a flow diagram of a process sequence for receiving and utilizing feedforward and feedback information to modify and/or generate functional unit recipes;

[0022]FIG. 7 depicts one example of a combined hardware and control process diagram of a copper wiring module illustrating one or more embodiments of the present invention;

[0023]FIG. 8 is a high-level block diagram depicting aspects of computing devices contemplated as part of and for use with one or more embodiments of the present invention; and

[0024]FIG. 9 illustrates one example of a memory medium which may be used for storing a computer implemented process of one or more embodiments of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0025] In accordance with one or more embodiments of the present invention, feedback and feedforward information is measured, transmitted and utilized by a number of functional units to optimize manufacturing processes used in the production of semiconductor wafers. For example, a sheet resistance or an interconnect line resistance output property of a copper wiring module may be optimized using information measured at the various tools within the module. Specifically, a first wafer property is initially measured during or after processing by a first process. Subsequently, the wafer is forwarded to a second process. A second wafer property is then measured during or after processing by the second process. At least one of these first and second wafer properties are used to optimize the second process. Specifically, one or more target parameters of a second process recipe are adjusted in a manner that obtains a desired final output property on the wafer by using these first and second wafer properties.

[0026]FIG. 1 depicts one example of a block diagram representation of a semiconductor manufacturing facility or fab 100 utilizable for implementing one or more aspects of the present invention. Fab 100 may be used to process semiconductor wafers to produce any number of semiconductor products, such as DRAMs, processors, etc. As shown in FIG. 1, fab 100 includes, among other components, any number of modules 120. Modules 120 individually process wafers to produce a module final product and operate in conjunction with each other to produce a fab final product. During operation, wafers are passed from one module to another where any number of operations may be performed. Examples of modules include copper wiring modules, physical vapor deposition (PVD) modules, dep-etch modules, and the like.

[0027] Each module includes, among other components, any number of tools 130. In a manner analogous to the above, tools 130 individually process wafers to produce a tool final product and operate in conjunction with each other to produce a module final product. Thus, similar to the module level, wafers are passed from one tool to another where any number of operations may be performed, the ultimate goal of which is to arrive at the module final product. In one or more embodiments of the present invention, at least some of the tools can be “cluster tools” (or the like) capable of performing multiple functions. Examples of tools include electro chemical plating (ECP), chemical mechanical polishing (CMP), chemical vapor deposition, etching, copper barrier seed, barrier polishing tools, and the like.

[0028]FIG. 2 depicts one example of a block diagram representation of a semiconductor manufacturing tool utilizable for producing a tool product in the fab of FIG. 1. Tool 130 includes any number of processing chambers 220. Each chamber may be responsible for performing a process or series of processes on a wafer. The sum total of these processes results in a tool final product. As an example, an ECP tool may include an electroplating or plating chamber, a material removal chamber, and a clearing chamber. In these examples, the plating chamber is responsible for applying a thin layer of plating material (i.e., metallization) onto a wafer substrate. From there, the wafer may be moved to the next chamber, in this case, the removal chamber, where any excess material may be removed. Processing continues in this manner, with the wafer being advanced from one chamber to another, until the desired final product has been produced. In conjunction with the processing that occurs in the ECP chambers, any number of metrology devices may be implemented to measure wafer property information (e.g., during or after processing in a chamber). Examples of wafer property information that may be collected include thickness profile information, edge exclusion data, copper film thickness, sheet resistance profile, reflectance, resistivity drop, reflectivity, etc.

[0029] As another example, chambers 220 in FIG. 2 may correspond to the platens in a CMP tool. In this example, a first platen (i.e., Chamber 1) may represent, for example, a bulk polish platen. The bulk polish platen may be utilized to remove relatively large amounts of plating material. In conjunction with bulk polishing, a metrology device may be implemented to measure wafer property information such as, for example, plating thickness, etc. Continuing with this example, the second platen (i.e., Chamber 2) may represent a copper clearing or endpoint platen. This platen performs a slower polishing step, and may be utilized to terminate the polishing process at an endpoint. In conjunction with this polishing process, a metrology device may be implemented to measure wafer property information, such as, for example, a copper clearing profile, reflectance, thickness uniformity, etc. The third platen (i.e., Chamber 3) may represent a barrier polish platen. Like the preceding platens, a metrology device may be implemented to measure wafer property information, such as, for example, electrical properties, sheet resistance, line resistance, leakage, capacitance, yield, deflectivity, etc. A commercial embodiment of a CMP apparatus could be, for example, any of a number of processing stations or devices offered by Applied Materials, Inc. of Santa Clara, Calif. including, for example, the Mirra Mesa™ CMP device.

[0030] The above described fabs, modules, tools, and chambers constitute examples of the different functional units within a typical wafer manufacturing facility.

[0031] Referring to FIGS. 1 and 2, and as will be discussed in greater detail below, in one or more embodiments of the present invention, any number of controllers may be implemented within the fab for overseeing operation of the various functional units. For example, controller 110 (FIG. 1) may be implemented at the fab level for controlling high-level operations of the entire fab. In a similar manner, lower level controllers, such as module level controller 112 (FIG. 1) and tool level controller 114 (FIG. 2) may be implemented at the module and tool levels for controlling processing by those functional units. In addition, controllers may also be implemented to control multiple functional units and functional units at distinct levels. One example of a tool controller includes iAPC offered by Applied Materials, Inc. of Santa Clara, Calif.

[0032] In addition to the controllers, any number of sensors or metrology devices may be implemented within the fab to operate in conjunction with the controllers for, e.g., quality control purposes. These metrology tools may be implemented as integrated or insitu sensors 240 within the functional units themselves or as inline sensors 230 outside of the functional units. As will be discussed in greater detail below, these sensors are implemented to collect wafer or metrology data, including, for example, any number of wafer properties, during or after processing by the functional units. In accordance with one or more embodiments of the present invention, this data may then be transmitted back to the instant processing functional unit, or other upstream or downstream functional units, and utilized to optimize processing procedures. Examples of such metrology tools include the RS-75™ offered by KLA-Tencor of San Jose, Calif. Examples of wafer properties that may be collected and transmitted include thickness, clearing time, reflectivity, etc.

[0033] As mentioned above, the controllers are responsible for directing the operation of the functional units (e.g., the fab, modules, or tools). The controllers may be stand-alone computing units or integrated within one or more of the functional units. As will be described below, based on a desired or target product (as defined by any number of target parameters) a controller may direct any number of functional units to perform the tasks or operations required to obtain those desired targets.

[0034] Generally speaking, each controller utilizes any number of models to attain these targets by determining the operations necessary to produce an output or product that has properties which fall within an acceptable range of the targets. Thus, the models determine and/or optimize the processes or operations required to produce an output that is within an acceptable range of the target. As will be discussed below, these operations are included with a recipe of the functional unit. As known to those of ordinary skill in the art, the models are typically created through physical understanding, experimentation, and/or previous observation. Models may exist at any of the fab, module or tool levels. For example, the model for a functional unit may be implemented in an associated controller. Thus, a fab-wide model may be implemented in fab controller 110. Each model is responsible for determining the specifics of the processes believed to be necessary to achieve the desired target parameter.

[0035] In accordance with one or more embodiments of the present invention, these models receive as inputs, for example, incoming wafer properties (e.g., an incoming thickness), material characteristics (e.g., properties of a substrate), the target parameters (e.g., a desired thickness), feedback from previous runs or the runs of other functional units, and any number of other inputs or information. In this regard, information or data passed from an upstream functional unit may be termed feedforward data. Likewise, information from a previous run (in the same functional unit) or in a downstream functional unit may be termed feedback data. Using this information, the models subsequently determine or identify the processes or operations believed to be necessary to achieve the desired targets.

[0036] In accordance with one or more embodiments of the present invention, recipes are generated by these models for obtaining the wafer properties required to achieve or obtain the desired final product. These recipes constitute a set of predefined process parameters believed to be required to effectuate a functional unit processing outcome. For example, a typical tool recipe may dictate one or more setpoints for any number of processes required to effect a desired tool output. Thus, a recipe may identify the required temperature, pressure, power, processing time, lift position, and flow rate of a material needed to produce a particular target wafer result. Examples of these results include film thickness, uniformity profiles, via depth, trench depth, sheet resistance, uniformity of the copper patterns, etc. An example of a technique utilizable for generating recipes is described in U.S. patent application Ser. No. 09/998,372, filed on Nov. 30, 2001, assigned to Applied Materials, Inc., of Santa Clara, Calif., which is incorporated herein by reference.

[0037] Referring now to FIG. 3, a high level process utilizable for implementing at least some optimizing techniques contemplated by one or more embodiments of the present invention is depicted. As shown in FIG. 3, a number of processes 312, 314, 316 are implemented in a module or other functional unit grouping. Processes 312, 314, 316 represent the processes or series of processes that are performed on a wafer to result in a final product. For example, processes 312, 314, 316 may correspond to the chambers in an individual tool or to the tools within a submodule or module. Thus, in the case of a copper wiring module, processes 312, 314, 316 may represent ECP, CMP and barrier polishing processes, respectively. Additionally, some other examples of plating processes contemplated by one or more embodiments of the present invention include electroless plating, physical vapor deposition plating, and other similar plating processes. Similarly, other examples of polishing processes contemplated by one or more embodiments of the present invention include electropolishing techniques and other similar processes.

[0038] As mentioned above, wafers are passed from one process to another where any number of operations may be performed by, for example, individual tools or modules, as dictated by their recipes. Thus, in the above copper wiring module example, a wafer may initially be moved into ECP tool 312, where a plating layer may be applied to a wafer substrate. From there, the wafer may be advanced to the next tool where subsequent operations may be performed. In this example, after processing has been completed at ECP tool 312, the wafer is advanced to CMP tool 314, where wafer polishing takes place. After polishing, the wafer may be transferred to subsequent downstream tools 316, where additional processing may occur.

[0039] In accordance with one or more embodiments of the present invention, at each processing step (i.e., at each of processes 312, 314, 316), any number of wafer properties may be collected by metrology tools 230, 240 (see, FIG. 1 or FIG. 2). These properties may be collected in real-time during processing by, for example, insitu sensors 240, or immediately after processing by, for example, inline sensors 230. In accordance with one or more embodiments of the present invention, these properties may be forwarded to downstream functional units 322, 324; upstream functional units 332, 334; or back to the instant functional units 342, 344 to optimize processing operations.

[0040] In addition to this metrology data, other information may also be transferred to the functional units. For example, incoming wafer properties, functional unit state conditions, substrate material characteristic information, and other similar information may be transferred for use in optimizing processing. More specifically, these properties may be forwarded to each of the functional unit controllers where they may be inputted into the functional unit models. As discussed above, using these inputs (e.g., the actual measured wafer properties and any additional information) the models generate or modify the recipes in a manner that leads to optimal outputs or results.

[0041] In accordance with one or more embodiments of the present invention, each functional unit may forward information or processing requests to upstream functional units that may be used to optimize their own results. In particular, a functional unit may inform or direct another functional unit to attempt to attain a particular target parameter that optimizes its own processing. Thus, a CMP tool may direct an upstream tool (e.g., an ECP tool) to produce a thickness that assists the CMP tool in attaining its final tool product. A simple example includes a large thickness at the CMP tool that requires a longer than optimal CMP polish time. In this situation, the CMP tool may optimize its processing by forwarding a request to the ECP tool for a thinner plated layer. If possible, the ECP tool model responds by modifying the ECP tool recipe to attain a thinner layer target parameter. For example, the ECP tool model identifies any processes that may be adjusted to attain these target parameters (e.g., a plating process) and makes appropriate modifications (e.g., decreasing the plating time).

[0042] After processing, the optimized wafer or product 350 (i.e., the wafer produced using the above-described optimizing techniques) may be tested 360. The results of these tests may be passed to an optimizer 380, where additional modifications to a process may be made (STEP 384).

[0043] The above techniques may be used to address unforeseeable relationships between the properties as well. In accordance with one or more embodiments of the present invention, the edge exclusion of the bevel cleaner in the ECP process (discussed below) plays a significant role in the removal rate behavior at the CMP process. As a result, edge exclusion parameters may be measured and adjusted at ECP processes to optimize or obtain better overall module results at CMP processes.

[0044] More specifically, the area of a plated layer at or near the edge of the substrate (i.e., the perimeter of the substrate) is known as the “bevel”. A number of problems occur at the bevel of the substrate. For example, because of higher current densities, the bevel tends to have a higher rate of deposition than at other areas of the substrate. Contact points present at or near the edge of the substrate may break after plating leading to irregularities at the edge. Thus, a multiple step bevel cleaning process (i.e., a bevel cleaner) is used to remove the bevel. This bevel cleaning process involves applying an etchant to the bevel region to remove metal near the substrate edge. Specifically, the metallization (i.e., the plated material) is removed from the substrate at a certain distance from the substrate edge. The etchant is then removed from the substrate through rinsing with deionized water. Lastly, the substrate is dried by spinning the substrate. The amount of material removed from the substrate constitutes the edge exclusion property of the wafer.

[0045] In accordance with one or more embodiments of the present invention, this edge exclusion property may be fed forward from an ECP tool to a CMP tool to optimize module processing. For example, larger edge exclusions on a substrate allow shorter relative polishing time at the edges during CMP processing. As a result, the edge exclusion may be controlled at an ECP process to obtain a result that leads to optimal processing at a CMP tool. In a similar manner, CMP polishing may be adjusted to account for edge exclusion. Thus, in these situations, edge exclusion data may be measured at or after an ECP process and fed forward to a downstream process (e.g., a CMP process) and used in optimization of the downstream process. Likewise, the edge exclusion parameter at an upstream ECP process may be adjusted in response to a downstream request or problem.

[0046]FIG. 4 depicts one example of a flow diagram of a process sequence for optimizing functional unit processing of one or more embodiments of the present invention. Although the example shown in FIG. 4 depicts processing in a copper wiring module, it is to be understood that the process illustrated therein may be implemented in any functional unit. For example, the process may just as easily be implemented in a PVD module, the chambers in an electroplating tool, between a number of modules, etc.

[0047] Initially, processing commences with the delivery of a substrate or wafer to an ECP tool (STEP 402). Specifically, a substrate handler, such as a robot, may be used to deliver the substrate to a first chamber of the ECP tool (e.g., an electroplating chamber). Once the substrate is positioned in the tool chamber, the ECP tool processes the wafer (STEP 404) as directed by the ECP tool recipe. In this example, the ECP tool applies a plating layer onto the substrate.

[0048] During (or after) the processing operations (e.g., STEP 404), a metrology tool may be utilized to measure any number of wafer properties of the substrate (STEP 406). For example, any of an insitu or inline sensor may be used to measure the wafer properties. With insitu sensors, the properties may be measured in real time during processing. With inline sensors, the properties may be measured immediately after processing by the tool. In the case of an ECP tool plating process, the metrology devices may collect thickness data, edge exclusion information, etc. More specifically, the thickness of a plated layer may be measured from any number of positions on the wafer. In one or more embodiments, the thickness may be measured at any number of key points, including for example, any number of inflection points on the wafer.

[0049] Upon completion of a process, the substrate may be moved or transferred to a subsequent chamber within the tool, where any number of additional processes may be performed. For example, a rinsing process may take place in a downstream chamber to remove an edge bead of the bevel. Alternatively, additional processes may be performed in a single chamber (i.e., the plating and rinsing processes may occur in the same chamber). Whatever the case, any number of metrology processes may occur at any time for the collection of additional wafer property data. For instance, as discussed above, the metrology devices may collect edge exclusion data corresponding to the substrates.

[0050] Once the metrology data has been collected, any additional processing required to transform the data into useable information may take place (STEP 408). For example, in the case of thickness data, the thickness measured at numerous positions on a wafer may be utilized to generate a thickness profile.

[0051] In accordance with one or more embodiments of the present invention, the metrology data may be forwarded to any number of functional units for optimizing processing at, for example, those functional units or at the transmitting functional unit. As one example, the metrology data may be fed backwards to an upstream functional unit (STEP 410). Similarly, the data may be fed forward to a downstream functional unit (STEP 414). In addition, the data may be fed back to the measuring functional unit for use in optimizing subsequent runs. Referring back to the above-described copper wiring module, after completion of processing at an ECP tool, the metrology data may be forwarded to a CMP tool. The metrology data may also be fed to a controller (STEP 412) for optimizing, for example, operations at a higher functional level. Likewise, the data may be fed back to the ECP tool to improve processing during subsequent ECP runs.

[0052] Once processing has been completed at a particular functional unit, the wafer or substrate may be transferred to a downstream function unit (STEP 416). In this example, the substrate may be moved or forwarded to a chamber in a CMP tool.

[0053] In accordance with one or more embodiments of the present invention, before processing takes place at the downstream functional unit, the downstream functional unit processes may be optimized utilizing, for example, the above described metrology data (STEP 418). For instance, forwarded metrology data from an upstream functional unit may be inputted into a model by a controller for adjusting the functional unit recipe to obtain optimized processing results. In addition, the information received is not limited to information from upstream functional units. As mentioned above, the controller may receive data from downstream functional units and/or information from previous runs. In this manner, information may be shared between functional units and/or processing runs to optimize processing.

[0054] As an example, the CMP controller may receive an indication from a downstream tool that the thickness of the wafer is thinner than optimal. In this case, the CMP recipe may be adjusted to decrease a polishing pressure. As another example, a CMP controller may receive a thickness profile from an upstream ECP tool. If the thickness at the center of the substrate is greater than expected, the CMP recipe may be adjusted to increase a polishing pressure at the center of the wafer. As yet another example, feedback from a previous run at the CMP tool may indicate that a wafer thickness is greater than expected after polishing. This condition may indicate, for example, that the polishing pads of the CMP tool have worn out. In this case, the CMP recipe may be adjusted to increase polishing time to account for the wear of the pads.

[0055] After optimization, the wafers are processed according to the optimized recipes (STEP 420). For example, the CMP tool polishes the wafer according to the recipe adjusted in the manner described above. Subsequently, a metrology tool may be utilized to measure any number of wafer properties of the substrate (STEP 422) during or after processing by the CMP tool. Examples include copper clearing time, reflectance, thickness, electrical properties, etc. As with the ECP tools, any of an insitu or inline sensor may be used to measure the wafer properties.

[0056] After the metrology data has been collected, the substrate may be transferred to other chambers within the CMP tool, where any number of additional processes may be performed. For example, the substrate may be transferred from a bulk polishing platen to an endpoint platen, or from an endpoint platen to a barrier polish platen. Alternatively, additional processes may be executed in the current chamber. Like with the above, any number of metrology processes may occur at this point for the collection of additional wafer property data for optimizing other or subsequent processes.

[0057] In accordance with one or more embodiments of the present invention, the metrology data from the CMP tool may be forwarded to any number of functional units for optimizing downstream, upstream or subsequent operation processing. In particular, the metrology data may be fed backwards to an upstream functional unit including, for example, the ECP tool (STEP 424). Similarly, the data may be fed forward to a downstream functional unit (STEP 428), such as, for example, a barrier polishing tool. Additionally, the metrology data may be fed to a controller (STEP 426) for optimizing, for example, operations at a higher functional level. Also, the data may be fed back to the measuring functional unit to improve processing during subsequent runs.

[0058] Once processing has been completed at the CMP tool, the wafer or substrate may be transferred to a downstream functional unit (STEP 430). In this example, the substrate may be moved or forwarded to a chamber in a barrier polishing tool.

[0059] Referring to FIGS. 4 and 2, a polishing procedure occurring at the CMP tool illustrates in greater detail one or more embodiments of the present invention. In this example, an output property of the CMP tool is optimized by controlling a number of CMP and/or ECP process steps, according to wafer property metrology data collected by the CMP and/or ECP tools. Examples of the output property that may be optimized include a sheet resistance distribution uniformity and interconnect line resistance, etc.

[0060] After processing at the ECP tool has been completed, the wafer or substrate may be delivered to a bulk polishing platen (see, e.g., STEP 416 in FIG. 4 and Chamber 1 in FIG. 2) of a CMP tool. At the bulk polishing platen, relatively large amounts of plated material (e.g., copper metallization applied at the ECP tool in STEP 404) may be removed. During or immediately after polishing, a metrology device may be used to measure metrology data or wafer property information. In this example, an inline sensor may be used to gather thickness data. From there, the wafer may be transferred to a copper clearing platen (see, e.g., Chamber 2 in FIG. 2) where additional plated material may be removed. Like with the first platen, a variety of metrology data may be collected at the second platen. In this example the data may include thickness uniformity as determined by a reflectance value measured in any number of zones on the wafer. Finally, the wafer may be transferred to a third platen (e.g., the barrier polish platen [i.e., Chamber 3 in FIG. 2]), where additional processing and metrology collection may take place. Examples of wafer property information that may be collected at the third platen include electrical parameters such as line resistance, leakage, etc.

[0061] In accordance with one or more embodiments of the present invention, the metrology data measured at any combination of the three platens may be transmitted to, for example, a module controller (e.g., controller 114 in FIG. 2). Subsequently, the controller modifies or optimizes the recipes used to control processing of the individual platens. As an example, the controller may modify any of the target parameters of the bulk polish platen, including, for example, pressure, speed, etc., according to the forwarded metrology data.

[0062] In addition, data from prior processes may also be utilized in the optimization. For instance, information from, for example, downstream etch or dielectric deposition functional units may be utilized to optimize CMP polishing processes. Specific examples of information that may be forwarded includes dielectric deposition thickness and uniformity, critical dimensions such as line depth and width after an etch process, trench depth value, uniformity after an etch process, etc.

[0063] Referring now to FIG. 5, one example of a process utilizable for controlling the forwarding of feedback and/or feedforward information is depicted. Although the example shown in FIG. 5 depicts processing in the ECP tool of a copper wiring module, it is to be understood that at least one or more embodiments of the process illustrated therein may be implemented in any functional unit.

[0064] To start, the ECP tool processes a wafer according to a tool recipe as described above (STEP 504). For example, a layer may be applied onto the substrate. During (or immediately after) processing, any number of metrology tools may be utilized to collect metrology data (i.e., wafer properties) from the wafer. For instance, the thickness of the plated layer may be measured at a number of key points (STEP 508). After measuring the metrology data, any necessary data transformations or processing may occur (STEP 512). For example, a thickness profile may be generated using the thickness measured at each of the above mentioned key points. In addition to thickness, other metrology data may also be measured. In particular, edge exclusion data may also be measured at this time (STEP 516).

[0065] For each set of measured or generated metrology data, a determination may be made to determine whether the metrology data should be forwarded to other functional units or to the measuring functional unit. A number of methods exist for determining whether data should be forwarded. In some cases, the data may be forwarded only if the measured property is not within a range of acceptable limits (STEP 520). Using thickness as an example, after comparing the measured properties against expected results, the metrology data may be automatically forwarded (to predetermined functional units) if the difference in thickness is greater than an acceptable level (STEP 532). These conditions indicate, for example, that a deficiency exists, which must be addressed. On the other hand, if the thickness is within an acceptable range, no information is forwarded (STEP 524). These conditions indicate, for example, that no modifications are necessary.

[0066] Another alternative (and possibly parallel) method that may be used to determine whether metrology data should be forwarded focuses on the capabilities of the receiving functional unit (STEP 528). In these cases, the metrology data is forwarded only if the other functional unit (i.e., the recipient of the metrology data) is capable of adequately addressing the deficiency (STEP 532). On the other hand, the metrology data is not forwarded if the other functional unit (i.e., the recipient of the metrology data) is not capable of adequately addressing the deficiency (STEP 524). Thus, in this methodology, metrology data is only forwarded if it is possible to remedy the deficiency.

[0067] Referring now to FIG. 6, one example of a flow diagram of a process sequence for receiving and utilizing feedforward and feedback information to modify and/or generate functional unit recipes is depicted. Initially, any input information to be utilized in modifying the recipes is received (STEP 604). As an example, and as discussed above, metrology information may be forwarded to a functional unit if that unit is capable of adequately addressing a deficiency or if measured data falls outside an acceptable target range (see, e.g., FIG. 5). The information may include feedforward information from an upstream functional unit (STEP 604). Similarly, the information may include feedback information from a downstream functional unit or from a previous run at the instant functional unit (STEP 608).

[0068] In accordance with one or more embodiments of the present invention, the input information may include any data that impacts processing of the instant functional unit. In these situations, the data may be used in modifying processes of the instant unit to ultimately optimize processing of that unit. Similarly, the input information may include any data that impacts processing of, for example, another functional unit (e.g., a downstream or upstream functional unit). In these situations, the data may be used in modifying processes of the instant unit to ultimately optimize processing of the other unit.

[0069] As an example, the information may include thickness information from a plating process that may result in the alteration of bulk and fine polishing times at a downstream polishing process. For instance, a thicker than expected thickness profile may result in a longer bulk polishing step at the polishing unit. As another example, the information may include a request from the polishing process to apply less plating material. In this case, exceedingly long bulk polish times may result in a request to the plating process for a reduction in plating time.

[0070] In accordance with one or more embodiments of the present invention, the input information is utilized to modify a functional unit recipe to optimize processing. Thus, the functional unit recipe is examined (STEP 612) and modified (STEP 620) in view of, for example, design of experiments (DOE) information and other similar data (STEP 616). Generally speaking, experiments derived from DOE based techniques may be used to modify or construct the functional unit recipes. DOE based techniques refer to a methodology where a set of experiments are determined to optimally provide information for developing a model or specific correlation structure. Thus, the models may be generated based on, for example, experimentation, previous observation, or knowledge of the desired results. The models then may be use to generate or alter the recipes. Based on the input information and the desired resulting outputs, and the relationships therebetween (as defined by the models relating the inputs to the outputs), the operations and processes required to obtain the final products may be determined.

[0071] In accordance with one or more embodiments of the present invention, this modification step results in a new recipe (STEP 624), which ideally optimizes the process of a functional unit. The recipe may then be forwarded or implemented at the corresponding functional unit (STEP 628), where it may be utilized to produce optimized outputs.

[0072] Referring to FIG. 7, a combined hardware and control process diagram of a copper wiring module 704 illustrating one or more embodiments of the present invention is depicted. As mentioned above, module 704 may include any number of tools including, for example, an ECP tool 720, a CMP tool 730, and any other similar tools (e.g., barrier polishing tool 740). In a typical process, wafers are advanced into module 704 from upstream tools of upstream modules and, after processing by module 704, are forwarded to downstream tools of downstream modules. In the example of FIG. 7, wafers are initially processed by ECP tool 720, where a plating process takes place for applying a layer of copper onto the wafer substrate. From there, the wafer may be moved downstream to CMP tool 730, where the wafers are polished to remove any excess plating material. Afterwards, the wafers may be moved to the next tool in the module 740, which may include, for example, a barrier polishing or other similar tool. The end result or final product of the module includes the remaining copper material, which forms the desired copper geometric circuit pattern.

[0073] In accordance with one or more embodiments of the present invention, module 704 additionally includes a module level controller 710. As mentioned above, controller 710 controls operation of module 704. For example, controller 710 may be responsible for generating and/or optimizing the recipes of the individual tools of module 704. Specifically, implemented in controller 710 is an optimizer process 714 which may be embodied as, for example, a computer program stored in controller memory (not shown). In operation, optimizer 714 utilizes a number of inputs, such as, for example, metrology data to optimize processing of the tools of module 704. Similarly, optimizer 714 may receive input information from upstream and downstream modules and forward information to those modules as well. In addition to metrology information from the tools within the module, optimizer 714 may also receive information regarding the characteristics of the wafer as well. For example, optimizer 714 may receive characteristics of the dielectric stack formed on the substrate for use in optimizing processes at the individual tools 716.

[0074] Although optimizer 714 is depicted as being implemented in a module level controller (e.g., controller 710), it may just as easily be implemented in controllers located at other functional levels. For instance, embodiments of the present invention contemplate that an optimizer process for optimizing operations of a module may be implemented in controllers located at the fab level, the tool level, or other levels as well.

[0075] Referring back to FIG. 7, after (or during) processing at ECP tool 720, a number of metrology tools may be used to collect metrology data. This data may then be forwarded to optimizer 714. As discussed, examples of the data that may be forwarded include thickness data (724) and edge exclusion information (722). This information (after any necessary transformations [see, e.g., STEP 408 in FIG. 4]) may be processed by optimizer 714 to generate, for example, an optimized recipe for CMP tool 730. Subsequently, the optimized recipe is downloaded to CMP tool 730 for use in controlling CMP processing runs. For example, an extremely thick profile from ECP tool 720 may cause optimizer 714 to direct CMP tool 730 (via a CMP tool recipe) to spend more time on a bulk polishing step to remove greater amounts of material.

[0076] As with ECP tool 720, after (or during) processing at CMP tool 730, a number of metrology tools may be used to collect metrology data. This data may similarly be forwarded to optimizer 714. One example of data that may be forwarded includes copper clearing time information (732). This information may be processed by optimizer 714 to generate, for example, an optimized recipe for ECP tool 720 and/or any other tools (e.g., tool 740). Subsequently, the optimized recipe is downloaded to ECP tool 720 and tool 740 for use in controlling their processing runs (726 and 742).

[0077] In addition to feedback and feedforward information within module 704, information may also be transmitted from outside the module (e.g., from other modules). For example, optimizer 714 may receive from or transmit to upstream modules (752) and downstream modules (756) for optimizing module level processing. Similar techniques may also be implemented within an individual tool for optimizing processing at the chamber and other levels as well.

[0078]FIG. 8 illustrates a block diagram of one example of the internal hardware of any of the controllers utilized to implement the models discussed above, examples of which include any of a number of different types of computers such as those having Pentium™ based processors as manufactured by Intel Corporation of Santa Clara, Calif. A bus 856 serves as the main information link interconnecting the other components of the system. CPU 858 is the central processing unit of the system, performing calculations and logic operations required to execute the processes of the instant invention as well as other programs. Read only memory (ROM) 860 and random access memory (RAM) 862 constitute the main memory of the system. Disk controller 864 interfaces one or more disk drives to the system bus 856. These disk drives are, for example, floppy disk drives 870, or CD ROM or DVD (digital video disks) drives 866, or internal or external hard drives 868. CPU 858 can be any number of different types of processors, including those manufactured by Intel Corporation or Motorola of Schaumberg, Illinois. The memory/storage devices can be any number of different types of memory devices such as DRAM and SRAM as well as various types of storage devices, including magnetic and optical media. Furthermore, the memory/storage devices can also take the form of a transmission.

[0079] A display interface 872 interfaces display 848 and permits information from the bus 856 to be displayed on display 848. Display 848 is also an optional accessory. Communications with external devices such as the other components of the system described above, occur utilizing, for example, communication port 874. For example, port 874 may be interfaced with a bus/network linked to a CMP tool. Optical fibers and/or electrical cables and/or conductors and/or optical communication (e.g., infrared, and the like) and/or wireless communication (e.g., radio frequency (RF), and the like) can be used as the transport medium between the external devices and communication port 874. Peripheral interface 854 interfaces the keyboard 850 and mouse 852, permitting input data to be transmitted to bus 856. In addition to these components, the control system also optionally includes an infrared transmitter 878 and/or infrared receiver 876. Infrared transmitters are optionally utilized when the computer system is used in conjunction with one or more of the processing components/stations that transmits/receives data via infrared signal transmission. Instead of utilizing an infrared transmitter or infrared receiver, the control system may also optionally use a low power radio transmitter 880 and/or a low power radio receiver 882. The low power radio transmitter transmits the signal for reception by components of the production process, and receives signals from the components via the low power radio receiver.

[0080]FIG. 9 is an illustration of an exemplary computer readable memory medium 984 utilizable for storing computer readable code or instructions including the model(s), recipe(s), etc). As one example, medium 984 may be used with disk drives illustrated in FIG. 8. Typically, memory media such as floppy disks, or a CD ROM, or a digital video disk will contain, for example, a multi-byte locale for a single byte language and the program information for controlling the above system to enable the computer to perform the functions described herein. Alternatively, ROM 860 and/or RAM 862 can also be used to store the program information that is used to instruct the central processing unit 858 to perform the operations associated with the instant processes. Other examples of suitable computer readable media for storing information include magnetic, electronic, or optical (including holographic) storage, some combination thereof, etc. In addition, one or more embodiments of the present invention contemplate that the computer readable medium can be a transmission.

[0081] Embodiments of the present invention contemplate that various portions of software for implementing the various aspects of the present invention as previously described can reside in the memory/storage devices.

[0082] In general, it should be emphasized that the various components of embodiments of the present invention can be implemented in hardware, software, or a combination thereof. In such embodiments, the various components and steps would be implemented in hardware and/or software to perform the functions of the present invention. Any presently available or future developed computer software language and/or hardware components can be employed in such embodiments of the present invention. For example, at least some of the functionality mentioned above could be implemented using C or C++ programming languages.

[0083] Further, it is to be understood that terms, such as “first” or “second,” used in describing components, such as, for example, functional units and other components of the present invention herein (and in the claims), do not denote any form of order. Rather, such terms are used merely for convenience to differentiate between multiple and distinct components.

[0084] It is also to be appreciated and understood that the specific embodiments of the invention described hereinbefore are merely illustrative of the general principles of the invention. Various modifications may be made by those skilled in the art consistent with the principles set forth hereinbefore.

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Classifications
U.S. Classification438/17, 257/E21.525, 438/687, 438/13, 257/E21.175, 438/692, 156/345.12, 438/10
International ClassificationB24B49/00, B24B37/04, C23F3/00, H01L21/00, H01L21/66, H01L21/288
Cooperative ClassificationB24B49/00, H01L22/20, H01L21/67276, B24B37/042, C23F3/00, H01L21/67253, H01L21/2885
European ClassificationH01L21/67S8B, H01L21/67S8E, B24B37/04B, B24B49/00, H01L21/288E, C23F3/00
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Jun 13, 2003ASAssignment
Owner name: APPLIED MATERIALS, INC., CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:SHANMUGASUNDRAM, ARULKUMAR;PARIKH, SUKETU A;REEL/FRAME:013776/0153;SIGNING DATES FROM 20030522 TO 20030527