FIELD OF THE INVENTION
This invention relates to a method of fabricating strained Si based layers of microelectronics quality. Furthermore it relates to the transfer of such strained layers to different substrates and also onto insulating materials. The invention additionally relates to devices made in these strained Si based layers and to electronic systems built with such devices.
BACKGROUND OF THE INVENTION
Today's integrated circuits include a vast number of transistor devices formed in a semiconductor. Smaller devices are the key to enhance performance and to increase reliability. As devices are scaled down, however, the technology becomes more complex and new methods are needed to maintain the expected performance enhancement from one generation of devices to the next. This relates mainly toward the primary semiconducting material of microelectronics, namely Si, or more broadly, to Si based materials. Such materials of promise are various SiGe mixtures, and further combinations, for instance with C. One of the most important indicators of device performance is the carrier mobility. There is great difficulty in keeping carrier mobility high in devices of the deeply submicron generations. A promising avenue toward better carrier mobility is to modify slightly the semiconductor that serves as raw material for device fabrication. It has been known, and recently further studied, that tensilely strained Si has intriguing carrier properties. A Si layer embedded in a Si/SiGe heterostructure grown by UHV-CVD has demonstrated enhanced transport properties, namely carrier mobilities, over bulk Si. In particular, a 90-95% improvement in the electron mobility has been achieved in a strain Si channel n-MOS (Metal Oxide Semiconductor transistor, a name with historic connotations for Si Field-Effect-Transistors (FET)) in comparison to a bulk Si n-MOS mobility. Similarly, a 30-35% improvements in the hole carrier mobility has been obtained for a strained Si channel p-MOS, in comparison to bulk silicon p-MOS. The great difficulty lies in the production of a layer of tensilely strained Si, or SiGe, that are of high enough crystalline quality, namely free of dislocations and other defects, to satisfy the exceedingly elevated demands of microelectronics.
However, if one achieves a material of sufficiently good quality and high carrier mobility, the underlying substrate may be a source of problems in as much as it can be a source of defects that eventually find their way into the good quality material on the surface. An additional potential area of concern may be the interaction of a semiconducting substrate with active devices on the surface. The underlying semiconducting substrate may introduce features which could limit harvesting the full advantage that a superior tensilely strained device layer would bestow. Often today's state of the art devices operate in a semiconducting layer which is separated from the semiconducting substrate by an insulating layer. This technology is commonly knows as SOI technology. (SOI stands for Si-on-insulator.) The standard method of producing SOI materials is called the SIMOX process. It involves the implantation of very high doses of oxygen ions at high energy into the semiconductor, and upon annealing, the oxygen forms an oxide layer under the surface of the semiconductor. In this manner one has a top semiconductor layer separated from the bulk of the substrate. However, the SIMOX process has many of its own problems that makes it unsuitable for the production of high mobility strained layers.
SUMMARY OF THE INVENTION
It is the object of this invention to show a method for producing a high crystalline quality Si based tensilely strained semiconductor layer on a substrate, typically a Si wafer. It is also disclosed how this Si based tensilely strained semiconductor layer can be transferred to another substrate, again most typically to another Si wafer, which is of higher crystalline quality than the substrate on which the strained Si based layer was produced. It is yet a further object of this invention to show how to transfer this Si based tensilely strained semiconductor layer on top of an insulating layer, making the Si based tensilely strained semiconductor suitable for building super-high performance devices.
There are numerous patents and publication relating to this subject. They cover some aspects of strained layer semiconductors, and some aspects of layer transfers and also elements of creating strained layers over insulators. But none teaches the full scope of this invention.
For example, U.S. Pat. No. 5,461,243 to B. A. Ek et al, titled “Substrate for Tensilely Strained Semiconductor” teaches the straining of one layer with another one grown on top of it, and sliding the bottom very thin Si layer on an SiO2 layer. But this patent does not teach the present invention.
In U.S. Pat. No. 5,906,951 to J. Chu and K. Ismail, titled “Strained Si/SiGe layers on Insulator” incorporated herein by reference, there are a variety layers deposited to yield two strained channels. However this patent again does not teach the present invention.
US patent application “Preparation of Strained Si/SiGe on Insulator by Hydrogen Induced Layer Transfer Technique” by D. Canaperi et al, filed Sep. 29, 2000, Ser. No. 09/675,840, (IBM Docket no.: YOR920000345US1) incorporated herein by reference, teaches strain layer deposition and Hydrogen induced layer transfer (SmartCut), but it does not teach the present invention.
Formation of graded SiGe layers can proceed as described in U.S. Pat. No. 5,659,187 to LeGoues et al. titled: “Low Defect Density/arbitrary Lattice Constant Heteroepitaxial Layers” incorporated herein by reference.
The following patent and applications bear reference to both semiconductor strain layer formation and layer transfer. US patent application “A Method of Wafer Smoothing for Bonding Using Chemo-Mechanical Polishing (CMP)” by D. F. Canaperi et al., Ser. No. 09/675,841 filed Sep. 29, 2000, (IBM Docket No.YOR920000683US1) incorporated herein by reference, describes surface polishing to reduce surface roughness in preparation to wafer bonding. US patent application “Layer Transfer of Low Defect SiGe Using an Etch-back Process” by J. 0. Chu, et al, Ser. No. 09/692,606 filed Oct. 19, 2000, (IBM Docket No.YOR920000344US1) incorporated herein by reference, describes methods to create relaxed SiGe layers and to use an etch-back process for layer transfer. U.S. Pat. No. 5,963,817 to J. Chu et al, titled “Bulk and Strained Silicon on Insulator Using Local Selective Oxidation” incorporated herein by reference, teaches using local selective oxidation in a layer transfer process.
In all the embodiments of the invention the deposited layers change properties, such as Ge concentration, defect density, dopant concentration, strain state, in the direction of growth, or deposition. In the direction parallel with the surfaces the layers are all uniform. Accordingly, when there is reference that some quantity, for instance Ge concentration, has a variation, this is always meant mean a variation in the thickness direction. The term full thickness refers to the surface, or interface, of a layer where the layer has become fully deposited, or grown.
A typical embodiment of the present invention starts with a standard Si wafer or substrate. In some cases this substrate can have preparatory steps already performed on it for facilitating a layer transfer process to be performed after the layer deposition steps. Such a preparatory step can be, for instance, the creation of a porous layer in connection with the so called ELTRAN (Epitaxial Layer TRANsfer, a registered trademark of Canon K.K.) process. The ELTRAN process is described in U.S. Pat. No. 5,371,037 to T. Yonehara, titled: “Semiconductor Member and Process for Preparing Semiconductor Member”, incorporated here by reference. A step-graded SiGe layer is deposited. The step-grading of Ge concentration substantially proceeds as in U.S. Pat. No. 5,659,187 to LeGoues et al. titled: “Low Defect Density/arbitrary Lattice Constant Heteroepitaxial Layers” incorporated previously by reference. The aim is to gradually change the lattice constant without having dislocations penetrating the top surface. Next, a relaxed SiGe buffer is deposited, which in this invention imbeds a unique Ge overshoot layer. The relaxed buffer is common in the process of creating epitaxial films, where due to lattice parameter mismatches there is considerable strain in the deposited films. This buffer, in which the Ge concentration is constant, is of sufficient thickness to diminish the likelihood that dislocations and other lattice defects penetrate from the step-grading layers to the layer of interest on the surface. The Ge concentration in the relaxed buffer is the same as the Ge concentration in the last step of the step-graded region.
It is an essential aspect of this invention that the relaxed buffer imbeds a Ge overshoot layer, or zone. This zone is characterized by an abrupt increase of the Ge concentration to a level above that of the Ge concentration in the relaxed buffer. The thickness of the Ge overshoot layer is only a fraction of the relaxed buffer thickness. The Ge overshoot layer is placed typically in the upper half of the relaxed buffer, namely nearer to that end of the relaxed buffer which touches the final strained Si based layer. This overshoot layer assures complete relaxation in the SiGe buffer. It also acts as a sink for lattice defects. A further role for the Ge overshoot layer can be found in some of the layer transfer schemes, where the overshoot layer serves selectivity purposes, in either etching, or as a layer for selective oxidation.
The relaxed buffer layer is followed by the final layer of Si, or SiGe (low Ge content) layer in which the high performance devices can then be built. This layer is virtually defect free due to the effect of the relaxed buffer which imbeds the Ge overshoot layer. The final Si base layer upon epitaxial deposition becomes tensilely strained as the result of the lattice mismatch between the high Ge concentration relaxed buffer surface and the pure Si, or low Ge concentration, high performance device layer.
Another differing embodiment of the invention is where the step-graded SiGe layer followed by the flat Ge concentration buffer layer is replaced by a linearly graded SiGe layer. The Ge concentration of this layer goes from zero at the interface with the substrate and to certain value at the full thickness of the layer. The aim is to gradually change the lattice constant without having dislocations penetrating the top surface. Again, as in the step-graded embodiment, it is an essential aspect of this invention that the linearly graded layer imbeds a Ge overshoot layer, or zone. This zone is characterized by an abrupt increase of the Ge concentration to a level above that of the highest Ge concentration in the linearly graded layer. The thickness of the Ge overshoot layer is only a fraction of the linearly graded layer thickness. The Ge overshoot layer is placed typically in the upper half of the linearly graded layer, namely nearer to that end of the linearly graded layer which touches the final strained Si based layer. This overshoot layer assures complete relaxation in the SiGe linearly graded layer. It acts as a sink for lattice defects, as well. A further role for the Ge overshoot layer can be found in some of the layer transfer schemes, where the overshoot layer serves selectivity purposes, in either etching, or as a layer for selective oxidation.
The linearly graded layer is followed by the final layer of Si, or SiGe (low Ge content) layer in which the high performance devices can then be built. This layer is virtually defect free due to the effect of the linearly graded layer which imbeds the Ge overshoot layer. The final Si based layer upon epitaxial deposition becomes tensilely strained as the result of the lattice mismatch between the high Ge concentration at the full thickness of the linearly graded layer surface and the pure Si, or low Ge concentration high performance device layer.
The two embodiments of the layer structures supporting the Si based strain layer in the following will be referred to as support structure. Accordingly the term support structure can mean either the step graded scheme with the relaxed buffer embodiment, or the linearly graded embodiment.
All the steps in creating the strained Si based layer in preferred embodiments are done by a UHV-CVD processes, and preferably in an AICVD system as described in U.S. Pat. No. 6,013,134 to J. Chu et al, titled: “Advance Integrated Chemical Vapor Deposition (AICVD) for Semiconductor Devices”, incorporated herein by reference. The AICVD system is also capable to go beyond, in situ, of the Si based strained layer process and fabricate structures in the strained Si based layer. The UHV-CVD method, and in particular the AICVD system is well suited to handle the large diameter, 8 in or 10 in, Si wafers of today technologies, or the diameters that may becoming standards in the future. UHV-CVD poses no inherent limit onto the diameter of the wafers and layers to be processed. Those skilled in the art, however, will recognize that other UHV-CVD method may also be used to fabricate the desired strained Si based layer. Such methods may be LP (low pressure)-CVD, or RT (rapid thermal)-CVD.
The tensilely strained Si based layer enhances the transport for both holes and electrons in a silicon layer structure suitable for conventional CMOS, or bipolar device processing. In long channel MOS devices made in the strained Si layer grown on a relaxed 25% SiGe heterostructure has yielded electron mobilities of about 1000 cm2/Vs and high field hole mobilities of well over 200 cm2/Vs which represents an increase of about 95% and 35% respectively over electron and hole mobilities in bulk Si MOS.
In some embodiments all the layers contain a low percentage of C. Carbon serves as a retardant of dopant diffusion. In yet another embodiment the C is introduced only into the top tensilely strained Si based layer. In such an embodiment the top tensilely strained layer is: Si1-b-cGebCc, where “b” and “c” represent Ge and C concentrations given as fractions.
In some embodiments of the invention the Si based tensilely strained semiconductor layer is transferred to a second substrate, most typically to another Si wafer. This second substrate can be of higher crystalline quality than the support structures on which the strained Si based layer was produced. Furthermore, the second substrate is advantageous from a heat conduction point of view because of its intimate contact with the strained Si based layer. In yet another embodiment the Si based tensilely strained layer is transferred onto an insulating layer, making the Si based tensilely strained semiconductor suitable for building super-high performance devices.
Once the proper layer stack is ready, with the high quality tensilely strained layer on the top, one can transfer this layer onto a semiconductor substrate, or to an insulator. This insulator typically is an insulating film, such as silicon dioxide, on top of a Si wafer. There a several ways known in the art that the transfer to either a semiconductor substrate, or to an insulator can be carried out. One is so called SmartCut (a registered trademark of SOITEC Corporation) technique, as described, for instance, in the referenced U.S. patent application Ser. No. 09/675,840. In another embodiment the layer transfer can be accomplished with the so called ELTRAN (Epitaxial Layer TRANsfer, a registered trademark of Canon K.K.) process, as described in U.S. Pat. No. 5,371,037 to T. Yonehara, titled: “Semiconductor Member and Process for Preparing Semiconductor Member”, incorporated here by reference. In another embodiment the layer transfer is accomplished by the CMP polishing, and etch-back process, as described, for instance, in the referenced U.S. patent application Ser. No. 09/692,606. A potential difference in using the layer transfer process in this invention compared to application Ser. No. 09/692,606 is that now the Ge overshoot layer can act as an etch stop by itself, but the discussed heavy B dopant layer in Ser. No. 09/692,606 can be introduced in an embodiment of this invention as well.
FIG. 1B shows fabrication of a same type of strained Si based layer as in FIG. 1A, but embodying a linearly graded scheme. In this embodiment the step-graded layer and relaxed buffer are replaced by a linearly graded concentration Ge layer. Again, one starts with a semiconductor substrate 160, which is typically a regular Si wafer. In some embodiments this substrate can have preparatory steps already performed, for instance having a porous layer of silicon on its surface, or just subsurface, for facilitating a layer transfer process to be performed after the layer deposition steps. In an ultra high vacuum chemical vapor deposition (UHV-CVD) apparatus upon proper cleaning of the substrate surface a linearly graded concentration Ge layer 110 is grown. The Ge concentration equals approximately zero at the bottom of the layer, at the interface with the substrate, and reaches Ge concentrations similar to that of the relaxed buffer of FIG. 1A, in the range of 20-30%. The total thickness of layers 110 is in the 1 to 3 μm range. In this invention the linearly graded Ge concentration layer imbeds a Ge overshoot layer, or zone, 130. In the overshoot zone the Ge concentration abruptly increases 5 to 10% over the maximum value of Ge concentration where the linearly graded layer reaches the interface with layer 100. The thickness of the overshoot zone is in the 10 nm to 50 nm range. The overshoot layer is placed near the full thickness of the linearly graded region, typically less than 500 nm from the interface with layer 100. The advantages of having the overshoot layer are many. The overshoot layer helps the complete relaxation in the required SiGe buffer. It acts as a sink for lattice defects, so fewer reaches to top sensitive strained layer. The overshoot layer helps through selectivity in the layer transfer step. The overshoot layer 130, can be either a selective etch stop, or etch enhancement layer, or a layer where oxidation, especially HIPOX oxidation proceeds rapidly. In the same manner as in FIG. 1A, with the step grading scheme, the last epitaxially deposited layer is the strained Si based layer. The thickness of layer 100 is typically between 5 nm and 30 nm, preferably in the 10 nm to 15 nm range. The strained Si based layer 100 in some embodiments is simply pure Si. In other preferred embodiment it is a SiGe layer with Ge concentration typically below 10%. The strained Si based layer 100 may incorporate a low, less than 5%, concentration of C. Carbon may be incorporated in all deposited layers 110, 130, and 100.