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Publication numberUS20030205817 A1
Publication typeApplication
Application numberUS 10/446,460
Publication dateNov 6, 2003
Filing dateMay 28, 2003
Priority dateJul 31, 1999
Also published asUS6596624
Publication number10446460, 446460, US 2003/0205817 A1, US 2003/205817 A1, US 20030205817 A1, US 20030205817A1, US 2003205817 A1, US 2003205817A1, US-A1-20030205817, US-A1-2003205817, US2003/0205817A1, US2003/205817A1, US20030205817 A1, US20030205817A1, US2003205817 A1, US2003205817A1
InventorsLubomyr Romankiw
Original AssigneeRomankiw Lubomyr Taras
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Process for making low dielectric constant hollow chip structures by removing sacrificial dielectric material after the chip is joined to a carrier
US 20030205817 A1
Abstract
Disclosed is a multilayer integrated circuit structure joined to a chip carrier, and a process of making, in which the area normally occupied by a solid dielectric material in the IC is at least partially hollow. The hollow area can be filled with a gas, such as air, or placed under vacuum, minimizing the dielectric constant. Several embodiments and processing variants are disclosed. In one embodiment of the invention, the wiring layers, which are embedded in a temporary dielectric, alternate with via layers, also embedded in a temporary dielectric, in which the vias, besides establishing electrical communication between the wiring layers, also provide mechanical support for after the temporary dielectric is removed. Additional support is optionally provided by support structures though the interior levels and at the periphery of the chip. The temporary dielectric is removed subsequent to joining by dissolution or by ashing in an oxygen-containing plasma.
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Claims(26)
What is claimed is:
1. An integrated circuit chip structure comprising within a plurality of via levels and a plurality of conductive wiring levels which is joined to a chip carrier and within which at least the plurality of conductive wiring levels are imbedded in a gaseous dielectric medium.
2. The structure recited in claim 1 including also a plurality of support studs strategically placed between levels within the structure and its periphery.
3. An integrated circuit chip structure which is joined to a chip carrier, the chip structure comprising: a plurality of via levels and a plurality of conductive wiring levels which are imbedded in a dielectric gas and a plurality of support studs strategically placed between levels within the structure and the periphery of the structure.
4. The structure recited in claim 3, wherein at least one via level includes a solid dielectric medium.
5. The structure recited in claim 3, wherein the dielectric gas is selected from the group consisting of air, argon, krypton and any mixture thereof.
6. In a process for fabricating a multilevel integrated circuit chip structure comprising alternating levels of conductive wiring and vias, at least one wiring level of which is imbedded in a sacrificial dielectric material, the step, subsequent to joining the structure to a chip carrier, of removing the sacrificial dielectric material.
7. A process for making a multilevel IC chip structure incorporating a gas dielectric, comprising: providing a semiconductor IC chip structure which is joined to a chip carrier and which comprises alternating levels of a plurality of via levels and conductive wiring levels, at least the wiring levels of which are temporarily embedded in a solid dielectric medium which is capable of being selectively removed; and removing the solid dielectric medium.
8. The process recited in claim 7, wherein the solid dielectric medium is selected from the group consisting of DLC, silicon oxide, polyimide, SILK, PMMA and a Novolac-type resist.
9. The process recited in claim 7 wherein the step of removing the solid dielectric medium comprises removing the solid dielectric medium by ashing or by dissolving into a solution.
10. The process recited in claim 7 wherein both the via levels and the wiring levels are temporarily imbedded in a solid dielectric medium and include support studs through the levels including the periphery.
11. A process for making a multilevel IC chip structure, comprising:
a. providing a semiconductor device level substrate;
b. applying a first diffusion barrier/adhesive plating seed layer onto the semiconductor device level substrate;
c. applying and curing a layer of photoresist over the first seed layer;
d. exposing and developing in the photoresist a mask for a first wiring level pattern;
e. plating a conductor into the developed first wiring level pattern to form a first wiring level;
f. applying and curing a layer of photoresist onto the first wiring level;
g. exposing and developing in the photoresist a mask for a first via level pattern;
h. plating a conductor into the developed first via level pattern to form a first via level;
i. removing the undeveloped photoresist and the seed thereunder;
j. backfilling the first via level with sacrificial dielectric, curing and planarizing the dielectric to expose vias and applying a second seed layer;
k. applying and curing a layer of photoresist over the seed layer;
l. exposing and developing in the photoresist a mask for a second wiring level including any dummy support studs;
m. plating a conductor into the developed second wiring level pattern to form a second wiring level;
n. repeating steps f through m for any third and subsequent levels until the total number of levels desired has been fabricated;
o. applying a layer of permanent solid dielectric over a final wiring level, applying and curing photoresist on the permanent solid dielectric exposing and developing a pad pattern and etching through the permanent solid dielectric to open a connection between vias and pads;
p. dicing the multilevel structure into individual chips;
q. joining at least one chip to a carrier; and
r. removing all temporary resist from the at least one chip.
12. The process recited in claim 11, wherein the step of applying a plating seed layer comprises sputtering a plating seed layer selected from a group of plating seed layers consisting of TiTa/Cu, Ti/Cu, Ta/Cu and TaN/Cu.
13. The process recited in claim 11, wherein the step of applying and curing a layer of photoresist comprises applying and curing a layer of photoresist selected from the group consisting of methacrylate, polyimide, Novolac, azide and cyclotene-based resins.
14. The process recited in claim 11, wherein the step of plating a conductor comprises electroplating a conductor selected from the group consisting of copper, silver, gold and alloys thereof.
15. The process recited in claim 11, comprising, between the step of fabrication of the total number of levels desired and the step of joining, the additional step of applying a dielectric material selected from the group consisting of SiO2, DLC, Si3N4, Al nitride and organic dielectric and exposing openings for connecting preselected vias and joining pads
16. The process recited in claim 11, wherein the step of removing photoresist comprises removing photoresist with a solvent comprising acetone or KOH or ashing in an oxygen-containing plasma.
17. The process recited in claim 11, including the additional step, subsequent to removal of sacrificial dielectric, of applying a corrosion inhibiting coating on the conductor.
18. The process recited in claim 17, wherein the step of applying a corrosion inhibiting coating on the conductor comprises applying a coating selected from the group consisting of Co/CO3, CoP, Ta and BTZ.
19. The process recited in claim 11, including the additional step, prior to dicing the multilevel structure into individual chips, of annealing the multilevel structure to stabilize it.
20. The process recited in claim 11, wherein the step of planarizing comprises chemical mechanical planarizing using alumina particles with ferric chloride, or KOH having a pH of about 9.
21. The process recited in claim 11, wherein the step of joining comprises C4 soldering using SnPb, SnBi, SnGa or SnAu.
22. The process recited in claim 11, wherein the step of removing the remaining temporary resist comprises blanket exposing the temporary resist and dissolving it in a photoresist developer.
23. The process recited in claim 11, wherein the steps of plating vias and plating wiring includes the additional, subsequent step of planarizing to be even with the level of the resist.
24. A process for making a multilevel chip structure, comprising:
a. providing a semiconductor substrate having a device level which includes planarized tungsten vias and transistors imbedded in SiO2 or SOI silicon-on-insulator;
b. applying a first diffusion barrier/adhesive plating seed layer onto the device level substrate;
c. applying and curing a first layer of photoresist over the first plating seed layer;
d. exposing and developing in the first layer of photoresist a mask for a first via level pattern; e. plating a conductor into the developed first via level pattern to form a first via level;
f. removing the remaining photoresist and the first plating seed layer thereunder;
g. depositing a semiconductor dielectric material onto the first via level and planarizing to expose the vias,
h. applying a second plating seed layer onto the planarized semiconductor dielectric material;
i. applying and curing a second layer of photoresist over the second plating seed layer;
j. exposing and developing in the second layer of photoresist a mask for a first wiring level pattern;
k. plating a conductor into the developed first wiring level pattern;
l. removing the remaining photoresist and the second plating seed layer thereunder;
m. applying a dielectric onto the first wiring level and planarizing to expose the wiring surface;
n. repeating steps b through m until the desired number of levels has been fabricated;
o. applying a final layer of DLC, preparing openings in the DLC for pad-to-via C4 plating and joining, plating conductor into the opening and plating solder onto the pads;
p. dicing the multilevel structure into chips;
q. joining at least one chip to a chip carrier; and
r. removing the dielectric from the at least one chip.
25. The process recited in claim 24, wherein the step of applying the dielectric comprises applying a dielectric selected from the group consisting of a silicon oxide, silicon nitride, and aluminum nitride.
26. The process recited in claim 24, wherein the step of removing the dielectric comprises preferentially dissolving the dielectric in a substantially nonaqueous composition which includes about 0.5M to about 15M of a fluoride in at least one organic solvent.
Description
    CLAIM OF PRIORITY
  • [0001]
    Priority is claimed on Provisional Application Serial No. 60/146,772, filed in the United States Patent Office Jul. 31, 1999.
  • DESCRIPTION
  • [0002]
    1. Field of the Invention
  • [0003]
    This invention relates to high density microminiaturized electronic circuit devices. More particularly, this invention relates to multilevel structures, and the formation of multilevel structures, comprised of alternating via levels and wiring levels embedded in a low dielectric constant medium and mounted on chip carriers.
  • [0004]
    2. Background of the Invention
  • [0005]
    Electrically integrated structures having multiple levels of conductive wiring horizontally supported in or on a dielectric material and vertically separated by intermediate levels of dielectric material are well known. Typically, alternating levels of wiring and vias can be quite numerous and complex in layout. The continuing drive toward reduction in dimensions and increase in density of features within these structures is inspired by aggressive requirements of memory, logic and storage density. Smaller device structures result in higher bit density, lower operating voltage, lower energy consumption and faster device speed. Smaller device structures require proportionately narrower and shorter conductor lines, narrower diameter vias and lower dielectric constant materials.
  • [0006]
    Increased also are the problems associated with such miniaturization and the proximity of the features to one another, including the risks of shorting, crosstalk and capacitive coupling between and especially within wiring levels, additional heat generation due to IR drop and the risk of failure due to electromigration and impeded signal speed.
  • [0007]
    As the design of the multilevel circuit structures becomes more aggressive, the need to reduce the dielectric constant (Er) of the dielectric insulating material to a value closer to the ideal value of value 1.0 in air or vacuum becomes a necessity. The lower the Er, the faster the signal speed and the rise time and the less the capacitive interaction. Lower Er permits operation of the device at a lower voltage which will result in lower thermal heating due to IR drop. In highly compact IC structures, the Er must be lowered not only in the via interlevels between wiring levels, but more importantly intralevel—within each wiring level. It is more critical to obtain extremely densely patterned circuitry levels separated by extremely low Er dielectric material between adjacent conductor lines within each wiring level to avoid capacitative interaction within the dense wiring levels. The lower the Er, the closer to each other can the lines in a wiring level be placed. It is therefore in the wiring level that the dielectric medium is more beneficially air, another suitable gas, or vacuum, i.e. a hollow structure.
  • [0008]
    Heat conductors in via levels and horizontal air movement through a hollow structure assure the elimination of any “hot spots”. Hot spots would contribute greatly to stress induced electromigration. Likewise, removing the additional heat generated by the densely configured operating structure and maintaining a low weight contribution to the ultimate device, for example such as laptop and hand-held devices, are important problems to solve in building high performance structures of the future.
  • [0009]
    Various materials, such as polyimide, epoxies, FR4-type resins, cyclotene, polymethyl methacrylate (PMMA) and Novolac-type resins, as well as fluorocarbons and others have been used as dielectric material in multilevel packaging structures, often with additives and fillers to affect properties such as thermal expansion (to reduce cracking and dislocation resulting from differing coefficients of thermal expansion among materials used in the structure), flame retardance, and Er. A high performance dielectric material might have an Er of about 3.2 to about 5.0; a pure fluoropolymer might have an Er as low as 2.1, a polyimide about 3.1 to about 3.5. In order to reduce further the Er to a number more nearly approaching the ideal value of pure air, various materials such as foam or hollow microspheres have been added to the resinous dielectric, the latter as described in U.S. Pat. No. 5,126,192 issued Jun. 30, 1992 to Chellis et al. and assigned to the assignee of the present invention. As the dimensions of the circuitry and particularly the spaces the individual conductor lines on any one level continue to decrease it is becoming more and more difficult to introduce hollow microspheres or foam dielectrics because the walls of the microspheres or the walls between air bubbles in the foam approach the dimension of the spaces between the conductor lines which is 1500A, 1000A, and eventually 500A.
  • [0010]
    Until recently in integrated circuit manufacturing, plated wiring was embedded in a dielectric material such as SiO2, polyimide, a combination of SiO2 and Si3O4, or other. One of the newer dielectric products is SiLK, a trademark product of Dow Chemical Company, which is a partially polymerized oligomeric spin-on material in a high purity NMP carrier solvent. The dielectric material provides electrical separation between and physical support for the individual conductor lines in the wiring levels. Support is particularly important in those structures which are built using a damascene process. Silicon dioxide has an Er of about 3.9 to about 4.5 and polyimide about 3.5, leaving room for improvement in current commercial structures as well as demanding improvement for structures of the future.
  • [0011]
    An article on pp. 575-585 published in the IBM Journal of Research and Development Volume 42 No. 5, September 1998, “Electrochemical process for advanced package fabrication”, coauthored by S. Krongelb, J. A. Tornello and L. T. Romankiw, the latter of whom is the inventor herein, includes a description of a process of making, and certain performance measurements of, a multilevel structure which incorporates polyimide dielectric layers and is on a chip carrier. In preparation for creating the scanning electron micrograph (SEM) images of the structure, seen as Figures 3 and 4 on p. 580 and Figure 5 on p. 581, polyimide was removed from a region of the structure by ashing in an oxygen containing plasma. Electrical measurements were performed in order to ascertain that the metallurgy was sound and that good metal-to-metal contact had been obtained during electroplating. The present invention, in which solid dielectric material is replaced by air or vacuum in order to obtain a mechanically sound, multilevel final structure having minimal Er, was not foretold by the reference. Up to the time of the present invention it was assumed that dielectric such as polyimide would provide a minimum Er which would be adequate for the thin film package (chip carrier).
  • [0012]
    An article on pp. 49-51 published in the journal Electrochemical and Solid State Letters published by the Electrochemical Society, Inc., 1(1), 1998, “Air-Gaps for Electrical Interconnections” is coauthored by Paul L. Kohl, Qiang Zhao, Kaushal Patel, Douglas Schmidt, Sue Ann Bidstrup-Allen, Robert Shick and S. Jayaraman. The reference describes the thermal decomposition of a sacrificial polymer at a temperature ramped up to 425 then to 450 degrees C. The sacrificial polymer is removed from between two metal line levels which are fully encapsulated within a permanent dielectric overcoat, and the products of the heat decomposition of the sacrificial polymer, less a thin residue, are forced out by diffusing through the overcoat, leaving a gap remaining in the region occupied by the polymer prior to its decomposition. It is stated in the reference that the effective dielectric constant between the two levels can be lowered to 2.3-2.7 for structures with a 1:1 aspect ratio (h:w), or perhaps lower, depending on the thickness and dielectric constant of the permanent overcoat. Clearly, the technique of thermal decomposition is quite different from that of the present invention. The feasibility of adapting and implementing a thermal decomposition technique in a manufacturing environment would be highly problematic. In order to manufacture a workable device it would be necessary to be able to fabricate more than two conductor line levels. That it would be possible to do so and to have the products of the heat decomposition of numerous levels of sacrificial polymer cleanly diffuse through multiple layers of permanent dielectric has not been described in the article.
  • [0013]
    A similar approach to removal of sacrificial carbon or photoresist by heating in oxygen at about 400 to 450 degrees C. for 2 hours, during which CO2 diffuses out through silicon oxide is described in GB2,330,00A, which was published 07.04.99 by Shih-Wei Sun. In the GB patent the term “ashing” is used for the removal process; in the electronics industry and in Applicant's invention ashing means exposing a substance to be removed to an oxygen plasma.
  • [0014]
    In the Technology News column on page 38 of the March 1999 edition of the journal Semiconductor International, Editor-in-Chief Peter Singer describes Toshiba's use of Carbon dioxide gas dielectric in the wiring level of a multilevel IC. Carbon dioxide is formed when the layer of carbon, which has been sputtered and covered with a thin layer of insulator is heated at 450 degrees C. in an oxygen atmosphere, resulting in the diffusion of oxygen through the thin layer of insulator and its combination with the underlying carbon to form carbon dioxide. Some key questions related to the workability of the resulting structure are identified. It appears from the example given that the process is performed one wiring level at a time, as only one such level is shown or described. It would be more efficient and practical if all levels to be hollowed we hollowed at one time, as in the present invention.
  • [0015]
    In an article “Future interconnect technologies and copper metallization” pages 63, 64, 68, 72, 74, 76 and 79 of the October, 1998 issue of the journal Solid State Technology, authors X. W. Lin and Dipu Pramanik describe a movement to electroplated copper wiring from aluminum wiring in the ICs of the future as an inevitable necessity. The authors further identify physical vapor deposited (PVD) or chemical vapor deposited (CVD) Ta, TaN, Si3N4 or W as known barriers to copper diffusion into silicon. Plated Cu is used in the present invention, in conjunction with diffusion barriers.
  • [0016]
    In an article “Air gaps lower k of interconnect dielectrics”, pages 51, 52, 54, 57 and 58 of the February, 1999 issue of the journal Solid State Technology, authors Ben Shieh, Krishna Saraswat, Mike Deal and Jim McVittio describe results of their modelling of air or vacuum as a dielectric medium in a variety of conductor line dimensions. Their simulation predicts a 40%-50% reduction in capacitance due to air gaps in the aluminum wiring level. The article predicts a possible problem with thermal conductivity in an air dielectric-based structure, which may be ameliorated by having SiO2 or HSQ (hydrogen silesquioxane) in the via levels, and another possible problem of fracture of a multilevel structure during CMP (chemical metal polishing). The cover article “In-line cure of SOD low-k films”, pages 29, 32 and 34 of the March, 1999 issue of the journal Solid State Technology, by Tom Batchelder, Wayne Cai, Jeff Bremmer and Doug Gray describes advantages of HSQ as a spin-on dielectric (SOD) due to the method of application being less complex and less expensive than CVD. A spin-on dielectric is a possible alternative permanent dielectric in the via levels of the present invention.
  • [0017]
    The present invention is unique in providing a functional multilevel chip structure which is mounted on a chip carrier, and a process for making the structure, in which an air, other suitable gas or an at least partial vacuum dielectric contributes to an Er which closely approaches the ideal value. In addition, the present invention provides enhanced cooling of the structure, reduced weight, circumvents thermal expansion mismatch problems, and obviates the need for any process steps related to the inclusion of fillers in dielectric material. In one example, a mechanically and electrically sound structure of up to eleven levels has been built successfully using air dielectric in both the wiring levels and the via levels. The resulting structure is not readily damaged or collapsed by application of reasonable pressure. In another structure of the present invention, in which diamond-like carbon (DLC) provides support in via levels, conductive lines in wiring levels having an air dielectric medium can be as close as 500 Angstroms apart.
  • [0018]
    In addition to lowering the Er, incorporating gas, such as air, inert gas, CO2, N2 or an at-least-partial vacuum dielectric medium into the structure of the present invention has the advantage of providing Er symmetry from level to level and across a level. In contrast to solid dielectric material, there is less likelihood of obtaining electrical anomalies due to the incorporation of conductive impurities or charged species. There is also less likelihood of XYZ dimensional distortion. Such dimensional instability can occur, for example, if a solid resinous dielectric material is exposed to temperatures at or above its glass transition temperature (Tg). Since areas of high mechanical stress are often sites at which electromigration is initiated, the fact that the conductive wiring is not confined within a solid dielectric can eliminate or reduce local stresses at corners and via/wiring intersections, hence reduce electromigration and electrical failure at the sites. The fact that joining of the chip to the carrier, such as by C4 or wire bonding, occurs before the removal of the temporary dielectric in Applicant's invention enables a strong solder bond to be created while preventing the solder from leaking into the chip structure. The subsequent removal of the temporary dielectric occurs through the open sides of the chip structure.
  • [0019]
    The present invention is applicable to high performance chips, radio frequency (rf) chips, analog chips, high performance SRAM and DRAM, MEMS and especially to fabrication of metallurgical interconnects referred to as back-of-the-line (BEOL) for mounting on packaging substrates such as ceramic or FR4, for use in memory, logic devices, displays, computers other applications, present and future, that will be apparent to one skilled in the art. The principles of the present invention are suitable for use in a chip structure having any conductor metallurgy, including Cu, Al, Au, Ag or alloys thereof
  • SUMMARY OF THE INVENTION
  • [0020]
    The present invention includes structures and processes useful for both thin film packages and multi-chip modules (MCM). The present invention provides a multilevel integrated wiring structure, and process of making the structure, which involves including a temporary dielectric material which, subsequent to dicing into chips and joining to a chip carrier, is readily and selectively removed, such as by dissolution or by ashing in an oxygen-containing or fluoride-containing atmosphere or plasma, depending on the composition of the sacrificial layers. Without compromising the integrity of the remaining structure, preselected levels are left having hollow areas to be filled with air or other suitable gas, or to be placed under at-least-partial vacuum, the gas or vacuum functioning as a permanent dielectric medium. Under the present invention, the electrically conducting columns, and “dummy” columns strategically placed uniformly throughout the chip and in the chip periphery also render strong mechanical support between wiring levels during the chemical mechanical polishing process (CMP) and subsequently in the completed chip and chip/carrier structure.
  • [0021]
    A structure has been fabricated having as many has 11 levels and an air dielectric medium in both the via and the wiring levels. Alternate structures under the present invention include solid permanent dielectric material in preselected via levels for additional support and the use of or a silicon-containing dielectric material as a temporary dielectric in the place of a temporary resin resist dielectric.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • [0022]
    [0022]FIG. 1A is an isometric view of a chip showing a structure of the present invention. Both vias and peripheral support studs (columns) are shown to support the wiring levels, which are otherwise separated by and are filled with the gas of choice or vacuum. A final cover layer of SiO2 or of DLC with imbedded top surface metallurgy and solder pads is indicated but not fully shown.
  • [0023]
    [0023]FIG. 1B illustrates from a top view a via level having metallic columns, with the via metallic columns shown disposed in the center area of a chip. Additional supports are shown disposed around the periphery. Circuitry is not shown, as the view is of the via/support level.
  • [0024]
    [0024]FIG. 2A taken with 2B are scanning electron micrographs (SEMs), in cross section, of a published case illustrating, by joining the various levels, removal of polyimide dielectric in every other via level. From a paper by J. Givens, S. Geissler, I. Cain, W. Clark, C. Koburger and J. Lee “A low temperature local interconnect process in a 0.25 micron channel CMOS logic technology with shallow trench isolation” at Proceedings of the 11th International VLSI Multilevel Interconnection Conference 1994, pages 43-48.
  • [0025]
    FIG. (2B) shows a part of two conductive wiring levels and one via level in which all dielectric was removed. From IBM Journal of Research and Development vol. 39, no. 4, July 1995 cover page.
  • [0026]
    [0026]FIG. 3 is an SEM of a self-supporting hollow structure of the present invention having eleven layers. The top level of semiconductor is not present in order to reveal the inner structure.
  • [0027]
    FIGS. 4(a), (b), (c), (d) and (e) shows steps in a typical dual damascene process. From pages 567-574 of IBM Journal of Research and Development, vol.42, No. 5, September. 1998.
  • BEST AND VARIOUS MODES FOR CARRYING OUT THE INVENTION
  • [0028]
    In order to facilitate understanding of the present invention, reference is made to the following detailed description taken in conjunction with the drawings.
  • [0029]
    In an embodiment of the present invention, support which is normally provided to a multilevel IC structure by a solid dielectric is provided instead by the conductive vias and by additional support columns located strategically among the devices and vias, at the chip periphery, or both. The supports are preferably made of the same material as the conductors, preferably copper or a copper-containing alloy. DLC and SiO2 can alternatively function as supports in places where it is required that the supports not be electrically conductive. In another embodiment of the present invention, a temporary dielectric material is removed, by means such as dissolution in a suitable solvent, sputter etching or plasma ashing, from wiring levels and from only selected via levels.
  • [0030]
    Aside from the presence of wiring, vias, and any supports and any other electronic device features, removal of temporary dielectric material in all via and wiring levels, or in selected levels of the structure, leaves those levels hollow, to be filled with air or another gas or an at-least-partial vacuum as the dielectric medium. It is particularly important to provide this minimum value dielectric medium in wiring levels.
  • [0031]
    Especially if vacuum is to be used as the dielectric material, means for providing heat dissipation is called for. DLC, with an Er contribution of about 3.5, SiO2, silicon nitride, aluminum nitride or any other compatible material having good dielectric and thermal properties can be present about every two, every four or every six via levels to function as thermal conductors. One suggested structure would include DLC in every via level and air or vacuum in the conductor, i.e. wiring, levels, except for the first and last via level. These thermally conductive permanent dielectrics also provide additional mechanical support to the structure.
  • [0032]
    It is recommended that at the completion of the fabrication of the structure on the substrate wafer but prior to dicing the substrate into chips, attaching the chips to a carrier, and removing the temporary dielectric layers, a brief anneal be performed to reduce any mechanical stresses and stabilize the structure.
  • [0033]
    The silicon substrate (5) of a structure of the present invention for BEOL application is shown in FIG. 1A. An interdiffusion barrier followed by seed (neither shown) have been deposited and conductive copper wiring patterned onto the substrate (5). Support studs (7) around the periphery of the chip provide additional support as well as heat dissipation. The additional supports are preferably made of the same material as the wiring (6) and the conductive vias (9), preferably copper, and deposited by plating. Vias (9) are used as conductors between wiring levels and as support studs. Conductive vias join a number of wiring levels and ultimately terminate at contact pads (4).
  • [0034]
    The space in the wiring levels (6 and 6′) which had been occupied earlier in the manufacture of the structure by a temporary dielectric material such as Novolac resin, polyimide, PMMA, SiLK or other has been removed, leaving vias and wiring in an otherwise hollow, air-filled dielectric environment and coated with an anticorrosion overcoat (not shown). Since the chip must be joined to a carrier prior to removal of the temporary dielectric material, the joining must be performed at sufficiently low temperature so that a resinous temporary dielectric material, such as AZ resist, would not totally polymerize or char. If material such as SiO2, polyimide or SiLK is used as the temporary dielectric, however, a higher joining temperature could be tolerated. For clarity of illustration, the top layer (8) is only indicated along the near edge of the periphery.
  • [0035]
    [0035]FIG. 1B shows from the top the support studs (7) at the periphery of the chip which extend vertically through the thickness of the chip. These peripheral studs provide additional support to a hollow structure and conduct heat away in a completed working device. They also play an important role during CMP. If the dielectric is softer than the metal conductor, the presence of strategically placed support studs in addition to vias will assure uniform chemical metal polishing.
  • [0036]
    [0036]FIGS. 2A and 2B are a cross section SEM of a BEOL structure. The SEM indicates stacked vias (9) vertically connected to wiring through contact pads (4) in the wiring levels at the right side of the FIG. 2B. In the SEM, a permanent dielectric material is present in all levels, as is typical in the prior art. In the present invention, all or most dielectric material is temporary. The area between the two SEMs shows how the prior art structure would appear with dielectric removed from conductive wiring levels, as in one aspect of the present invention. The temporary dielectric material can be a cured resist, SiO2, PI, PMMA, SiLK or presumably any other dielectric material which is otherwise compatible with the fabrication process and which can be selectively removed after soldering or otherwise joining the chip to the package under conditions which are not injurious to other elements of the structure or to the structure as a whole.
  • [0037]
    In the eleven-level structure shown in the FIG. 3 SEM, the temporary dielectric material was a polyimide, which has been removed by ashing in an oxygen-containing plasma in order to nondestructively compose the SEM and in order to perform measurements. In the SEM, the lighter, parallel features are the plated copper. The FIG. 3 structure was built by the plate and fill approach, which produces two levels at a time with one seed layer.
  • [0038]
    [0038]FIG. 4 represents a typical dual damascene process, in which via level dielectric (11) and conductor level dielectric (10) have been coated top and bottom with a layer of silicon nitride (17), as shown in FIG. 4A. In FIG. 4B the top layer of silicon nitride (17) has been opened and the beginning of via (12) has been etched through conductor level dielectric (10). In FIG. 4C silicon nitride (17) separating via level dielectric (11) and conductor level dielectric (10) has been opened, the etching for via (12) has been completed through via level dielectric (11) and etching for conductor line (13) has been completed through conductor level dielectric (10). In FIG. 4D barrier layer (14) has been deposited onto the interior surface of via (12) and conductor line (13), and plating seed layer (15) has been deposited over barrier layer (14). In FIG. 4E metal has been plated over seed layer (15) to fill via (12) and conductor line (13), and silicon nitride (17) has been redeposited in preparation for further processing.
  • [0039]
    In the examples which follow:
  • [0040]
    The term seed layer refers to a layer of conductive material deposited in order to form a conductive base for the plating of metal. A sputtered seed layer comprised of Ta or TaN (the diffusion barrier component)/Cu (the adhesive component for plated conductor) has been found satisfactory, as has Ti/Cu or TiTa/Cu. The diffusion barrier component of the seed inhibits interdiffusion of copper and SiO2 dielectric; the adhesion component assures initiation of plating and adhesion of the plated metal to the substrate. Alternatively, the adhesion/diffusion barrier can be electroless CoP, CoSnP, CoWP or others known in the art.
  • [0041]
    Photoresist refers to a light sensitive working resist the use of which is compatible with the processing steps of the invention. Novolac, an azide resist which cures at about 110 to about 140 degrees C., has been found satisfactory. Other resists, such as polymethyl methacrylate (PMMA) or cyclotene can also be used effectively. Removal of Novolac resist is satisfactorily accomplished in acetone, by ashing in an oxygen-containing plasma or, if blanket exposed, by a KOH developer or by a suitable organic solvent.
  • [0042]
    Temporary (aka sacrificial) dielectric refers to those layers of material designated to be removed and replaced by air, other suitable gas or at-least-partial vacuum. Cured resist is preferred; certain other material such as SiO2 are alternate choices.
  • [0043]
    The step to mount the chip to a carrier is referred to as soldering or as joining. C4 soldering has been found satisfactory, even for low-temperature joining. Soldering must be completed before the removal of the temporary dielectric material.
  • [0044]
    Above the substrate level, any SiO2 and DLC levels have been deposited by sputtering or CVD. Alternatively, an organosilicate material may be spun on in a liquid form and cured.
  • [0045]
    Chemical metal planarization (CMP) has been performed after the plating of the via/studs to assure that the studs are of even height with the dielectric material in that stud level and to assure electrical contact with the wiring level immediately following. Planarization using a combination of alumina particles and ferric chloride has been found satisfactory for silicon-containing material as well.
  • [0046]
    It is advisable that any copper to be in contact with air dielectric or other chemically active gas be coated with an anti-corrosion overcoat. Co/CoO3, electroless CoP or benzotriazole (BZT) have each been found satisfactory.
  • EXAMPLE 1
  • [0047]
    A hollow multilevel structure wherein the substrate is Si and the temporary dielectric material is a resist. In this example, DLC can be used as a dielectric in the via levels.
  • [0048]
    1. A Si wafer substrate with the semiconductor devices is metal film seeded with an adhesive and conductive metallic material and a positive photoresist is applied over the seed layer and cured. A mask pattern for a first wiring level, including any support studs, is exposed and developed, and copper wiring is plated into the openings developed in the resulting photoresist mask. This conductor level is aligned with tungsten vias which provide connection through the bottom SiO2 to the substrate and to active devices.
  • [0049]
    2. A fresh layer of photoresist is applied, cured, and exposed and developed in a first via level pattern. Vias and any studs and peripheral supports are plated and vias are planarized before removal of resist.
  • [0050]
    3. The remaining resist and the seed layer underlying it are removed and a fresh layer of resist is backfilled, cured, and CMP planarized to expose the top surface of the vias. A new adhesive/conductive seed layer is applied. A fresh layer of resist is spun on over the seed and cured, and a pattern for a second level of wiring is exposed, developed and wiring is plated through the photoresist mask.
  • [0051]
    4. Steps 2 and 3 are repeated until the number of levels desired have been fabricated.
  • [0052]
    5. A cover layer of SiO2 is sputtered or spun on and planarized before removal of resist.
  • [0053]
    6. Resist is applied, exposed and developed, vias are opened in SiO2 and remaining resist is removed.
  • [0054]
    7. A seed layer is sputtered, resist is applied, exposed and developed and copper pads are electroplated. The copper pads are plated with a Ni barrier followed by electroplating of SnPb solder.
  • [0055]
    8. Resist is removed, seed layer is etched away and plated solder is reflowed.
  • [0056]
    9. The wafer is diced into individual chips and at least one chip is joined to a package or to a chip carrier using a soldering process.
  • [0057]
    10. The remaining, temporary, dielectric is removed by chemical etching or plasma, leaving a hollow joined chip structure comprising alternating wiring and via levels in which the temporary resist dielectric has been removed and replaced by air, some other suitable gas or at least a partial vacuum.
  • EXAMPLE 2
  • [0058]
    A variation in which additional stability is obtained for the hollow multilevel structure by applying DLC, SiO2, silicon nitride or the like in one or more via levels.
  • [0059]
    1. A Si wafer substrate is seeded with an adhesive and conductive metallic material and a positive photoresist is applied over the seed layer and cured. A mask pattern for a first via level is exposed in the photoresist and developed, and copper is plated into the via openings developed in the photoresist mask.
  • [0060]
    2. The remaining resist and the seed underlying it are removed. SiO2 is applied onto the via level and planarized to reveal the top surfaces of the vias.
  • [0061]
    3. The applied SiO2 is seeded with an adhesive and conducive metallic material and a positive photoresist is applied over the seed and cured. A mask pattern for a first wiring level, including any support studs, is exposed and developed. Copper is plated into the openings developed in the resist mask.
  • [0062]
    4. The undeveloped resist is removed. Fresh resist is applied and planarized to expose the top surfaces of the wiring.
  • [0063]
    5. A fresh seed layer is applied to the planarized wiring level, and photoresist is applied over the seed layer and cured. A mask pattern for a second via level, including any support studs, is exposed and developed in the photoresist. Copper is plated into the developed via level openings and is planarized.
  • [0064]
    6. The remaining photoresist and seed layer thereunder are removed, and SiO2 is applied onto the second via level and planarized to reveal the top surfaces of the vias.
  • [0065]
    7. Steps 3-6 are repeated until the number of levels desired have been fabricated.
  • [0066]
    8. A cover layer of SiO2 is applied and planarized.
  • [0067]
    9. Resist is applied, cured, exposed and developed, vias are etched in SiO2 to make connection to the vias and dummy studs including those studs around the periphery of the chip.
  • [0068]
    10. Resist used in step 9 is removed and a seed layer is applied.
  • [0069]
    11. A fresh thick resist is applied, cured, exposed and developed to define the solder pads and form the C4 bumps.
  • [0070]
    12. Copper is plated on the pads followed by a Ni barrier layer and very thin gold is plated, followed by thick SnPb.
  • [0071]
    13. Resist and seed layer are removed by electrochemical and/or chemical etching, SnPb oxide is cleaned off and the C4 SnPb is reflowed.
  • [0072]
    14. The wafer is diced into individual chips, and at least one chip is joined to a package or a BEOL carrier using a low temperature joining process such as wire bonding or C4 bonding.
  • [0073]
    10. Step #10 from example 1 above is performed.
  • EXAMPLE 3
  • [0074]
    A hollow multilevel structure wherein the first dielectric layer is DLC and the temporary dielectric is SiO2.
  • [0075]
    In example 3 below, DLC comprises the first and the final dielectric layers of the structure, and a silicon-containing material, such as SiO2 is used instead of resist as the temporary dielectric material. When the desired number of levels has been fabricated, the structure is soldered to a carrier and the SiO2 is removed in a fluoride-containing solvent such as the one described in U.S. Pat. No. 6,033,996 to Jagannathan et al. which does not attack the metal or DLC, leaving a self supporting hollow chip structure which is filled with air dielectric, other gas, or an at-least-partial vacuum. If the structure requires additional stability, DLC can be sputtered during fabrication no more frequently than in alternate via levels
  • [0076]
    1. A Si device substrate is seeded with an adhesive and conductive metallic material and a positive photoresist is applied over the seed layer and cured. A mask pattern for a first via level is exposed and developed, and vias and any additional support studs are plated through openings in the resulting photoresist mask.
  • [0077]
    2. The undeveloped resist and the seed underlying it are removed and SiO2, silicon nitride or another Si-containing material is backfilled into the first via level. The backfilled SiO2 is planarized to open up the conductive vias, then seeded with an adhesive and conductive metallic material, and photoresist is applied over the seed layer and cured.
  • [0078]
    3. A mask pattern for a first wiring level is exposed and developed, and conductive copper wiring is plated through the openings in the resulting photoresist mask.
  • [0079]
    4. The resist remaining and the seed underlying it are removed. A fresh layer of SiO2 is applied to the plated first wiring level and planarized to expose the wiring. Photoresist is cured, exposed and developed, and a second via level is plated through openings in the resulting photoresist mask.
  • [0080]
    5. The fabrication steps for the second via level are the same as for the first via level except for being on SiO2 rather than DLC. Subsequent alternating layers of wiring and via levels are fabricated until the total number desired has been fabricated.
  • [0081]
    6. The final layer, DLC, is sputtered and the top surface metallurgy is fabricated as described in steps 9 through 13 of Example 2 above.
  • [0082]
    7. The wafer is diced into chips, and at least one chip is low-temperature joined to a carrier. The Si-containing material is etched away preferentially in a substantially nonaqueous organic fluoride-containing solution.
  • EXAMPLE 4
  • [0083]
    In another alternative a conventional dual damascene process is used. Adapting the conventional damascene approach, which is illustrated in FIG. 4, conductor and via patterns are opened in SiO2 inorganic dielectric or in SILK or other organic dielectric.
  • [0084]
    1. The Si substrate, including patterned lines and vias, is seeded.
  • [0085]
    2. Copper is electroplated, followed by CMP planarization, which results in a structure like the one illustrated in FIG. 4(e).
  • [0086]
    3. Another two layers of inorganic or of organic dielectric described above, SiO2 in the present example, are applied and the opening and seeding processes described above are repeated. The process is repeated as many times as necessary to produce a structure such as the one illustrated in FIG. 2(a) or 2(b).
  • [0087]
    4. Top surface metallurgy is fabricated as described in steps 9 through 13 of Example 2 above.
  • [0088]
    5. The structure is diced into chips and the chips are attached to a carrier using C4.
  • [0089]
    6. The SiO2 is then selectively chemically etched away, or if organic dielectric or other dielectric removable by O2, etched away in an oxygen-containing plasma, resulting in a hollow structure having an overall dielectric constant about equal to 1.
  • [0090]
    7. After removal of the dielectric the exposed copper conductors can be protected by electroless plating of CoP or by overcoating with BTA.
  • EXAMPLE 5
  • [0091]
    In this example the dielectric layers are alternated between SiO2 and DLC or between SiO2 and SILK or other organic dielectric. The more rigid dielectric is preferably used in the via levels and the less rigid dielectric in the conductor levels. The process followed is like the one described in Example 5. When sufficient layers are completed to produce a structure such as is shown in FIGS. 2(A) and 2(B) the wafer is diced into individual chips which are C4 bonded to a carrier.
  • [0092]
    Assuming the metal in the structure is protected from attack by the plasma, if a temporary dielectric selected for the conductor levels is removable in O2 plasma and a permanent dielectric selected for the via levels is not, treatment with O2 plasma will leave the permanent dielectric in place in the via levels while selectively removing the temporary dielectric from the conductor levels leaving the conductor levels to be filled with air, other suitable gas or partial vacuum. The result will be a dielectric constant of 1 in the conductor levels, where low dielectric constant matters most, highly supported by the via levels. Assuming the solvent selected will not attack the metal in the structure, the same strong structure having very low dielectric constant will result if a temporary dielectric selected for the conductor levels is removable in an organic solvent and a permanent dielectric selected for the via levels is not. If the via level dielectric is DLC, thermal conductivity will be enhanced.
  • [0093]
    It will be obvious to one skilled in the art that other combinations of specific materials and other processes can be used as long as the following key requirements described in Examples 1-5 are maintained:
  • [0094]
    1. The mask design for the initial chip layout should incorporate strategically placed vias to be plated with support studs throughout the chip and around the periphery of the chip as shown in FIGS. 1A and 1B
  • [0095]
    2. The support studs must be plated each time another level of vias and another level of conductors is plated. The support studs also undergo every CMP processing step.
  • [0096]
    3. The means for removal of the temporary dielectric should be selective and should not damage the metal or permanent dielectric material.
  • [0097]
    4. The top surface metallurgy, including SnPb bumps or gold bumps, are formed.
  • [0098]
    5. Prior to removal of the temporary dielectric material, the chips must be diced and attached to the chip carrier (aka package) using such conventional means as C4, thermal compression, wire bonding and the like.
  • [0099]
    The above examples are intended to be illustrative rather than exhaustive, and while the invention has been described in conjunction with specific embodiments, many additional embodiments, modifications and applications will be apparent now and in the future to those skilled in the art.
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