US 20030212729 A1 Abstract Modular multiplication of two elements X(t) and Y(t), over GF(2), where m is a field degree, may utilize field degree to determine, at least in part, the number of iterations. An extra shift operation may be employed when the number of iterations is reduced. Modular multiplication of two elements X(t) and Y(t), over GF(2), may include a shared reduction circuit utilized during multiplication and reduction. In addition, a modular multiplication of binary polynomials X(t) and Y(t), over GF(2), may utilize the Karatsuba algorithm, e.g., by recursively splitting up a multiplication into smaller operands determined according to the Karatsuba algorithm.
Claims(31) 1. A method of performing a modular multiplication of two elements X(t) and Y(t), of GF(2^{m}), where m is a field degree, comprising:
performing a polynomial multiplication in a number of iterations, the number of iterations being determined, at least in part, according to the field degree m and digit size d, the digit size d being at least two bits, and supplying an intermediate result thereof. 2. The method as recited in ^{m}). 3. The method as recited in performing an additional shift operation when the field degree is less than a predetermined amount prior to supplying the intermediate result for the reduction operation.
4. The method as recited in shifting a current intermediate result in a register (Z) by an amount d to produce a shifted intermediate result, d being less than a size of the register Z;
adding to the shifted intermediate result a product of a portion of a register X initially containing X(t), the portion being d bits in size, and contents of register Y, initially containing Y(t); and
shifting the X register by d bits.
5. The method as recited in 6. The method as recited in 7. The method as recited in summing a plurality of partial products, each partial product formed utilizing three partial products in the form of Xh*Yh, Xl*Yl and (Xh−Xl)*Yh−Yl), where Xh are high order bits of at least a portion of X(t), Xl are low order bits of the portion of X(t), Yh are high order bits of at least a portion of Y(t), and Yl are low order bits of the portion of Y(t).
8. An apparatus for performing a modular multiplication of two polynomial elements X(t) and Y(t), of GF(2^{m}), where m is a field degree, and supplying as an output an element P(t) of GF(2^{m}), comprising:
a first register (X) for storing an initial value of X(t) and coupled to supply a d number of bits, d being an integer; a shift circuit coupled to shift the first register X by d bits; a second register (Y) coupled to supply n bits, n being an integer; a multiplier coupled to multiply d bits of the first register and n bits of the second register and supply a multiplier output; a third register (Z) at least 2n bits wide providing an intermediate result; an adder coupled to add the multiplier output and an output of the third register Z; a reduction circuit coupled to receive an intermediate result from the third register, the intermediate result received by the reduction circuit being one of an output of the third register and a shifted output of the third register resulting from an additional shift operation on contents of the third register Z, the additional shift operation being determined according to the field degree m. 9. The apparatus as recited in 10. An apparatus comprising:
means for supplying two elements X(t) and Y(t), of GF(2 ^{m}), where m is a field degree; and means for providing a modular multiplication of the two elements X(t) and Y(t), of GF(2 ^{m}), and supplying as an output an element P(t) of GF(2^{m}), the modular multiplication being optimized, in terms of number of iterations utilized to perform the modular multiplication, according to the field degree m and a digit size d, d being at least two. 11. The apparatus as recited in 12. The apparatus as recited in 13. A method of performing modular multiplication of two elements X(t) and Y(t), of GF(2^{m}), comprising reducing one of the multiplicands in the process of generating an intermediate result in a reduction circuit and reducing the intermediate result in the reduction circuit to generate an element P(t) of GF(2^{m}). 14. The method as recited in 15. A method of performing a modular multiplication of two elements X(t) and Y(t), of GF(2^{m}), X(t) and Y(t) being stored initially in a register X and a register Y, respectively, and supplying as an output element P(t) of GF(2^{m}), comprising:
performing a polynomial multiplication of the contents of register X and Y using a number of iterations, and supplying an intermediate result; performing a reduction operation on contents of Y, during each of the iterations, in a reduction circuit; and performing a reduction operation in the reduction circuit on the intermediate result to provide the output element P(t). 16. The method as recited in adding to a current intermediate result a product of a portion of register X, the portion being d bits in size, and contents of the Y register;
shifting the X register by d bits; and
shifting the Y register by d bits to produce a shifted result, reducing the shifted result and then storing the shifted result into the Y register.
17. The method as recited in summing a plurality of partial products, each partial product formed utilizing three partial products in the form of Xh*Yh, Xl*Yl and (Xh−Xl)*(Yh−Yl), where Xh are high order bits of at least a portion of X(t), Xl are low order bits of the portion of X(t), Yh are high order bits of at least a portion of Y(t), and Yl are low order bits of the portion of Y(t).
18. The method as recited in 19. An apparatus for performing a modular multiplication of two elements X(t) and Y(t), of GF(2^{m}), where m is a field degree, and supplying as an output an element P(t) of GF(2m), comprising:
a first register (X) storing an initial value of X(t) and coupled to supply d bits, d being an integer; a second register (Y) storing an initial value of Y(t) coupled to supply n bits; a multiplier coupled to multiply d bits of the first register and n bits of the second register and supply a multiplier output; a third register (Z) coupled to supply an intermediate result; an adder coupled to add the multiplier output and an output of the third register Z; and a reduction circuit coupled to selectably receive one of the intermediate result from the third register and to receive a shifted value of the second register (Y). 20. The apparatus as recited in 21. The apparatus as recited in 22. The apparatus as recited in 23. The apparatus as recited in 1), where Xh are high order bits of at least a portion of X(t), X1 are low order bits of the portion of X(t), Yh are high order bits of at least a portion of Y(t), and Yl are low order bits of the portion of Y(t). 24. A method of performing a modular multiplication of two elements X(t) and Y(t), of GF(2^{m}), X(t) and Y(t) being stored initially in a register X and a register Y and supplying as an output an element P(t) of GF(2^{m}), comprising:
performing a polynomial multiplication of the contents of register X and Y using a number of iterations; wherein one iteration includes:
adding to a current reduced intermediate result a product of a portion of register X, the portion being d bits in size, and contents of the register Y to produce a sum;
performing a first reduction operation on shifted contents of the Y register in a first reduction circuit;
performing a second reduction operation in a second reduction circuit on the sum to generate a reduced sum.
25. An apparatus for performing a modular multiplication of two elements X(t) and Y(t), of GF(2^{m}), where m is a field degree, and supplying as an output an element P(t) of GF(2^{m}), comprising:
a first register (X) storing an initial value of X(t) and coupled to supply d bits, d being an integer; a second register (Y) storing an initial value of Y(t) coupled to supply n bits; a multiplier coupled to multiply d bits of the first register and n bits of the second register and supply a multiplier output; a third register (Z) coupled to supply an intermediate result; an adder coupled to add the multiplier output and an output of the third register Z; a first reduction circuit coupled to the adder to supply the third register Z with result of the first reduction circuit; and a second reduction circuit coupled to receive a shifted value of the second register (Y) and to supply an output of the second reduction circuit to the second register (Y). 26. A method of performing a modular multiplication of binary polynomials X(t) and Y(t), over GF(2), the modular multiplication comprising:
summing a plurality of partial products, each partial product formed utilizing three partial products in the form of Xh*Yh, Xl*Yl and (Xh−Xl)*(Yh−Yl), where Xh is a high portion of X(t), Xl is a low portion of X(t), Yh is a high portion of Y(t), and Yl is a low portion of Y(t). 27. A method of performing a modular multiplication of two binary polynomial elements X(t) and Y(t), the modular multiplication comprising recursively splitting up a multiplication into smaller operands determined according to the Karatsuba algorithm. 28. A method of performing a modular multiplication of two elements X(t) and Y(t), over GF(2), the modular multiplication comprising:
applying a multiplication algorithm utilizing three partial products in the form of Xh*Yh, Xl*Yl and(Xh−Xl)*(Yh−Yl), where Xh is a high portion of X(t), Xl is a low portion of X(t), Yh is a high portion of Y(t), and Yl is a low portion of Y(t); recursively applying the multiplication algorithm utilizing three partial products in the form of Xhh*Yhh, Xhl*Yhl and(Xhh−Xhl)*(Yhh−Yhl), where Xhh is a high portion of Xh, Xhl is a low portion of Xh, Yhh is a high portion of Yh, and Yhl is a low portion of Yh, to determine the product of Xh*Yh; and utilizing a serial shift and add multiplication at a low level to the three partial products. 29. A method of performing a hybrid long-word multiplication of two binary polynomials X(t) and Y(t), the multiplication comprising:
utilizing a shift and add algorithm that sums partial products; and generating the partial products utilizing a multiplication algorithm that utilizes three partial products in the form of Xh*Yh, Xl*Yl and (Xh−Xl)*(Yh−Yl), where Xh is a high portion of X, Xl is a low portion of X, Yh is a high portion of Y, and Yl is a low portion of Y, X and Y being a portion of X(t) and Y(t). 30. A method of performing a modular multiplication of binary polynomials X(t) and Y(t), over GF(2), comprising selecting one of a plurality of hardwired reduction circuits to use in a reduction operation associated with the modular multiplication according to an underlying field extension field of GF(2). 31. An apparatus for performing a modular multiplication of binary polynomials X(t) and Y(t), over GF(2), comprising a plurality of hardwired reduction circuits selected for use in a reduction operation associated with the modular multiplication according to an underlying extension field of GF(2).Description [0001] This application claims the benefit under 35 U.S.C. §119(e) of the following provisional applications No. 60/376,742, filed May 1, 2002; No. 60/379,316, filed May 10, 2002; No. 60/389,135 filed Jun. 14, 2002; No. 60/400,223 filed Aug. 1, 2002; and No. 60/426,783, filed Nov. 15, 2002; all of which are incorporated herein by reference. [0002] 1. Field of the Invention [0003] This invention relates to multiplication and particularly to modular multiplication techniques. [0004] 2. Description of the Related Art [0005] Elliptic Curve Cryptography (ECC) is evolving as an attractive alternative to other public-key schemes such as RSA by offering the smallest key size and the highest strength per bit and efficient computation. Internet standards such as Secure Socket Layer (SSL), IP security (IPsec), and Pretty Good Privacy (PGP) rely on public-key cryptosystems for key management. [0006] The mathematical simplicity of RSA and the Diffie-Hellman key exchange allows for a straightforward implementation of the underlying arithmetic operations. Implementations are available in various cryptographic libraries. Arithmetically, RSA and the Diffie-Hellman key exchange operate on integer fields and primarily involve modular multiplication. In comparison, ECC is more complex. It is specified over both integer and binary polynomial fields and involves modular division in addition to modular multiplication. Implementing ECC is further complicated by algorithmic choices. Algorithms may be chosen according to the characteristics of the system architecture and constraints such as processor speed, data path width or memory size. [0007] Different fields can underlie elliptic curves, including integer fields GF(p) and binary polynomial fields GF(2 [0008] To make ECC commercially viable, its integration into secure protocols needs to be standardized. As an emerging alternative to RSA, the US government has adopted ECC for the Elliptic Curve Digital Signature Algorithm (ECDSA) and recommended a set of named curves over binary polynomial fields for key sizes of 163, 233, 283, 409 and 571 bit. Additional curves for commercial use were recommended by the Standards for Efficient Cryptography Group (SECG). However, only few ECC-enabled protocols have been deployed so far. Today's dominant secure Internet protocols such as SSL and IPsec rely on RSA and the Diffie-Hellman key exchange. Although standards for the integration of ECC into secure Internet protocols have been proposed, they have not yet been finalized. [0009] The evolving wireless and web-based environment has millions of client devices including portable and desktop computers, cell phones, PDAs and SmartCards connecting to servers over secure connections. The aggregation of connections and transactions requested by client devices leads to high computational demand on the server side. Small key sizes and computational efficiency of both public and private key operations make ECC attractive to both server systems that need to process large numbers of secure connections and client devices which may have limited processing capabilities. While small key sizes and computational efficiency of both public and private key operations allow secure protocols based on ECC standards to be handled in software on the client side, the aggregation of secure connections demands high computational power on the server side that easily exceeds the capabilities of a general-purpose CPU. [0010] While optimized implementations for specific named curves and field degrees can provide high performance, it is a desired security feature for server-side implementations to provide both ECC software libraries and hardware accelerators that support generic elliptic curves over a wide range of binary polynomial fields GF(2 [0011] Accordingly, it would be desirable to provide improved modular multiplication techniques. [0012] One way to improve modular multiplication is to provide optimization of the multiplication operation based on the field degree of the operands. Accordingly, a method is provided for performing a modular multiplication of two elements X(t) and Y(t), of GF(2 [0013] An apparatus is provided for performing a modular multiplication of two polynomial elements X(t) and Y(t), of GF(2 [0014] A method of performing modular multiplication of two elements X(t) and Y(t), of GF(2 [0015] A method is provided for performing a modular multiplication of two elements X(t) and Y(t), of GF(2 [0016] A method is provided for performing a modular multiplication of two elements X(t) and Y(t), of GF(2 [0017] An apparatus is provided for performing a modular multiplication of two elements X(t) and Y(t), of GF(2 [0018] In addition, a modular multiplication of binary polynomials X(t) and Y(t), over GF(2), may utilize the Karatsuba algorithm, which includes summing a plurality of partial products, each partial product formed utilizing three partial products in the form of Xh*Yh, Xl*YL and(Xh−Xl)*(Yh−Yl), where Xh is a high portion of X(t), Xl is a low portion of X(t), Yh is a high portion of Y(t), and Yl is a low portion of Y(t). The Karatsuba algorithm can be utilized in modular multiplication of binary polynomials in various ways, e.g., by recursively splitting up a multiplication into smaller operands determined according to the Karatsuba algorithm. [0019] The present invention may be better understood, and its numerous objects, features, and advantages made apparent to those skilled in the art by referencing the accompanying drawings. [0020]FIG. 1A illustrates an embodiment of a system utilizing ECC hardware acceleration. [0021]FIG. 1B illustrates another embodiment of a system utilizing ECC hardware acceleration. [0022]FIG. 2A illustrates an exemplary block diagram of a hardware accelerator. [0023] FIGS. [0024]FIG. 3 illustrates a register set of an exemplary accelerator. [0025]FIG. 4 illustrates an instruction set of an exemplary accelerator. [0026]FIG. 5 illustrates exemplary instruction formats. [0027]FIG. 6 illustrates additional detail of an exemplary control unit for the accelerator. [0028]FIG. 7 illustrates overlapping instruction execution. [0029]FIG. 8 illustrates parallel instruction execution. [0030]FIG. 9 shows an exemplary memory mapping of accelerator addresses. [0031]FIG. 10 illustrates the word order for the DMEM and IMEM. [0032]FIG. 11 illustrates the contents of the Command and Status Register (CSR). [0033]FIG. 12 illustrates the organization of the program call frame. [0034]FIG. 13 illustrates an arithmetic logic unit for squaring, additions, and shifting. [0035]FIG. 14 illustrates polynomial multiplication using a serial shift-and-add algorithm. [0036]FIG. 15 illustrates modular reduction of a multiplication result. [0037]FIG. 16 illustrates an example of hardwired reduction. [0038]FIG. 17 shows a block diagram of a circuit performing modular multiplication with digit size d. [0039]FIG. 18 illustrates a multiplier shown in FIG. 17 optimized by considering the field size. [0040]FIG. 19 illustrates a digit serial shift and add multiplier circuit that can be used with hardwired reduction. [0041]FIG. 20 illustrates an embodiment of an LSD modular multiplier. [0042]FIG. 21 illustrates an embodiment of an LSD modular multiplier circuit with shared reduction logic. [0043]FIG. 22 illustrates another embodiment of a modular multiplier circuit. [0044]FIG. 23 shows a block diagram of an LSD multiplier supporting hardwired reduction for multiple named curves. [0045]FIG. 24 illustrates how the partial product is calculated during a multiplication iteration of the modular multiplier illustrated in FIG. 18. [0046]FIG. 25 illustrates an alternative way to calculate partial products by applying the Karatsuba algorithm. [0047]FIG. 26 illustrates use of the Karatsuba algorithm. [0048]FIGS. 27A and 27B illustrate recursive application of the Karatsuba algorithm. [0049]FIG. 28 illustrates a serial shift and add multiplier. [0050]FIG. 29 shows another utilization of the Karatsuba algorithm. [0051]FIG. 30 illustrates a reduction iteration for a pentanomial. [0052]FIG. 31 illustrates a result of a multiplication for arbitrary curves that requires reduction. [0053]FIG. 32 shows an alternative approach to reduction. [0054]FIG. 33 illustrates the use of partial reduction. [0055]FIG. 34 shows a multiplier with data paths customized for partial reduction. [0056]FIG. 35 illustrates an embodiment of a multiplier circuit providing optimized performance for named curves and at the same time support for generic curves. [0057]FIG. 36 shows the state diagram for the generic LSD multiplier. [0058]FIG. 37 shows a block diagram of an MSD multiplier for named curves. [0059]FIG. 38 illustrates a generic MSD multiplier that can handle both named and generic curves. [0060]FIG. 39 shows the state diagram for the generic MSD multiplier [0061]FIG. 40 illustrates a divider circuit. [0062]FIG. 41 illustrates an assembly code fragment for implementing projective Montgomery point multiplication. [0063] The use of the same reference symbols in different drawings indicates similar or identical items. [0064] Referring to FIG. 1A a system [0065] The exemplary accelerator provides the basic functions needed to execute point multiplications on elliptic curves specified over binary polynomial fields. In one embodiment the accelerator is an FPGA-based PCI card that implements a co-processor for accelerating elliptic curve cryptography (ECC). More specifically, it enhances the performance of point multiplications on elliptic curves specified over binary polynomial fields. The hardware accelerator provides high performance for named elliptic curves (e.g., those named curves for key sizes of 163, 233, 283, 409, and 571) and supports point multiplications on other arbitrary curves, which may be less frequently used or unknown at implementation time. [0066]FIG. 2A shows an exemplary block diagram of the data and control path of the hardware accelerator. The hardware accelerator is implemented as a programmable processor designed to execute ECC point multiplication. The data path of the exemplary hardware accelerator illustrated in FIG. 2A implements a 256-bit architecture. The exemplary hardware accelerator includes a data memory DMEM [0067]FIG. 2B illustrates an alternative embodiment that uses only one bus shared by source and destination operands. FIG. 2C illustrates another embodiment that uses two source buses (SBUS [0068] The register set includes general-purpose registers R [0069] Referring again to FIG. 2A, program execution is orchestrated by the micro-programmed control unit [0070] Memory instructions LD and ST transfer operands between the DMEM [0071]FIG. 4 illustrates the instruction set utilized by an embodiment of the accelerator. The instruction set is composed of memory instructions, arithmetic/logic instructions and control instructions. In one embodiment the accelerator implements a load/store architecture. Thus, in an embodiment, memory can be accessed by load and store operations only, and all arithmetic instructions use register operands only. The memory instructions define two operands, a register and a memory operand. Memory instructions LD and ST transfer operands between the DMEM and the register file. The memory operand is specified by an 8-bit absolute address. Memory is accessed in 256-bit words aligned to 256-bit word addresses. [0072] The arithmetic instructions DIV, MUL, MULPR, MULNR, ADD, and SQR are defined for binary polynomial fields. The operands contain bit strings b [0073] The reduction may be implemented in different ways. The multiplier contains hardwired reduction logic for named curves and generic reduction logic (the multiplier) is used for generic curves. More specifically, the MUL instruction uses the hardwired reduction logic for named curves (when the parameter nc is not equal to 0) and uses generic reduction logic for generic curves (when the parameter nc is equal to 0). The parameter nc is defined by the program call frame as explained further herein. The MULPR instruction uses the reduction logic for generic curves (i.e., the multiplier, various embodiments of which are described further herein). For named curves, the irreducible polynomial is implicitly specified by the configuration register RC, whereas for generic curves the polynomial used for reduction is explicitly given by the contents of the register RM. In the latter case when reduction is based on the partial reduction method, RM contains (M−t [0074] The DIV instruction executed by the divider performs a reduction by the polynomial held in RM. The SQR instruction executed by the ALU uses hardwired reduction for named curves. Reduction for generic curves may not be implemented in the ALU. Therefore, in one embodiment, SQR instructions are translated into MUL instructions by the instruction decoder if nc specifies a generic curve. [0075] There are three conditional branch instructions and one unconditional branch instruction to implement non-sequential program execution. BMZ is a conditional branch that is taken if condition code MZ is set to one. The condition code MZ is generated when a shift left (SL) instruction is executed. More specifically, if the most significant bit of the operand shifted is zero, MZ is set to one. BEQ is a conditional branch instruction that is taken if the condition code EQ is set to one. EQ is set to one if the result of the last ADD, SQR, or SL instruction executed is zero. BNC is a conditional branch that is taken if NC is set to one (NC is 1 when RC.nc≠0 and NC is 0 when RC.nc=0). RC.nc specifies the named curve and is equal to 0 if a generic curve rather than a named curve is specified. JMP implements an unconditional branch. BMZ, BEQ, BNC, and JMP specify the target of the branch with a 9-bit absolute address. Program execution is ended by the END instruction. The NOP instruction is provided as a way to remove data dependencies. The instructions given are exemplary. Additional instructions or fewer instructions may be implemented in a given embodiment. [0076] Exemplary instruction formats are shown in FIG. 5. In the illustrated embodiment, instructions have a uniform size of 16 bits. Four bits are utilized for the opcode. Four bits are used to specify each source and destination register. An 8-bit instruction field specifies DMEM addresses making it possible to address a total of 256 256-bit words. A 9-bit instruction field specifies IMEM addresses allowing for addressing 512 16-bit instructions. [0077] The execution of arithmetic instructions can take multiple cycles and, in the case of division, the execution time may even be data dependent. To control the flow of the program execution, the conditional branch instructions BMZ and BEQ, the unconditional branch instruction JMP and the program termination instruction END can be used. [0078]FIG. 6 illustrates additional details of exemplary microprogrammed control unit [0079] The execution of an arithmetic instruction consists of the following stages: [0080] 1. Fetch: The instruction is fetched from the IMEM and decoded. [0081] 2. Load RS: The source operands are transferred over the SBUS from the register file into the arithmetic unit. [0082] 3. Execute: The instruction is executed in the arithmetic unit. The execution time varies with the instruction and can take several clock cycles. [0083] 4. Store RD: The result is transferred over the DBUS from the arithmetic unit into the register file. [0084] The finite state machines (FSMs) [0085] The data path may allow instructions to be executed in parallel and/or overlapped. In one embodiment, the control unit overlaps the execution of arithmetic instructions by prefetching the instruction as well as preloading the first source operand. This is illustrated in FIG. 7. While instruction 10 is being “executed” (referring to the overall execution of the instruction and not just to the execute stage in the arithmetic unit), the next instruction I [0086] Parallel execution of instructions is implemented for the instruction sequence I [0087] In one embodiment, the memory and registers implemented by a PCI device are mapped by a device driver into user and kernel address spaces of the host machine with the help of Base Address Registers (BARs). The memory space with Base Address [0088] In the illustrated embodiment, control registers are in little-endian order. The order for the DMEM and the IMEM is shown in FIG. 10. As described previously, accelerator memories have two ports, one connected to the PCI bus and the other one connected to the control unit and the accelerator data path, respectively. On the PCI side, addresses are byte addresses with paddr referring to the base addresses of the memories. On the accelerator side, addresses are 16-bit-word addresses for the IMEM and 256-bit-word addresses for the DMEM with caddr referring to the memories' base addresses. [0089]FIG. 11 defines the Command and Status Register (CSR) [0090] The host, (e.g. CPU [0091] The sequence of steps for executing a program is as follows: [0092] 1. Host transfers code into IMEM. [0093] 2. Host initializes Program Call Frame in DMEM. [0094] 3. Host sets the CSR bit Start to 1. [0095] 4. ECC Accelerator sets CSR bit Done to 0. [0096] 5. Host sets CSR bit Start to 0. [0097] 6. ECC Accelerator executes the program. When the END instruction is encountered, ECC Accelerator sets CSR bit Done to 1. [0098] 7. Host polls CSR bit Done until it is set to 1. [0099] 8. Host reads result from Program Call Frame in DMEM. [0100] Step 1 is only needed for a first program execution and can be omitted thereafter. [0101] Before describing the various arithmetic units in more detail a brief background on ECC arithmetic in GF(2 [0102] The fundamental and most expensive operation underlying ECC is point multiplication, which is defined over finite fields. For a non-supersingular elliptic curve C: y [0103] Cases (1a) and (1b) describe a point addition and cases (1c) and (1d) describe a point doubling. For a point P in G and a positive integer k, the point multiplication kP is defined by adding P (k−1) times to itself, e.g. 4P=P+P+P+P. One suitable algorithm to efficiently compute point multiplications is Montgomery's point multiplication algorithm using projective coordinates. That algorithm allows for simple implementations in both hardware and software. It avoids expensive divisions by representing affine point coordinates (x,y) as projective triples (X,Y,Z) with x=X/Z and y=Y/Z. In addition, it reduces the number of arithmetic operations by only computing the x-coordinate of intermediate points. Hardware implementations can exploit the fact that most multiplications can be executed in parallel to squarings or additions. Using projective coordinate representation, Montgomery point multiplication requires 6└log [0104] Elliptic curve cryptography over finite fields is based on modular addition, subtraction, multiplication, squaring and division. These operations are specific to the underlying field. The notation GF(2 [0105] M is of degree m, which is also referred to as the field degree. Note that while an irreducible polynomial M defines the field degree m, there can be different irreducible polynomials of the same field degree. Elements of a field GF(2 [0106] The field addition of two elements α; b∈GF(2 [0107] Field multiplication of two elements α,b∈GF(2 [0108] of degree less than 2m−1, i.e., deg(c [0109] Note that c [0110] The first step of a squaring operation, which is a special case of polynomial multiplication, does not require a full multiplication since all mixed terms c [0111] Division
[0112] α, b∈GF(2 [0113] Field multiplication and squaring operations require reduction by an irreducible polynomial M. Rather than computing a full polynomial division, reduction can be done by executing a sequence of polynomial multiplications and additions based on the congruency [0114] Note that u and k can be arbitrary polynomials over GF(2) and do not have to be in reduced canonical representation. A special case of Equation (1), used for reduction, is [0115] Reduction of a product c [0116] Using (2), the following congruency is obvious [0117] Given that deg(c [0118] until [0119] the reduced result c=c [0120] it follows that a better upper bound for deg(c [0121] The minimum number of iterations i is given by
[0122] To enable efficient implementations, M is often chosen to be either a trinomial M [0123] Choosing M such that
[0124] apparently limits the number of reduction iterations to two. This is the case for all irreducible polynomials recommended by NIST and SECG. Furthermore, the multiplications c [0125] Now that some of the underlying mathematics has been presented, the additional details can be presented about the arithmetic units. The ALU [0126] As described above, the multiplication function takes two elements X(t) and Y(t) as inputs and generates an element P(t) of GF(2 [0127]FIG. 14 illustrates polynomial multiplication using a serial shift-and-add algorithm. It takes m iterations to calculate the product. In the example shown in FIG. 14, m=4. The polynomials used in the example are X(t)=t
[0128] Referring to the pseudocode above and FIG. 14, first Z is initialized to 0. An iteration includes testing the LSB of X and, if the bit is a “1”, adding Y to the right-shifted version of Z. An iteration ends with shifting X to the right. For polynomial fields, the addition operation is defined as a bit-wise XOR of the operands. Considering a hardware implementation, one iteration typically corresponds to one clock cycle. The result is Z(t)=t [0129]FIG. 15 illustrates how modular reduction of the multiplication result Z is performed. First Z
[0130] While the reduction can be implemented with the help of a general-purpose multiplier that calculates Z [0131] To efficiently support ECC in hardware, GF(2 [0132] The serial shift-and-add algorithms take as many iterations as there are bits in the operands. The number of iterations can be reduced by considering more than one bit per iteration. The number of bits examined during an iteration is the digit size d. This way, the number of iterations needed is reduced to ┌m/d┐. [0133]FIG. 17 shows a block diagram of a circuit performing modular multiplication with digit size d. The circuit includes registers [0134] The pseudo code for operation of the modular multiplier shown in FIG. 17 is as follows:
[0135] The for loop takes n/d cycles while the modular reduction step takes 1 cycle. It is assumed that n is a multiple of d. Looking at an iteration, the d low-order bits of X are examined, and for each bit set to 1 the correspondingly shifted version of Y is added to Z. After n/d clock cycles, register Z contains the multiplication result. Once Z is calculated, a reduction is performed by the reduction logic [0136] Referring now to FIG. 18, the execution time of the multiplier shown in FIG. 17 can also be improved by considering the field size. If the field degree m is significantly smaller than n such that the high order digits contain only Os, there is no need to execute all n/d iterations. That is, the number of iterations required to calculate the product is ceiling m/d(┌m/d┐). The modular multiplier circuit illustrated in FIG. 18 saves iterations if m<n−d. The pseudo code for the operation of the modular multiplier illustrated in FIG. 18 is as follows:
[0137] Applied to the modular multiplier circuit illustrated in FIG. 17, three iterations are needed for m=113, 131, 163 and four iterations are needed for m=193, 233, and 239. Note that an additional shift operation is needed if less than n/d iterations are performed. The illustrated modular multiplier circuit in FIG. 18 implements the extra shift operation utilizing multiplexer [0138]FIG. 24 illustrates how the partial product X[d−1 . . . 0]*Y is calculated during a multiplication iteration of the modular multiplier illustrated in FIG. 18, which is obtained by applying the shift-and-add algorithm. [0139] Another exemplary multiplier circuit [0140]FIG. 20 illustrates an embodiment of an LSD modular multiplier for field degrees<n. Similar to FIG. 18, the modular multiplier circuit is optimized such that only ceiling (m/d) iterations rather than n/d iterations are required. In FIG. 20, the optimization only requires the finite state machine controlling the multiplier to stop after ceiling (m/d) iterations. There is no additional multiplexer needed as was the case for the modular multiplier circuit illustrated in FIG. 18. Given two polynomials of field degree m, the irreducible polynomial M, digit size d, and operand size n, the multiplication result Z using a least significant digit (LSD) multiplier such as shown in FIG. 20, is obtained according to the following pseudo code:
[0141] In each iteration, the following computation steps are performed: (i) the least significant digit (LSD) of X is multiplied with Y; (ii) X is shifted to the right by d bits; (iii) Y is shifted to the left by d bits and subsequently reduced. After ┌m/d┐ iterations have been performed, one more step is needed to obtain the result P by reducing the accumulated value Z′. Note that two reduction circuits [0142] The least significant digit (LSD) multiplier is attractive since it limits the size of the register used to accumulate the partial product to n+d bits. Thus, this type of multiplier is particularly interesting for small d's in that the size of the register is approximately n bits rather than approximately 2n bits. The following equation describes the underlying math for LSD multiplication for d=1.
[0143]FIG. 21 illustrates another embodiment of an LSD modular multiplier circuit. In the illustrated embodiment, a single reduction circuit, 2101 is used to calculate (shift_left (Y,d) mod M) and (Z′ mod M). Calculating the reductions at different times allows the single reduction circuit to be used for both reductions. [0144]FIG. 22 illustrates another embodiment of a modular multiplier circuit in which the final reduction is moved into the cycle performing a multiplication iteration. While this makes the critical path longer, it reduces the overall execution time to ceiling (m/d) cycles. The pseudo code illustrating operation of the circuit in FIG. 22 is as follows:
[0145] In one embodiment, the modular multiplier can handle different field degrees as part of a hardware accelerator. The multiplier width in one embodiment is n=256 and the hardwired reduction circuit can handle in an exemplary embodiment field degrees of m=113, 131, 163, 193, 233 and 239. Since the irreducible polynomial M is different for each field, the hardwired reduction circuit supporting those field degrees is more complicated than the reduction circuit [0146] In one embodiment, the LSD multiplier supports different field degrees m≦n. FIG. 23 shows a block diagram of an LSD multiplier, similar to the one shown in FIG. 20, that supports hardwired reduction for multiple named curves of field degrees 163, 193, and 233. As this implementation shows, all three computation steps of an iteration and, in particular, the multiplication and the reduction operations can be performed in parallel. Thus, the synchronous circuit shown requires ┌m/d┐+1 clock cycles to perform the modular multiplication. The embodiment illustrated in FIG. 23 utilizes two reduction circuits [0147] Note that in the digit serial multiplication illustrated, the execution time of the multiplier can be decreased by increasing the digit size d. As d is increased, the number of resources needed to implement the d×n partial product generator increases. In one embodiment, with n=256 and d=64, it is the 64×256 partial product generator that uses the majority of the chip resources and, consequently, determines the size of the implementation. [0148]FIG. 25 illustrates an alternative way to calculate partial products by applying the Karatsuba algorithm. While the Karatsuba method was originally proposed for integer multiplication, it is here applied to binary polynomials. While traditional long-word arithmetic requires the calculation of four partial products X [0149] Similar to the shift-and-add algorithm, the Karatsuba algorithm can be serialized as well. The serialization can be done in different ways as shown in the embodiments illustrated in FIGS. 26 and 27. FIG. 26 illustrates use of the Karatsuba algorithm to calculate the 64 bit by 256 bit multiplication shown, e.g., in FIGS. 17 and 18. In the example, X[d−1 . . . 0] and Y[n−1 . . . 0] are being multiplied where n=256 and d=64. Each partial product X [0150] While FIG. 26 shows how to first serialize and then apply the Karatsuba algorithm, FIGS. 27A and 27B illustrate how to reverse the order of these operations. As illustrated in FIG. 27A, the 256 bit by 256 bit multiplication is recursively split up into smaller operand sizes up to the point where, in FIG. 27B, 32 bit by 32 bit multiplications need to be performed. In the example illustrated, there are 27 of these multiplications which are calculated by serially performing four 8 bit by 32 bit multiplications. The serial shift and add multiplier illustrated in FIG. 28 can be used to perform the 27 32 bit by 32 bit multiplications. [0151] The Karatsuba algorithm is attractive for use in the polynomial multiplications described herein because it reduces the bit complexity from order n [0152] The Karatsuba algorithm may be applied to the LSD multipliers shown, e.g., in FIG. 20 or to other of the MSD multipliers, described further herein. That is, the techniques illustrated in FIGS. 26 and 27A and [0153] In the case of squaring, both polynomial multiplication and reduction can typically be combined and executed in a single clock cycle. Since squaring only requires the insertion of zeros, no intermediate result c [0154] For implementations of a small number of fields GF(2 [0155] While various embodiments shown above, e.g., in FIGS. [0156] An alternative approach is shown in FIG. 32 in which an operand a is multiplied by an operand b. It is assumed that deg(a) and deg(b) are both less than m. First, operand a is multiplied by the constant factor t
[0157] all require one MULNR each, while the multiplication r :=r [0158] Rather than using the technique described in FIG. 32, the utilization of partial reduction eliminates the two multiplications used for operand alignment described above. First, the mathematical basis for partial reduction will be provided. Then, various embodiments of techniques to implement partial reduction will be provided. [0159] Polynomials c∈GF(2 [0160] For a multiplication c [0161] The result c=c [0162] A second, mathematically identical way to compute subsequent polynomials c [0163] NIST and SECG recommend curves over fields GF(2 [0164] Using partial reduction eliminates the two multiplications used for operand aligmnent shown in FIG. 32. This is illustrated in FIG. 33 for operand polynomials a′, b′, deg(a′)<n, deg(b′)<n and an arbitrary irreducible polynomial M, deg(M)<n. Reduction of a partially reduced polynomial c′, deg(c′)<n to a congruent c≡c′ mod M, deg(c)<m can be performed with the approach of FIG. 32 by setting a=c′ and omitting the second step (r :=r [0165] Note that hardwired reducers such as shown in FIG. 19 only work for named curves. One alternative to reduction is to add a path in FIG. 19 to bypass the reducer, i.e. the product of the polynomial multiplication Z=X*Y can be written back into two result registers. Then the reduction operations can be implemented as shown in FIG. 32 using instructions ADD and MULNR. [0166] To better support partial reduction, dedicated multiplier circuitry can be used. FIG. 34 shows an n×n-bit multiplier with data paths customized for partial reduction. Initially, the operand registers [0167] Partial reduction can also be employed in the implementation of a compact and complete ECC software library. Besides high performance, a design goal for a software library may be to support arbitrary curves that are not known at implementation time. In one embodiment, in addition to hardcoded implementations for known curves, a generic point multiplication routine using partial reduction is provided. Calls to the library can be dispatched according to whether or not an accelerated implementation exists. Furthermore, partial reduction can be useful in verifying implementations optimized for known curves. On today's general purpose processors, polynomial multiplication is commonly implemented through a sequence of shift and XOR instructions. Partial reduction allows for operating on word-sized operands without having to extract bit fields. For example, to implement point multiplication over GF(2 [0168] Further advantages of implementations using partial reduction include a small memory footprint and code that can be easily verified. [0169] As illustrated in FIG. 35, another embodiment provides optimized multiplication performance for named curves and at the same time support for generic curves. The LSD multiplier as shown in FIG. 23 was modified as shown in FIG. 35 to allow for operating on generic curves in addition to named curves in that the d×n partial product generator P (
[0170] Using partial reduction to reduce to the register size n rather than to the field degree m simplifies the design of a generic LSD multiplier significantly. With partial reduction, the operand bits that go into the multiplier do not depend on the field degree m. As the pseudo code illustrates, partial reduction takes the d most significant bits of Y and Z, respectively, and multiplies them with M′=(M−t [0171] Note that the multiplier in FIG. 35 always takes ┌n/d┐ iterations since partial reduction reduces the multiplication result P to n bits. For smaller field degrees, the LSD multiplier shown in FIG. 35 could be optimized such that it only executes ┌n/d┐ iterations and reduces the result to ┌n/d┐*d bits. Doing this requires multiplexers to extract the MSD of Y and the MSD of P+Z. However, increasing the fan-out of Y may be undesirable in certain embodiments as it is a critical timing path in at least some embodiments. [0172] As there is only one partial product generator [0173]FIG. 36 shows the state diagram for the generic LSD multiplier. Separate control flows are given for named and generic curves. [0174] For named curves, the source operands are loaded from the SBUS in states S [0175] Looking at generic curves, the state diagram is specified as follows as shown in FIG. 36. The source operands are loaded from the SBUS in states S [0176] In one embodiment, the modified LSD multiplier illustrated in FIG. 35 takes a total of seven cycles to perform a modular multiplication for named curves with m≦192, eight cycles for named curves with 192<m≦255, and 13 cycles for generic curves with m≦255. The cycle counts include two cycles needed for loading the source operands and one cycle needed for storing the destination operand. Similar to named curves, the cycle count could be optimized for generic curves. Doing this requires an additional multiplexer connected to Y that increases the length of the critical path. [0177] In one embodiment some restrictions are imposed on the irreducible polynomial. More particularly, when reducing shift_left(Y) and P, it was assumed that the partially reduced result of the multiplications Y[n−1 . . . n−d]*(M−t [0178] Given a partial product generator that multiplies d×n bits and m,k, as described in the paragraph describing equations 3-9 above, the number of reduction iterations i is
[0179] For limiting partial reduction to a single iteration it follows that d≦m−k. For d=64 this limits irreducible polynomials P to those with m−k>64. All polynomials recommended by NIST and SECG satisfy this condition. In another embodiment, polynomials with m−k<64 are accommodated by allowing for multiple reduction iterations. However, in such an embodiment, multiplier performance may be significantly reduced. [0180] In another embodiment, shown in FIG. 37, a most significant digit (MSD) multiplier is utilized rather than an LSD multiplier, which provides a performance improvement over the LSD multiplier. The corresponding pseudo code looks as follows:
[0181] The MSD multiplier performs the following three computation steps in parallel: (i) the most significant digit (MSD) of X is multiplied with Y ; (ii) X is shifted to the left by d bits; (iii) Z is shifted to the left by d bits, added to P, and subsequently reduced. FIG. 37 shows a block diagram of an MSD multiplier for named curves of field degrees 163, 193, and 233. It takes ┌n/d┐+1 clock cycles to perform the modular multiplication, that is, the number of multiplication steps executed depends on m. This optimization requires that the registers X and Y are loaded with the operands shifted to the left by d*└(n−m)/d┘ bits. In one embodiment, only a shift by d bits is supported. That is, for n=256 and d=64, the modular multiplication takes five clock cycles for m>192 and four clock cycles for m<192. Note that the operands are left aligned by shifters [0182] Comparing embodiments using the LSD multiplier and embodiments using the MSD multiplier, notice that each embodiment has its advantages. The LSD multiplier is simpler with respect to optimizing the number of multiplication steps based on the field degree as the operands do not have to be shifted. On the other hand, the MSD multiplier simplifies reduction in that it only requires one reduction circuit. Looking at a multiplication iteration, the LSD multiplier reduces Y, while the MSD multiplier reduces P. After all iterations have been performed, a final reduction of P is needed. Thus, the LSD multiplier requires a reducer in two places while MSD requires a reducer in one place. [0183] Referring now to FIG. 38, a generic MSD multiplier is illustrated that can handle both named and generic curves. The pseudo code for performing modular multiplication on generic curves looks as follows:
[0184] Similar to the generic LSD multiplier, there is one partial product generator that is alternately used to perform a multiplication step and a reduction step. Compared with the LSD multiplier illustrated in FIG. 35, the pipelining of the MSD multiplier works out more efficiently saving one clock cycle. Rather then reordering the multiplication and reduction steps to remove data dependencies, the computation can begin with executing two multiplication steps before the first reduction step is executed. That is, P and Z are computed in the order {P [0185]FIG. 39 shows the state diagram for the generic MSD multiplier. Separate control flows are given for named and generic curves. The state diagram for named curves looks as follows. The source operands are loaded from the SBUS in states S [0186] Looking at generic curves, the state diagram is specified as follows. The source operands are loaded from the SBUS in states S [0187] Table 1 below gives the cycle counts for the generic LSD multiplier and the generic MSD multiplier. The cycle counts include the time needed to load and store the operands. As pointed out, the more efficient pipelining of the MSD multiplier saves one cycle when operating on generic curves. Note that it is assumed that it takes a single multiplication to execute a reduction step. As explained previously, this is true for d≦m−k.
[0188] While various multipliers have been described, a variety of multipliers may be utilized to perform modular multiplication. Note that while the examples of modular multiplication may be based on binary polynomial fields, the examples of modular multiplication provided herein may also apply to integer fields. [0189] The ECC processor implements a modular divider based on an algorithm described in application serial no. 10/091,962 filed Mar. 5, 2002 which is incorporated herein by reference, that has similarities to Euclid's GCD algorithm. The divider is illustrated in FIG. 40 and includes four 256-bit registers A, B, U, and V and a fifth register holding the irreducible polynomial M. It can compute division for arbitrary irreducible polynomials M and field degrees up to m=255. [0190] Initially, A is loaded with the divisor X, B with the irreducible polynomial M, U with the dividend Y , and V with 0. Throughout the division, the following invariants are maintained: [0191] Through repeated additions and divisions by t, A and B are gradually reduced to 1 such that U (respectively V) contains the quotient Y/X mod M. Note that a polynomial is divisible by t if it is even, i.e. the least significant bit of the corresponding bit string is 0. Division by t can be efficiently implemented as a shift right operation. Two counters, CA and CB, are used to test for termination of the algorithm. For named curves, CB is initialized with the field degree m and CA with m−1. For generic curves, CB is initialized with the register size n and CA with n−1. CA and CB represent the upper bound for the order of A and B. This is due to the fact that the order of A+B is never greater than the order of A if CA>CB and never greater than the order of B if CA≦CB. The following pseudo code describes the operation of the divider:
[0192] A modular division can be computed in a maximum of 2m clock cycles for named curves and in a maximum of 2n clock cycles for generic curves. Note that the divider fully reduces the result to the field degree. In particular, divisions by 1 can be used to reduce a polynomial of degree less than n to a polynomial of degree less than m. [0193] Reduction of a partially reduced polynomial c′, deg(c′)<n to a congruent polynomial c≡c′ mod M, deg(c)<m can be performed utilizing the approach illustrated in FIG. 32. [0194] Referring again to FIG. 34, the final reduction of c′ could also be performed with the multiplier illustrated in FIG. 34 by setting a′=c′ and b′=t [0195] Another option to reduce the partially reduced polynomial c′, deg(c′)<n to a congruent polynomial c≡c′ mod M, deg(c)<m is to use the divider circuit illustrated in FIG. 40. The divider circuit can be initialized with register A=1, B=M, U=c′, V=0, CA=n−1 CB=n. The division is then performed as described above. [0196] A point multiplication kP using Montgomery's algorithm can be computed with └log
[0197] For all following bits of k, with k [0198] Similarly, for k [0199] The computation of the four equations shown above for X [0200] Data dependencies may be detected in different ways. The assembler checks for dependencies that would prevent overlapped instruction execution. In those cases, the programmer needs to resolve the dependencies by reordering operands or inserting NOP instructions. With respect to parallel instruction execution, the control unit examines dependencies and decides whether instructions can be executed in parallel or not. [0201] The code fragment in FIG. 41 shows no data dependencies for any MUL/SQR or MUL/ADD instruction sequence. Hence, for named curves, all MUL/SQR and MUL/ADD sequences are executed in parallel. Furthermore, since there are no data dependencies between subsequent arithmetic instructions, instruction execution can be overlapped, thus, saving one cycle per instruction. [0202] Code execution looks different for generic curves as illustrated. In this case, all MUL/SQR sequences have to be executed sequentially as SQR instructions are now executed as MUL instructions. However, there still is one SQR/ADD sequence and one MUL/ADD sequence left that can be executed in parallel. Similar to the previous trace, overlapped execution saves one cycle per instruction. [0203] Assembly code for point multiplication on an exemplary crypto accelerator (CRAC) described herein based on Montgomery Scalar Multiplication is shown in Appendix A. The same code base is used for named and generic curves. Curve- dependent branches (BNC instructions) control the execution based on whether a named or generic curve is used. [0204] The embodiments described above are presented as examples and are subject to other variations in structure and implementation within the capabilities of one reasonably skilled in the art. For examples, while certain embodiments show particular named curves, the embodiments described above using named curves may use any or all of the named curves with field degrees of 113, 131, 163,193, 233, or 239 or may use named curves of different field degrees in addition to or instead of the named curves identified herein. The details provided above should be interpreted as illustrative and not as limiting. Variations and modifications of the embodiments disclosed herein, may be made based on the description set forth herein, without departing from the scope and spirit of the invention as set forth in the following claims. Referenced by
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