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Publication numberUS20030221966 A1
Publication typeApplication
Application numberUS 10/284,953
Publication dateDec 4, 2003
Filing dateOct 31, 2002
Priority dateMay 31, 2002
Also published asDE10223957A1, DE10223957B4
Publication number10284953, 284953, US 2003/0221966 A1, US 2003/221966 A1, US 20030221966 A1, US 20030221966A1, US 2003221966 A1, US 2003221966A1, US-A1-20030221966, US-A1-2003221966, US2003/0221966A1, US2003/221966A1, US20030221966 A1, US20030221966A1, US2003221966 A1, US2003221966A1
InventorsMatthias Bonkass, Axel Preusse, Markus Nopper
Original AssigneeMatthias Bonkass, Axel Preusse, Markus Nopper
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
A patterned dielectric layer including small diameter vias and large diameter trenches, a pulse reverse electroplating sequence with a two-component chemistry is modified to substantially fill the vias, while in a subsequent DC
US 20030221966 A1
Abstract
In a new method of electroplating metal onto a patterned dielectric layer including small diameter vias and large diameter trenches, a pulse reverse electroplating sequence with a two-component chemistry is modified to substantially fill the vias, while in a subsequent DC deposition the bulk material is deposited to completely fill the large diameter trenches. Thus, good control quality compared to conventional three-component chemistry electroplating is obtained while the superior characteristics of a metal layer deposited by a two-component chemistry are preserved. The method is particularly advantageous in electroplating copper.
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Claims(13)
What is claimed:
1. A method of depositing a metal over a substrate including a patterned dielectric layer with a small diameter opening and a large diameter opening by electroplating, the method comprising:
providing an electrolyte bath including a suppressor additive and an accelerator additive;
positioning the substrate in said electrolyte bath;
generating a plurality of forward current pulses, each with a first time period, and a plurality of reverse current pulses, each with a second time period, in said electrolyte bath to deposit metal on said substrate, wherein said forward current pulses and said reverse current pulses are provided in an alternating fashion; and
generating a DC current for a predefined third time period in said electrolyte bath to deposit metal on said substrate, wherein the first and second time periods are less than the third time period.
2. The method of claim 1, wherein at least one of a height of the forward current pulse, a height of the reverse current pulse, the first time period, the second time period and a time interval for applying the current pulses and the reverse current pulses is selected to completely fill at least the small diameter opening.
3. The method of claim 1, wherein at least one of a height of the DC current and the third time period is controlled to adjust the final thickness of the metal layer deposited on and in the patterned dielectric layer.
4. The method of claim 1, wherein said forward current pulses and said reverse current pulses are applied for a predefined time interval and a ratio of said time interval and said third time period is controlled to adjust a quality of said metal layer.
5. The method of claim 1, further comprising annealing said substrate to adjust a grain size in said metal layer.
6. The method of claim 1, wherein said electrolyte bath includes copper ions.
7. A method of electroplating a metal over a substrate including a surface portion with a patterned dielectric layer including a small diameter opening and a large diameter opening, the method comprising:
providing an electrolyte bath including a two-component additive chemistry for non-conformal filling in said small diameter opening;
positioning the substrate in the electrolyte bath;
performing a pulse reverse plating sequence to substantially fill the small diameter opening; and
applying a DC current of a predefined height for a predefined time period to completely fill the large diameter opening.
8. The method of claim 7, wherein a time period of the pulse reverse plating sequence is controlled to adjust a surface quality of the final metal layer.
9. The method of claim 7, wherein at least one of said predefined height and said predefined time period of the DC current is selected to adjust a surface quality of the final metal layer.
10. The method of claim 7, wherein a height and a duration of forward current pulses and reverse current pulses in said pulse reverse plating sequence is selected to substantially completely fill the small diameter opening.
11. The method of claim 7, wherein at least one of a height and a duration of forward current pulses and reverse current pulses in said pulse reverse plating sequence, a time period of said pulse reverse plating sequence, the predefined height of said DC current, and the predefined time period of the DC current is controlled to adjust a surface quality of the final metal layer.
12. The method of claim 7, wherein said metal comprises copper.
13. The method of claim 7, further comprising annealing said substrate to adjust a grain size in said metal layer.
Description
BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention generally relates to the fabrication of integrated circuits, and, more particularly, to the formation of metallization layers, wherein a metal is deposited over a patterned dielectric layer and excess metal is subsequently removed by chemical mechanical polishing (CMP).

[0003] 2. Description of the Related Art

[0004] In every new generation of integrated circuits, device features are further reduced, whereas the complexity of the circuits steadily increases. Reduced feature sizes not only require sophisticated photolithography methods and advanced etch techniques to appropriately pattern the circuit elements, but also places an ever-increasing demand on deposition techniques. Presently, the minimum feature sizes approach 0.1 μm, which allows the fabrication of fast-switching transistor elements covering only a minimum of chip area. However, as a consequence of the reduced feature sizes, the available floor space for the required metal interconnects decreases, while the number of necessary interconnections between the individual circuit elements increases. A decreasing cross-sectional area of metal connects makes it necessary to replace the commonly used aluminum by a metal that allows a higher current density at a reduced electrical resistivity to obtain reliable chip interconnects with high quality. In this respect, copper has proven to be a promising candidate due to its advantages such as low resistivity, high reliability, high heat conductivity, relatively low cost and a crystalline structure that may be controlled to obtain relatively large grain sizes. Furthermore, copper shows a significantly higher resistance against electromigration and therefore allows higher current densities while the resistivity is low, thus allowing the introduction of lower supply voltages.

[0005] Despite the many advantages of copper compared to aluminum, semiconductor manufacturers in the past have been reluctant to introduce copper into the manufacturing sequence for several reasons. One major issue in processing copper in a semiconductor line is the copper's capability of readily diffusing in silicon and silicon dioxide at moderate temperatures. Copper diffused into silicon may lead to a significant increase in the leakage current of transistor elements, since copper acts as a deep-level trap in the silicon band-gap. Moreover, copper diffused into silicon dioxide may compromise the insulating properties of silicon dioxide and may lead to higher leakage currents between adjacent metal lines, or may even form shorts between neighboring metal lines. Thus, great care must be taken to avoid any contamination of silicon wafers with copper during the entire process sequence.

[0006] A further issue arises from the fact that copper may not be effectively applied in greater amounts by deposition methods, such as physical vapor deposition (PVD) and chemical vapor deposition (CVD), which are well-known and well-established techniques in depositing other materials, such as aluminum. Accordingly, copper is now commonly applied by a wet process, such as electroplating, which provides, compared to electroless plating, the advantages of a higher deposition rate and a less complex electrolyte bath. Although at a first glance electroplating seems to be a relatively simple and well-established deposition method, the demand of reliably filling high aspect ratio openings with dimensions of 0.1 μm, as well as wide trenches having a lateral extension on the order of micrometers, renders electroplating of copper, as well as other metals that may be used in metallization layers, a highly complex deposition method, in particular as subsequent process steps, such as chemical mechanical polishing and any metrology processes, directly depend on the quality of the electroplating process.

[0007] With reference to FIGS. 1a-1 f, a typical process sequence for manufacturing a metallization layer will now be described. According to FIG. 1a, a semiconductor device 100 comprises a substrate 101 including circuit elements, such as transistors, resistors, capacitors, and the like, which, for the sake of simplicity, are not depicted in FIG. 1a. A first dielectric layer 102 is formed above the substrate 101 and is separated by an etch stop layer 103 from a second dielectric layer 104. For example, the first and second dielectric layers 102, 104 may be comprised of silicon dioxide, whereas the etch stop layer 103 may comprise silicon nitride. In the second dielectric layer 104, an opening 105 is formed having the dimensions of a via to be formed subsequently in the first dielectric layer 102. The methods for forming the semiconductor device 100 as depicted in FIG. 1a are well-established in the art and a description thereof will be omitted.

[0008]FIG. 1b schematically shows the semiconductor device 100 with the via 105 formed in the first dielectric layer 102 and an overlying trench 106 formed in the second dielectric layer 104. Moreover, a wide trench 107 is formed in the second dielectric layer 104 that has a significantly larger lateral dimension than the via 105 and the trench 106. The inner surfaces of the via 105, the trench 106 and the wide trench 107 are covered by a barrier diffusion layer 108 followed by a copper seed layer 109.

[0009] The via 105, the trench 106 and the wide trench 107 are formed by anisotropic etching, wherein the etch process stops at the etch stop layer 103, which has been removed at the via 105 in a preceding, separate etch step. Commonly, the barrier diffusion layer 108, such as tantalum nitride or titanium nitride, is formed by chemical vapor deposition followed by a sputter deposition process to form the seed layer 109 that acts as a current distribution layer for the subsequent electroplating process.

[0010]FIG. 1c depicts the semiconductor device 100 with a copper layer 110 filled in the via 105, the trench 106 and the wide trench 107, wherein the copper layer 110 exhibits an extra thickness so as to completely fill the wide trench 107 over which the topology of the copper layer 110 is significantly determined by the underlying wide trench 107.

[0011] After depositing the copper layer 110, an anneal step may be performed to establish a required crystallinity in the copper layer 110. Thereafter, the semiconductor device 100 is subjected to a CMP process to remove the excess copper and to provide for a planar surface that allows the formation of a further metallization layer. Since CMP is in itself a highly complex process, the result of the polishing process strongly depends on the properties of the copper layer 110. For example, a minor non-uniformity of the copper layer 110 at different positions on the wafer may already lead to an intolerable variation in the resulting copper lines, since, while in a region with an increased copper thickness the excess metal is still being removed and thus the underlying trenches are still intact, in a region with a reduced copper thickness, the underlying copper trench, for example trench 106, may already be exposed and subjected to undesired polishing, resulting in a loss of copper within the trench, which may compromise its reliability. Hence, any non-uniformities obtained by the copper plating procedure may place a great burden on the CMP process, thereby jeopardizing the quality of the metal lines.

[0012]FIG. 1d schematically shows the semiconductor structure 100 after completion of the CMP process, wherein the excess copper, as well as portions of the diffusion barrier layer 108 at the exposed surface areas of the second dielectric layer 104, are removed. Thus, metal lines 106 and 107 are obtained that are electrically insulated from each other. Usually, a further dielectric diffusion barrier layer is deposited on the semiconductor substrate 100 after completion of the metallization sequence so as to passivate the exposed copper surface of the metal lines 106 and 107 and avoid out-diffusion of copper into overlying dielectrics and metals.

[0013] For reliable metal interconnects, it is not only important to deposit the copper as uniformly as possible over the entire surface of a 200 or even 300 mm diameter substrate, but it is also important to reliably fill vias having an aspect ratio of approximately 10:1 without any voids or defects. As a consequence, it is essential to deposit the copper in a highly non-conformal manner, as will be explained with reference to FIGS. 1e and 1 f, which schematically show the via 105 in enlarged form.

[0014] In FIG. 1e, filling in of the via 105 is depicted in an initial state, wherein copper has accumulated with a certain thickness at horizontal portions 111, i.e., at the bottom of the trench 106 (see FIG. 1d), whereby the thickness at a corner 112 shows a maximum copper accumulation. At the bottom corners 113, the copper amount is minimal, whereas in the center of the via bottom 114, an increased amount of copper is accumulated; however, in a significantly less amount than on the horizontal portion 111 and the corner 112. The copper distribution in FIG. 1e corresponds to a “normal” copper electroplating deposition in which a DC current is supplied to the electrolyte bath containing an acidic copper-containing solution. The discrepancy in the copper distribution is mainly caused by the varying density of copper ions at the various regions, since, in regions of sub-micron dimensions, the number of available copper ions is substantially determined by diffusion rather than by electrolyte flow. As the number of copper ions per unit area is substantially the same, the number of ions arriving at the top side of the via 105 have to be distributed over the entire (large) inner surface, thereby leading to a significantly reduced deposition rate compared to the horizontal portion 111. Moreover, at an initial state, the deposition rate may also depend on the electrical resistance of the underlying barrier diffusion layer and copper seed layer 108, 109, so that any non-uniformity of these layers also translates into a non-uniformity of the bulk copper layer 110. Typically, sputter depositing of the copper seed layer into the high-aspect ratio via 105 may result in a layer thickness profile that is quite similar to the profile of the initial copper layer as shown in FIG. 1e and thus enhances the undesired deposition behavior. The right-hand side of FIG. 1e shows a void 115 that may be formed during an electroplating process due to the increased copper accumulation at the corners 112. Since the void 115 significantly reduces the current capability of the via 105, a corresponding circuit element may show a decreased reliability or may be prone to premature failure due to the increased current density in the remaining copper of the via 105.

[0015] Accordingly, great efforts have been made to establish an electroplating technique that allows a highly non-conformal deposition of a metal, such as copper, in which the via 105 is filled substantially from bottom to top.

[0016]FIG. 1f schematically shows an initial state of a desired copper fill-in method in which the via 105 is substantially filled from the bottom also with an enhanced deposition rate at the sidewalls 116 of the via 105. Contrary to the “normal” deposition, the deposition rate at the horizontal portions 111 and the corners 112 is significantly reduced, so that finally a completely-filled via covered by a substantially uniform “excess” layer 110 is formed, as shown on the right-hand side of FIG. 1f.

[0017] It has been recognized that a fill-in behavior as described in FIG. 1f may be obtained by controlling the deposition kinetics within the via 105 and on the horizontal portions and edges 111 and 112. This may be achieved by introducing additives into the electrolyte bath to influence the rate of copper ions that deposit on the respective locations. For example, an organic agent of relatively large, slow-diffusing molecules, such as polyethylene glycol, may be added to the electrolyte and preferentially absorbed on the flat surface and corner portions 111 and 112. Hence, contact of copper ions at these regions is reduced and thus the deposition rate is decreased. A correspondingly-acting agent is also often referred to as a “suppressor.” On the other hand, a further additive, including smaller and faster-diffusion molecules, may be used that preferentially absorbs within the via 105 and enhances the deposition rate by offsetting the effects of the suppressor additive. A corresponding additive is often also referred to as an “accelerator.” In addition to using an accelerator and a suppressor, it has been found that a simple DC deposition, i.e., deposition by supplying a substantially constant DC current, may not result in the required deposition behavior despite the employment of accelerator and suppressor additives. Instead, the so-called pulse reverse deposition has become a preferred operation mode in depositing copper. In the pulse reverse deposition technique, current pulses of alternating polarity are applied to the electrolyte bath so as to deposit copper on the substrate during forward current pulses and to release a certain amount of copper during reverse current pulses, thereby improving the fill capability of the electroplating process. Typically, the current and/or the duration of the forward current pulses is equal or higher than that of the reverse pulses to achieve a net deposition effect.

[0018]FIG. 2a qualitatively shows a current time diagram for carrying out a copper deposition with an electrolyte bath including a suppressor and an accelerator additive, which allows one to substantially completely fill the vias 105 and trenches 106 as well as the wide trenches 107 depicted in FIG. 1. Although the quality of the copper deposited into the vias and trenches in view of the number of defects and voids is strongly affected by the composition of the electrolyte bath and thus requires a thorough control of the additives contained therein, the provision of an accelerator and a suppressor is now well-established and well-controllable so that a long-term stability of such a two-component chemistry electrolyte bath may be readily ensured.

[0019] The electroplating recipe including an electrolyte bath with a suppressor and an accelerator with a pulse reverse operation mode, although allowing the reliable filling of high-aspect ratio vias, exhibits one major drawback in view of filling wide trenches 107.

[0020]FIG. 2b schematically shows a typical result of electroplating copper with the above-explained recipe, wherein prominent protrusions 120 are formed at the edges of the wide trench 107. The formation of the protrusions 120 may be avoided if a large amount of “overdeposition” is carried out, wherein, however, the surface roughness of the copper layer 110 significantly increases and wherein, most importantly, the subsequent CMP process has to remove a large amount of excess metal, thereby increasing process time and thus the amount of copper erosion formed during the CMP process.

[0021] Thus, it has become standard practice to modify the electrolyte bath by adding a further agent, a so-called leveler, in an extremely minute dose to slow down the copper deposition rate at the edges of the wide trench 107. When using such a three-component chemistry in the electrolyte bath, i.e., an electrolyte bath including a suppressor, an accelerator and a leveler, to obtain the required deposition behavior, it is essential to reliably control the low concentration of the leveler within tightly-set tolerances to provide for stable electroplating conditions. Measuring a low concentration of a leveler in a concentrated suppressor and accelerator environment is, however, quite complex and requires great effort in terms of time and equipment.

[0022] In view of the above-mentioned problems, it would therefore be highly desirable to provide an electroplating process that minimizes the burden on the subsequent CMP process while allowing simple control of the electrolyte conditions.

SUMMARY OF THE INVENTION

[0023] Generally, the present invention is directed to a method that provides an electroplating sequence with a two-component chemistry in the electrolyte bath, wherein the requirements for different products (i.e., different layouts), different technologies (i.e., different minimal feature sizes), and different metal layers (i.e., varying size and density of metal lines) may readily be fulfilled while at the same time the burden on post-electroplating processes is relaxed. To this end, the present invention proposes to use an additional DC electroplating step after the pulse reverse fill-in step of small vias and trenches is substantially completed.

[0024] According to one illustrative embodiment of the present invention, a method of electroplating a metal on a substrate including a dielectric layer having a small-diameter and a large diameter opening comprises providing a two-component electrolyte bath including a suppressor and an accelerator and positioning the substrate in the electrolyte bath. Next, a pulse reverse sequence is performed to substantially fill the small-diameter opening. Subsequently, a DC deposition is carried out to completely fill the large diameter of the opening.

[0025] According to a further illustrative embodiment of the present invention, a method of depositing a metal over a substrate including a patterned dielectric layer with a small diameter opening and a large diameter opening by electroplating comprises providing an electrolyte bath including a suppressor additive and an accelerator additive and positioning the substrate in the electrolyte bath. The method further includes generating a plurality of forward current pulses, each with a first time period, and a plurality of reverse current pulses, each with a second time period, in the electrolyte bath to deposit metal on the substrate during the forward current pulses, wherein the forward current pulses and the reverse current pulses are provided in an alternating fashion. Additionally, a DC current is generated for a predefined third time period in the electrolyte bath to deposit metal on the substrate, wherein the first and second time periods are less than the third time period.

BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The invention may be understood by reference to the following description taken in conjunction with the accompanying drawings, in which like reference numerals identify like elements, and in which:

[0027]FIGS. 1a-1 f schematically show cross-sectional views of a semiconductor device during various manufacturing stages when receiving a copper metallization layer;

[0028]FIG. 2a schematically shows a diagram depicting current vs. time in a typical pulse reverse electroplating process;

[0029]FIG. 2b schematically shows the result of electroplating copper over a wide trench using a two-component chemistry and the conventional pulse reverse recipe;

[0030]FIG. 3 schematically depicts an idealized electroplating reactor in an oversimplified manner;

[0031]FIG. 4a schematically depicts a diagram illustrating a current waveform vs. time according to one illustrative embodiment of the present invention; and

[0032]FIG. 4b schematically shows the result of one illustrative embodiment of the two-component chemistry in connection with a deposition current waveform as shown in FIG. 3a.

[0033] While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific embodiments is not intended to limit the invention to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.

DETAILED DESCRIPTION OF THE INVENTION

[0034] Illustrative embodiments of the invention are described below. In the interest of clarity, not all features of an actual implementation are described in this specification. It will of course be appreciated that in the development of any such actual embodiment, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art having the benefit of this disclosure.

[0035] The present invention is based on the inventor's finding that the superior characteristics of a two-component chemistry electrolyte bath, in terms of controllability and surface quality of the final metal layer, compared to a three-component chemistry may be maintained, while at the same time a reliable and substantially conformal filling of wide trenches, having a lateral extension on the order of magnitude of one to several micrometers, is ensured in that a final DC step is carried out to deposit a “cap” layer required for completely filling the wide trenches. Due to the relatively simple composition of the electrolyte bath, reproducible electroplating conditions may be maintained during the processing of a large number of substrates. Moreover, by varying the duration and/or the amount of current applied during the DC cap layer deposition, the ratio of the thickness of the cap layer, i.e., the portion of the metal deposited during the final DC deposition step, to the total layer thickness may readily be adjusted, allowing the adaptation of the process recipe to different metals, different layouts of the metallization layers, to different minimal feature sizes and to a varying density of metal lines on different metallization layers.

[0036] With reference to FIGS. 3 and 4, illustrative embodiments of the present invention will now be described, wherein for the sake of simplicity, it is also partially referred to FIG. 1, and to the same reference numerals are used for corresponding parts in FIGS. 3 and 4 and the detailed description of those corresponding parts is omitted.

[0037] Moreover, in the following illustrative embodiments, copper is referred to as the metal to be deposited by electroplating since copper, as previously noted, is expected to be mainly used in future sophisticated integrated circuits, and the embodiments described hereinafter are particularly advantageous in electroplating copper. The present invention is, however, also applicable to other metals and metal compounds and metal alloys.

[0038]FIG. 3 shows a schematic and oversimplified view of an electroplating reactor 300 which may be used to describe the present invention. In general, the result of an electroplating process depends on the kinetics within the electroplating reactor. However, the basic concept of the present invention may be applied to any type of electroplating reactor presently used in the fabrication of integrated circuits, including copper metallization layer. Thus, it should be borne in mind that the electroplating reactor 300, in reality, comprises additional means for obtaining the desired electrolyte flow within the reactor, such as shields, supply lines, means for rotating the wafer and/or shields, and the like. In one embodiment, an electroplating reactor may be used that is available from Semitool Inc. under the name LT210C™. It should be noted that the present invention may be applied to any electroplating reactor.

[0039] The reactor 300 additionally comprises an electrode 301 coupled to a power source 302, which in the present invention is adapted to provide an output current with a predefined magnitude, duration and polarity. Opposite to the electrode 301, a substrate 100 is positioned, such as the semiconductor device 100 of FIG. 1, including the patterned dielectric layers 102 and 104 with the barrier diffusion layer 108 and the copper seed layer 109. The reactor 300 further comprises an electrolyte 303, the main component of which is a copper sulfate acidified with sulfuric acid. The electrolyte 303 further comprises a suppressor additive 304 and an accelerator additive 305, a concentration of which may readily be controlled, for example by polarization measurements on a copper layer deposited on a previously processed test or product substrate. The copper layer includes a certain minute amount of the suppressor 304 and the accelerator 305 that modifies the optical characteristics of the copper layer when reflecting an incident light beam. Such two-component electrolyte baths are readily available, for example from Shiply under the name of Nanoplate. The accelerator may be comprised of propane sulfonic acid. A typical concentration of the accelerator is in the range of approximately 1-10 ml/l. The suppressor may be comprised of a polyalkylene glycol type polymer. A typical concentration of the suppressor is in the range of approximately 1-30 ml/l. It should be noted that the present invention is not restricted to a specific electrolyte and may be practiced with any electrolytes currently available or electrolytes that will be available in the future.

[0040] Upon application of voltage pulses of alternating polarity including a first polarity, i.e., a polarity that makes the electrode 301 the anode, and the substrate 100 the cathode, a current is induced, leading to a migration of the copper ions to the surface of the substrate 100. Thereby, the voltage pulse of the first polarity is selected such that a substantially constant current of a predefined height is generated, which will be referred to as forward current pulse. The corresponding migration of copper ions is indicated by arrows 306. Each voltage pulse of the first polarity is followed by a voltage pulse of a second polarity, i.e., of a polarity that makes the electrode 301 the cathode and the substrate 100 the anode, which is applied and adjusted so as to generate a substantially constant current with a predefined height (in the reverse direction) as indicated by arrows 307. The current generated by the voltage of the second polarity will be referred to as reverse current pulse. As previously noted, the alternating application of forward current pulses and reverse current pulses leads to a reliable deposition of copper within small diameter openings such as the via 105 and the trench 106 in the dielectric layers 104 and 102.

[0041] The height of the forward current pulses and the reverse current pulses depends on the size of the substrate 100 and the structure of the patterned dielectric layer 104 and 102. Typically, a current of approximately 1 to 20 ampere for a substrate surface including vias and trenches down to 0.1 μm and below is selected for the forward current pulses. The corresponding reverse pulses may range from approximately 1-20 ampere. Typically, a duration T1 of a single forward current pulse may range from approximately 1-100 seconds. The duration T2 of a single reverse current pulse may be in the range of approximately 1-100 seconds. During the application of alternating forward pulses and the reverse pulses for a predefined time period TS, herein also referred to as pulse reverse sequence, small diameter openings, i.e., vias 105 and possibly the overlying trenches 106 are substantially filled, whereas the substantially conformal deposition over the wide trench 107 requires an additional deposition step to reliably completely fill the wide trench 107. Contrary to the conventional process recipe, in which the pulse height, the duration (T1, T2) of the individual pulses and the time period TS are selected so as to obtain the required over-deposition, resulting, in the present example of a two-component chemistry, in additional protrusions 120, as shown in FIG. 2, in the present invention the over-deposition is accomplished by a final DC current deposition step, whereby the height of the current and/or the duration of the DC current is selected to obtain the required amount of over-deposition to reliably fill the trench 107.

[0042]FIG. 4a qualitatively depicts the time dependency of the currents applied to the substrate 100. During the pulse reverse sequence, copper is deposited on the substrate 100 in the forward pulses of duration T1 corresponding to T1 and the magnitude of the current. During the reverse current pulses, a certain degree of redistribution of the copper takes place depending on the period T2 and the magnitude of the (reverse) current. After the pulse reverse sequence TS, the DC step is carried out for a time period T3 with a predefined height of the DC current. It should be noted that, in principle, the current time integral of the various current pulses is a measure of the amount of copper deposited on the substrate 100. Thus, in some embodiments requiring a high throughput, the magnitude of the current during the DC step may be raised to obtain a desired high overall deposition rate, thereby slightly compromising the surface quality of the copper layer 110. Moreover, by appropriately selecting TS and/or T3 or the ratio of TS to T3, i.e., by selecting the ratio of the “via fill-in” capability to the (DC) “conformal deposition” capability, the final surface quality of the copper layer, and thus the “burden” for the subsequent CMP, may be adjusted.

[0043]FIG. 4b schematically shows the structure 100 after applying a process sequence as shown in FIG. 4a, wherein the copper layer 110 is deposited over the wide trench 107 with a thickness that ensures complete filling of the wide trench 107 after the subsequent CMP process. Moreover, any protrusions, such as those shown in FIG. 2b, may reliably be avoided, thus generating a high quality copper layer 110 without the need of providing a highly complex three-component electrolyte bath including a leveler.

[0044] After deposition of the copper, the structure 100 may be annealed to adjust the final grain size of the copper layer 110, which significantly affects the characteristics of the completed copper lines with respect to electromigration.

[0045] The quality of the surface of the copper layer 110 may be estimated on the basis of the amount of light reflected from an incident light beam, since a rougher surface will scatter a larger portion of the incident light beam and thus reduce the intensity of the reflected light beam. A plurality of semiconductor substrates 100 with a copper layer 110 formed according to a typical standard two-component plating recipe and a plurality of semiconductor substrates 100 having a copper layer formed according to the embodiments as described above have been examined and revealed that the reflectivity of the substrates processed according to the standard process recipe exhibit a reflectivity of approximately 3%, whereas the substrates processed according to the present invention exhibit a reflectivity of approximately 32%. Thus, the significant improvement in reflectivity according to the present invention not only indicates a smoother surface of the copper layer 110 but also allows one to more reliably obtain optical measurement results from correspondingly processed substrates. For example, the CMP process is commonly monitored optically to detect the end of the polishing process, wherein a light beam is directed to the surface while being polished and the intensity of the reflected light beam is detected. Consequently, an increased initial reflectivity provides for less noisy and thus more reliable endpoint signals. In particular, the endpoint detection signal of the substrates processed according to the present invention, exhibits a substantially flat plateau with a sharp falling edge that indicates the end of the process more precisely, whereas the substrates processed according to the standard reverse pulse recipe exhibit a varying plateau with a noisy signal at the falling edge of the endpoint detection signal. Thus, the endpoint of the CMP process will be determined more precisely by applying the process recipe according to the present invention. Moreover, as already indicated by the high reflectivity of the copper layer 110, the CMP process of the copper layer 110 is less critical and also requires significantly less polish time. Examinations performed on the above prepared substrates revealed a polish time reduction of approximately 23%. The reduction of polish time also significantly contributes to an improvement in copper surface quality due to reduced formation of copper erosion and discoloration. A further advantageous effect of the present invention regards dishing and erosion occurring during the chemical mechanical polishing of the copper layer 110. Dishing of copper trenches, i.e., the faster removal of copper compared to the neighboring dielectric, and erosion, i.e., removal of dielectric material, compared to the initial layer thickness, is also relaxed due to the reduced polish time, the improved detection of the endpoint and the high surface quality of the deposited copper. Moreover, the defect level is remarkably reduced.

[0046] Thus, the present invention allows an improved process and controllability compared to standard three-component chemistry without compromising the superior characteristics of reverse pulse electroplating using a two-component chemistry, such as improved resistance against electromigration of the completed copper lines due to an increased grain size of the copper, reliable filling of small diameter openings, such as vias in the range of 0.1 μm, and of large diameter openings, such as wide trenches on the order of several micrometers.

[0047] The particular embodiments disclosed above are illustrative only, as the invention may be modified and practiced in different but equivalent manners apparent to those skilled in the art having the benefit of the teachings herein. For example, the process steps set forth above may be performed in a different order. Furthermore, no limitations are intended to the details of construction or design herein shown, other than as described in the claims below. It is therefore evident that the particular embodiments disclosed above may be altered or modified and all such variations are considered within the scope and spirit of the invention. Accordingly, the protection sought herein is as set forth in the claims below.

Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US6883153 *Jan 10, 2003Apr 19, 2005Intel CorporationMinimization of microelectronic interconnect thickness variations
US6958247 *Sep 19, 2003Oct 25, 2005Advanced Micro Devices, Inc.Method of electroplating copper over a patterned dielectric layer to enhance process uniformity of a subsequent CMP process
US8506788 *Sep 11, 2012Aug 13, 2013Rohm And Haas Electronic Materials LlcLeveler compounds
US20090114542 *Nov 6, 2007May 7, 2009Spansion LlcProcess of forming an electronic device including depositing a conductive layer over a seed layer
US20130001088 *Sep 11, 2012Jan 3, 2013Rohm And Haas Electronic Materials LlcLeveler compounds
WO2006032346A1 *Aug 30, 2005Mar 30, 2006Atotech Deutschland GmbhGalvanic process for filling through-holes with metals, in particular of printed circuit boards with copper
Classifications
U.S. Classification205/103, 205/150, 205/118
International ClassificationC25D3/38, C25D5/18, H05K3/42, C25D7/12
Cooperative ClassificationC25D3/38, H05K3/423, C25D5/18, C25D7/123
European ClassificationC25D3/38, C25D5/18, C25D7/12
Legal Events
DateCodeEventDescription
Oct 31, 2002ASAssignment
Owner name: ADVANCED MICRO DEVICES, INC., TEXAS
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:PREUSSE, AXEL;BONKASS, MARTHIAS;NOPPER, MARKUS;REEL/FRAME:013454/0677
Effective date: 20020705