BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to the fabrication of integrated circuits, and, more particularly, to the formation of metallization layers, wherein a metal is deposited over a patterned dielectric layer and excess metal is subsequently removed by chemical mechanical polishing (CMP).
2. Description of the Related Art
In every new generation of integrated circuits, device features are further reduced, whereas the complexity of the circuits steadily increases. Reduced feature sizes not only require sophisticated photolithography methods and advanced etch techniques to appropriately pattern the circuit elements, but also places an ever-increasing demand on deposition techniques. Presently, the minimum feature sizes approach 0.1 μm, which allows the fabrication of fast-switching transistor elements covering only a minimum of chip area. However, as a consequence of the reduced feature sizes, the available floor space for the required metal interconnects decreases, while the number of necessary interconnections between the individual circuit elements increases. A decreasing cross-sectional area of metal connects makes it necessary to replace the commonly used aluminum by a metal that allows a higher current density at a reduced electrical resistivity to obtain reliable chip interconnects with high quality. In this respect, copper has proven to be a promising candidate due to its advantages such as low resistivity, high reliability, high heat conductivity, relatively low cost and a crystalline structure that may be controlled to obtain relatively large grain sizes. Furthermore, copper shows a significantly higher resistance against electromigration and therefore allows higher current densities while the resistivity is low, thus allowing the introduction of lower supply voltages.
Despite the many advantages of copper compared to aluminum, semiconductor manufacturers in the past have been reluctant to introduce copper into the manufacturing sequence for several reasons. One major issue in processing copper in a semiconductor line is the copper's capability of readily diffusing in silicon and silicon dioxide at moderate temperatures. Copper diffused into silicon may lead to a significant increase in the leakage current of transistor elements, since copper acts as a deep-level trap in the silicon band-gap. Moreover, copper diffused into silicon dioxide may compromise the insulating properties of silicon dioxide and may lead to higher leakage currents between adjacent metal lines, or may even form shorts between neighboring metal lines. Thus, great care must be taken to avoid any contamination of silicon wafers with copper during the entire process sequence.
A further issue arises from the fact that copper may not be effectively applied in greater amounts by deposition methods, such as physical vapor deposition (PVD) and chemical vapor deposition (CVD), which are well-known and well-established techniques in depositing other materials, such as aluminum. Accordingly, copper is now commonly applied by a wet process, such as electroplating, which provides, compared to electroless plating, the advantages of a higher deposition rate and a less complex electrolyte bath. Although at a first glance electroplating seems to be a relatively simple and well-established deposition method, the demand of reliably filling high aspect ratio openings with dimensions of 0.1 μm, as well as wide trenches having a lateral extension on the order of micrometers, renders electroplating of copper, as well as other metals that may be used in metallization layers, a highly complex deposition method, in particular as subsequent process steps, such as chemical mechanical polishing and any metrology processes, directly depend on the quality of the electroplating process.
With reference to FIGS. 1a-1 f, a typical process sequence for manufacturing a metallization layer will now be described. According to FIG. 1a, a semiconductor device 100 comprises a substrate 101 including circuit elements, such as transistors, resistors, capacitors, and the like, which, for the sake of simplicity, are not depicted in FIG. 1a. A first dielectric layer 102 is formed above the substrate 101 and is separated by an etch stop layer 103 from a second dielectric layer 104. For example, the first and second dielectric layers 102, 104 may be comprised of silicon dioxide, whereas the etch stop layer 103 may comprise silicon nitride. In the second dielectric layer 104, an opening 105 is formed having the dimensions of a via to be formed subsequently in the first dielectric layer 102. The methods for forming the semiconductor device 100 as depicted in FIG. 1a are well-established in the art and a description thereof will be omitted.
FIG. 1b schematically shows the semiconductor device 100 with the via 105 formed in the first dielectric layer 102 and an overlying trench 106 formed in the second dielectric layer 104. Moreover, a wide trench 107 is formed in the second dielectric layer 104 that has a significantly larger lateral dimension than the via 105 and the trench 106. The inner surfaces of the via 105, the trench 106 and the wide trench 107 are covered by a barrier diffusion layer 108 followed by a copper seed layer 109.
The via 105, the trench 106 and the wide trench 107 are formed by anisotropic etching, wherein the etch process stops at the etch stop layer 103, which has been removed at the via 105 in a preceding, separate etch step. Commonly, the barrier diffusion layer 108, such as tantalum nitride or titanium nitride, is formed by chemical vapor deposition followed by a sputter deposition process to form the seed layer 109 that acts as a current distribution layer for the subsequent electroplating process.
FIG. 1c depicts the semiconductor device 100 with a copper layer 110 filled in the via 105, the trench 106 and the wide trench 107, wherein the copper layer 110 exhibits an extra thickness so as to completely fill the wide trench 107 over which the topology of the copper layer 110 is significantly determined by the underlying wide trench 107.
After depositing the copper layer 110, an anneal step may be performed to establish a required crystallinity in the copper layer 110. Thereafter, the semiconductor device 100 is subjected to a CMP process to remove the excess copper and to provide for a planar surface that allows the formation of a further metallization layer. Since CMP is in itself a highly complex process, the result of the polishing process strongly depends on the properties of the copper layer 110. For example, a minor non-uniformity of the copper layer 110 at different positions on the wafer may already lead to an intolerable variation in the resulting copper lines, since, while in a region with an increased copper thickness the excess metal is still being removed and thus the underlying trenches are still intact, in a region with a reduced copper thickness, the underlying copper trench, for example trench 106, may already be exposed and subjected to undesired polishing, resulting in a loss of copper within the trench, which may compromise its reliability. Hence, any non-uniformities obtained by the copper plating procedure may place a great burden on the CMP process, thereby jeopardizing the quality of the metal lines.
FIG. 1d schematically shows the semiconductor structure 100 after completion of the CMP process, wherein the excess copper, as well as portions of the diffusion barrier layer 108 at the exposed surface areas of the second dielectric layer 104, are removed. Thus, metal lines 106 and 107 are obtained that are electrically insulated from each other. Usually, a further dielectric diffusion barrier layer is deposited on the semiconductor substrate 100 after completion of the metallization sequence so as to passivate the exposed copper surface of the metal lines 106 and 107 and avoid out-diffusion of copper into overlying dielectrics and metals.
For reliable metal interconnects, it is not only important to deposit the copper as uniformly as possible over the entire surface of a 200 or even 300 mm diameter substrate, but it is also important to reliably fill vias having an aspect ratio of approximately 10:1 without any voids or defects. As a consequence, it is essential to deposit the copper in a highly non-conformal manner, as will be explained with reference to FIGS. 1e and 1 f, which schematically show the via 105 in enlarged form.
In FIG. 1e, filling in of the via 105 is depicted in an initial state, wherein copper has accumulated with a certain thickness at horizontal portions 111, i.e., at the bottom of the trench 106 (see FIG. 1d), whereby the thickness at a corner 112 shows a maximum copper accumulation. At the bottom corners 113, the copper amount is minimal, whereas in the center of the via bottom 114, an increased amount of copper is accumulated; however, in a significantly less amount than on the horizontal portion 111 and the corner 112. The copper distribution in FIG. 1e corresponds to a “normal” copper electroplating deposition in which a DC current is supplied to the electrolyte bath containing an acidic copper-containing solution. The discrepancy in the copper distribution is mainly caused by the varying density of copper ions at the various regions, since, in regions of sub-micron dimensions, the number of available copper ions is substantially determined by diffusion rather than by electrolyte flow. As the number of copper ions per unit area is substantially the same, the number of ions arriving at the top side of the via 105 have to be distributed over the entire (large) inner surface, thereby leading to a significantly reduced deposition rate compared to the horizontal portion 111. Moreover, at an initial state, the deposition rate may also depend on the electrical resistance of the underlying barrier diffusion layer and copper seed layer 108, 109, so that any non-uniformity of these layers also translates into a non-uniformity of the bulk copper layer 110. Typically, sputter depositing of the copper seed layer into the high-aspect ratio via 105 may result in a layer thickness profile that is quite similar to the profile of the initial copper layer as shown in FIG. 1e and thus enhances the undesired deposition behavior. The right-hand side of FIG. 1e shows a void 115 that may be formed during an electroplating process due to the increased copper accumulation at the corners 112. Since the void 115 significantly reduces the current capability of the via 105, a corresponding circuit element may show a decreased reliability or may be prone to premature failure due to the increased current density in the remaining copper of the via 105.
Accordingly, great efforts have been made to establish an electroplating technique that allows a highly non-conformal deposition of a metal, such as copper, in which the via 105 is filled substantially from bottom to top.
FIG. 1f schematically shows an initial state of a desired copper fill-in method in which the via 105 is substantially filled from the bottom also with an enhanced deposition rate at the sidewalls 116 of the via 105. Contrary to the “normal” deposition, the deposition rate at the horizontal portions 111 and the corners 112 is significantly reduced, so that finally a completely-filled via covered by a substantially uniform “excess” layer 110 is formed, as shown on the right-hand side of FIG. 1f.
It has been recognized that a fill-in behavior as described in FIG. 1f may be obtained by controlling the deposition kinetics within the via 105 and on the horizontal portions and edges 111 and 112. This may be achieved by introducing additives into the electrolyte bath to influence the rate of copper ions that deposit on the respective locations. For example, an organic agent of relatively large, slow-diffusing molecules, such as polyethylene glycol, may be added to the electrolyte and preferentially absorbed on the flat surface and corner portions 111 and 112. Hence, contact of copper ions at these regions is reduced and thus the deposition rate is decreased. A correspondingly-acting agent is also often referred to as a “suppressor.” On the other hand, a further additive, including smaller and faster-diffusion molecules, may be used that preferentially absorbs within the via 105 and enhances the deposition rate by offsetting the effects of the suppressor additive. A corresponding additive is often also referred to as an “accelerator.” In addition to using an accelerator and a suppressor, it has been found that a simple DC deposition, i.e., deposition by supplying a substantially constant DC current, may not result in the required deposition behavior despite the employment of accelerator and suppressor additives. Instead, the so-called pulse reverse deposition has become a preferred operation mode in depositing copper. In the pulse reverse deposition technique, current pulses of alternating polarity are applied to the electrolyte bath so as to deposit copper on the substrate during forward current pulses and to release a certain amount of copper during reverse current pulses, thereby improving the fill capability of the electroplating process. Typically, the current and/or the duration of the forward current pulses is equal or higher than that of the reverse pulses to achieve a net deposition effect.
FIG. 2a qualitatively shows a current time diagram for carrying out a copper deposition with an electrolyte bath including a suppressor and an accelerator additive, which allows one to substantially completely fill the vias 105 and trenches 106 as well as the wide trenches 107 depicted in FIG. 1. Although the quality of the copper deposited into the vias and trenches in view of the number of defects and voids is strongly affected by the composition of the electrolyte bath and thus requires a thorough control of the additives contained therein, the provision of an accelerator and a suppressor is now well-established and well-controllable so that a long-term stability of such a two-component chemistry electrolyte bath may be readily ensured.
The electroplating recipe including an electrolyte bath with a suppressor and an accelerator with a pulse reverse operation mode, although allowing the reliable filling of high-aspect ratio vias, exhibits one major drawback in view of filling wide trenches 107.
FIG. 2b schematically shows a typical result of electroplating copper with the above-explained recipe, wherein prominent protrusions 120 are formed at the edges of the wide trench 107. The formation of the protrusions 120 may be avoided if a large amount of “overdeposition” is carried out, wherein, however, the surface roughness of the copper layer 110 significantly increases and wherein, most importantly, the subsequent CMP process has to remove a large amount of excess metal, thereby increasing process time and thus the amount of copper erosion formed during the CMP process.
Thus, it has become standard practice to modify the electrolyte bath by adding a further agent, a so-called leveler, in an extremely minute dose to slow down the copper deposition rate at the edges of the wide trench 107. When using such a three-component chemistry in the electrolyte bath, i.e., an electrolyte bath including a suppressor, an accelerator and a leveler, to obtain the required deposition behavior, it is essential to reliably control the low concentration of the leveler within tightly-set tolerances to provide for stable electroplating conditions. Measuring a low concentration of a leveler in a concentrated suppressor and accelerator environment is, however, quite complex and requires great effort in terms of time and equipment.
In view of the above-mentioned problems, it would therefore be highly desirable to provide an electroplating process that minimizes the burden on the subsequent CMP process while allowing simple control of the electrolyte conditions.
SUMMARY OF THE INVENTION
Generally, the present invention is directed to a method that provides an electroplating sequence with a two-component chemistry in the electrolyte bath, wherein the requirements for different products (i.e., different layouts), different technologies (i.e., different minimal feature sizes), and different metal layers (i.e., varying size and density of metal lines) may readily be fulfilled while at the same time the burden on post-electroplating processes is relaxed. To this end, the present invention proposes to use an additional DC electroplating step after the pulse reverse fill-in step of small vias and trenches is substantially completed.
According to one illustrative embodiment of the present invention, a method of electroplating a metal on a substrate including a dielectric layer having a small-diameter and a large diameter opening comprises providing a two-component electrolyte bath including a suppressor and an accelerator and positioning the substrate in the electrolyte bath. Next, a pulse reverse sequence is performed to substantially fill the small-diameter opening. Subsequently, a DC deposition is carried out to completely fill the large diameter of the opening.
According to a further illustrative embodiment of the present invention, a method of depositing a metal over a substrate including a patterned dielectric layer with a small diameter opening and a large diameter opening by electroplating comprises providing an electrolyte bath including a suppressor additive and an accelerator additive and positioning the substrate in the electrolyte bath. The method further includes generating a plurality of forward current pulses, each with a first time period, and a plurality of reverse current pulses, each with a second time period, in the electrolyte bath to deposit metal on the substrate during the forward current pulses, wherein the forward current pulses and the reverse current pulses are provided in an alternating fashion. Additionally, a DC current is generated for a predefined third time period in the electrolyte bath to deposit metal on the substrate, wherein the first and second time periods are less than the third time period.