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Publication numberUS20030232487 A1
Publication typeApplication
Application numberUS 10/458,471
Publication dateDec 18, 2003
Filing dateJun 9, 2003
Priority dateJun 11, 2002
Also published asUS7265029, US7888235, US20040235268, US20070269960, WO2003105219A1
Publication number10458471, 458471, US 2003/0232487 A1, US 2003/232487 A1, US 20030232487 A1, US 20030232487A1, US 2003232487 A1, US 2003232487A1, US-A1-20030232487, US-A1-2003232487, US2003/0232487A1, US2003/232487A1, US20030232487 A1, US20030232487A1, US2003232487 A1, US2003232487A1
InventorsFabrice Letertre, Bruno Ghyselen, Olivier Rayssac
Original AssigneeFabrice Letertre, Bruno Ghyselen, Olivier Rayssac
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Fabrication of substrates with a useful layer of monocrystalline semiconductor material
US 20030232487 A1
Abstract
The invention concerns a method of fabricating a substrate that includes a layer of at least one semiconductor material on a support. The substrate is fabricated by affixing a nucleation layer to an intermediate support substrate to form a barrier layer against diffusion of atoms from the intermediate support substrate, depositing at least one layer of semiconductor material to the nucleation layer; attaching a target substrate to the deposited semiconductor material to form a final support assembly, and removing the intermediate support substrate and the nucleation layer from the final support assembly. The final support assembly includes the target substrate, the deposited semiconductor material, the nucleation layer and the intermediate support substrate so that, after removal of the intermediate support substrate, a substrate is provided that includes at least one layer of at least one semiconductor material on a support.
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Claims(25)
What is claimed is:
1. A method for fabricating a substrate comprising at least one layer of at least one semiconductor material on a support, which comprises:
providing an intermediate support that includes a nucleation layer as a barrier against diffusion of atoms from the intermediate support;
providing at least one layer of a semiconductor material upon the nucleation layer;
bonding a target substrate to the deposited semiconductor material to form a final support assembly comprising the target substrate, the deposited semiconductor material, the nucleation layer and the intermediate support; and
processing the final support assembly to chemically remove at least one of the intermediate support or the nucleation layer, thus providing a substrate comprising the at least one layer of semiconductor material on the target substrate.
2. The method according to claim 1, wherein the intermediate support is removed by etching.
3. The method according to claim 2, wherein the intermediate support is etched with an acid solution.
4. The method according to claim 1, wherein the intermediate support is provided by:
implanting atomic species into at least a portion of a source substrate to define the nucleation layer, wherein a main concentration of implanted atomic species defines a detachment zone;
attaching the source substrate implanted with the atomic species to at least a portion of the intermediate support to form a source substrate-intermediate support assembly;
treating the assembly to detach the intermediate support and nucleation layer.
5. The method according to claim 2, wherein the treating step comprises applying thermal or mechanical stress to the assembly to detach the intermediate support and nucleation layer.
6. The method according to claim 1, which further comprises affixing the nucleation layer to the intermediate support by molecular bonding.
7. The method according to claim 6, wherein at least one bonding layer is applied to at least one of the nucleation layer or the intermediate support prior to affixing the nucleation layer to the intermediate support.
8. The method according to claim 1, wherein the intermediate support is selected from the group consisting of: silicon, gallium arsenide, zinc oxide, lithium gallium oxide and lithium aluminum oxide.
9. The method according to claim 1, wherein the semiconductor material comprises at least one mono or poly-metallic nitride.
10. The method according to claim 9, wherein the semiconductor material layer comprises gallium nitride, and further wherein the nucleation layer is selected from the group consisting of silicon carbide, gallium nitride and sapphire.
11. The method according to claim 1, wherein the final support includes a reflective coating.
12. The method according to claim 1, wherein the layer of semiconductor material is epitaxially deposited on the nucleation layer.
13. The method according to claim 1, which further comprises providing a second barrier layer between the nucleation layer and the intermediate support.
14. A method for fabricating a substrate comprising a layer of semiconductor material on a support, wherein the method comprises:
providing an intermediate support that includes a barrier layer that is resistant to diffusing elements derived from dissociation of the intermediate support, providing a nucleation layer affixed to the barrier layer;
depositing upon the nucleation layer at least one layer of semiconductor material by epitaxial growth;
bonding the at least one layer of semiconductor material to a final support such that a first surface of the semiconductor material is attached to the intermediate support and a second surface of the semiconductor material is attached to the final support; and
chemically removing the intermediate support from the semiconductor material to obtain the at least one layer of semiconductor material on the final support.
15. The method according to claim 14, wherein the intermediate support is removed by etching.
16. The method according to claim 15, wherein the intermediate support is etched with an acid solution.
17. The method according to claim 14, wherein method further comprises:
implanting the atomic species into at least a portion of a source substrate to define at least one of the barrier layer or the nucleation layer, wherein a main concentration of the implanted atomic species defines a detachment zone;
bonding the source substrate implanted with the atomic species to at least a portion of the intermediate support to form a source substrate-intermediate support assembly; and
treating the assembly to detach the intermediate support and barrier or nucleation layer.
18. The method according to claim 17, wherein the treating step comprises applying a thermal or mechanical stress at the detachment zone.
19. The method according to claim 14, wherein the barrier layer is first applied to the intermediate support and the nucleation layer is then applied to the barrier layer.
20. The method according to claim 19, wherein a layer of adhesive is applied to at least one of the surfaces of the barrier layer or the nucleation layer to define a bonding layer.
21. The method according to claim 14, wherein at least one of the barrier layer or the nucleation layer is formed by a deposition technique.
22. The method according to claim 14, wherein the intermediate support is selected from the group consisting of silicon, gallium arsenide, zinc oxide, lithium gallium oxide and lithium aluminum oxide.
23. The method according to claim 14, wherein the semiconductor layer comprises at least one mono or poly-metallic nitride.
24. The method according to claim 14, wherein the semiconductor material layer is comprises gallium nitride, and further wherein the nucleation layer is selected from the group consisting of silicon carbide, gallium nitride and sapphire.
25. The method according to claim 14, wherein the final support includes a reflective coating.
Description
FIELD OF INVENTION

[0001] The present invention relates to a method of fabricating a support carrying a substrate comprising a layer of monocrystalline semiconductor material, especially a wide band gap material, and in particular a mono or poly-metallic nitride substrate, such as gallium nitride (GaN) or aluminum nitride (AlN), or a diamond substrate.

BACKGROUND OF THE INVENTION

[0002] Semiconductor technology based on the use of GaN, AlN, and compounds thereof as semiconductor material, currently suffer from a lack of large-sized bulk substrates of such materials.

[0003] The most widely known technique for producing a bulk GaN substrate consists of depositing the GaN on a substrate by a process known as hetero-epitaxy.

[0004] In order to produce a substrate having good crystal quality, the substrate material and the epitaxial monocrystal to be deposited thereon, must have little lattice mismatch. Additionally, the thermal expansion coefficient of both the substrate material and the epitaxial monocrystal must be relatively similar, because the high temperatures involved in hetero-epitaxy is known to sometimes cause dissociation and diffusion of elements of the substrate to the epitaxial layer. Thirdly, the substrate material must be mechanically and chemically stable at high temperatures so as to obtain good crystal quality. Naturally, qualities such as surface condition and crystal quality of the starting substrate are also important factors.

[0005] Currently, sapphire and silicon carbide (SiC), are commonly used as the substrate material. However, sapphire and silicon carbide are far from being optimal substrate material due to their lattice parameters and their expansion coefficients.

[0006] Another common practice is growing layers of GaN on substrates such as zirconium oxide (ZnO), lithium gallium oxide (LiGaO2), lithium aluminum oxide (LiAlO2) (See “Growth of III-Nitrides on ZnO, LiGaO2 and LiAlO2 substrates”, Mackenzie et al., J. Electrochem. Soc., vol. 145, NO 7, July 1998, p. 2581) or of neodymium gallium oxide (NdGaO3) (see “GaN bulk substrates for GaN based LEDs and LDs”, Oda et al., Phys. Stat. Sol., (a) 180, 51 (2000). Although these substrate materials are often selected for their small lattice mismatch and their similar coefficient of expansion with GaN, they suffer from having poor chemical stability under high temperatures as compared to sapphire or silicon carbide. For example, when the oxide substrates are exposed to high temperatures, dissociation of the metal and/or the oxygen occurs and such dissociated metal and/or oxygen diffuses to the epitaxial layer. As described in Impurity contamination of GaN epitaxial films from the sapphire, SiC, and ZnO substrates, Popovici et al., Appl. Phys. Lett., 71(23), Dec. 8, 1997, and incorporated herein, contamination of the epitaxial layer by zinc and oxygen from a ZnO substrate compromises the quality and purity of the epitaxial layer.

[0007] Furthermore, once the layer or layers intended to form the substrate have been formed, in the majority of cases the support on which growth has been carried out has to be removed, which necessitates either chemical attack of said support and thus its loss even if it is produced from an expensive material, thereby increasing the cost of the process, or by rupture between the layers formed by epitaxial growth and said support, which can be difficult to control and/or can necessitate particular dispositions which complicate the method or make it more expensive.

[0008] More generally, it has been proven that, for the purpose of temporary support removal, chip manufacturers mostly prefer an etching technique rather than a rupturing technique. This is mainly because, in the semiconductor industry, etching techniques have been mastered for years and most often do not require any additional investment while rupture techniques are more difficult to control or require significant capital investment, thus adding complexity to the process.

[0009] In parallel, an etching approach would be valuable only if the material of the support is relatively inexpensive, but such inexpensive materials, such as gallium Arsenide GaAs, introduce additional drawbacks.

[0010] In this regard, the article “Preparation of large freestanding GaN substrates by Hydride Vapor Phase Epitaxy using GaAs as a starting substrate”, Motoki et al., Jpn. J. Appl. Phys., Vol. 41 (2001), p. 140-143, proposes using a gallium arsenide GaAs substrate on which to grow GaN by hetero-epitaxy. However, when heated to the high temperatures involved in epitaxy, GaAs undergoes surface dissociation, which causes arsenic to evaporate, which can contaminate the GaN monocrystal.

[0011] The present invention now seeks to overcome these disadvantages.

SUMMARY OF THE INVENTION

[0012] The invention relates to a method for fabricating a substrate comprising at least one layer of at least one semiconductor material on a support. This method comprises providing an intermediate support that includes as a barrier against diffusion of atoms from the intermediate support; providing at least one layer of a semiconductor material upon the nucleation layer; bonding a target substrate to the deposited semiconductor material to form a final support assembly comprising the target substrate, the deposited semiconductor material, the nucleation layer and the intermediate support; and processing the final support assembly to chemically remove at least one of the intermediate support or the nucleation layer, thus providing a substrate comprising at least one layer of semiconductor material on the target substrate.

[0013] Preferably, the layer(s) of semiconductor material may be epitaxially deposited on the barrier layer and is a monocrystalline material. Also, the intermediate support may conveniently be removed by etching, such as with an acid solution. If necessary, a barrier layer can be provided between the nucleation layer and the intermediate support.

[0014] The intermediate support is advantageously provided by implanting atomic species into at least a portion of a source substrate to define the nucleation layer, wherein a main concentration of implanted atomic species defines a detachment zone; attaching the source substrate implanted with the atomic species to at least a portion of the intermediate support to form a source substrate-intermediate support assembly; and treating the assembly to detach the intermediate support and nucleation layer.

[0015] The nucleation layer is preferably affixed to the intermediate support by molecular bonding, and the treating step preferably comprises applying thermal or mechanical stress to the assembly to detach the intermediate support and nucleation layer. Also, a least one bonding layer is applied to at least one of the nucleation layer or the intermediate support prior to affixing the nucleation layer to the intermediate support.

[0016] The invention also relates to a method for fabricating a substrate that includes a layer of semiconductor material on a support. This method comprises providing an intermediate support that includes a barrier layer that is resistant to diffusing elements derived from dissociation of the intermediate support; depositing upon the barrier layer at least one layer of semiconductor material by epitaxial growth; bonding the at least one layer of semiconductor material to a final support such that a first surface of the semiconductor material is attached to the intermediate support and a second surface of the semiconductor material is attached to the final support; and chemically removing the intermediate support from the semiconductor material by etching such as with an acid solution to obtain the at least one layer of semiconductor material on the final support.

[0017] As described above, the intermediate support can include a nucleation layer affixed to the barrier layer. If so, the method can further comprise implanting the atomic species into at least a portion of a source substrate to define at least one of the barrier layer or the nucleation layer, wherein a main concentration of the implanted atomic species defines a detachment zone; bonding the source substrate implanted with the atomic species to at least a portion of the intermediate support to form a source substrate-intermediate support assembly; and treating the assembly to detach the intermediate support and barrier or nucleation layer.

[0018] The barrier layer may be first applied to the intermediate support and the nucleation layer is then applied to the barrier layer. Also, a layer of adhesive can be applied to at least one of the surfaces of the barrier layer or the nucleation layer to define a bonding layer. Generally, at least one of the barrier layer or the nucleation layer is formed by a deposition technique.

[0019] In these methods, the intermediate support is selected from the group consisting of silicon, gallium arsenide, zinc oxide, lithium gallium oxide and lithium aluminum oxide, and the semiconductor layer comprises at least one mono or poly-metallic nitride. A preferred semiconductor material layer is gallium nitride, and the nucleation layer can be selected from the group consisting of silicon carbide, gallium nitride and sapphire. If desired, the final support can include a reflective coating.

BRIEF DESCRIPTION OF THE DRAWING FIGURES

[0020] Other aspects, aims and advantages of the present invention become clear from the following description of a preferred implementation, given by way of non-limiting example and made with reference to the accompanying drawings in which:

[0021]FIGS. 1A to 1G illustrate the successive steps of a method in accordance with the invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0022] The present invention preferably provides a method for fabricating a substrate by hetero-epitaxial growth wherein the epitaxial layer(s) is protected against contamination from the substrate material despite exposure to the high temperatures necessary for growth. The invention also provides a method for easy removal of the support on which the epitaxial layer is grown.

[0023] Generally, the intermediate support is a material that can be chemically attacked by a given attack medium, and the material of the nucleation layer forms a barrier against diffusion of elements deriving from any thermal dissociation of the intermediate support material.

[0024] In one specific arrangement, the method involves epitaxial growing of the monocrystalline semiconductor material on the nucleation layer. Preferably, monocrystalline semiconductor material is deposited on the nucleation layer by epitaxy. However, other methods are suitable, as is known in the art.

[0025] As noted above, the material of the intermediate support is one that can be chemically attacked or etched by a given etching medium, it is subject to thermal dissociation when exposed to a the temperature of epitaxial growing of the semiconductor layer, and is made of a material that is less expensive that materials that are more resistant to thermal dissociation at epitaxial growth temperatures.

[0026] Referring to FIGS. 1A to 1G, FIG. 1A shows a source substrate 10, such as monocrystalline silicon carbide SiC, in which ions, e.g., hydrogen ions, have been implanted at a certain depth using an ionic bombardment machine, a plasma implantation machine, or any other known method in the art. The implantation of ions defines a nucleation layer 12 of implanted ions on a portion of the source substrate 10, wherein the main concentration of ions on the source substrate define a detachment zone 14. Typically, ions are implanted to a depth in the range of about 200 nanometers (nm) to 1000 nm, using ions with energy in the range of about 50 kilo electron volts (keV) to 200 keV, and an implantation dose in the range of about 5×1016 ions per square centimeter (ions/cm2) to 1×1017 ions/cm2.

[0027] Referring to FIG. 1B, substrate 10 having layer 12 is attached to an intermediate growth support substrate 20 by molecular bonding to form a source substrate-intermediate growth support substrate assembly. For example, the growth support substrate 20 may comprise monocrystalline gallium arsenide GaAs. Typically, the intermediate growth support substrate 20 has a thickness in the range of about 400 micrometers (μm) to 800 μm.

[0028] Optionally, at least one surface of source substrate 10 and/or support substrate 20 is provided with bonding layers 13, 23 in a manner known in the art. Such bonding layers may be silicon oxide SiO2 or silicon nitride Si3N4. However, other materials may be used as known in the art. When formed from SiO2 on Si, the bonding layer(s) are provided on the surface of the source substrate or the intermediate support substrate by thermal oxidation, or alternatively, by deposition. The bonding energy of the bonding interface is brought to the required level by heat treatment, typically at a temperature of more than about 300° C. for a period that is typically 2 hours. However, other known methods may be used.

[0029] Stresses, such as thermal and/or mechanical, but which could be of some other nature, are applied to the source substrate-intermediate growth support substrate assembly so as to detach the intermediate growth support substrate 20 and the nucleation layer 12 from the remaining source substrate 10, at the detachment zone 14. Such detachment can be accomplished using the known Smart-Cut® technique developed by Applicant. To this end, a heat treatment is typically carried out at a temperature in the range 800° C. to 900° C. for a period in the range 30 minutes to 3 hours. Such heat treatment can be combined with that used to strengthen the bonding interface.

[0030] As illustrated in FIG. 1C, a structure comprising a GaAs growth support 20 having a thin nucleation layer 12 of monocrystalline SiC is obtained. The free surface of said layer can undergo polishing/cleaning and in particular chemical-mechanical polishing or ion beam smoothing intended to allow good-quality epitaxial growth to be performed thereon.

[0031] A metal organic chemical vapor deposition (MOCVD) hetero-epitaxy technique is carried out on this surface to produce a stack of deposits of gallium nitride GaN with different types of doping, said technique being known to produce a GaN stack 30 having good crystal quality.

[0032] Such technique is carried out at a temperature of about 1050° C. to 1100° C., at which temperature partial dissociation of the GaAs of the support substrate 20 is observed. The presence of the SiC nucleation layer 12, however, forms a barrier layer against the diffusion of arsenic or gallium atoms towards the deposited layer 30, and thereby maintains the quality of the and the purity of layer 30.

[0033] The stack of GaN is typically a few microns thick, i.e., it is a thin layer, as opposed to the thick layers with a minimum thickness of about 200 μm to 300 μm, which renders the stack self-supporting.

[0034]FIG. 1D shows the resulting structure.

[0035] After growth of the GaN stack 30, the assembly comprising the support substrate layers 20, bonding layer 23, bonding layer 13, implanting layer 12 and layer 30 is applied to a target substrate 40 of monocrystalline or polycrystalline silicon so as to form the final support of the GaN layer.

[0036] At its surface receiving the GaN layer, said final support 40 advantageously has metallization 41 allowing the final support to comprise a reflector for visible or UV radiation emitted by the electroluminescent components which have been formed in the layer 30. The metallization 41 of the surface of the final support 40 is preferably achieved by cathode sputtering or vacuum evaporation of gold, tin, or palladium (or of any suitable alloy) with a thickness of 500 nm, for example.

[0037] The free surface of the GaN stack 30 undergoes polishing treatment, typically a chemical-mechanical polishing or ion beam smoothing intended to provide a flatness that is suitable for molecular bonding with the target substrate 40, which itself must have satisfactory flatness prior to metallization.

[0038] The thickness of substrate 40 is typically in the range of about 300 μm to 500 μm.

[0039] Fixing is achieved by molecular bonding or by eutectic bonding (which means that polishing can be dispensed with), if necessary supplying heat energy at a temperature in the range 200° C. to 350° C. for several hours to produce the desired bonding forces.

[0040] Optionally, prior to fixing, the GaN stack 30 can undergo all or some treatments for producing components such as blue or green LEDs, laser diodes, etc.

[0041] The assembly is exposed to chemical attack with a solution comprising a mixture including HF, HNO3, CH3COOH, and H2O in proportions of 1:3:3:5 to completely remove the intermediate GaAs support 20.

[0042] The nucleation layer, and if appropriate, the bonding layers 13, 23 (if they have not been removed chemically) are removed preferably by ionic etching. Additionally, it is also possible to remove a portion of the epitaxial layers that have been formed, in particular to remove initial epitaxial layers containing defects.

[0043] The method described herein with mention of certain examples is not meant to be limiting, and as is known in the art variants are also encompassed within the invention. For instance, the choice of nucleation layer 12 is principally conditioned by the search for a compromise between the lattice parameter, thermal expansion coefficient, stability at high temperatures, ability to form a barrier layer against the diffusion of elements from possible partial decomposition of the layer forming the intermediate support. Preferably, either SiC as indicated above is selected, or GaN, or even sapphire is selected. However, other materials may be used as known in the art.

[0044] The material of the intermediate support 20 is not critical as regards to lattice parameter, but it should be selected principally as a result of finding a compromise between its thermal expansion coefficient compared with that of the material of the epitaxial layer, the stability of the epitaxial layer under high temperatures, and in particular the facility with which it is removed chemically.

[0045] In addition to GaAs, other materials may be used such as silicon, certain oxides such as ZnO, LiGa2 or NdGaO3 Further, the material deposited by epitaxial growth to form the useful layer or layers of the substrate is typically a stack of differently doped layers of GaN, in a manner that is known in the art. However, it can also be a stack of a variety of other metal nitrides such as AlN or GaAlN, etc.

[0046] Finally, the final support 40 can be any support selected as a function of a compromise between its ability to receive the metallization 41 if appropriate, its ability to receive the deposited layer 30 by bonding or any other technique, its properties in terms of mechanical and chemical stability during treatments for producing components in the stack of layers 30, its thermal properties, its fabrication cost, etc.

[0047] In another embodiment, not shown in the Figures, comprises two distinct layers deposited on or applied to the intermediate support, one forming a barrier to the diffusion of elements deriving from dissociation of the material of the intermediate support, and the other, outer layer, forming a nucleation layer. It should be noted in this respect that the barrier layer can be formed, deposited or applied either onto the source substrate 10, or onto the intermediate support 20, prior to bonding.

EXAMPLE

[0048] A 500 nm thick layer of SiO2 is produced on one face of a monocrystalline SiC source substrate by thermal oxidation. Hydrogen ions are then implanted with an energy of 100 keV and using a dose of 8×1016 ions/cm2 into the source substrate using ion bombardment equipment.

[0049] A 500 μm thick monocrystalline GaAs substrate intended to form the intermediate support is also prepared, and one face of the substrate is coated with a 500 nm thick SiO2 layer by chemical vapor deposition.

[0050] Surface activation is then carried out, for example by chemical-mechanical polishing, to smooth the surfaces and provide them with a certain hydrophilic nature.

[0051] The faces of the source substrate and the intermediate support substrate are then brought together and bonded, and a suitable bonding energy is obtained by heat treatment at 350° C. for a period of 2 hours.

[0052] This assembly then undergoes heat treatment at 900° C. for a period of one hour to obtain detachment at the implanted zone.

[0053] The face of the layer 12 is then polished at the detachment location using ionic smoothing by ion cluster smoothing.

[0054] Different GaN layers are then deposited by epitaxial growth. Typically, said GaN stack 30 has the following succession of layers:

[0055] an 8 nm AlN buffer layer;

[0056] a 1 μm GaN layer.

[0057] After said operation, the free face of the stack 30 is polished by an ion cluster technique.

[0058] Meanwhile, a monocrystalline silicon substrate with a normal commercial grade of surface polishing and a thickness of 500 μm is coated with a metallization based on indium/palladium over a thickness of 400 nm.

[0059] The intermediate support 20 carrying the stack 30 and the substrate 40 carrying the metallization 41 are then bonded together by molecular bonding, the bonding interface being reinforced by heat treatment at 350° C. for a period of 2 hours.

[0060] The GaAs intermediate support is then attacked by immersion in an attack solution composed of a mixture of HF, HNO3, CH3COOH, and H2O in proportions of 1:3:3:5, peripheral attack of the metallic layer 41 being minor and without consequence.

[0061] The attack finishes at the SiC layer 12.

[0062] This latter layer is then removed, for example by SF6/O2 reactive ionic etching.

[0063] Clearly, the present invention is not limited to the preferred implementations described and shown in the drawings, and the skilled person is capable of providing variants and modifications, all of which are included within the scope of the appended claims.

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US7407867 *Aug 24, 2006Aug 5, 2008S.O.I.Tec Silicon On Insulator TechnologiesMethod for concurrently producing at least a pair of semiconductor structures that each include at least one useful layer on a substrate
US7537949Mar 21, 2005May 26, 2009S.O.I.Tec Silicon On Insulator TechnologiesOptoelectronic substrate and methods of making same
US7839001 *Aug 5, 2009Nov 23, 2010S.O.I.Tec Silicon On Insulator TechnologiesMethods for making substrates and substrates formed therefrom
US7939428Oct 28, 2010May 10, 2011S.O.I.Tec Silicon On Insulator TechnologiesMethods for making substrates and substrates formed therefrom
US8012289 *Feb 25, 2009Sep 6, 2011S.O.I.Tec Silicon On Insulator TechnologiesMethod of fabricating a release substrate
US8541290 *Jun 7, 2011Sep 24, 2013SoitecOptoelectronic substrate and methods of making same
US8598013 *Oct 8, 2008Dec 3, 2013Semiconductor Energy Laboratory Co., Ltd.Method for manufacturing SOI substrate and semiconductor device
US20090200569 *Apr 16, 2009Aug 13, 2009S.O.I.Tec Silicon On Insulator Technologies S.A.Optoelectronic substrate and methods of making same
US20110237008 *Jun 7, 2011Sep 29, 2011S.O.I.Tec Silicon On Insulator TechnologiesOptoelectronic substrate and methods of making same
EP1681712A1 *Jan 13, 2005Jul 19, 2006S.O.I. Tec Silicon on Insulator Technologies S.A.Method of producing substrates for optoelectronic applications
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Classifications
U.S. Classification438/459, 257/E21.087, 257/E21.127, 257/E21.121, 257/E21.568, 257/E21.542
International ClassificationH01L21/04, C30B25/18, C30B25/02, H01L21/76, H01L21/20, H01L21/762, H01L21/18
Cooperative ClassificationY10S438/967, H01L29/1608, H01L21/7605, C30B25/02, C30B29/406, C30B29/403, C30B25/18, H01L21/185, H01L21/76254
European ClassificationC30B25/18, C30B29/40B, C30B29/40B2, C30B25/02, H01L21/762D8B, H01L21/76P
Legal Events
DateCodeEventDescription
Mar 4, 2012ASAssignment
Owner name: SOITEC, FRANCE
Free format text: CHANGE OF NAME;ASSIGNOR:S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES;REEL/FRAME:027800/0911
Effective date: 20110906
Jun 9, 2003ASAssignment
Owner name: S.O.I. TEC SILICON ON INSULATOR TECHNOLOGIES S.A.,
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:LETERTRE, FABRICE;GHYSELEN, BRUNO;RAYSSAC, OLIVIER;REEL/FRAME:014174/0100
Effective date: 20030605