US20040005732A1 - Microelectronic device packages and methods for controlling the disposition of non-conductive materials in such packages - Google Patents

Microelectronic device packages and methods for controlling the disposition of non-conductive materials in such packages Download PDF

Info

Publication number
US20040005732A1
US20040005732A1 US10/190,019 US19001902A US2004005732A1 US 20040005732 A1 US20040005732 A1 US 20040005732A1 US 19001902 A US19001902 A US 19001902A US 2004005732 A1 US2004005732 A1 US 2004005732A1
Authority
US
United States
Prior art keywords
conductive
microelectronic substrate
generally non
support member
couplers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
US10/190,019
Other versions
US6673649B1 (en
Inventor
William Hiatt
Warren Farnworth
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
US Bank NA
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to US10/190,019 priority Critical patent/US6673649B1/en
Assigned to MICRON TECHNOLOGY, INC. reassignment MICRON TECHNOLOGY, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: HIATT, WILLIAM MARK, FARNWORTH, WARREN
Priority to US10/701,128 priority patent/US7087995B2/en
Application granted granted Critical
Publication of US6673649B1 publication Critical patent/US6673649B1/en
Publication of US20040005732A1 publication Critical patent/US20040005732A1/en
Priority to US11/248,914 priority patent/US7470563B2/en
Assigned to U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT reassignment U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT SECURITY INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: MICRON TECHNOLOGY, INC.
Assigned to MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT reassignment MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT PATENT SECURITY AGREEMENT Assignors: MICRON TECHNOLOGY, INC.
Assigned to U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT reassignment U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Assignors: MICRON TECHNOLOGY, INC.
Assigned to JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT reassignment JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT SECURITY INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: MICRON SEMICONDUCTOR PRODUCTS, INC., MICRON TECHNOLOGY, INC.
Assigned to MICRON TECHNOLOGY, INC. reassignment MICRON TECHNOLOGY, INC. RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS). Assignors: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Assigned to MICRON TECHNOLOGY, INC. reassignment MICRON TECHNOLOGY, INC. RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS). Assignors: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Assigned to MICRON SEMICONDUCTOR PRODUCTS, INC., MICRON TECHNOLOGY, INC. reassignment MICRON SEMICONDUCTOR PRODUCTS, INC. RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS). Assignors: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/46—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids
    • H01L23/467—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids by flowing gases, e.g. air
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/46—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids
    • H01L23/473—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids by flowing liquids
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05568—Disposition the whole external layer protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
    • H01L2224/10122—Auxiliary members for bump connectors, e.g. spacers being formed on the semiconductor or solid-state body to be connected
    • H01L2224/10125—Reinforcing structures
    • H01L2224/10126—Bump collar
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13022—Disposition the bump connector being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83102—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus using surface energy, e.g. capillary forces
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83194—Lateral distribution of the layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01039—Yttrium [Y]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01075—Rhenium [Re]

Definitions

  • the present invention is directed generally toward microelectronic device packages and methods for controlling the disposition and/or extent of non-conductive materials in such packages.
  • Existing microelectronic device packages typically include a microelectronic substrate or die attached to a support member, such as a printed circuit board. Bond pads or other terminals on the die are electrically connected to corresponding terminals on the support member, for example, with solder balls.
  • the connection between the die and the support member can be encapsulated, for example, with a protective underfill material, to form a device package.
  • the package can then be electrically connected to other microelectronic devices or circuits, for example, in a consumer or industrial electronic product such as a computer.
  • a package 10 can include a support member 20 that carries a microelectronic die 30 .
  • Solder balls 50 provide an electrical connection between upwardly facing bond pads of the support member 20 and downwardly facing bond pads of the die 30 . Accordingly, a gap (partially filled by the solder balls) is initially formed between the support member 20 and the die 30 .
  • an underfill material 40 is initially disposed adjacent to two of the outer edges of the die 30 .
  • the underfill material 40 flows into the gap between the die 30 and the support member 20 to provide a protective encapsulant around the solder balls 50 .
  • the underfill material 40 can flow both directly into the gap (as indicated by arrows A) and around the outer edges of the die 30 (as indicated by arrows B).
  • the underfill material 40 can flow more quickly around the die 30 (arrows B) than directly into the gap beneath the die 30 (arrows A). Accordingly, the underfill material 40 can trap air or other gases in the gap.
  • a drawback with this arrangement is that the gases within the gap may expand when the temperature of the package 10 is elevated, causing the electrical connections provided by the solder balls 50 between the die 30 and the support member 20 to fail.
  • One existing approach for addressing the foregoing drawback is to control the viscosity of the underfill material 40 so that it preferentially wicks more quickly through the gap than around the periphery of the die 30 .
  • the viscosity can be controlled by controlling the temperature at which the underfill process is conducted, or the concentration of particulates in the underfill material 40 .
  • the surface characteristics of the die 30 and/or the support member 20 can be selected to produce a faster underfill flow rate through the gap than around the periphery of the die 30 .
  • the foregoing methods can produce satisfactory results, it may in some cases be difficult and/or expensive to accurately control the aforementioned variables.
  • the underfill material 40 typically provides a permanent bond between the die 30 and the support member 20 , making it difficult if not impossible to replace a defective die 30 without destroying the entire package 10 .
  • the present invention is directed toward microelectronic packages and methods for forming such packages.
  • a method in accordance with one aspect of the invention includes positioning a microelectronic substrate proximate to a support member, with the microelectronic substrate having a first surface, a second surface facing opposite from the first surface, and a plurality of first connection sites at least proximate to the first surface.
  • the support member can have a plurality of second and third connection sites.
  • the method can further include connecting the microelectronic substrate to the support member by attaching a plurality of electrically conductive couplers between the plurality of first connection sites and the second connection sites, with neighboring conducted couplers being spaced apart to define at least one fluid flow channel, and with the support member and the microelectronic substrate forming a package.
  • the package can then be provided for electrical coupling to other electrical structures via the third connection sites, with the at least one fluid flow channel accessible to a region external to the package.
  • flowable, electrically conductive couplers can be disposed at the first connection sites, and a generally non-conductive material can be disposed between the conductive couplers.
  • a gap dimension can be selected based on a target underfill flow rate, and at least a portion of the generally non-conductive material can be removed to form a gap having the selected gap dimension and being positioned between neighboring conductive couplers.
  • the microelectronic substrate and the support member can be connected by attaching the conductive couplers to the second bond sites of the support member, and an underfill material can be flowed into the gap at at least approximately the target underfill material flow rate.
  • a method in accordance with another aspect of the invention includes providing a first microelectronic substrate having first connection sites carrying first flowable, electrically conductive couplers that define a first plane.
  • a first generally non-conductive material is applied to the first conductive couplers and to the first microelectronic substrate, and at least some of the first generally non-conductive material is removed to recess the first generally non-conductive material from the first plane by a first recess distance.
  • the method can further include providing a second microelectronic substrate having second flowable, electrically conductive couplers defining a second plane spaced apart from the second microelectronic substrate by a second distance different than the first distance.
  • a second generally non-conductive material is applied to the second conductive couplers, and at least some of the second generally non-conductive material is removed from between the second conductive couplers to recess the second generally non-conductive material from the second plane by a second recess distance that is at least approximately the same as the first recess distance.
  • a method in accordance with still another aspect of the invention includes connecting the microelectronic substrate to the support member by attaching the conductive couplers and disposing at least one generally non-conductive material adjacent to the conductive couplers, with the at least one generally non-conductive material being spaced apart from the support member.
  • the at least one generally non-conductive material can be a first generally non-conductive material
  • the method can further include disposing a second generally non-conductive material adjacent to the support member and the conductive couplers, with the second generally non-conductive material being spaced apart from the first generally non-conductive material.
  • a method in accordance with yet another aspect of the invention includes providing a first generally non-conductive material between flowable conductive couplers of a microelectronic substrate, with the first generally non-conductive material being recessed to define a flow channel having an inner region and an outer region disposed outwardly from the inner region.
  • a second generally non-conductive material can be disposed on the support member to form a layer having a first region and a second region disposed outwardly from the first region, with the first region having a greater thickness than the second region.
  • the inner region of the flow channel is then engaged with the first region of the second generally non-conductive material, while the second generally non-conductive material is at least partially flowable, and the microelectronic substrate and the support member are moved toward each other while forcing gas within the flow channel generally outwardly to the outer region of the flow channel.
  • FIG. 1 is a partially schematic, plan view of a microelectronic package formed by a method in accordance with the prior art.
  • FIG. 2 is a partially schematic, cross-sectional side view of a microelectronic package having fluid flow channels in accordance with an embodiment of the invention.
  • FIGS. 3 A- 3 E illustrate a process for forming fluid flow channels in a microelectronic package in accordance with an embodiment of the invention.
  • FIGS. 4 A- 4 B illustrate a microelectronic package having portions of non-conductive material separated from each other in accordance with another embodiment of the invention.
  • FIG. 5 is a partially schematic, exploded cross-sectional side view of a microelectronic package having a gap positioned to control the flow of underfill material adjacent to a microelectronic substrate.
  • FIG. 6 is a partially schematic, exploded cross-sectional side view of two packages having gaps formed in accordance with another embodiment of the invention.
  • FIGS. 7 A- 7 B illustrate a process for reducing and/or eliminating gaps in a device package having a no-flow underfill material.
  • microelectronic substrate packages and methods for forming such packages.
  • microelectronic substrate is used throughout to include substrates upon which and/or in which microelectronic circuits or components, data storage elements or layers, and/or vias or conductive lines are or can be fabricated.
  • FIGS. 2 - 7 B Many specific details of certain embodiments of the invention are set forth in the following description and in FIGS. 2 - 7 B to provide a thorough understanding of these embodiments.
  • FIGS. 2 - 7 B to provide a thorough understanding of these embodiments.
  • the present invention may have additional embodiments, and that the invention may be practiced without several of the details described below.
  • FIG. 2 is a partially schematic illustration of a package 110 having fluid flow channels 161 in accordance with an embodiment of the invention.
  • the package 110 can include a microelectronic substrate 130 carried by a support member 120 .
  • the microelectronic substrate 130 can include a first surface 131 , a second surface 132 facing opposite from the first surface 131 , and internal components (not visible in FIG. 2), such as memory circuits and/or linking circuitry, positioned between the first surface 131 and the second surface 132 .
  • a plurality of first connection sites 133 (such as bond pads) can be coupled to the internal components and can be positioned proximate to the first surface 131 .
  • the support member 120 can include second connection sites 122 (such as bond pads) coupled to the first connection sites 133 with flowable, electrically conductive couplers 150 .
  • the conductive couplers 150 can include solder balls (formed from solder particles disposed in a flux medium) or other conductive materials that can be reflowed after being applied to the microelectronic substrate 130 to form an electrical connection between the microelectronic substrate 130 and the support member 120 .
  • the conductive couplers 150 can include other features and/or compositions.
  • the support member 120 can include third connection sites 121 (such as bond pads) configured to be electrically coupled to other devices and/or circuits external to the package 110 .
  • the microelectronic substrate 130 can include a generally non-conductive material 160 disposed in the interstices between neighboring conductive couplers 150 . Portions of the non-conductive material 160 can be recessed away from the support member 120 to define at least a portion of the fluid flow channels 161 . Accordingly, air and/or other fluids can move through the fluid flow channels 161 .
  • the fluid flow channels 161 can be in fluid communication with the environment external to the package 110 so that the fluid within the fluid flow channels 161 is free to move into and/or out of the fluid flow channels 161 .
  • the dimensions of the fluid flow channel 161 can be selected according to design criteria that account for fluid flow rate, package geometry and/or support for the conductive couplers 150 .
  • the fluid flow channel 161 can have a transverse or widthwise dimension W that is determined by the spacing between neighboring conductive couplers 150 and/or by the amount of non-conductive material 160 selected to strengthen the connection between the conductive couplers 160 and the first connection sites 133 .
  • the depthwise dimension D of the flow channel 161 can be determined based on the height of the conductive couplers 150 and/or by the amount of non-conductive material 160 selected to strengthen the connection between the conductive couplers 160 and the first connection sites 133 .
  • the fluid flow channel 161 can have a variety of dimensions, and can range from a relatively small channel (e.g., offset from the sides of neighboring conductive couplers 150 and offset the first surface 131 of the microelectronic substrate 120 ), to a relatively large channel (extending transversely to expose the sides of neighboring conductive couplers 150 , and extending depthwise to expose the first surface 131 ).
  • the non-conductive material 160 can be reduced in size to a small ring around each first connection site 133 .
  • the package 110 can further include an optional adhesive layer 170 disposed around a periphery of the non-conductive material 160 .
  • the adhesive layer 170 can provide for an additional connection between the microelectronic substrate 130 and the support member 120 and can constrain the relative thermal expansion of these components as the temperature of the package 110 changes.
  • the adhesive material 170 can be disposed adjacent to two sides of the microelectronic substrate 130 , leaving the regions adjacent to the remaining two sides of the microelectronic substrate 130 open to allow fluid to move into and/or out of the fluid flow channels 161 .
  • One feature of an embodiment of the package 110 described above with reference to FIG. 2 is that the fluid flow channels 161 can be in fluid communication with the environment external to the package 110 .
  • An advantage of this feature is that any fluid (such as air or another gas) present in the fluid flow channels 161 as the package 110 is fabricated can freely exit the fluid flow channels 161 as the temperature of the package 110 increases. As a result, the package 110 will be less likely to fail due to the pressure exerted by the expanding fluid within the fluid flow channels 161 . As the package 110 cools, fluid can re-enter the fluid flow channels 161 so that the package 110 is not subjected to inwardly directed pressure exerted by the environment around the package 110 .
  • fluid flow channels 161 can provide an avenue for cooling flow to cool the components of the package 110 . Accordingly, the cooling flow can be in more intimate contact with the interior portions of the package 110 than existing cooling flows that contact only the external surfaces of the microelectronic substrate 130 and/or the support member 120 . As a result, the components in the package 110 may be less likely to overheat and fail at normal operating temperatures, and may be more likely to survive extreme operating temperatures.
  • FIGS. 3 A- 3 E schematically illustrate a process for forming a microelectronic package generally similar to that described above with reference to FIG. 2.
  • the process can include providing a microelectronic substrate 130 having a thickness T 1 .
  • the microelectronic substrate 130 can include first connection sites 133 carrying conductive couplers 150 , such as solder balls.
  • the non-conductive material 160 can be disposed over the first surface 131 of the microelectronic substrate 130 to cover the conductive couplers 150 .
  • the non-conductive material 160 can include one or more strengthening materials, such as FP 4450, available from Dexter Hysol of Seabrook, N.H.
  • the non-conductive material 160 can include thermoset epoxy polymers, such as those disclosed in U.S. Pat. No. 6,180,527, incorporated herein in its entirety by reference. In still further embodiments, the non-conductive material 160 can include other generally electrically- non-conductive materials.
  • the non-conductive material 160 can strengthen the microelectronic substrate 130 and can accordingly allow operations on the microelectronic substrate 130 that would not be practical without the non-conductive material 160 .
  • material can be removed from the second surface 132 of the microelectronic substrate 130 to thin the microelectronic substrate 130 and form a new second surface 132 a , as shown in FIG. 3C.
  • the microelectronic substrate 130 can accordingly have a thickness T 2 that is less than the initial thickness T 1 shown in FIG. 3B.
  • the thinner microelectronic substrate 130 can be easier to cool and can occupy less volume in the devices in which it is installed.
  • the thinning process described above with reference to FIG. 3C can be eliminated.
  • the non-conductive material 160 can be removed to form the fluid flow channels 161 shown in FIG. 2.
  • the non-conductive material 160 can first be smoothed and reduced in thickness, for example, by chemical action, mechanical action or chemical mechanical planarization (CMP).
  • CMP chemical mechanical planarization
  • a mask 162 can be positioned over the resulting external surface 165 of the non-conductive material 160 .
  • the mask 162 can include apertures 163 aligned with the interstices between neighboring conductive couplers 150 .
  • the non-conductive material 160 can be exposed to an etchant or other removing agent to form the fluid flow channels 161 .
  • the mask 162 can then be removed and any material positioned over the conductive couplers 150 can be excised, as shown in FIG. 3E to expose the tips of the conductive couplers 150 . Accordingly, the conductive couplers 150 can bond to a support member 120 (FIG. 2) to form a microelectronic package. Further details of processes for removing portions of the non-conductive material 160 positioned between the conductive couplers 150 are disclosed in U.S. Pat. No. 6,118,179, incorporated herein in its entirety by reference.
  • an anisotropic etchant can be used to form the flow channels 161 , and an isotropic etchant can be used to remove the material positioned directly above the conductive couplers 150 .
  • other combinations of etchants and/or process techniques can be used to remove at least a portion of the non-conductive material 160 .
  • the entirety of the non-conductive material 160 can be removed prior to attaching the microelectronic substrate 130 to the support member 120 .
  • FIGS. 4 A- 4 B illustrate a device package 410 configured in accordance with another embodiment of the invention.
  • the package 410 can include a support member 120 that carries a microelectronic substrate 130 .
  • the microelectronic substrate 130 can include first bond sites 133 and conductive couplers 150 arranged generally as described above with reference to FIGS. 2 - 3 E.
  • a first generally non-conductive material 460 a is positioned in the interstitial regions between neighboring conductive couplers 150 .
  • the support member 120 can include second bond sites 122 , each of which can optionally carry a quantity of a second generally non-conductive material 460 b, such as WS609 flux, available from Alpha Metals of Jersey City, N.J., and typically referred to in the industry as a “brick.”
  • the second generally non-conductive material 460 b can include a “no-clean” fluxing agent and an epoxy.
  • the second generally non-conductive material 460 b can include other constituents, such as a water clean flux.
  • an additional quantity of conductive material (such as solder) can be mixed in with the second generally non-conductive material 460 b.
  • the microelectronic substrate 130 and the support member 120 can be moved toward each other and heated to reflow the conductive couplers 150 and couple the first connection sites 133 of the microelectronic substrate 130 to the second connection sites 122 of the support member 120 .
  • the elevated temperature can also cause the second non-conductive material 460 b to flow outwardly from the second connection sites 122 .
  • the second non-conductive material 460 b can form a continuous layer in the interstices between the conductive couplers 150 , adjacent to the support member 120 .
  • the second non-conductive material 460 b can form an isolated meniscus around each conductive coupler 150 . In either embodiment, when the second non-conductive material 460 b includes an epoxy or other thermoset material, this material is then cured to a hardened, solid state.
  • the second non-conductive material 460 b can extend from the support member 120 , part-way along the sides of the conductive couplers 150
  • the first non-conductive material 460 a can extend from the microelectronic substrate 130 , part-way along the sides of the conductive couplers 150 without contacting the first non-conductive material 460 a.
  • the package 410 can include gaps 464 between the first non-conductive material 460 a and the second non-conductive material 460 b .
  • An advantage of this feature is that the gaps 464 can act as cooling flow channels, in a manner generally similar to that described above with reference to FIG. 2. Accordingly, the package 410 can operate more efficiently and/or be less likely to fail when exposed to high temperatures.
  • gaps 464 are limit the structural connection between the microelectronic substrate 130 and the support member 120 to the link provided by the conductive couplers 150 . Accordingly, the microelectronic substrate 130 can be removed from the support member 120 , for example, by elevating the temperature of the conductive couplers 150 , causing the conductive couplers 150 to reflow. If either the microelectronic substrate 130 or the support member 120 is defective, the defective component can be separated from the package 410 (without damaging the non-defective component) and replaced with another, comparable component.
  • FIG. 5 is a partially exploded, cross-sectional side view of a package 510 configured in accordance with another embodiment of the invention.
  • the package 510 can include a support member 120 that carries a microelectronic substrate 130 .
  • the microelectronic substrate 130 can include conductive couplers 150 positioned on the first connection sites 133 in a manner generally similar to that described above with reference to FIG. 2.
  • the microelectronic substrate 130 can further include a generally non-conductive material 560 positioned in the interstices between the conductive couplers 150 .
  • the outer surfaces of the conductive couplers 150 can define a plane P and the outer surface of the non-conductive material 560 can be recessed from the plane P to provide a gap 564 .
  • the gap 564 can be selectively sized such that when the microelectronic substrate 130 is connected to the support member 120 and an underflow material 540 flows into the gap 564 from a position adjacent to the microelectronic substrate 130 , the underflow material 540 will tend to wick more quickly into the gap 564 than around the periphery of the microelectronic substrate 130 .
  • the gap 564 can have a depth of about 25 microns in one embodiment.
  • the gap 564 can have other depths greater than or less than 25 microns. In still further embodiments, the gap 564 can have a size based on the mean diameter of particulates in the underflow material 540 . For example, the gap 564 can have a depth that is about three times the mean diameter of such particulates.
  • Suitable underflow materials 540 are available from Locktite Corp. of Rocky Hills, Conn., Nagase America Corp. of New York, N.Y., and Dexter Hysol of Seabrook, N.H.
  • the underflow material 540 flowing through the gap 564 will tend to push out any gas in the gap 564 before wicking around the periphery of the microelectronic substrate 130 and sealing off the gap 564 .
  • An advantage of this arrangement is that by reducing and/or eliminating trapped gas between the microelectronic substrate 130 and support member 120 , the package 510 will be less likely to fail as it undergoes temperature excursions.
  • FIG. 6 is a partially exploded, cross-sectional side view of two device packages 610 (shown as a first package 610 a and a second package 610 b ) configured in accordance with still another embodiment of the invention.
  • the first package 610 a can include a first support member 620 a that carries a first microelectronic substrate 630 a .
  • the first microelectronic substrate 630 a can include a plurality of first conductive couplers 650 a and a first generally non-conductive material 660 a disposed in the interstices between the first conductive couplers 650 a .
  • the first conductive couplers 650 a can define a plane P 1 , and the first non-conductive material 660 a can be recessed from the plane P 1 to define a gap 664 a .
  • an underfill material 640 a can flow through the gap 664 a at a pre-selected rate, in a manner generally similar to that described above with reference to FIG. 5.
  • the second package 610 b can include a second support member 620 b and a second microelectronic substrate 630 b .
  • the second microelectronic substrate 630 b can include second conductive couplers 650 b that are larger than the first conductive couplers 650 a and that define a plane P 2 .
  • a second non-conductive material 660 b can be disposed in the interstices between neighboring second conductive couplers 650 b and can be recessed from the plane P 2 to define a second gap 664 b.
  • the second gap 664 b can have approximately the same depth as the first gap 664 a , even though the second conductive couplers 650 b are substantially larger than the first conductive couplers 650 a .
  • the second package 610 b can include a volume of second underflow material 640 b that has approximately the same size as the first underflow material volume 640 a .
  • FIGS. 7 A- 7 B illustrate a process for forming a device package 710 in accordance with still another embodiment of the invention.
  • the package 710 can include a support member 720 and a microelectronic substrate 730 .
  • the microelectronic substrate 730 can include conductive couplers 750 and a generally non-conductive material 760 disposed in the interstices between neighboring conductive couplers 750 .
  • the generally non-conductive material 760 can be recessed from the outer surfaces of the conductive couplers 750 to form a gap 764 .
  • the support member 720 can include an upper surface 723 , connection sites 722 at least proximate to the upper surface 723 , and a generally non-conductive, no-flow underfill material 740 disposed on the upper surface 723 and the second connection sites 722 .
  • Suitable no-flow underfill materials are available from Locktite Corp., Nagase America Corp., and Dexter Hysol Corp.
  • the underfill material 740 can have a generally domed shape before the microelectronic substrate 730 is connected to the support member 720 .
  • the underfill material 740 when the microelectronic substrate 730 is brought into contact with the underfill material 740 , the underfill material 740 will tend to fill the central portion of the gap 764 before filling the outer portion of the gap 764 . As the microelectronic substrate 730 and the support member 720 move closer together, the underfill material 740 forces the gas in the gap 764 generally outwardly. Accordingly, as shown in FIG. 7B, the completed package 710 can have the underfill material 740 completely filling the gap 764 .
  • An advantage of this arrangement is that, by reducing and/or eliminating trapped gas between the support member 720 and the microelectronic substrate 730 , the package 710 will be less likely to fail during temperature excursions.

Abstract

A microelectronic package and method for forming such a package. In one embodiment, the package can include a microelectronic substrate having first connection sites, and a support member having second connection sites and third connection sites, with the third connection sites accessible for electrical coupling to other electrical structures. A plurality of electrically conductive couplers are connected between the first connection sites and the second connection sites, with neighboring conductive couplers being spaced apart to define at least one flow channel. The at least one flow channel is in fluid communication with a region external to the microelectronic substrate. The generally non-conductive material can be spaced apart from the support member to allow the microelectronic substrate to be separated from the support member.

Description

    TECHNICAL FIELD
  • The present invention is directed generally toward microelectronic device packages and methods for controlling the disposition and/or extent of non-conductive materials in such packages. [0001]
    • BACKGROUND
  • Existing microelectronic device packages typically include a microelectronic substrate or die attached to a support member, such as a printed circuit board. Bond pads or other terminals on the die are electrically connected to corresponding terminals on the support member, for example, with solder balls. The connection between the die and the support member can be encapsulated, for example, with a protective underfill material, to form a device package. The package can then be electrically connected to other microelectronic devices or circuits, for example, in a consumer or industrial electronic product such as a computer. [0002]
  • In one existing arrangement shown in FIG. 1, a [0003] package 10 can include a support member 20 that carries a microelectronic die 30. Solder balls 50 provide an electrical connection between upwardly facing bond pads of the support member 20 and downwardly facing bond pads of the die 30. Accordingly, a gap (partially filled by the solder balls) is initially formed between the support member 20 and the die 30.
  • In one existing process, an [0004] underfill material 40 is initially disposed adjacent to two of the outer edges of the die 30. The underfill material 40 flows into the gap between the die 30 and the support member 20 to provide a protective encapsulant around the solder balls 50. The underfill material 40 can flow both directly into the gap (as indicated by arrows A) and around the outer edges of the die 30 (as indicated by arrows B).
  • One characteristic the process described above with reference to FIG. 1 is that in some cases, the [0005] underfill material 40 can flow more quickly around the die 30 (arrows B) than directly into the gap beneath the die 30 (arrows A). Accordingly, the underfill material 40 can trap air or other gases in the gap. A drawback with this arrangement is that the gases within the gap may expand when the temperature of the package 10 is elevated, causing the electrical connections provided by the solder balls 50 between the die 30 and the support member 20 to fail.
  • One existing approach for addressing the foregoing drawback is to control the viscosity of the [0006] underfill material 40 so that it preferentially wicks more quickly through the gap than around the periphery of the die 30. For example, the viscosity can be controlled by controlling the temperature at which the underfill process is conducted, or the concentration of particulates in the underfill material 40. Alternatively, the surface characteristics of the die 30 and/or the support member 20 can be selected to produce a faster underfill flow rate through the gap than around the periphery of the die 30. Although the foregoing methods can produce satisfactory results, it may in some cases be difficult and/or expensive to accurately control the aforementioned variables. Furthermore, the underfill material 40 typically provides a permanent bond between the die 30 and the support member 20, making it difficult if not impossible to replace a defective die 30 without destroying the entire package 10.
    • SUMMARY
  • The present invention is directed toward microelectronic packages and methods for forming such packages. A method in accordance with one aspect of the invention includes positioning a microelectronic substrate proximate to a support member, with the microelectronic substrate having a first surface, a second surface facing opposite from the first surface, and a plurality of first connection sites at least proximate to the first surface. The support member can have a plurality of second and third connection sites. The method can further include connecting the microelectronic substrate to the support member by attaching a plurality of electrically conductive couplers between the plurality of first connection sites and the second connection sites, with neighboring conducted couplers being spaced apart to define at least one fluid flow channel, and with the support member and the microelectronic substrate forming a package. The package can then be provided for electrical coupling to other electrical structures via the third connection sites, with the at least one fluid flow channel accessible to a region external to the package. [0007]
  • In another aspect of the invention, flowable, electrically conductive couplers can be disposed at the first connection sites, and a generally non-conductive material can be disposed between the conductive couplers. A gap dimension can be selected based on a target underfill flow rate, and at least a portion of the generally non-conductive material can be removed to form a gap having the selected gap dimension and being positioned between neighboring conductive couplers. The microelectronic substrate and the support member can be connected by attaching the conductive couplers to the second bond sites of the support member, and an underfill material can be flowed into the gap at at least approximately the target underfill material flow rate. [0008]
  • A method in accordance with another aspect of the invention includes providing a first microelectronic substrate having first connection sites carrying first flowable, electrically conductive couplers that define a first plane. A first generally non-conductive material is applied to the first conductive couplers and to the first microelectronic substrate, and at least some of the first generally non-conductive material is removed to recess the first generally non-conductive material from the first plane by a first recess distance. The method can further include providing a second microelectronic substrate having second flowable, electrically conductive couplers defining a second plane spaced apart from the second microelectronic substrate by a second distance different than the first distance. A second generally non-conductive material is applied to the second conductive couplers, and at least some of the second generally non-conductive material is removed from between the second conductive couplers to recess the second generally non-conductive material from the second plane by a second recess distance that is at least approximately the same as the first recess distance. [0009]
  • A method in accordance with still another aspect of the invention includes connecting the microelectronic substrate to the support member by attaching the conductive couplers and disposing at least one generally non-conductive material adjacent to the conductive couplers, with the at least one generally non-conductive material being spaced apart from the support member. In another aspect of the invention, the at least one generally non-conductive material can be a first generally non-conductive material, and the method can further include disposing a second generally non-conductive material adjacent to the support member and the conductive couplers, with the second generally non-conductive material being spaced apart from the first generally non-conductive material. [0010]
  • A method in accordance with yet another aspect of the invention includes providing a first generally non-conductive material between flowable conductive couplers of a microelectronic substrate, with the first generally non-conductive material being recessed to define a flow channel having an inner region and an outer region disposed outwardly from the inner region. A second generally non-conductive material can be disposed on the support member to form a layer having a first region and a second region disposed outwardly from the first region, with the first region having a greater thickness than the second region. The inner region of the flow channel is then engaged with the first region of the second generally non-conductive material, while the second generally non-conductive material is at least partially flowable, and the microelectronic substrate and the support member are moved toward each other while forcing gas within the flow channel generally outwardly to the outer region of the flow channel.[0011]
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a partially schematic, plan view of a microelectronic package formed by a method in accordance with the prior art. [0012]
  • FIG. 2 is a partially schematic, cross-sectional side view of a microelectronic package having fluid flow channels in accordance with an embodiment of the invention. [0013]
  • FIGS. [0014] 3A-3E illustrate a process for forming fluid flow channels in a microelectronic package in accordance with an embodiment of the invention.
  • FIGS. [0015] 4A-4B illustrate a microelectronic package having portions of non-conductive material separated from each other in accordance with another embodiment of the invention.
  • FIG. 5 is a partially schematic, exploded cross-sectional side view of a microelectronic package having a gap positioned to control the flow of underfill material adjacent to a microelectronic substrate. [0016]
  • FIG. 6 is a partially schematic, exploded cross-sectional side view of two packages having gaps formed in accordance with another embodiment of the invention. [0017]
  • FIGS. [0018] 7A-7B illustrate a process for reducing and/or eliminating gaps in a device package having a no-flow underfill material.
    • DETAILED DESCRIPTION
  • The present disclosure describes microelectronic substrate packages and methods for forming such packages. The term “microelectronic substrate” is used throughout to include substrates upon which and/or in which microelectronic circuits or components, data storage elements or layers, and/or vias or conductive lines are or can be fabricated. Many specific details of certain embodiments of the invention are set forth in the following description and in FIGS. [0019] 2-7B to provide a thorough understanding of these embodiments. One skilled in the art, however, will understand that the present invention may have additional embodiments, and that the invention may be practiced without several of the details described below.
  • FIG. 2 is a partially schematic illustration of a [0020] package 110 having fluid flow channels 161 in accordance with an embodiment of the invention. In one aspect of this embodiment, the package 110 can include a microelectronic substrate 130 carried by a support member 120. The microelectronic substrate 130 can include a first surface 131, a second surface 132 facing opposite from the first surface 131, and internal components (not visible in FIG. 2), such as memory circuits and/or linking circuitry, positioned between the first surface 131 and the second surface 132. A plurality of first connection sites 133 (such as bond pads) can be coupled to the internal components and can be positioned proximate to the first surface 131.
  • The [0021] support member 120 can include second connection sites 122 (such as bond pads) coupled to the first connection sites 133 with flowable, electrically conductive couplers 150. In one embodiment, the conductive couplers 150 can include solder balls (formed from solder particles disposed in a flux medium) or other conductive materials that can be reflowed after being applied to the microelectronic substrate 130 to form an electrical connection between the microelectronic substrate 130 and the support member 120. In other embodiments, the conductive couplers 150 can include other features and/or compositions. In any of these embodiments, the support member 120 can include third connection sites 121 (such as bond pads) configured to be electrically coupled to other devices and/or circuits external to the package 110.
  • In a further aspect of an embodiment shown in FIG. 2, the [0022] microelectronic substrate 130 can include a generally non-conductive material 160 disposed in the interstices between neighboring conductive couplers 150. Portions of the non-conductive material 160 can be recessed away from the support member 120 to define at least a portion of the fluid flow channels 161. Accordingly, air and/or other fluids can move through the fluid flow channels 161. In yet a further aspect of this embodiment, the fluid flow channels 161 can be in fluid communication with the environment external to the package 110 so that the fluid within the fluid flow channels 161 is free to move into and/or out of the fluid flow channels 161.
  • In one embodiment, the dimensions of the [0023] fluid flow channel 161 can be selected according to design criteria that account for fluid flow rate, package geometry and/or support for the conductive couplers 150. For example, the fluid flow channel 161 can have a transverse or widthwise dimension W that is determined by the spacing between neighboring conductive couplers 150 and/or by the amount of non-conductive material 160 selected to strengthen the connection between the conductive couplers 160 and the first connection sites 133. The depthwise dimension D of the flow channel 161 can be determined based on the height of the conductive couplers 150 and/or by the amount of non-conductive material 160 selected to strengthen the connection between the conductive couplers 160 and the first connection sites 133. Based on these criteria, the fluid flow channel 161 can have a variety of dimensions, and can range from a relatively small channel (e.g., offset from the sides of neighboring conductive couplers 150 and offset the first surface 131 of the microelectronic substrate 120), to a relatively large channel (extending transversely to expose the sides of neighboring conductive couplers 150, and extending depthwise to expose the first surface 131). When the package 110 includes larger fluid flow channels 161, the non-conductive material 160 can be reduced in size to a small ring around each first connection site 133.
  • The [0024] package 110 can further include an optional adhesive layer 170 disposed around a periphery of the non-conductive material 160. The adhesive layer 170 can provide for an additional connection between the microelectronic substrate 130 and the support member 120 and can constrain the relative thermal expansion of these components as the temperature of the package 110 changes. In one embodiment, the adhesive material 170 can be disposed adjacent to two sides of the microelectronic substrate 130, leaving the regions adjacent to the remaining two sides of the microelectronic substrate 130 open to allow fluid to move into and/or out of the fluid flow channels 161.
  • One feature of an embodiment of the [0025] package 110 described above with reference to FIG. 2 is that the fluid flow channels 161 can be in fluid communication with the environment external to the package 110. An advantage of this feature is that any fluid (such as air or another gas) present in the fluid flow channels 161 as the package 110 is fabricated can freely exit the fluid flow channels 161 as the temperature of the package 110 increases. As a result, the package 110 will be less likely to fail due to the pressure exerted by the expanding fluid within the fluid flow channels 161. As the package 110 cools, fluid can re-enter the fluid flow channels 161 so that the package 110 is not subjected to inwardly directed pressure exerted by the environment around the package 110.
  • Another advantage of the [0026] fluid flow channels 161 is that they can provide an avenue for cooling flow to cool the components of the package 110. Accordingly, the cooling flow can be in more intimate contact with the interior portions of the package 110 than existing cooling flows that contact only the external surfaces of the microelectronic substrate 130 and/or the support member 120. As a result, the components in the package 110 may be less likely to overheat and fail at normal operating temperatures, and may be more likely to survive extreme operating temperatures.
  • FIGS. [0027] 3A-3E schematically illustrate a process for forming a microelectronic package generally similar to that described above with reference to FIG. 2. Beginning with FIG. 3A, the process can include providing a microelectronic substrate 130 having a thickness T1. The microelectronic substrate 130 can include first connection sites 133 carrying conductive couplers 150, such as solder balls. As shown in FIG. 3B, the non-conductive material 160 can be disposed over the first surface 131 of the microelectronic substrate 130 to cover the conductive couplers 150. In one embodiment, the non-conductive material 160 can include one or more strengthening materials, such as FP 4450, available from Dexter Hysol of Seabrook, N.H. In other embodiments, the non-conductive material 160 can include thermoset epoxy polymers, such as those disclosed in U.S. Pat. No. 6,180,527, incorporated herein in its entirety by reference. In still further embodiments, the non-conductive material 160 can include other generally electrically- non-conductive materials.
  • In a further aspect of this embodiment, the [0028] non-conductive material 160 can strengthen the microelectronic substrate 130 and can accordingly allow operations on the microelectronic substrate 130 that would not be practical without the non-conductive material 160. For example, material can be removed from the second surface 132 of the microelectronic substrate 130 to thin the microelectronic substrate 130 and form a new second surface 132 a, as shown in FIG. 3C. The microelectronic substrate 130 can accordingly have a thickness T2 that is less than the initial thickness T1 shown in FIG. 3B. The thinner microelectronic substrate 130 can be easier to cool and can occupy less volume in the devices in which it is installed. In alternate embodiments that do not materially benefit from this feature, the thinning process described above with reference to FIG. 3C can be eliminated.
  • In either of the embodiments described above, at least a portion of the [0029] non-conductive material 160 can be removed to form the fluid flow channels 161 shown in FIG. 2. For example, as shown in FIG. 3D, the non-conductive material 160 can first be smoothed and reduced in thickness, for example, by chemical action, mechanical action or chemical mechanical planarization (CMP). A mask 162 can be positioned over the resulting external surface 165 of the non-conductive material 160. The mask 162 can include apertures 163 aligned with the interstices between neighboring conductive couplers 150. The non-conductive material 160 can be exposed to an etchant or other removing agent to form the fluid flow channels 161. The mask 162 can then be removed and any material positioned over the conductive couplers 150 can be excised, as shown in FIG. 3E to expose the tips of the conductive couplers 150. Accordingly, the conductive couplers 150 can bond to a support member 120 (FIG. 2) to form a microelectronic package. Further details of processes for removing portions of the non-conductive material 160 positioned between the conductive couplers 150 are disclosed in U.S. Pat. No. 6,118,179, incorporated herein in its entirety by reference.
  • In one aspect of an embodiment described above with reference to FIGS. [0030] 3A-3E, an anisotropic etchant can be used to form the flow channels 161, and an isotropic etchant can be used to remove the material positioned directly above the conductive couplers 150. In other embodiments, other combinations of etchants and/or process techniques can be used to remove at least a portion of the non-conductive material 160. In still further embodiments (for example, when the inherent structure of the microelectronic substrate 130 is sufficiently strong), the entirety of the non-conductive material 160 can be removed prior to attaching the microelectronic substrate 130 to the support member 120.
  • FIGS. [0031] 4A-4B illustrate a device package 410 configured in accordance with another embodiment of the invention. Referring first to FIG. 4A, the package 410 can include a support member 120 that carries a microelectronic substrate 130. The microelectronic substrate 130 can include first bond sites 133 and conductive couplers 150 arranged generally as described above with reference to FIGS. 2-3E. A first generally non-conductive material 460 a is positioned in the interstitial regions between neighboring conductive couplers 150. The support member 120 can include second bond sites 122, each of which can optionally carry a quantity of a second generally non-conductive material 460 b, such as WS609 flux, available from Alpha Metals of Jersey City, N.J., and typically referred to in the industry as a “brick.” In one aspect of this embodiment, the second generally non-conductive material 460 b can include a “no-clean” fluxing agent and an epoxy. In other embodiments, the second generally non-conductive material 460 b can include other constituents, such as a water clean flux. In any of these embodiments, an additional quantity of conductive material (such as solder) can be mixed in with the second generally non-conductive material 460 b.
  • Referring now to FIG. 4B, the [0032] microelectronic substrate 130 and the support member 120 can be moved toward each other and heated to reflow the conductive couplers 150 and couple the first connection sites 133 of the microelectronic substrate 130 to the second connection sites 122 of the support member 120. The elevated temperature can also cause the second non-conductive material 460 b to flow outwardly from the second connection sites 122. In one embodiment, the second non-conductive material 460 b can form a continuous layer in the interstices between the conductive couplers 150, adjacent to the support member 120. In another embodiment, the second non-conductive material 460 b can form an isolated meniscus around each conductive coupler 150. In either embodiment, when the second non-conductive material 460 b includes an epoxy or other thermoset material, this material is then cured to a hardened, solid state.
  • In one aspect of an embodiment of the [0033] package 410 described above with reference to FIGS. 4A and 4B, the second non-conductive material 460 b can extend from the support member 120, part-way along the sides of the conductive couplers 150, and the first non-conductive material 460 a can extend from the microelectronic substrate 130, part-way along the sides of the conductive couplers 150 without contacting the first non-conductive material 460 a. Accordingly, the package 410 can include gaps 464 between the first non-conductive material 460 a and the second non-conductive material 460 b. An advantage of this feature is that the gaps 464 can act as cooling flow channels, in a manner generally similar to that described above with reference to FIG. 2. Accordingly, the package 410 can operate more efficiently and/or be less likely to fail when exposed to high temperatures.
  • Another advantage of the [0034] gaps 464 is that they limit the structural connection between the microelectronic substrate 130 and the support member 120 to the link provided by the conductive couplers 150. Accordingly, the microelectronic substrate 130 can be removed from the support member 120, for example, by elevating the temperature of the conductive couplers 150, causing the conductive couplers 150 to reflow. If either the microelectronic substrate 130 or the support member 120 is defective, the defective component can be separated from the package 410 (without damaging the non-defective component) and replaced with another, comparable component.
  • FIG. 5 is a partially exploded, cross-sectional side view of a [0035] package 510 configured in accordance with another embodiment of the invention. In one aspect of this embodiment, the package 510 can include a support member 120 that carries a microelectronic substrate 130. The microelectronic substrate 130 can include conductive couplers 150 positioned on the first connection sites 133 in a manner generally similar to that described above with reference to FIG. 2. The microelectronic substrate 130 can further include a generally non-conductive material 560 positioned in the interstices between the conductive couplers 150.
  • In a further aspect of this embodiment, the outer surfaces of the [0036] conductive couplers 150 can define a plane P and the outer surface of the non-conductive material 560 can be recessed from the plane P to provide a gap 564. The gap 564 can be selectively sized such that when the microelectronic substrate 130 is connected to the support member 120 and an underflow material 540 flows into the gap 564 from a position adjacent to the microelectronic substrate 130, the underflow material 540 will tend to wick more quickly into the gap 564 than around the periphery of the microelectronic substrate 130. For example, the gap 564 can have a depth of about 25 microns in one embodiment. In other embodiments, the gap 564 can have other depths greater than or less than 25 microns. In still further embodiments, the gap 564 can have a size based on the mean diameter of particulates in the underflow material 540. For example, the gap 564 can have a depth that is about three times the mean diameter of such particulates. Suitable underflow materials 540 are available from Locktite Corp. of Rocky Hills, Conn., Nagase America Corp. of New York, N.Y., and Dexter Hysol of Seabrook, N.H.
  • In any of the foregoing embodiments described above with reference to FIG. 5, (and in contrast to the process described above with reference to FIG. 1), the [0037] underflow material 540 flowing through the gap 564 will tend to push out any gas in the gap 564 before wicking around the periphery of the microelectronic substrate 130 and sealing off the gap 564. An advantage of this arrangement is that by reducing and/or eliminating trapped gas between the microelectronic substrate 130 and support member 120, the package 510 will be less likely to fail as it undergoes temperature excursions.
  • FIG. 6 is a partially exploded, cross-sectional side view of two device packages [0038] 610 (shown as a first package 610 a and a second package 610 b) configured in accordance with still another embodiment of the invention. In one aspect of this embodiment, the first package 610 a can include a first support member 620 a that carries a first microelectronic substrate 630 a. The first microelectronic substrate 630 a can include a plurality of first conductive couplers 650 a and a first generally non-conductive material 660 a disposed in the interstices between the first conductive couplers 650 a. The first conductive couplers 650 a can define a plane P1, and the first non-conductive material 660 a can be recessed from the plane P1 to define a gap 664 a. When the first microelectronic substrate 630 a is positioned adjacent to the support member 620 a, an underfill material 640 a can flow through the gap 664 a at a pre-selected rate, in a manner generally similar to that described above with reference to FIG. 5.
  • The [0039] second package 610 b can include a second support member 620 b and a second microelectronic substrate 630 b. The second microelectronic substrate 630 b can include second conductive couplers 650 b that are larger than the first conductive couplers 650 a and that define a plane P2. A second non-conductive material 660 b can be disposed in the interstices between neighboring second conductive couplers 650 b and can be recessed from the plane P2 to define a second gap 664 b.
  • In one aspect of an embodiment shown in FIG. 6, the [0040] second gap 664 b can have approximately the same depth as the first gap 664 a, even though the second conductive couplers 650 b are substantially larger than the first conductive couplers 650 a. Accordingly, the second package 610 b can include a volume of second underflow material 640 b that has approximately the same size as the first underflow material volume 640 a. An advantage of this arrangement is that packages having larger conductive couplers 650 b need not necessarily require larger volumes of underflow material. Accordingly, the cost of packages having larger conductive couplers can be reduced when compared to existing devices.
  • FIGS. [0041] 7A-7B illustrate a process for forming a device package 710 in accordance with still another embodiment of the invention. In one aspect of this embodiment, the package 710 can include a support member 720 and a microelectronic substrate 730. The microelectronic substrate 730 can include conductive couplers 750 and a generally non-conductive material 760 disposed in the interstices between neighboring conductive couplers 750. The generally non-conductive material 760 can be recessed from the outer surfaces of the conductive couplers 750 to form a gap 764.
  • In a further aspect of this embodiment, the [0042] support member 720 can include an upper surface 723, connection sites 722 at least proximate to the upper surface 723, and a generally non-conductive, no-flow underfill material 740 disposed on the upper surface 723 and the second connection sites 722. Suitable no-flow underfill materials are available from Locktite Corp., Nagase America Corp., and Dexter Hysol Corp. The underfill material 740 can have a generally domed shape before the microelectronic substrate 730 is connected to the support member 720. Accordingly, when the microelectronic substrate 730 is brought into contact with the underfill material 740, the underfill material 740 will tend to fill the central portion of the gap 764 before filling the outer portion of the gap 764. As the microelectronic substrate 730 and the support member 720 move closer together, the underfill material 740 forces the gas in the gap 764 generally outwardly. Accordingly, as shown in FIG. 7B, the completed package 710 can have the underfill material 740 completely filling the gap 764. An advantage of this arrangement is that, by reducing and/or eliminating trapped gas between the support member 720 and the microelectronic substrate 730, the package 710 will be less likely to fail during temperature excursions.
  • From the foregoing, it will be appreciated that specific embodiments of the invention have been described herein for purposes of illustration, but that various modifications may be made without deviating from the spirit and scope of the invention. Accordingly, the invention is not limited except as by the appended claims. [0043]

Claims (53)

I/we claim:
1. A method for packaging a microelectronic substrate, comprising:
positioning a microelectronic substrate proximate to a support member, the microelectronic substrate having a first surface, a second surface facing opposite from the first surface, and a plurality of first connection sites at least proximate to the first surface, the support member having a plurality of second and third connection sites;
connecting the microelectronic substrate to the support member by attaching a plurality of electrically conductive couplers between the plurality of first connection sites of the microelectronic substrate and the plurality of second connection sites of the support member, with neighboring conductive couplers being spaced apart to define at least one fluid flow channel, and with the support member and the microelectronic substrate forming a package; and
providing the package for electrical coupling to other electrical structures, with the third connection sites accessible for electrical coupling to the other electrical structures, and with the at least one fluid flow channel accessible to a region external to the package.
2. The method of claim 1, further comprising cooling the microelectronic substrate by passing a flow of gaseous fluid through the at least one fluid flow channel while the package is electrically coupled to the other electrical structures.
3. The method of claim 1, further comprising:
applying the conductive couplers to the first connection sites;
applying a generally non-conductive support material to the first surface of the microelectronic substrate and adjacent to the conductive couplers;
removing material from the second surface of the microelectronic substrate to thin the microelectronic substrate; and
removing at least some of the generally non-conductive support material from between at least some of the conductive couplers to form the at least one fluid flow channel.
4. The method of claim 1, further comprising selecting the conductive couplers to include solder balls.
5. The method of claim 1, further comprising applying an adhesive material at an interface between the microelectronic substrate and the support member, with the adhesive material having at least one opening positioned to allow fluid communication between the at least one fluid flow channel and a region external to the package.
6. The method of claim 1, further comprising:
applying a generally non-conductive material to the first surface of the microelectronic substrate adjacent to the conductive couplers; and
forming the cooling flow channel by etching at least some of the generally non-conductive material from between at least some of the conductive couplers.
7. The method of claim 1, further comprising:
applying a generally non-conductive material to the first surface of the microelectronic substrate and adjacent to the conductive couplers; and
forming the at least one fluid flow channel by etching at least some of the material from between at least some of the conductive couplers to expose at least a portion of the conductive couplers.
8. The method of claim 1, further comprising:
applying a generally non-conductive first material to the first surface of the microelectronic substrate adjacent to the conductive couplers; and
applying a generally non-conductive second material to the support member, with the first and second generally non-conductive materials being separated by a gap, and with the gap defining the at least one fluid flow channel.
9. The method of claim 1, further comprising selecting the microelectronic substrate to include at least one memory device.
10. A method for packaging a microelectronic substrate, comprising:
providing a microelectronic substrate having a first surface, a second surface facing opposite from the first surface, and a plurality of first connection sites at least proximate to the first surface;
disposing flowable, electrically conductive couplers at the first connection sites;
disposing a generally non-conductive material between the conductive couplers;
selecting a gap dimension based on a target underfill material flow rate;
removing at least a portion of the generally non-conductive material to form a gap between neighboring conductive couplers, the gap having the selected gap dimension in a direction generally normal to the first surface of the microelectronic substrate;
connecting the microelectronic substrate to a support member by attaching the conductive couplers to second bond sites of the support member; and
flowing an underfill material into the gap at at least approximately the target underfill material flow rate.
11. The method of claim 10 wherein selecting the gap dimension includes selecting the gap dimension to be at least 25 microns.
12. The method of claim 10 wherein the underfill material includes a plurality of particles having a mean diameter, and wherein selecting the gap dimension includes selecting the gap dimension to be at least three times the mean diameter of the particles.
13. The method of claim 10 wherein the microelectronic substrate has a plurality of edges, and wherein the method further comprises disposing the underfill material along at least one of the edges, further wherein flowing an underfill material into the gap at at least approximately the target underfill material flow rate includes filling the gap before the underfill material wicks completely around the edges of the microelectronic substrate.
14. The method of claim 10, further comprising selecting the conductive couplers to include solder balls.
15. The method of claim 10, further comprising selecting the conductive couplers to include a flux material and a plurality of solder particles disposed in the flux material.
16. The method of claim 10, further comprising removing material from the second surface of the microelectronic substrate to thin the microelectronic substrate before removing at least a portion of the generally non-conductive material.
17. The method of claim 10 wherein removing at least a portion of the generally non-conductive material includes etching at least some of the generally non-conductive material.
18. A method for processing microelectronic substrates, comprising:
providing a first microelectronic substrate having a first surface, a second surface facing opposite from the first surface, and a plurality of first connection sites positioned at least proximate to the first surface, each first connection site carrying a first flowable, electrically conductive coupler, each first conductive coupler having a first outer surface spaced apart from the first surface of the first microelectronic substrate by a first distance, the first outer surfaces defining a first plane;
applying a first generally non-conductive material to the first conductive couplers and the first surface of the first microelectronic substrate;
selecting a first recess distance;
removing at least some of the first generally non-conductive material from between the first conductive couplers to recess the first generally non-conductive material from the first plane by the first recess distance;
providing a second microelectronic substrate having a first surface, a second surface facing opposite from the first surface, and a plurality of second connection sites positioned at least proximate to the first surface of the second microelectronic substrate, each second connection site having a second flowable, electrically conductive coupler, each second conductive coupler having a second outer surface spaced apart from the first surface of the second microelectronic substrate by a second distance different than the first distance, the second outer surfaces defining a second plane;
applying a second generally non-conductive material to the second conductive couplers and the first surface of the second microelectronic substrate;
selecting a second recess distance to be at least approximately the same as the first recess distance; and
removing at least some of the second generally non-conductive material from between the second conductive couplers to recess the second generally non-conductive material from the second plane by the second recess distance.
19. The method of claim 18, further comprising:
removing material from the second surface of the first microelectronic substrate to thin the first microelectronic substrate prior to removing at least some of the first generally non-conductive material; and
removing material from the second surface of the second microelectronic substrate to thin the second microelectronic substrate prior to removing at least some of the second generally non-conductive material.
20. The method of claim 18, further comprising selecting the first and second generally non-conductive materials to have at least approximately the same composition.
21. The method of claim 18, further comprising selecting the first and second conductive couplers to include solder balls.
22. The method of claim 18, further comprising selecting the first and second recess distances to be about 25 microns or more.
23. The method of claim 18, further comprising flowing an underfill material between the first microelectronic substrate and a first support member attached to the first conductive couplers, wherein the underfill material includes a plurality of particles, the particles having a mean diameter, and wherein selecting the first and second recess distances includes selecting the first and second recess distances to be about three times the mean diameter of the particles.
24. A method for forming a microelectronic package, comprising:
positioning a microelectronic substrate proximate to a support member, the microelectronic substrate having a first surface, a second surface facing opposite from the first surface, and a plurality of first connection sites at least proximate to the first surface, the support member having a plurality of second connection sites;
connecting the microelectronic substrate to a support member by attaching conductive couplers between the first connection sites of the microelectronic substrate and the second connection sites of the support member; and
disposing at least one generally non-conductive material adjacent to the conductive couplers, the at least one generally non-conductive material being spaced apart from the support member.
25. The method of claim 24 wherein the at least one generally non-conductive material is a first generally non-conductive material, and wherein the method further comprises disposing a second generally non-conductive material adjacent to the support member and the conductive couplers, the second generally non-conductive material being spaced apart from the first generally non-conductive material.
26. The method of claim 24, further comprising separating the microelectronic substrate from the support member without damaging either the microelectronic substrate or the support member.
27. The method of claim 24, further comprising separating the microelectronic substrate from the support member by elevating a temperature of the conductive couplers.
28. The method of claim 24 wherein the microelectronic substrate is a first microelectronic substrate and wherein the method further comprises removing the first microelectronic substrate from the support member and attaching a second microelectronic substrate to the support member in place of the first microelectronic substrate.
29. The method of claim 24 wherein attaching conductive couplers between the first and second connection sites includes disposing on the second connection sites a flux material, and elevating a temperature of the flux material.
30. The method of claim 24 wherein disposing a first generally non-conductive material adjacent to the conductive couplers includes disposing on the second connection sites a flux material having an epoxy component, and wherein the method further includes curing the epoxy.
31. A method for forming a microelectronic package, comprising:
providing a microelectronic substrate having a first surface, a second surface facing opposite from the first surface, and a plurality of first connection sites positioned at least proximate to the first surface, with each first connection site carrying a flowable conductive coupler, the conductive couplers having an outer surface defining an outer surface plane spaced apart from the first surface, the microelectronic substrate further having a first generally non-conductive material disposed between the conductive couplers, the first generally non-conductive material being recessed from the outer surface plane to define a flow channel between the volumes of flowable conductive material, the flow channel having an inner region and an outer region disposed outwardly from the inner region;
disposing a second generally non-conductive material on a support member, the support member having a plurality of second bond sites, the second generally non-conductive material forming a layer over the second bond sites, the layer having a first region and a second region disposed outwardly from the first region, the first region having a greater thickness than the second region;
engaging the inner region of the flow channel with the first region of the second generally non-conductive material while the second generally non-conductive material is at least partially flowable; and
moving at least one of the microelectronic substrate and the support member toward the other while forcing gas within the flow channel generally outwardly through the flow channel to the outer region of the flow channel.
32. The method of claim 31 wherein disposing the first generally non-conductive material includes disposing an epoxy material.
33. The method of claim 31 wherein disposing the second generally non-conductive material includes disposing an underfill material.
34. The method of claim 31 wherein disposing the second generally non-conductive material includes disposing the second generally non-conductive material to have an at least approximately dome shaped volume.
35. The method of claim 31, further comprising forcing at least approximately all the gas outwardly out of the flow channel.
36. The method of claim 31 wherein the flow channel is one of a plurality of flow channels, each having an inner region and an outer region disposed outwardly from the inner region, and wherein the method further comprises forcing gas within the flow channels generally outwardly through the flow channels to the outer regions of the flow channels.
37. The method of claim 31, further comprising filling the flow channel with the second generally non-conductive material.
38. A microelectronic package, comprising:
a microelectronic substrate having a first surface, a second surface facing opposite from the first surface, and a plurality of first connection sites at least proximate to the first surface;
a support member having a plurality of second connection sites positioned proximate to the first connection sites of the microelectronic substrate, the support member further having a plurality of third connection sites accessible for electrical coupling to other electrical structures;
a plurality of electrically conductive couplers connected between the plurality of first connection sites of the microelectronic substrate and the plurality of second connection sites of the support member, with neighboring conductive couplers being spaced apart to define at least one flow channel, the at least one flow channel being in fluid communication with a region external to the microelectronic substrate; and
a generally non-conductive material disposed on the microelectronic substrate between neighboring conductive couplers, the generally non-conductive material being offset from the support member to define a portion of the at least one flow channel.
39. The package of claim 38 wherein the microelectronic substrate has a peripheral region and wherein the package further comprises an adhesive film disposed between the microelectronic substrate and the support member at the peripheral region, the adhesive film being positioned to allow cooling flow to pass into the cooling flow channels.
40. The package of claim 38 wherein the conductive couplers include solder balls.
41. The package of claim 38 wherein the at least one of the flow channel has a dimension generally normal to the microelectronic substrate of about 25 microns.
42. A plurality of microelectronic device assemblies, comprising:
a first microelectronic device assembly that includes:
a first microelectronic substrate having a first surface, a second surface facing opposite from the first surface, and a plurality of first connection sites positioned at least proximate to the first surface, each first connection site carrying a first flowable, electrically conductive coupler, each first conductive coupler having a first outer surface spaced apart from the first surface of the first microelectronic substrate by a first distance, the first outer surfaces defining a first plane;
a first generally non-conductive material applied to the first conductive couplers and the first surface of the first microelectronic substrate and recessed from the first plane by a first recess distance;
a second microelectronic device assembly that includes:
a second microelectronic substrate having a first surface, a second surface facing opposite from the first surface, and a plurality of second connection sites positioned at least proximate to the first surface, each second connection site having a second flowable, electrically conductive coupler, each second conductive coupler having a second outer surface spaced apart from the first surface of the second microelectronic substrate by a second distance different than the first distance, the second outer surfaces defining a second plane; and
a second generally non-conductive material applied to the second conductive couplers and the first surface of the second microelectronic substrate, the second support material being recessed from the second plane by a second recess distance at least approximately the same as the first recess distance.
43. The assemblies of claim 42 wherein the first microelectronic device assembly further includes a first support member having third bond sites, with the first conductive couplers connected between the third bond sites and the first bond sites of the first microelectronic substrate; and
wherein the second microelectronic device assembly further includes a second support member having fourth bond sites, with the second conductive couplers connected between the fourth bond sites and the second bond sites of the second microelectronic substrate.
44. The assemblies of claim 42 wherein the first microelectronic device assembly further includes a first support member having third bond sites, with the first conductive couplers connected between the third bond sites and the first bond sites of the first microelectronic substrate, further wherein neighboring first conductive couplers are spaced apart to define at least one first flow channel; and
wherein the second microelectronic device assembly further includes a second support member having fourth bond sites, with the second conductive couplers connected between the fourth bond sites and the second bond sites of the second microelectronic substrate, further wherein neighboring second conductive couplers are spaced apart to define at least one second flow channel.
45. The assemblies of claim 42 wherein the first recess distance is about 25 microns or more.
46. The assemblies of claim 42 wherein the first microelectronic device assembly includes a first support member bonded to the first conductive couplers, and wherein the first microelectronic device assembly further includes a first underfill material between the first support member and the first microelectronic substrate, the first underfill material having particles with a mean diameter, the first recess distance being about three times the mean diameter or more.
47. The method of claim 42 wherein the first and second conductive couplers include solder balls.
48. A microelectronic package, comprising:
a microelectronic substrate having a first surface, a second surface facing opposite from the first surface, and a plurality of first connection sites at least proximate to the first surface, each first connection site carrying a flowable, electrically conductive coupler;
a support member having second connection sites attached to the conductive couplers; and
at least one generally non-conductive material adjacent to the conductive couplers, the at least one generally non-conductive material being spaced apart from the support member.
49. The package of claim 48 wherein the at least one generally non-conductive material includes a first generally non-conductive material, and wherein the support member includes a second generally non-conductive material disposed adjacent to the conductive couplers and spaced apart from the first generally non-conductive material.
50. The package of claim 48 wherein at least one of the conductive couplers has a first interface surface adjacent to one of the first connection sites, a second interface surface adjacent to one of the second connection sites, and an intermediate surface between the at least one and second interface surfaces, and wherein the at least one generally non-conductive material extends outwardly along the intermediate surface from the first connection site.
51. The package of claim 48 wherein the at least one generally non-conductive material defines at least one surface of at least one flow channel.
52. The package of claim 48 wherein the at least one generally non-conductive material includes an epoxy.
53. The package of claim 48 wherein the conductive couplers include solder balls.
US10/190,019 2002-07-05 2002-07-05 Microelectronic device packages and methods for controlling the disposition of non-conductive materials in such packages Expired - Lifetime US6673649B1 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
US10/190,019 US6673649B1 (en) 2002-07-05 2002-07-05 Microelectronic device packages and methods for controlling the disposition of non-conductive materials in such packages
US10/701,128 US7087995B2 (en) 2002-07-05 2003-11-03 Microelectronic device packages and methods for controlling the disposition of non-conductive materials in such packages
US11/248,914 US7470563B2 (en) 2002-07-05 2005-10-11 Microelectronic device packages and methods for controlling the disposition of non-conductive materials in such packages

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/190,019 US6673649B1 (en) 2002-07-05 2002-07-05 Microelectronic device packages and methods for controlling the disposition of non-conductive materials in such packages

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US10/701,128 Division US7087995B2 (en) 2002-07-05 2003-11-03 Microelectronic device packages and methods for controlling the disposition of non-conductive materials in such packages

Publications (2)

Publication Number Publication Date
US6673649B1 US6673649B1 (en) 2004-01-06
US20040005732A1 true US20040005732A1 (en) 2004-01-08

Family

ID=29735274

Family Applications (3)

Application Number Title Priority Date Filing Date
US10/190,019 Expired - Lifetime US6673649B1 (en) 2002-07-05 2002-07-05 Microelectronic device packages and methods for controlling the disposition of non-conductive materials in such packages
US10/701,128 Expired - Fee Related US7087995B2 (en) 2002-07-05 2003-11-03 Microelectronic device packages and methods for controlling the disposition of non-conductive materials in such packages
US11/248,914 Expired - Fee Related US7470563B2 (en) 2002-07-05 2005-10-11 Microelectronic device packages and methods for controlling the disposition of non-conductive materials in such packages

Family Applications After (2)

Application Number Title Priority Date Filing Date
US10/701,128 Expired - Fee Related US7087995B2 (en) 2002-07-05 2003-11-03 Microelectronic device packages and methods for controlling the disposition of non-conductive materials in such packages
US11/248,914 Expired - Fee Related US7470563B2 (en) 2002-07-05 2005-10-11 Microelectronic device packages and methods for controlling the disposition of non-conductive materials in such packages

Country Status (1)

Country Link
US (3) US6673649B1 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040057649A1 (en) * 2002-09-24 2004-03-25 Steven Towle Electrooptic assembly
US20060057774A1 (en) * 2002-07-05 2006-03-16 Hiatt William M Microelectronic device packages and methods for controlling the disposition of non-conductive materials in such packages
FR2919426A1 (en) * 2007-07-23 2009-01-30 Commissariat Energie Atomique PROCESS FOR COATING TWO HYBRID ELEMENTS BETWEEN THEM USING A BRASURE MATERIAL
WO2018031457A1 (en) * 2016-08-08 2018-02-15 Invensas Corporation Warpage balancing in thin packages

Families Citing this family (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7109588B2 (en) * 2002-04-04 2006-09-19 Micron Technology, Inc. Method and apparatus for attaching microelectronic substrates and support members
US7115998B2 (en) * 2002-08-29 2006-10-03 Micron Technology, Inc. Multi-component integrated circuit contacts
US7067903B2 (en) * 2002-11-07 2006-06-27 Kabushiki Kaisha Kobe Seiko Sho Heat spreader and semiconductor device and package using the same
SG143931A1 (en) * 2003-03-04 2008-07-29 Micron Technology Inc Microelectronic component assemblies employing lead frames having reduced-thickness inner lengths
DE10318074B4 (en) * 2003-04-17 2009-05-20 Qimonda Ag Process for making BOC module assemblies with improved mechanical properties
SG153627A1 (en) 2003-10-31 2009-07-29 Micron Technology Inc Reduced footprint packaged microelectronic components and methods for manufacturing such microelectronic components
US6908789B1 (en) * 2003-12-15 2005-06-21 Intel Corporation Method of making a microelectronic assembly
SG145547A1 (en) * 2004-07-23 2008-09-29 Micron Technology Inc Microelectronic component assemblies with recessed wire bonds and methods of making same
TWI237370B (en) * 2004-07-30 2005-08-01 Advanced Semiconductor Eng Chip package structure and process for fabricating the same
US7157310B2 (en) * 2004-09-01 2007-01-02 Micron Technology, Inc. Methods for packaging microfeature devices and microfeature devices formed by such methods
US20060162850A1 (en) * 2005-01-24 2006-07-27 Micron Technology, Inc. Methods and apparatus for releasably attaching microfeature workpieces to support members
US8278751B2 (en) * 2005-02-08 2012-10-02 Micron Technology, Inc. Methods of adhering microfeature workpieces, including a chip, to a support member
US7169248B1 (en) * 2005-07-19 2007-01-30 Micron Technology, Inc. Methods for releasably attaching support members to microfeature workpieces and microfeature assemblies formed using such methods
US7807505B2 (en) * 2005-08-30 2010-10-05 Micron Technology, Inc. Methods for wafer-level packaging of microfeature devices and microfeature devices formed using such methods
US20070045812A1 (en) * 2005-08-31 2007-03-01 Micron Technology, Inc. Microfeature assemblies including interconnect structures and methods for forming such interconnect structures
US7745944B2 (en) 2005-08-31 2010-06-29 Micron Technology, Inc. Microelectronic devices having intermediate contacts for connection to interposer substrates, and associated methods of packaging microelectronic devices with intermediate contacts
US7749806B2 (en) * 2005-09-22 2010-07-06 Chipmos Technologies Inc. Fabricating process of a chip package structure
US20070148820A1 (en) * 2005-12-22 2007-06-28 Micron Technology, Inc. Microelectronic devices and methods for manufacturing microelectronic devices
SG133445A1 (en) 2005-12-29 2007-07-30 Micron Technology Inc Methods for packaging microelectronic devices and microelectronic devices formed using such methods
US7749349B2 (en) * 2006-03-14 2010-07-06 Micron Technology, Inc. Methods and systems for releasably attaching support members to microfeature workpieces
SG136009A1 (en) 2006-03-29 2007-10-29 Micron Technology Inc Packaged microelectronic devices recessed in support member cavities, and associated methods
US7910385B2 (en) 2006-05-12 2011-03-22 Micron Technology, Inc. Method of fabricating microelectronic devices
US8030754B2 (en) * 2007-01-31 2011-10-04 Hewlett-Packard Development Company, L.P. Chip cooling channels formed in wafer bonding gap
US7955898B2 (en) 2007-03-13 2011-06-07 Micron Technology, Inc. Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices
DE102010023003A1 (en) * 2010-06-08 2012-05-10 Markus Gruber Semiconductor component with integrated chamber for a coolant and method for producing a semiconductor component with integrated chamber for a coolant and recording device for receiving such a semiconductor component
JP5965185B2 (en) * 2012-03-30 2016-08-03 デクセリアルズ株式会社 Circuit connection material and method of manufacturing semiconductor device using the same
US9041215B2 (en) * 2013-03-12 2015-05-26 Taiwan Semiconductor Manufacturing Company, Ltd. Single mask package apparatus and method
US9023691B2 (en) 2013-07-15 2015-05-05 Invensas Corporation Microelectronic assemblies with stack terminals coupled by connectors extending through encapsulation
US9034696B2 (en) 2013-07-15 2015-05-19 Invensas Corporation Microelectronic assemblies having reinforcing collars on connectors extending through encapsulation
US8883563B1 (en) 2013-07-15 2014-11-11 Invensas Corporation Fabrication of microelectronic assemblies having stack terminals coupled by connectors extending through encapsulation
US9214454B2 (en) 2014-03-31 2015-12-15 Invensas Corporation Batch process fabrication of package-on-package microelectronic assemblies
DE112014006844T5 (en) * 2014-07-28 2017-04-13 GM Global Technology Operations LLC Reinforced gluing systems and methods

Family Cites Families (72)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR920008251B1 (en) * 1988-09-26 1992-09-25 가부시기가이샤 히다찌세이사꾸쇼 Apparatus which cools an electro-device
JPH02304958A (en) * 1989-05-19 1990-12-18 Hitachi Ltd Electronic circuit device
JP2675173B2 (en) * 1990-03-02 1997-11-12 株式会社日立製作所 Electronic device cooling system
JP3000307B2 (en) * 1991-08-28 2000-01-17 株式会社日立製作所 Semiconductor device with cooling device and method of manufacturing the same
JP2515200B2 (en) * 1991-12-16 1996-07-10 スタンレー電気株式会社 Lightwave distance measuring device for vehicles
GB9301049D0 (en) * 1993-01-20 1993-03-10 The Technology Partnership Plc Mounting assembly
US5600203A (en) * 1993-04-26 1997-02-04 Futaba Denshi Kogyo Kabushiki Kaisha Airtight envelope for image display panel, image display panel and method for producing same
US5774334A (en) * 1994-08-26 1998-06-30 Hitachi, Ltd. Low thermal resistant, fluid-cooled semiconductor module
US5864178A (en) * 1995-01-12 1999-01-26 Kabushiki Kaisha Toshiba Semiconductor device with improved encapsulating resin
US5677566A (en) 1995-05-08 1997-10-14 Micron Technology, Inc. Semiconductor chip package
JPH08335774A (en) * 1995-06-06 1996-12-17 Ibiden Co Ltd Method and structure for mounting electronic device
SG48462A1 (en) * 1995-10-26 1998-04-17 Ibm Lead protective coating composition process and structure thereof
US6790473B2 (en) * 1995-10-26 2004-09-14 International Business Machines Corporation Lead protective coating composition, process and structure thereof
US5733800A (en) 1996-05-21 1998-03-31 Micron Technology, Inc. Underfill coating for LOC package
US5866953A (en) 1996-05-24 1999-02-02 Micron Technology, Inc. Packaged die on PCB with heat sink encapsulant
US5980977A (en) * 1996-12-09 1999-11-09 Pinnacle Research Institute, Inc. Method of producing high surface area metal oxynitrides as substrates in electrical energy storage
JP3572833B2 (en) 1996-12-19 2004-10-06 株式会社デンソー Method for manufacturing resin-encapsulated semiconductor device
US5891753A (en) 1997-01-24 1999-04-06 Micron Technology, Inc. Method and apparatus for packaging flip chip bare die on printed circuit boards
JPH10229059A (en) * 1997-02-17 1998-08-25 Mitsubishi Electric Corp Semiconductor device and manufacture thereof
US6180696B1 (en) * 1997-02-19 2001-01-30 Georgia Tech Research Corporation No-flow underfill of epoxy resin, anhydride, fluxing agent and surfactant
US6008996A (en) 1997-04-07 1999-12-28 Micron Technology, Inc. Interdigitated leads-over-chip lead frame, device, and method for supporting an integrated circuit die
US6271582B1 (en) 1997-04-07 2001-08-07 Micron Technology, Inc. Interdigitated leads-over-chip lead frame, device, and method for supporting an integrated circuit die
JPH10294418A (en) * 1997-04-21 1998-11-04 Oki Electric Ind Co Ltd Semiconductor device
US6159764A (en) 1997-07-02 2000-12-12 Micron Technology, Inc. Varied-thickness heat sink for integrated circuit (IC) packages and method of fabricating IC packages
US6107122A (en) 1997-08-04 2000-08-22 Micron Technology, Inc. Direct die contact (DDC) semiconductor package
US6048744A (en) 1997-09-15 2000-04-11 Micron Technology, Inc. Integrated circuit package alignment feature
US6037658A (en) * 1997-10-07 2000-03-14 International Business Machines Corporation Electronic package with heat transfer means
US6441487B2 (en) 1997-10-20 2002-08-27 Flip Chip Technologies, L.L.C. Chip scale package using large ductile solder balls
US6097087A (en) 1997-10-31 2000-08-01 Micron Technology, Inc. Semiconductor package including flex circuit, interconnects and dense array external contacts
US6046496A (en) 1997-11-04 2000-04-04 Micron Technology Inc Chip package
US5989941A (en) 1997-12-12 1999-11-23 Micron Technology, Inc. Encapsulated integrated circuit packaging
US6049125A (en) 1997-12-29 2000-04-11 Micron Technology, Inc. Semiconductor package with heat sink and method of fabrication
US6002165A (en) 1998-02-23 1999-12-14 Micron Technology, Inc. Multilayered lead frame for semiconductor packages
US6314639B1 (en) 1998-02-23 2001-11-13 Micron Technology, Inc. Chip scale package with heat spreader and method of manufacture
US5933713A (en) 1998-04-06 1999-08-03 Micron Technology, Inc. Method of forming overmolded chip scale package and resulting product
US6072233A (en) 1998-05-04 2000-06-06 Micron Technology, Inc. Stackable ball grid array package
US6075288A (en) 1998-06-08 2000-06-13 Micron Technology, Inc. Semiconductor package having interlocking heat sinks and method of fabrication
US6288451B1 (en) * 1998-06-24 2001-09-11 Vanguard International Semiconductor Corporation Flip-chip package utilizing a printed circuit board having a roughened surface for increasing bond strength
US6215175B1 (en) 1998-07-06 2001-04-10 Micron Technology, Inc. Semiconductor package having metal foil die mounting plate
US6326687B1 (en) 1998-09-01 2001-12-04 Micron Technology, Inc. IC package with dual heat spreaders
US6048755A (en) 1998-11-12 2000-04-11 Micron Technology, Inc. Method for fabricating BGA package using substrate with patterned solder mask open in die attach area
US6232666B1 (en) 1998-12-04 2001-05-15 Mciron Technology, Inc. Interconnect for packaging semiconductor dice and fabricating BGA packages
US6081429A (en) 1999-01-20 2000-06-27 Micron Technology, Inc. Test interposer for use with ball grid array packages assemblies and ball grid array packages including same and methods
US6252772B1 (en) 1999-02-10 2001-06-26 Micron Technology, Inc. Removable heat sink bumpers on a quad flat package
US6310390B1 (en) 1999-04-08 2001-10-30 Micron Technology, Inc. BGA package and method of fabrication
US6239484B1 (en) * 1999-06-09 2001-05-29 International Business Machines Corporation Underfill of chip-under-chip semiconductor modules
US6352881B1 (en) * 1999-07-22 2002-03-05 National Semiconductor Corporation Method and apparatus for forming an underfill adhesive layer
US6122171A (en) 1999-07-30 2000-09-19 Micron Technology, Inc. Heat sink chip package and method of making
US6180527B1 (en) 1999-08-09 2001-01-30 Micron Technology, Inc. Method and apparatus for thinning article, and article
JP3518434B2 (en) * 1999-08-11 2004-04-12 株式会社日立製作所 Multi-chip module cooling system
US6338980B1 (en) * 1999-08-13 2002-01-15 Citizen Watch Co., Ltd. Method for manufacturing chip-scale package and manufacturing IC chip
US6118179A (en) 1999-08-27 2000-09-12 Micron Technology, Inc. Semiconductor component with external contact polymer support member and method of fabrication
US6208519B1 (en) 1999-08-31 2001-03-27 Micron Technology, Inc. Thermally enhanced semiconductor package
US6303981B1 (en) 1999-09-01 2001-10-16 Micron Technology, Inc. Semiconductor package having stacked dice and leadframes and method of fabrication
US6373142B1 (en) * 1999-11-15 2002-04-16 Lsi Logic Corporation Method of adding filler into a non-filled underfill system by using a highly filled fillet
US6337513B1 (en) * 1999-11-30 2002-01-08 International Business Machines Corporation Chip packaging system and method using deposited diamond film
US6614122B1 (en) * 2000-09-29 2003-09-02 Intel Corporation Controlling underfill flow locations on high density packages using physical trenches and dams
US6459581B1 (en) * 2000-12-19 2002-10-01 Harris Corporation Electronic device using evaporative micro-cooling and associated methods
JP2003051568A (en) * 2001-08-08 2003-02-21 Nec Corp Semiconductor device
SG104293A1 (en) * 2002-01-09 2004-06-21 Micron Technology Inc Elimination of rdl using tape base flip chip on flex for die stacking
US6673649B1 (en) * 2002-07-05 2004-01-06 Micron Technology, Inc. Microelectronic device packages and methods for controlling the disposition of non-conductive materials in such packages
US6794225B2 (en) * 2002-12-20 2004-09-21 Intel Corporation Surface treatment for microelectronic device substrate
US7301222B1 (en) * 2003-02-12 2007-11-27 National Semiconductor Corporation Apparatus for forming a pre-applied underfill adhesive layer for semiconductor wafer level chip-scale packages
US6916684B2 (en) * 2003-03-18 2005-07-12 Delphi Technologies, Inc. Wafer-applied underfill process
US7239024B2 (en) * 2003-04-04 2007-07-03 Thomas Joel Massingill Semiconductor package with recess for die
US6908789B1 (en) * 2003-12-15 2005-06-21 Intel Corporation Method of making a microelectronic assembly
DE102004011203B4 (en) * 2004-03-04 2010-09-16 Robert Bosch Gmbh Method for mounting semiconductor chips and corresponding semiconductor chip arrangement
US7015592B2 (en) * 2004-03-19 2006-03-21 Intel Corporation Marking on underfill
US7199466B2 (en) * 2004-05-03 2007-04-03 Intel Corporation Package design using thermal linkage from die to printed circuit board
US7459345B2 (en) * 2004-10-20 2008-12-02 Mutual-Pak Technology Co., Ltd. Packaging method for an electronic element
US7067350B1 (en) * 2005-01-31 2006-06-27 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacturing a semiconductor device using electrical contacts formed in an isolation layer
JP4535969B2 (en) * 2005-08-24 2010-09-01 新光電気工業株式会社 Semiconductor device

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060057774A1 (en) * 2002-07-05 2006-03-16 Hiatt William M Microelectronic device packages and methods for controlling the disposition of non-conductive materials in such packages
US7470563B2 (en) * 2002-07-05 2008-12-30 Micron Technology, Inc. Microelectronic device packages and methods for controlling the disposition of non-conductive materials in such packages
US20040057649A1 (en) * 2002-09-24 2004-03-25 Steven Towle Electrooptic assembly
US7039263B2 (en) * 2002-09-24 2006-05-02 Intel Corporation Electrooptic assembly
FR2919426A1 (en) * 2007-07-23 2009-01-30 Commissariat Energie Atomique PROCESS FOR COATING TWO HYBRID ELEMENTS BETWEEN THEM USING A BRASURE MATERIAL
WO2009016304A3 (en) * 2007-07-23 2009-04-16 Commissariat Energie Atomique Method for coating two elements hybridized by means of a soldering material
US7846770B2 (en) 2007-07-23 2010-12-07 Commissariat A L'energie Atomique Method for coating two elements hybridized by means of a soldering material
WO2018031457A1 (en) * 2016-08-08 2018-02-15 Invensas Corporation Warpage balancing in thin packages
CN109564913A (en) * 2016-08-08 2019-04-02 伊文萨思公司 Warpage balance in thin encapsulation

Also Published As

Publication number Publication date
US20060057774A1 (en) 2006-03-16
US7470563B2 (en) 2008-12-30
US6673649B1 (en) 2004-01-06
US20040101991A1 (en) 2004-05-27
US7087995B2 (en) 2006-08-08

Similar Documents

Publication Publication Date Title
US7470563B2 (en) Microelectronic device packages and methods for controlling the disposition of non-conductive materials in such packages
CN101904230B (en) The methods of fluxless micro-piercing of solder ball and the device of gained
US20200140267A1 (en) Seal for microelectronic assembly
US7566649B2 (en) Compressible films surrounding solder connectors
CN105967137B (en) Alleviate the structures and methods of welding offset for crystal wafer chip dimension encapsulation part (WLCSP) application
US7063127B2 (en) Method and apparatus for chip-cooling
US6638638B2 (en) Hollow solder structure having improved reliability and method of manufacturing same
US20090051029A1 (en) Flip-chip type semiconductor device
US8884432B2 (en) Substrate and assembly thereof with dielectric removal for increased post height
JP2006041532A (en) Cap wafer having hollow part, semiconductor package using same, and manufacturing method of cap wafer
CN103762187A (en) Chip packaging method and structure
US10679966B2 (en) Gallium liquid metal embrittlement for device rework
US10315914B2 (en) Reconstructed wafer based devices with embedded environmental sensors and process for making same
US20060099736A1 (en) Flip chip underfilling
JP2005340448A (en) Semiconductor device, its manufacturing method, circuit board, and electronic apparatus
JP2005340450A (en) Semiconductor device, its manufacturing method, circuit board, and electronic apparatus
JP2009049115A (en) Semiconductor device, and manufacturing method thereof
JP2006332385A (en) Method and device for mounting semiconductor device
KR20080051658A (en) Printed circuit board, method of manufacturing the printed circuit board, semiconductor package having the printed circuit board and method of manufacturing the semiconductor package
JP4416618B2 (en) Semiconductor device package and manufacturing method thereof
JP5271982B2 (en) Semiconductor device
JP4845664B2 (en) Coating device
JP3648238B2 (en) Manufacturing method of semiconductor device
JP2007335480A (en) Semiconductor device and manufacturing method therefor
CN117096106A (en) Package and method of forming the same

Legal Events

Date Code Title Description
AS Assignment

Owner name: MICRON TECHNOLOGY, INC., IDAHO

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:HIATT, WILLIAM MARK;FARNWORTH, WARREN;REEL/FRAME:013086/0583;SIGNING DATES FROM 20020607 TO 20020628

FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

STCF Information on status: patent grant

Free format text: PATENTED CASE

CC Certificate of correction
FPAY Fee payment

Year of fee payment: 4

FPAY Fee payment

Year of fee payment: 8

FPAY Fee payment

Year of fee payment: 12

AS Assignment

Owner name: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT, CALIFORNIA

Free format text: SECURITY INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:038669/0001

Effective date: 20160426

Owner name: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGEN

Free format text: SECURITY INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:038669/0001

Effective date: 20160426

AS Assignment

Owner name: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT, MARYLAND

Free format text: PATENT SECURITY AGREEMENT;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:038954/0001

Effective date: 20160426

Owner name: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL

Free format text: PATENT SECURITY AGREEMENT;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:038954/0001

Effective date: 20160426

AS Assignment

Owner name: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT, CALIFORNIA

Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:043079/0001

Effective date: 20160426

Owner name: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGEN

Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:043079/0001

Effective date: 20160426

AS Assignment

Owner name: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT, ILLINOIS

Free format text: SECURITY INTEREST;ASSIGNORS:MICRON TECHNOLOGY, INC.;MICRON SEMICONDUCTOR PRODUCTS, INC.;REEL/FRAME:047540/0001

Effective date: 20180703

Owner name: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT, IL

Free format text: SECURITY INTEREST;ASSIGNORS:MICRON TECHNOLOGY, INC.;MICRON SEMICONDUCTOR PRODUCTS, INC.;REEL/FRAME:047540/0001

Effective date: 20180703

AS Assignment

Owner name: MICRON TECHNOLOGY, INC., IDAHO

Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT;REEL/FRAME:047243/0001

Effective date: 20180629

AS Assignment

Owner name: MICRON TECHNOLOGY, INC., IDAHO

Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT;REEL/FRAME:050937/0001

Effective date: 20190731

AS Assignment

Owner name: MICRON TECHNOLOGY, INC., IDAHO

Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT;REEL/FRAME:051028/0001

Effective date: 20190731

Owner name: MICRON SEMICONDUCTOR PRODUCTS, INC., IDAHO

Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT;REEL/FRAME:051028/0001

Effective date: 20190731