US20040016969A1 - Silicon on isulator (SOI) transistor and methods of fabrication - Google Patents
Silicon on isulator (SOI) transistor and methods of fabrication Download PDFInfo
- Publication number
- US20040016969A1 US20040016969A1 US10/426,261 US42626103A US2004016969A1 US 20040016969 A1 US20040016969 A1 US 20040016969A1 US 42626103 A US42626103 A US 42626103A US 2004016969 A1 US2004016969 A1 US 2004016969A1
- Authority
- US
- United States
- Prior art keywords
- silicon
- single crystalline
- silicon alloy
- alloy film
- amorphous
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 110
- 239000010703 silicon Substances 0.000 title claims abstract description 110
- 238000000034 method Methods 0.000 title claims description 60
- 238000004519 manufacturing process Methods 0.000 title abstract description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 109
- 229910000676 Si alloy Inorganic materials 0.000 claims abstract description 89
- 229910021419 crystalline silicon Inorganic materials 0.000 claims abstract description 83
- 239000000758 substrate Substances 0.000 claims abstract description 55
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 48
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 46
- 238000002425 crystallisation Methods 0.000 claims description 28
- 230000008025 crystallization Effects 0.000 claims description 28
- 239000004065 semiconductor Substances 0.000 claims description 25
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 12
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- 238000005498 polishing Methods 0.000 claims description 3
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 3
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 2
- 229920005591 polysilicon Polymers 0.000 claims 2
- 239000012212 insulator Substances 0.000 abstract description 13
- 239000010410 layer Substances 0.000 description 68
- 235000012431 wafers Nutrition 0.000 description 11
- 238000007517 polishing process Methods 0.000 description 5
- 235000012239 silicon dioxide Nutrition 0.000 description 5
- 239000000377 silicon dioxide Substances 0.000 description 5
- 238000005468 ion implantation Methods 0.000 description 4
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 4
- 238000000151 deposition Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 239000007943 implant Substances 0.000 description 3
- 238000010899 nucleation Methods 0.000 description 3
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 239000007772 electrode material Substances 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- 208000031872 Body Remains Diseases 0.000 description 1
- 229910020750 SixGey Inorganic materials 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 239000012297 crystallization seed Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000007521 mechanical polishing technique Methods 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 125000004430 oxygen atom Chemical group O* 0.000 description 1
- 239000002002 slurry Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78639—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a drain or source connected to a bulk conducting substrate
Definitions
- the present invention relates to the field of semiconductor devices and more specifically to a silicon on insulator (SOI) transistor and methods of fabrication.
- SOI silicon on insulator
- FIG. 1 illustrates a standard partially depleted silicon on insulator (SOI) transistor 100 .
- SOI transistor 100 includes a single crystalline silicon substrate 102 having an insulating layer 104 , such as a buried oxide formed thereon.
- a single crystalline silicon film body 106 is formed on the insulating layer 104 .
- a gate dielectric layer 108 is formed on the single crystalline silicon body 106 and a gate electrode 110 formed on the gate dielectric 108 .
- Source and drain regions 112 and 114 are formed in silicon body 106 along laterally opposite sides of gate electrode 110 .
- SOI substrates where an single crystalline silicon body 106 is formed on an insulating layer 104 which inturn is formed on a single crystalline silicon substrate.
- SIMOX silicon on insulator
- oxygen atoms are implanted at a high dose into a single crystalline silicon substrate and annealed to form the buried oxide 104 within the substrate.
- the portion of the single crystalline silicon substrate above the buried oxide becomes the silicon body.
- Another technique currently used to form SOI substrates is an epitaxial silicon film transferred technique.
- Another technique currently used to form SOI substrates is generally referred to as bonded SOI.
- a first silicon wafer has a thin oxide grown on its surface that will later serve as the buried oxide in the SOI structure.
- a high dose hydrogen implant is done to form a high stress region below the silicon wafer surface.
- This first wafer is then flipped over and bonded to the surface of a second silicon wafer.
- the first wafer is then cleaved along the high stress plane created by the hydrogen implant. This results in the SOI structure with a thin silicon layer on top, buried oxide underneath, all on top of a single crystal silicon substrate.
- the silicon body 106 of an SOI transistor formed with these techniques have thicknesses of greater than 100 nanometers.
- the SOI transistor is in operation and “turned ON” and the channel region 120 of the device inverts into the conductivity of the source/drain regions to form a conductive channel therebetween the inverted conductive channel region 120 does not completely invert or deplete the entire thickness of the silicon body.
- the SOI transistor is considered a partially depleted SOI transistor and not a fully depleted transistor.
- the silicon body film In order to fully deplete the silicon body, the silicon body film would need to be less than 30 nm.
- a fully depleted SOI transistor has better electrical performance and characteristics than does a partially depleted SOI transistor. As such, present techniques are unable to fabricate fully depleted SOI transistors.
- FIG. 1 is an illustration of a cross-sectional view of a prior art partially depleted silicon on insulator (SOI) transistor.
- SOI silicon on insulator
- FIG. 2 is an illustration of an silicon on insulator (SOI) transistor in accordance with an embodiment of the present invention.
- FIGS. 3 A- 3 H illustrates a method of forming an SOI transistor in accordance with an embodiment of the present invention.
- FIGS. 4 A- 4 F illustrates a method of forming an SOI transistor in accordance with an embodiment of the present invention.
- the present invention is a novel silicon on insulator (SOI) transistor and its method of fabrication.
- SOI silicon on insulator
- the present invention is a novel SOI transistor and its method of fabrication.
- the SOI transistor is fabricated utilizing the lateral crystallization of a thin deposited amorphous or polycrystalline silicon or silicon alloy that contacts a single crystalline silicon substrate through a small seed window in the insulating layer.
- the process of the present invention can be used to form very thin (less than 30 nanometers) and uniform thickness single crystalline silicon films for the body of the transistor enabling fully depleted SOI transistors to be fabricated across a wafer.
- a polished stop layer along with a polishing planarization step are used to precisely control the thickness and uniformity of the silicon or silicon alloy body.
- Transistor 200 includes a single crystalline silicon substrate 202 .
- Single crystalline silicon substrate 202 can include a top deposited silicon or silicon alloy epitaxial film.
- An insulating layer 204 such as silicon dioxide or silicon nitride, is formed on the single crystalline silicon substrate 202 .
- a semiconductor body film 206 is formed on the insulating layer 204 .
- Semiconductor body film 206 can be a silicon film or a silicon alloy film, such as silicon germanium (Si x Ge y ).
- a single crystalline window portion 208 connects the silicon or silicon alloy body film 206 to the single crystalline silicon substrate 202 through a window or opening 207 formed in insulating layer 204 .
- the silicon or silicon alloy body film includes at least a single crystalline silicon or silicon alloy portion 210 from which the active channel region of the device is formed.
- the active channel region 230 is formed by the lateral crystallization of an amorphous or polycrystalline silicon or silicon alloy film deposited on the insulating layer 204 and on the single crystalline silicon substrate 202 within the opening 207 .
- a heating step causes crystallization of the body film to start from the single silicon substrate 202 in the window and laterally extend a length across insulating layer 204 .
- the length of crystallization is on the order of 1.0 micron so that a device's active or channel region 230 can be formed within the crystallization region.
- a gate dielectric layer 214 such as silicon dioxide or silicon oxynitride, is formed on the single crystalline silicon or silicon alloy body portion 210 .
- a gate electrode 216 such as a highly doped polycrystalline silicon gate electrode 216 , is formed on the gate dielectric layer 214 .
- a source region 218 and a drain region 220 are formed in the silicon or silicon alloy body film 206 on laterally opposite sides of gate electrode 216 .
- the source and drain regions have the same doping concentration and conductivity type wherein the channel region of the silicon body is of the opposite conductivity type and of lower doping.
- the source and drain regions are of n type conductivity and have a doping density of between 10 20 -10 21 cm ⁇ 3 while the channel region is of p type conductivity and has a doping density of between 10 17 -10 19 cm ⁇ 3 .
- the source and drain regions have a p type conductivity and a doping density of between 10 20 -10 21 cm ⁇ 3 while the channel region has a n type conductivity and a doping density of between 10 17 -10 19 cm ⁇ 3 .
- the drain region 220 has a single crystalline silicon or silicon alloy portion 224 formed by crystallization and an amorphous or polycrystalline silicon portion 226 which is not crystallized.
- the drain region is formed of only silicon crystalline silicon or silicon alloy and does not include an amorphous or polycrystalline silicon portion 226 .
- the drain region 220 is completely isolated from monocrystalline silicon substrate 202 by insulating layer 204 .
- the source region 218 is formed in single crystalline silicon body portion 210 .
- source region 218 also includes single crystalline silicon window portion 208 and a portion 228 of single crystalline silicon substrate 202 .
- Directly connecting the silicon body layer 206 to the single crystalline silicon substrate 202 through seed window 207 provides a thermal heat sink advantage to the SOI transistor of the present invention.
- source region 218 can include only single crystalline silicon body portion 210 and be completely isolated by insulator 204 from monocrystalline silicon substrate 202 .
- a depletion region is formed in channel region 230 along with an inversion layer at the surface of region 230 .
- the inversion layer has the same conductivity type as the source and drain regions and forms a conductive channel between the source 218 and drain 220 regions to allow current to flow there between.
- the depletion region depletes free carriers from beneath the inversion layer. This depletion region extends to the bottom of region 230 , thus the SOI transistor can be said to be a fully depleted SOI transistor.
- Full depleted SOI transistors have improved electrical performance characteristics over non-fully depleted, or partially depleted SOI transistors.
- a single crystalline substrate 300 such as a single crystalline silicon substrate is provide as shown in FIG. 3A.
- the single crystalline silicon substrate 300 is doped with impurities to form a p type conductivity substrate with a doping concentration of between 10 15 -10 18 cm ⁇ 3 .
- Monocrystalline silicon substrate 300 can include a top deposited epitaxial film, if desired.
- Insulating layer 302 is formed on single crystalline silicon substrate 300 as also shown in FIG. 3A.
- Insulating layer 302 is of a sufficient thickness and quality to isolate a subsequently formed semiconductor body from single crystalline substrate 300 .
- Insulating layer 302 can be any suitable insulating layer, such as silicon dioxide or silicon nitride.
- insulating layer 302 is an oxide film formed by thermal oxidation utilizing a wet ambient and is formed to a thickness of approximately 100 nanometers.
- a seed window or opening 304 is formed in insulating layer 302 to expose a portion of underlying single crystalline substrate 300 .
- Opening 304 exposes a portion 306 of silicon substrate 300 which will be subsequently used as a seeding site from which to laterally crystallize a subsequently formed silicon body layer for the SOI transistor of the present invention.
- Opening 304 can be made as small as the critical dimension or minimum of feature size of the process used to fabricate the transistor.
- the window has a width of approximately 60 nanometers.
- a thin semiconductor body film 308 is formed on portion 306 of single crystalline silicon substrate 300 in window 304 and on insulating layer 302 .
- Semiconductor body film 308 can be an amorphous or polycrystalline silicon film or an amorphous or polycrystalline silicon alloy film, such as silicon germanium.
- silicon body 308 is an amorphous or polycrystalline silicon or silicon alloy film which is deposited in a two step deposition process. The first deposition process is a selective deposition and as such, only deposits on silicon areas, such as silicon substrate region 306 in window 304 , and not on insulating layer 302 .
- the second deposition step is a non-selective deposition which deposits silicon on the previously deposited silicon within window 304 as well as on insulating layer 302 .
- the thickness of semiconductor body layer 308 is chosen so that the entire channel region of a transistor formed on the silicon body will fully deplete when the transistor is turned “ON”.
- silicon body layer 308 is formed to a thickness less than 30 nanometers and ideally to a thickness of approximately 20 nanometers plus or minus two nanometers over the entire surface of a wafer.
- Dielectric capping layer 310 is formed on silicon body film 308 as shown in FIG. 3D.
- Dielectric capping layer 310 can be used to keep the top surface of silicon body 308 smooth during the subsequent lateral crystallization step.
- Dielectric capping layer 310 can be any suitable dielectric layer, such as silicon dioxide or silicon nitride formed to a thickness of approximately 100 nm.
- silicon or silicon alloy body 310 is crystallized to form a single crystalline silicon or silicon alloy film portion 314 as shown in FIG. 3E.
- a high temperature anneal can be used to laterally crystallize the silicon body film 308 .
- Crystallization begins at the silicon seed portion 307 and then grows laterally over insulating layer 302 as shown in FIG. 3E.
- the crystallization length 316 should be sufficiently long in order to provide a sufficient amount of single crystalline silicon or silicon alloy film 314 for at least one transistors active channel region. In an embodiment of the present invention, the crystallization length 316 is sufficiently long to provide single crystalline silicon for multiple transistors. In an embodiment of the present invention, the crystallization length is on the order of approximately 1.0 micron.
- the crystallization step need not crystallize the entire silicon or silicon body 308 and can leave a portion 312 as amorphous or polycrystalline silicon or silicon alloy, as shown in FIG. 3E.
- the crystallization anneal is accomplished with a method that provides a thermal gradient which keeps the silicon seed portion 306 of substrate 300 relatively cool while heating the silicon body 308 .
- the crystalline structure of the seed layer 306 remains aligned while the silicon body layer heats up, melts and aligns to the crystalline structure of the seed area 306 of single crystalline substrate 300 .
- a laser anneal process is used to form single crystalline silicon or silicon alloy body portion 314 .
- the wavelength of light chosen would be such that most of the radiant energy is absorbed in the silicon, or silicon alloy layer 308 and not in the dielectric layer or in the underlying silicon substrate 300 .
- a rapid thermal process may be utilized. The anneal temperature time, and/or energy is utilized to control the crystallization length 316 of silicon body portion 314 .
- a single crystalline silicon or silicon alloy film 314 has been formed on an insulating layer 302 enabling the subsequent formation of a silicon on insulator transistor.
- Well-known and standard process techniques can now be used to complete the fabrication of a silicon on insulator transistor.
- the dielectric capping layer 310 is now removed from silicon body 308 .
- well-known ion-implantation techniques can be used to dope silicon body 308 to p type conductivity for n type devices and n type conductivity for p type devices.
- Well-known masking and doping techniques such as ion-implantation or solid source diffusion may be utilized to dope silicon body 308 .
- silicon body 308 is patterned with well-known photolithography and etching techniques to remove portions of silicon body 308 to form openings 318 in the silicon body film in order to electrically isolate adjacent transistors.
- FIG. 3F silicon body 308 is patterned with well-known photolithography and etching techniques to remove portions of silicon body 308 to form openings 318 in the silicon body film in order to electrically isolate adjacent transistors.
- a gate dielectric layer 320 such as a silicon dioxide or silicon oxynitride film, is grown on silicon body 308 with well-known techniques.
- a gate electrode material such as polycrystalline silicon, is deposited on the gate dielectric layer.
- well-known photolithograph and etching techniques are utilized to pattern the gate electrode material and gate dielectric layer into a gate electrode 322 and gate dielectric 320 as shown in FIG. 3F. It is to be appreciated that gate electrode 322 and gate dielectric 320 are positioned over single crystalline silicon or silicon alloy portion 314 of silicon body 308 as shown in FIG. 3F.
- Source region 326 and a drain region 324 are formed in silicon body 308 as shown in FIG. 3G.
- Source region 326 and drain region 324 are formed along laterally opposite sidewalls of gate electrode 322 defining a channel region 328 therebetween.
- Source region 326 and drain region 324 are formed of n type conductivity for NMOS devices and a p type conductivity for PMOS devices.
- Source region 326 and drain region 324 can be formed with well-known techniques, such as ion-implantation or solid source diffusion. In an embodiment of the present invention, the source region and drain region are formed by ion-implantation.
- the source/drain doping step can be used to highly dope a polycrystalline gate electrode 322 .
- the drain region 324 formed and located so that it includes a portion of single crystalline silicon body 314 and a portion 312 of amorphous or polycrystalline silicon body.
- source region 326 is formed and located so that the source region includes single crystalline silicon or silicon alloy 314 formed in window 304 of insulating layer 302 as well as a portion of single crystalline silicon substrate 300 .
- Well-known semiconductor fabrication processes can now be utilized to interconnect the fabricated SOI transistor with other transistors formed on substrate 300 to form an integrated circuit.
- well-known interlayer dielectric fabrication techniques can be used to form an interlayer dielectric 330 and well-known contact techniques can be utilized to form source, drain and gate contacts 332 to enable electrical coupling by metallization layers 334 to other devices in the integrated circuit.
- the present invention utilizes a lateral crystallization of a deposited amorphous or polycrystalline silicon film to form a single crystalline silicon film on which the SOI transistor of the present invention is subsequently formed. Because the present invention relies upon the lateral crystallization, it is desirable to keep the lateral crystallization length (i.e., distance the single crystalline silicon grows from the seed area over insulating layer 302 as shown in FIG. 3D) short as possible in order to insure a quality single crystalline silicon film. Accordingly, in an embodiment of the present invention, the crystallization length is kept to less than 10 microns and greater than 1 microns.
- seed windows 304 would be formed in an insulating layer 302 for each integrated circuit in order to provide a sufficient amount of crystallized single crystalline silicon from which to form the SOI transistors of the integrated circuit.
- the crystallization of the amorphous or polycrystalline silicon body film 308 begins at the seeding cite 306 and grows in all directions (including into and out of the page in FIG. 3E). Additionally, it is to be appreciated that windows 306 also extend into and out of the page along the gate width of the transistor.
- the gate length of a transistor refers to the dimension of the gate electrode separating the source and drain regions as shown in FIGS. 3 A- 3 H while the gate width is the direction perpendicular thereto (i.e., in a direction into and out of the page of FIGS. 3 A- 3 H).
- the present invention forms multiple seed windows 304 in insulating layer 302 to provide multiple seeding sites from which a deposited amorphous or polycrystalline silicon film can be crystallized into single crystalline silicon for the various SOI transistors of an integrated circuit.
- sufficient seed windows are formed and located to insure the complete crystallization of the entire amorphous or polycrystalline silicon film during the crystallization step. It is to be appreciated, however, that the entire amorphous or polycrystalline silicon film need not necessarily be crystallized into single crystalline silicon and some can remain as polycrystalline or amorphous silicon as long as the transistor layout restrictions place the active channel regions over crystallized silicon 314 .
- the SOI transistors should be located so that the amorphous or polycrystalline silicon film forms part of the drain region of the device as shown in FIG. 3H.
- the silicon body 308 is shown connected to the single crystalline silicon substrate 300 by the portion of silicon in window 304 , the silicon body need not necessarily be directly coupled to the substrate.
- the transistors can be properly positioned so that the silicon in or above window 304 can be etched away or isolated from the silicon body during the silicon body etch step of FIG. 3F to provide isolation between adjacent transistors.
- the deposited silicon body is thinned by a polishing process and the thickness precisely controlled by the use of a thin polish stop layer.
- a polish stop film 403 is conformally formed on insulating layer 302 formed on single crystalline silicon substrate 300 as shown in FIG. 4A.
- the polish stop layer 403 is used to form a plurality of polish stops on insulating layer 302 for the subsequent polishing of the deposited silicon body film.
- the polish stop film is formed of a material which can be selectively polished with respect to the subsequently formed silicon body.
- polish stop film 403 is formed of a material which can be polished slower, preferably at least 5 times slower, than the silicon body film.
- the polish stop is a deposited silicon nitride, silicon oxide or silicon carbide film.
- the polish stop film 403 is deposited to the thickness desired of the silicon body for the SOI transistor.
- the polish stop layer 403 is formed to a thickness of less than 40 nanometers and ideally to a thickness of less than or equal to 20 nanometers so that a fully depleted SOI transistor can be formed.
- polish stop layer 403 is patterned with well-known photolithography and etching techniques to form a plurality of polish stop features 405 on insulating layer 302 .
- the region 407 between polish stop features 405 are the location at which an SOI transistor or plurality of transistors are formed. As such, the spaces between features should be at least sufficient to accommodate at least one SOI transistor.
- polish stop features 405 are separated by a distance of at least 1.0 micron in order to provide sufficient area for the transistors length.
- a silicon seed window 304 is formed through insulating layer 302 to expose a portion 306 of single crystalline substrate 300 as described above. Seed window 304 is formed within opening 407 between polish stop features 405 .
- an amorphous or polycrystalline silicon or silicon alloy body film 308 is blanket deposited onto polish stop features 405 , onto insulating layer 302 within opening 407 and onto single crystalline silicon substrate portion 306 of substrate 300 .
- the amorphous or polycrystalline silicon body film can be deposited to a thickness greater than the thickness desired of the body layer for the fabricated transistor because it is to be subsequently polished back. It is thought that by forming a thicker amorphous or polycrystalline silicon body layer 308 that the subsequent lateral crystallization anneal can obtain further lengths do to the increased thickness of the film.
- the amorphous or polycrystalline silicon or silicon alloy film 308 is formed to a thickness greater then 100 nanometers. Amorphous or polycrystalline silicon or silicon alloy film 308 can be formed with techniques as described above.
- a dielectric capping layer 310 is formed on amorphous or polycrystalline silicon or silicon alloy layer 308 as described above.
- the amorphous or polycrystalline silicon or silicon alloy film 308 is subjected to a high temperature anneal to laterally crystallize the film 308 to form a single crystalline silicon or silicon alloy film 314 as described above. It is thought that by increasing the thickness of the silicon body film 308 that the lateral crystallization length can be increased over what is possible when a thin amorphous or polycrystalline silicon or silicon alloy body film is crystallized. A portion 312 of the amorphous or polycrystalline silicon or silicon alloy body film 308 may remain as amorphous or polycrystalline silicon or silicon alloy as shown in FIG. 4D.
- the dielectric capping layer is removed with well-known techniques.
- the silicon body layer 308 is now polished back with well-known chemical mechanical polishing techniques.
- the silicon body layer 308 is polished down to the polish stop features 405 as shown in FIG. 4E.
- the silicon body is polished with a polishing process and slurry which can selectively polish the silicon body film 308 with respect to polish stop features 405 .
- the polishing process is continued until all of the silicon body film 308 is removed from polish stop features 405 as shown in FIG. 4E.
- the top surface of silicon body 308 is substantially planar with the top surface of the polish stop features 405 as shown in FIG. 4E.
- polish stop features 405 can be placed in appropriate locations to provide such a function.
- a silicon body 308 on which SOI transistor of the present invention is fabricated can formed to a precise and uniform thickness across the wafer and from wafer to wafer.
- a gate dielectric layer 320 , a gate electrode 322 , a source region 326 and a drain region 324 are formed as described above. This completes the fabrication of the SOI transistor in accordance with an alternative embodiment of the present invention.
Abstract
The present invention is a silicon on insulator (SOI) transistor and its method of fabrication. According to the present invention, an opening is formed in the insulating layer formed on a single crystalline silicon substrate. An amorphous or polycrystalline silicon or silicon alloy is then formed in the opening on the single crystalline silicon substrate and on the insulating layer. The amorphous or polycrystalline silicon or silicon alloy in the opening and at least a portion of the amorphous or polycrystalline silicon or silicon alloy on the insulating layer is crystallized into a single crystalline silicon or silicon alloy film.
Description
- 1. Field of the Invention
- The present invention relates to the field of semiconductor devices and more specifically to a silicon on insulator (SOI) transistor and methods of fabrication.
- 2. Discussion of Related Art
- In order to increase device performance, silicon on insulator (SOI) transistors have been proposed for the fabrication of modern integrated circuits. FIG. 1 illustrates a standard partially depleted silicon on insulator (SOI)
transistor 100.SOI transistor 100 includes a singlecrystalline silicon substrate 102 having aninsulating layer 104, such as a buried oxide formed thereon. A single crystallinesilicon film body 106 is formed on theinsulating layer 104. A gatedielectric layer 108 is formed on the singlecrystalline silicon body 106 and agate electrode 110 formed on the gate dielectric 108. Source anddrain regions silicon body 106 along laterally opposite sides ofgate electrode 110. - There are presently a couple different methods of forming SOI substrates where an single
crystalline silicon body 106 is formed on aninsulating layer 104 which inturn is formed on a single crystalline silicon substrate. In one method of forming a silicon on insulator (SOI) substrate, known as the SIMOX technique, oxygen atoms are implanted at a high dose into a single crystalline silicon substrate and annealed to form the buriedoxide 104 within the substrate. The portion of the single crystalline silicon substrate above the buried oxide becomes the silicon body. Another technique currently used to form SOI substrates is an epitaxial silicon film transferred technique. Another technique currently used to form SOI substrates is generally referred to as bonded SOI. In this technique a first silicon wafer has a thin oxide grown on its surface that will later serve as the buried oxide in the SOI structure. Next a high dose hydrogen implant is done to form a high stress region below the silicon wafer surface. This first wafer is then flipped over and bonded to the surface of a second silicon wafer. The first wafer is then cleaved along the high stress plane created by the hydrogen implant. This results in the SOI structure with a thin silicon layer on top, buried oxide underneath, all on top of a single crystal silicon substrate. - A problem with the bonded technique and the oxygen implant technique for forming SOI wafers or substrates, is that they cannot form thin, less than 10 nm, uniform epitaxial silicon body films. As such, the
silicon body 106 of an SOI transistor formed with these techniques have thicknesses of greater than 100 nanometers. As such, when the SOI transistor is in operation and “turned ON” and thechannel region 120 of the device inverts into the conductivity of the source/drain regions to form a conductive channel therebetween the invertedconductive channel region 120 does not completely invert or deplete the entire thickness of the silicon body. As such, the SOI transistor is considered a partially depleted SOI transistor and not a fully depleted transistor. In order to fully deplete the silicon body, the silicon body film would need to be less than 30 nm. A fully depleted SOI transistor has better electrical performance and characteristics than does a partially depleted SOI transistor. As such, present techniques are unable to fabricate fully depleted SOI transistors. - FIG. 1 is an illustration of a cross-sectional view of a prior art partially depleted silicon on insulator (SOI) transistor.
- FIG. 2 is an illustration of an silicon on insulator (SOI) transistor in accordance with an embodiment of the present invention.
- FIGS.3A-3H illustrates a method of forming an SOI transistor in accordance with an embodiment of the present invention.
- FIGS.4A-4F illustrates a method of forming an SOI transistor in accordance with an embodiment of the present invention.
- The present invention is a novel silicon on insulator (SOI) transistor and its method of fabrication. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. In other instances, well-known semiconductor processing techniques have not been described in particular detail in order to not unnecessarily obscure the present invention.
- The present invention is a novel SOI transistor and its method of fabrication. The SOI transistor is fabricated utilizing the lateral crystallization of a thin deposited amorphous or polycrystalline silicon or silicon alloy that contacts a single crystalline silicon substrate through a small seed window in the insulating layer. The process of the present invention can be used to form very thin (less than 30 nanometers) and uniform thickness single crystalline silicon films for the body of the transistor enabling fully depleted SOI transistors to be fabricated across a wafer. In an embodiment of the present invention, a polished stop layer along with a polishing planarization step are used to precisely control the thickness and uniformity of the silicon or silicon alloy body.
- SOI Transistors
- Shown in FIG. 2 is an
SOI transistor 200 in accordance with an embodiment of the present invention.Transistor 200 includes a singlecrystalline silicon substrate 202. Singlecrystalline silicon substrate 202 can include a top deposited silicon or silicon alloy epitaxial film. Aninsulating layer 204, such as silicon dioxide or silicon nitride, is formed on the singlecrystalline silicon substrate 202. Asemiconductor body film 206 is formed on theinsulating layer 204.Semiconductor body film 206 can be a silicon film or a silicon alloy film, such as silicon germanium (SixGey). A singlecrystalline window portion 208 connects the silicon or siliconalloy body film 206 to the singlecrystalline silicon substrate 202 through a window or opening 207 formed ininsulating layer 204. The silicon or silicon alloy body film includes at least a single crystalline silicon or silicon alloy portion 210 from which the active channel region of the device is formed. Theactive channel region 230 is formed by the lateral crystallization of an amorphous or polycrystalline silicon or silicon alloy film deposited on theinsulating layer 204 and on the singlecrystalline silicon substrate 202 within theopening 207. A heating step causes crystallization of the body film to start from thesingle silicon substrate 202 in the window and laterally extend a length acrossinsulating layer 204. The length of crystallization is on the order of 1.0 micron so that a device's active orchannel region 230 can be formed within the crystallization region. - A gate
dielectric layer 214, such as silicon dioxide or silicon oxynitride, is formed on the single crystalline silicon or silicon alloy body portion 210. Agate electrode 216, such as a highly doped polycrystallinesilicon gate electrode 216, is formed on the gatedielectric layer 214. Asource region 218 and a drain region 220 are formed in the silicon or siliconalloy body film 206 on laterally opposite sides ofgate electrode 216. The source and drain regions have the same doping concentration and conductivity type wherein the channel region of the silicon body is of the opposite conductivity type and of lower doping. In an embodiment of the present invention, for a NMOS device the source and drain regions are of n type conductivity and have a doping density of between 1020-1021 cm−3 while the channel region is of p type conductivity and has a doping density of between 1017-1019 cm−3. For a PMOS device the source and drain regions have a p type conductivity and a doping density of between 1020-1021 cm−3 while the channel region has a n type conductivity and a doping density of between 1017-1019 cm−3. - In an embodiment of the present invention, the drain region220 has a single crystalline silicon or
silicon alloy portion 224 formed by crystallization and an amorphous orpolycrystalline silicon portion 226 which is not crystallized. In an embodiment of the present invention, the drain region is formed of only silicon crystalline silicon or silicon alloy and does not include an amorphous orpolycrystalline silicon portion 226. The drain region 220 is completely isolated frommonocrystalline silicon substrate 202 byinsulating layer 204. - The
source region 218 is formed in single crystalline silicon body portion 210. In an embodiment of the present invention,source region 218 also includes single crystallinesilicon window portion 208 and aportion 228 of singlecrystalline silicon substrate 202. Directly connecting thesilicon body layer 206 to the singlecrystalline silicon substrate 202 throughseed window 207 provides a thermal heat sink advantage to the SOI transistor of the present invention. Alternatively,source region 218 can include only single crystalline silicon body portion 210 and be completely isolated byinsulator 204 frommonocrystalline silicon substrate 202. - When the SOI transistor is turned “ON” a depletion region is formed in
channel region 230 along with an inversion layer at the surface ofregion 230. The inversion layer has the same conductivity type as the source and drain regions and forms a conductive channel between thesource 218 and drain 220 regions to allow current to flow there between. The depletion region depletes free carriers from beneath the inversion layer. This depletion region extends to the bottom ofregion 230, thus the SOI transistor can be said to be a fully depleted SOI transistor. Full depleted SOI transistors have improved electrical performance characteristics over non-fully depleted, or partially depleted SOI transistors. - Methods of Fabrication of SOI Transistors
- Fabrication of the SOI transistor in accordance with embodiments of the present invention, will be described with respect to FIGS.3A-3H and FIGS. 4A-4F. In a method of forming a silicon on insulator (SOI) semiconductor device in accordance with an embodiment of the present invention, a single
crystalline substrate 300, such as a single crystalline silicon substrate is provide as shown in FIG. 3A. In an embodiment of the present invention, the singlecrystalline silicon substrate 300 is doped with impurities to form a p type conductivity substrate with a doping concentration of between 1015-1018 cm−3.Monocrystalline silicon substrate 300 can include a top deposited epitaxial film, if desired. An insulatinglayer 302 is formed on singlecrystalline silicon substrate 300 as also shown in FIG. 3A. Insulatinglayer 302 is of a sufficient thickness and quality to isolate a subsequently formed semiconductor body from singlecrystalline substrate 300. Insulatinglayer 302 can be any suitable insulating layer, such as silicon dioxide or silicon nitride. In an embodiment of the present invention, insulatinglayer 302 is an oxide film formed by thermal oxidation utilizing a wet ambient and is formed to a thickness of approximately 100 nanometers. - Next, as shown in FIG. 3B, a seed window or
opening 304 is formed in insulatinglayer 302 to expose a portion of underlying singlecrystalline substrate 300.Opening 304 exposes aportion 306 ofsilicon substrate 300 which will be subsequently used as a seeding site from which to laterally crystallize a subsequently formed silicon body layer for the SOI transistor of the present invention. Opening 304 can be made as small as the critical dimension or minimum of feature size of the process used to fabricate the transistor. In an embodiment of the present invention, the window has a width of approximately 60 nanometers. - Next, as shown in FIG. 3C, a thin
semiconductor body film 308 is formed onportion 306 of singlecrystalline silicon substrate 300 inwindow 304 and on insulatinglayer 302.Semiconductor body film 308 can be an amorphous or polycrystalline silicon film or an amorphous or polycrystalline silicon alloy film, such as silicon germanium. In an embodiment of the present invention,silicon body 308 is an amorphous or polycrystalline silicon or silicon alloy film which is deposited in a two step deposition process. The first deposition process is a selective deposition and as such, only deposits on silicon areas, such assilicon substrate region 306 inwindow 304, and not on insulatinglayer 302. The second deposition step is a non-selective deposition which deposits silicon on the previously deposited silicon withinwindow 304 as well as on insulatinglayer 302. The thickness ofsemiconductor body layer 308 is chosen so that the entire channel region of a transistor formed on the silicon body will fully deplete when the transistor is turned “ON”. In an embodiment of the present invention,silicon body layer 308 is formed to a thickness less than 30 nanometers and ideally to a thickness of approximately 20 nanometers plus or minus two nanometers over the entire surface of a wafer. - Next, a
dielectric capping layer 310 is formed onsilicon body film 308 as shown in FIG. 3D.Dielectric capping layer 310 can be used to keep the top surface ofsilicon body 308 smooth during the subsequent lateral crystallization step.Dielectric capping layer 310 can be any suitable dielectric layer, such as silicon dioxide or silicon nitride formed to a thickness of approximately 100 nm. - Next, silicon or
silicon alloy body 310 is crystallized to form a single crystalline silicon or siliconalloy film portion 314 as shown in FIG. 3E. A high temperature anneal can be used to laterally crystallize thesilicon body film 308. Crystallization begins at the silicon seed portion 307 and then grows laterally over insulatinglayer 302 as shown in FIG. 3E. Thecrystallization length 316 should be sufficiently long in order to provide a sufficient amount of single crystalline silicon orsilicon alloy film 314 for at least one transistors active channel region. In an embodiment of the present invention, thecrystallization length 316 is sufficiently long to provide single crystalline silicon for multiple transistors. In an embodiment of the present invention, the crystallization length is on the order of approximately 1.0 micron. The crystallization step need not crystallize the entire silicon orsilicon body 308 and can leave aportion 312 as amorphous or polycrystalline silicon or silicon alloy, as shown in FIG. 3E. Ideally, the crystallization anneal is accomplished with a method that provides a thermal gradient which keeps thesilicon seed portion 306 ofsubstrate 300 relatively cool while heating thesilicon body 308. In this way, the crystalline structure of theseed layer 306 remains aligned while the silicon body layer heats up, melts and aligns to the crystalline structure of theseed area 306 of singlecrystalline substrate 300. In an embodiment of the present invention, a laser anneal process is used to form single crystalline silicon or siliconalloy body portion 314. In the case of laser anneal, the wavelength of light chosen would be such that most of the radiant energy is absorbed in the silicon, orsilicon alloy layer 308 and not in the dielectric layer or in theunderlying silicon substrate 300. In an alternative embodiment of the present invention, a rapid thermal process (RTP) may be utilized. The anneal temperature time, and/or energy is utilized to control thecrystallization length 316 ofsilicon body portion 314. At this point, a single crystalline silicon orsilicon alloy film 314 has been formed on an insulatinglayer 302 enabling the subsequent formation of a silicon on insulator transistor. Well-known and standard process techniques can now be used to complete the fabrication of a silicon on insulator transistor. - For example, as shown in FIG. 3F, the
dielectric capping layer 310 is now removed fromsilicon body 308. At this time, well-known ion-implantation techniques can be used todope silicon body 308 to p type conductivity for n type devices and n type conductivity for p type devices. Well-known masking and doping techniques, such as ion-implantation or solid source diffusion may be utilized todope silicon body 308. Next, as also shown in FIG. 3F,silicon body 308 is patterned with well-known photolithography and etching techniques to remove portions ofsilicon body 308 to formopenings 318 in the silicon body film in order to electrically isolate adjacent transistors. Next, as also shown in FIG. 3F, agate dielectric layer 320, such as a silicon dioxide or silicon oxynitride film, is grown onsilicon body 308 with well-known techniques. Next, a gate electrode material, such as polycrystalline silicon, is deposited on the gate dielectric layer. Next, well-known photolithograph and etching techniques are utilized to pattern the gate electrode material and gate dielectric layer into agate electrode 322 and gate dielectric 320 as shown in FIG. 3F. It is to be appreciated thatgate electrode 322 andgate dielectric 320 are positioned over single crystalline silicon orsilicon alloy portion 314 ofsilicon body 308 as shown in FIG. 3F. - Next, a
source region 326 and adrain region 324 are formed insilicon body 308 as shown in FIG. 3G.Source region 326 and drainregion 324 are formed along laterally opposite sidewalls ofgate electrode 322 defining achannel region 328 therebetween.Source region 326 and drainregion 324 are formed of n type conductivity for NMOS devices and a p type conductivity for PMOS devices.Source region 326 and drainregion 324 can be formed with well-known techniques, such as ion-implantation or solid source diffusion. In an embodiment of the present invention, the source region and drain region are formed by ion-implantation. The source/drain doping step can be used to highly dope apolycrystalline gate electrode 322. In an embodiment of the present invention, thedrain region 324 formed and located so that it includes a portion of singlecrystalline silicon body 314 and aportion 312 of amorphous or polycrystalline silicon body. Additionally, in an embodiment of the present invention, as shown in FIG. 3G,source region 326 is formed and located so that the source region includes single crystalline silicon orsilicon alloy 314 formed inwindow 304 of insulatinglayer 302 as well as a portion of singlecrystalline silicon substrate 300. At this point, the fabrication of the silicon on insulator transistor of the present invention is complete. - Well-known semiconductor fabrication processes can now be utilized to interconnect the fabricated SOI transistor with other transistors formed on
substrate 300 to form an integrated circuit. For example, well-known interlayer dielectric fabrication techniques can be used to form aninterlayer dielectric 330 and well-known contact techniques can be utilized to form source, drain andgate contacts 332 to enable electrical coupling bymetallization layers 334 to other devices in the integrated circuit. - It is to be appreciated that the present invention utilizes a lateral crystallization of a deposited amorphous or polycrystalline silicon film to form a single crystalline silicon film on which the SOI transistor of the present invention is subsequently formed. Because the present invention relies upon the lateral crystallization, it is desirable to keep the lateral crystallization length (i.e., distance the single crystalline silicon grows from the seed area over insulating
layer 302 as shown in FIG. 3D) short as possible in order to insure a quality single crystalline silicon film. Accordingly, in an embodiment of the present invention, the crystallization length is kept to less than 10 microns and greater than 1 microns. It is to be appreciated that because it is desirable to reduce the crystallization length, many (literally millions) ofseed windows 304 would be formed in an insulatinglayer 302 for each integrated circuit in order to provide a sufficient amount of crystallized single crystalline silicon from which to form the SOI transistors of the integrated circuit. In an embodiment of the present invention, there is between 1:1 to 1:10 ratio crystallization seed windows to transistors. It is to be appreciated that the crystallization of the amorphous or polycrystallinesilicon body film 308 begins at the seeding cite 306 and grows in all directions (including into and out of the page in FIG. 3E). Additionally, it is to be appreciated thatwindows 306 also extend into and out of the page along the gate width of the transistor. (As in typical convention, the gate length of a transistor refers to the dimension of the gate electrode separating the source and drain regions as shown in FIGS. 3A-3H while the gate width is the direction perpendicular thereto (i.e., in a direction into and out of the page of FIGS. 3A-3H).) - Thus, accordingly the present invention forms
multiple seed windows 304 in insulatinglayer 302 to provide multiple seeding sites from which a deposited amorphous or polycrystalline silicon film can be crystallized into single crystalline silicon for the various SOI transistors of an integrated circuit. In an embodiment of the present invention, sufficient seed windows are formed and located to insure the complete crystallization of the entire amorphous or polycrystalline silicon film during the crystallization step. It is to be appreciated, however, that the entire amorphous or polycrystalline silicon film need not necessarily be crystallized into single crystalline silicon and some can remain as polycrystalline or amorphous silicon as long as the transistor layout restrictions place the active channel regions over crystallizedsilicon 314. If some of the silicon body remains as amorphous or polycrystalline silicon, the SOI transistors should be located so that the amorphous or polycrystalline silicon film forms part of the drain region of the device as shown in FIG. 3H. Additionally, although thesilicon body 308 is shown connected to the singlecrystalline silicon substrate 300 by the portion of silicon inwindow 304, the silicon body need not necessarily be directly coupled to the substrate. For example, the transistors can be properly positioned so that the silicon in or abovewindow 304 can be etched away or isolated from the silicon body during the silicon body etch step of FIG. 3F to provide isolation between adjacent transistors. - In a method of forming an SOI transistor in accordance with another embodiment of the present invention, as shown in FIGS.4A-4F, the deposited silicon body is thinned by a polishing process and the thickness precisely controlled by the use of a thin polish stop layer. According to this embodiment of the present invention, a
polish stop film 403 is conformally formed on insulatinglayer 302 formed on singlecrystalline silicon substrate 300 as shown in FIG. 4A. Thepolish stop layer 403 is used to form a plurality of polish stops on insulatinglayer 302 for the subsequent polishing of the deposited silicon body film. As such, the polish stop film is formed of a material which can be selectively polished with respect to the subsequently formed silicon body. (That ispolish stop film 403 is formed of a material which can be polished slower, preferably at least 5 times slower, than the silicon body film.) In an embodiment of the present invention, the polish stop is a deposited silicon nitride, silicon oxide or silicon carbide film. Thepolish stop film 403 is deposited to the thickness desired of the silicon body for the SOI transistor. In an embodiment of the present invention, thepolish stop layer 403 is formed to a thickness of less than 40 nanometers and ideally to a thickness of less than or equal to 20 nanometers so that a fully depleted SOI transistor can be formed. - Next, as shown in FIG. 4B, the
polish stop layer 403 is patterned with well-known photolithography and etching techniques to form a plurality of polish stop features 405 on insulatinglayer 302. Theregion 407 between polish stop features 405 are the location at which an SOI transistor or plurality of transistors are formed. As such, the spaces between features should be at least sufficient to accommodate at least one SOI transistor. In an embodiment of the present invention, polish stop features 405 are separated by a distance of at least 1.0 micron in order to provide sufficient area for the transistors length. - Next, as also shown in FIG. 4B, a
silicon seed window 304 is formed through insulatinglayer 302 to expose aportion 306 of singlecrystalline substrate 300 as described above.Seed window 304 is formed withinopening 407 between polish stop features 405. - Next, as shown in FIG. 4C, an amorphous or polycrystalline silicon or silicon
alloy body film 308 is blanket deposited onto polish stop features 405, onto insulatinglayer 302 withinopening 407 and onto single crystallinesilicon substrate portion 306 ofsubstrate 300. In this embodiment of the present invention, the amorphous or polycrystalline silicon body film can be deposited to a thickness greater than the thickness desired of the body layer for the fabricated transistor because it is to be subsequently polished back. It is thought that by forming a thicker amorphous or polycrystallinesilicon body layer 308 that the subsequent lateral crystallization anneal can obtain further lengths do to the increased thickness of the film. In an embodiment of the present invention, the amorphous or polycrystalline silicon orsilicon alloy film 308 is formed to a thickness greater then 100 nanometers. Amorphous or polycrystalline silicon orsilicon alloy film 308 can be formed with techniques as described above. - Next, a
dielectric capping layer 310 is formed on amorphous or polycrystalline silicon orsilicon alloy layer 308 as described above. - Next, as shown in FIG. 4D, the amorphous or polycrystalline silicon or
silicon alloy film 308 is subjected to a high temperature anneal to laterally crystallize thefilm 308 to form a single crystalline silicon orsilicon alloy film 314 as described above. It is thought that by increasing the thickness of thesilicon body film 308 that the lateral crystallization length can be increased over what is possible when a thin amorphous or polycrystalline silicon or silicon alloy body film is crystallized. Aportion 312 of the amorphous or polycrystalline silicon or siliconalloy body film 308 may remain as amorphous or polycrystalline silicon or silicon alloy as shown in FIG. 4D. - Next, as shown in FIG. 4E, the dielectric capping layer is removed with well-known techniques. The
silicon body layer 308 is now polished back with well-known chemical mechanical polishing techniques. Thesilicon body layer 308 is polished down to the polish stop features 405 as shown in FIG. 4E. The silicon body is polished with a polishing process and slurry which can selectively polish thesilicon body film 308 with respect to polish stop features 405. The polishing process is continued until all of thesilicon body film 308 is removed from polish stop features 405 as shown in FIG. 4E. After the polishing process, the top surface ofsilicon body 308 is substantially planar with the top surface of the polish stop features 405 as shown in FIG. 4E. In this embodiment of the present invention, there is no need to etch the silicon body layer in order electrically isolated adjacent transistors because the polish stop features 405 can be placed in appropriate locations to provide such a function. By utilizing a polishing process and polish stop features 405, asilicon body 308 on which SOI transistor of the present invention is fabricated can formed to a precise and uniform thickness across the wafer and from wafer to wafer. - Next, as shown in FIG. 4F, a
gate dielectric layer 320, agate electrode 322, asource region 326 and adrain region 324 are formed as described above. This completes the fabrication of the SOI transistor in accordance with an alternative embodiment of the present invention. - Thus, an SOI transistor and its methods of fabrication have been described.
Claims (34)
1. A semiconductor device comprising:
a silicon or silicon alloy film formed on an insulating layer formed on a single crystalline silicon substrate, said silicon film having a single crystalline silicon or silicon alloy portion;
a gate dielectric on said single crystalline silicon portion of said silicon film;
a gate electrode on said gate dielectric;
a source and a drain region formed on opposite sides of said gate electrode in said silicon or silicon alloy film; and
a single crystalline silicon or silicon alloy window portion extending from said single crystalline silicon substrate through an opening in said insulating layer to said single crystalline silicon or silicon alloy portion of said silicon film.
2. The semiconductor device of claim 1 wherein said single crystalline silicon or silicon alloy portion of said silicon or silicon alloy film has a thickness of less than 30 nanometers.
3. The semiconductor device of claim 1 wherein said single crystalline silicon window portion forms part of said source region.
4. The semiconductor device of claim 1 wherein said silicon or silicon alloy film further includes a polysilicon or an amorphous silicon or silicon alloy portion.
5. The semiconductor device of claim 4 wherein said polysilicon or amorphous silicon or silicon alloy portion forms part of said drain region.
6. A semiconductor device comprising:
a silicon or silicon alloy film formed on an insulating layer formed on a single crystalline silicon substrate, said silicon or silicon alloy film having a single crystalline silicon or silicon alloy portion having a thickness of less than or equal to 30 nanometers;
a gate dielectric on said single crystalline silicon or silicon alloy portion of said silicon or silicon alloy film;
a gate electrode on said gate dielectric; and
a source region and a drain region in said silicon or silicon alloy film on opposite sides of said gate electrode.
7. The semiconductor device of claim 6 wherein in said silicon or silicon alloy film further comprises an amorphous or polycrystalline portion.
8. The semiconductor device of claim 7 wherein said amorphous or polycrystalline portion forms part of said drain region.
9. The semiconductor device of claim 7 further comprising a single crystalline silicon or silicon alloy window portion extending from said single crystalline silicon substrate through an opening in said insulating layer to said single crystalline silicon or silicon alloy portion of said silicon or silicon alloy film.
10. The semiconductor device of claim 9 wherein said single crystalline silicon or silicon alloy window portion forms part of said source region.
11. A semiconductor device comprising:
a silicon or silicon alloy film formed on an insulating layer formed on a single crystalline silicon substrate, said silicon or silicon alloy film having a single crystalline silicon or silicon alloy portion and an amorphous or polycrystalline portion;
a gate dielectric on said single crystalline silicon or silicon alloy portion;
a gate electrode on said gate dielectric; and
a source and a drain region in said silicon or silicon alloy film on opposite sides of said gate electrode.
12. The semiconductor device of claim 6 further comprising a polish stop layer on said insulating layer adjacent to said silicon film.
13. The semiconductor device of claim 11 wherein said polish stop layer is selected from the group consisting of silicon nitride and silicon carbide.
14. A method of forming a semiconductor device comprising:
forming an opening in an insulating layer formed on a single crystalline silicon substrate;
forming an amorphous or polycrystalline silicon or silicon alloy layer in said opening on said single crystalline silicon substrate and on said insulating layer; and
crystallizing said amorphous or polycrystalline silicon or silicon alloy film in said opening and a least a portion of said amorphous or polycrystalline silicon or silicon alloy film formed on said insulating layer into a single crystalline silicon or silicon alloy film.
15. The method of claim 14 further comprising forming a gate dielectric layer on said single crystalline silicon or silicon alloy portion on said insulating layer; and
forming a gate electrode on said gate dielectric.
16. The method of claim 14 wherein the length of said crystallized portion of said single crystalline silicon or silicon alloy film on said insulating layer is greater than 1.0 micron.
17. The method of claim 14 further comprising forming a dielectric capping layer on said amorphous or polycrystalline silicon or silicon alloy film prior to crystallizing said amorphous or polycrystalline silicon or silicon alloy film.
18. The method of claim 14 further comprising forming a source region and a drain region on opposite sides of said gate electrode in said silicon or silicon alloy film.
19. The method of claim 18 wherein said source region includes said single crystalline silicon or silicon alloy film in said opening.
20. The method of claim 18 wherein said drain region includes a single crystalline silicon or silicon alloy portion and a amorphous or polycrystalline silicon or silicon alloy portion.
21. The method of claim 14 wherein said amorphous or polycrystalline silicon or silicon alloy film is formed to a thickness less than 30 nanometers.
22. The method of claim 14 wherein said crystallization step comprises a laser anneal.
23. The method of claim 14 wherein said crystallization step includes a high temperature anneal.
24. A method of forming a semiconductor device comprising:
forming a polish stop layer on a insulating layer formed on a single crystalline silicon substrate;
forming an opening in said polish stop layer;
forming an opening in said insulating layer within said opening in said polish stop layer;
forming an amorphous or polycrystalline silicon or silicon alloy film in said opening on said single crystalline silicon substrate in said opening of said insulating layer, on said insulating layer within said opening in said polish stop layer, and on said polish stop layer;
crystallizing said amorphous or polycrystalline silicon or silicon alloy film in said opening in said insulating layer and at least a portion of said amorphous or polycrystalline silicon or silicon alloy film formed on said insulating layer within said polish stop layer into a single crystalline silicon or silicon alloy film; and
polishing said single crystalline silicon or silicon alloy film on said insulating layer until said single crystalline silicon or silicon alloy film is removed from said polish stop layer and is substantially planar with said polish stop layer.
25. The method of claim 24 further comprising forming a gate dielectric layer on said single crystalline silicon or silicon alloy portion on said insulating layer; and
forming a gate electrode on said gate dielectric.
26. The method of claim 24 wherein the length of said crystallized portion of said single crystalline silicon or silicon alloy film on said insulating layer is greater than 0.05 micron.
27. The method of claim 24 further comprising forming a dielectric capping layer on said amorphous or polycrystalline silicon or silicon alloy film prior to crystallizing said amorphous or polycrystalline silicon or silicon alloy film.
28. The method of claim 24 further comprising forming a source region and a drain region on opposite sides of said gate electrode in said silicon or silicon alloy film.
29. The method of claim 28 wherein said source region includes said single crystalline silicon or silicon alloy film in said opening.
30. The method of claim 28 wherein said drain region includes a single crystalline silicon or silicon alloy portion and a amorphous or polycrystalline silicon or silicon alloy portion.
31. The method of claim 24 wherein said amorphous or polycrystalline silicon or silicon alloy film is formed to a thickness greater than >100 nanometers.
32. The method of claim 24 wherein said crystallization step comprises a laser anneal.
33. The method of claim 24 wherein said crystallization step includes a high temperature anneal.
34. The method of claim 24 wherein said polish stop layer is selected from the group consisting of silicon nitride and silicon carbide or silicon oxide.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/426,261 US20040016969A1 (en) | 2002-07-29 | 2003-04-29 | Silicon on isulator (SOI) transistor and methods of fabrication |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/208,890 US6919238B2 (en) | 2002-07-29 | 2002-07-29 | Silicon on insulator (SOI) transistor and methods of fabrication |
US10/426,261 US20040016969A1 (en) | 2002-07-29 | 2003-04-29 | Silicon on isulator (SOI) transistor and methods of fabrication |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/208,890 Division US6919238B2 (en) | 2002-07-29 | 2002-07-29 | Silicon on insulator (SOI) transistor and methods of fabrication |
Publications (1)
Publication Number | Publication Date |
---|---|
US20040016969A1 true US20040016969A1 (en) | 2004-01-29 |
Family
ID=30770582
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/208,890 Expired - Fee Related US6919238B2 (en) | 2002-07-29 | 2002-07-29 | Silicon on insulator (SOI) transistor and methods of fabrication |
US10/426,261 Abandoned US20040016969A1 (en) | 2002-07-29 | 2003-04-29 | Silicon on isulator (SOI) transistor and methods of fabrication |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/208,890 Expired - Fee Related US6919238B2 (en) | 2002-07-29 | 2002-07-29 | Silicon on insulator (SOI) transistor and methods of fabrication |
Country Status (1)
Country | Link |
---|---|
US (2) | US6919238B2 (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040199183A1 (en) * | 1997-06-27 | 2004-10-07 | Oz Mehmet C. | Method and apparatus for circulatory valve repair |
US20050104072A1 (en) * | 2003-08-14 | 2005-05-19 | Slater David B.Jr. | Localized annealing of metal-silicon carbide ohmic contacts and devices so formed |
US20060211262A1 (en) * | 2005-03-18 | 2006-09-21 | Samsung Electronics Co., Ltd. | Methods of laterally forming single crystalline thin film regions from seed layers |
US20070066023A1 (en) * | 2005-09-20 | 2007-03-22 | Randhir Thakur | Method to form a device on a soi substrate |
US20080311736A1 (en) * | 2007-06-14 | 2008-12-18 | Cree, Inc. | Methods of forming ohmic layers through ablation capping layers |
Families Citing this family (47)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6909151B2 (en) | 2003-06-27 | 2005-06-21 | Intel Corporation | Nonplanar device with stress incorporation layer and method of fabrication |
US7456476B2 (en) | 2003-06-27 | 2008-11-25 | Intel Corporation | Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication |
KR100513310B1 (en) * | 2003-12-19 | 2005-09-07 | 삼성전자주식회사 | Semiconductor device having two different operation modes employing an asymmetrical buried insulating layer and method of fabricating the same |
US7672558B2 (en) * | 2004-01-12 | 2010-03-02 | Honeywell International, Inc. | Silicon optical device |
US7247528B2 (en) * | 2004-02-24 | 2007-07-24 | Samsung Electronics Co., Ltd. | Methods of fabricating semiconductor integrated circuits using selective epitaxial growth and partial planarization techniques |
US7177489B2 (en) * | 2004-03-18 | 2007-02-13 | Honeywell International, Inc. | Silicon-insulator-silicon thin-film structures for optical modulators and methods of manufacture |
US20050214989A1 (en) * | 2004-03-29 | 2005-09-29 | Honeywell International Inc. | Silicon optoelectronic device |
US7154118B2 (en) | 2004-03-31 | 2006-12-26 | Intel Corporation | Bulk non-planar transistor having strained enhanced mobility and methods of fabrication |
US7042009B2 (en) | 2004-06-30 | 2006-05-09 | Intel Corporation | High mobility tri-gate devices and methods of fabrication |
US7348284B2 (en) | 2004-08-10 | 2008-03-25 | Intel Corporation | Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow |
US7422946B2 (en) | 2004-09-29 | 2008-09-09 | Intel Corporation | Independently accessed double-gate and tri-gate transistors in same process flow |
US7332439B2 (en) | 2004-09-29 | 2008-02-19 | Intel Corporation | Metal gate transistors with epitaxial source and drain regions |
JP4603845B2 (en) * | 2004-10-12 | 2010-12-22 | Okiセミコンダクタ株式会社 | Manufacturing method of semiconductor device |
US20060086977A1 (en) | 2004-10-25 | 2006-04-27 | Uday Shah | Nonplanar device with thinned lower body portion and method of fabrication |
US7518196B2 (en) | 2005-02-23 | 2009-04-14 | Intel Corporation | Field effect transistor with narrow bandgap source and drain regions and method of fabrication |
US20060202266A1 (en) | 2005-03-14 | 2006-09-14 | Marko Radosavljevic | Field effect transistor with metal source/drain regions |
JP2006278632A (en) * | 2005-03-29 | 2006-10-12 | Seiko Epson Corp | Semiconductor substrate, semiconductor device, process for producing semiconductor substrate, and process for fabricating semiconductor device |
US8022408B2 (en) | 2005-05-13 | 2011-09-20 | Samsung Electronics Co., Ltd. | Crystalline nanowire substrate, method of manufacturing the same, and method of manufacturing thin film transistor using the same |
KR101127132B1 (en) * | 2005-05-13 | 2012-03-21 | 삼성전자주식회사 | Si nanowire substrate and fabrication method of the same, and fabrication method of thin film transistor using the same |
US7858481B2 (en) | 2005-06-15 | 2010-12-28 | Intel Corporation | Method for fabricating transistor with thinned channel |
US7547637B2 (en) | 2005-06-21 | 2009-06-16 | Intel Corporation | Methods for patterning a semiconductor film |
US7279375B2 (en) | 2005-06-30 | 2007-10-09 | Intel Corporation | Block contact architectures for nanoscale channel transistors |
US7709313B2 (en) * | 2005-07-19 | 2010-05-04 | International Business Machines Corporation | High performance capacitors in planar back gates CMOS |
US7402875B2 (en) | 2005-08-17 | 2008-07-22 | Intel Corporation | Lateral undercut of metal gate in SOI device |
US7479421B2 (en) | 2005-09-28 | 2009-01-20 | Intel Corporation | Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby |
US20070090416A1 (en) | 2005-09-28 | 2007-04-26 | Doyle Brian S | CMOS devices with a single work function gate electrode and method of fabrication |
US20070101927A1 (en) * | 2005-11-10 | 2007-05-10 | Honeywell International Inc. | Silicon based optical waveguide structures and methods of manufacture |
US7362443B2 (en) | 2005-11-17 | 2008-04-22 | Honeywell International Inc. | Optical gyro with free space resonator and method for sensing inertial rotation rate |
US7485503B2 (en) | 2005-11-30 | 2009-02-03 | Intel Corporation | Dielectric interface for group III-V semiconductor device |
US7566630B2 (en) * | 2006-01-18 | 2009-07-28 | Intel Corporation | Buried silicon dioxide / silicon nitride bi-layer insulators and methods of fabricating the same |
KR100790869B1 (en) * | 2006-02-16 | 2008-01-03 | 삼성전자주식회사 | Single crystal substrate and fabrication method thereof |
US7700461B2 (en) * | 2006-03-17 | 2010-04-20 | Samsung Electronics Co., Ltd. | Methods of laterally forming single crystalline thin film regions from seed layers |
KR100722768B1 (en) * | 2006-04-03 | 2007-05-30 | 삼성전자주식회사 | Method of manufacturing a semiconductor device |
US7463360B2 (en) | 2006-04-18 | 2008-12-09 | Honeywell International Inc. | Optical resonator gyro with integrated external cavity beam generator |
US20070274655A1 (en) * | 2006-04-26 | 2007-11-29 | Honeywell International Inc. | Low-loss optical device structure |
US7454102B2 (en) | 2006-04-26 | 2008-11-18 | Honeywell International Inc. | Optical coupling structure |
US7535576B2 (en) | 2006-05-15 | 2009-05-19 | Honeywell International, Inc. | Integrated optical rotation sensor and method for sensing rotation rate |
JP4755946B2 (en) * | 2006-07-11 | 2011-08-24 | 株式会社東芝 | Semiconductor memory device and manufacturing method thereof |
US8143646B2 (en) | 2006-08-02 | 2012-03-27 | Intel Corporation | Stacking fault and twin blocking barrier for integrating III-V on Si |
KR100829616B1 (en) * | 2006-12-27 | 2008-05-14 | 삼성전자주식회사 | Method for forming channel silicon layer and method for manufacturing stacked semiconductor device using the same |
KR101329352B1 (en) * | 2007-10-17 | 2013-11-13 | 삼성전자주식회사 | Method for manufacturing of semiconductor device |
US8193071B2 (en) * | 2008-03-11 | 2012-06-05 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device |
US8362566B2 (en) | 2008-06-23 | 2013-01-29 | Intel Corporation | Stress in trigate devices using complimentary gate fill materials |
US9349863B2 (en) * | 2013-08-07 | 2016-05-24 | Globalfoundries Inc. | Anchored stress-generating active semiconductor regions for semiconductor-on-insulator finfet |
CN104576381B (en) * | 2013-10-14 | 2018-01-09 | 中国科学院微电子研究所 | A kind of asymmetric ultra-thin SOI mos transistor structure and its manufacture method |
US9312164B2 (en) * | 2014-04-13 | 2016-04-12 | Texas Instruments Incorporated | Localized region of isolated silicon over dielectric mesa |
US9466520B2 (en) * | 2014-04-13 | 2016-10-11 | Texas Instruments Incorporated | Localized region of isolated silicon over recessed dielectric layer |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4381202A (en) * | 1980-03-27 | 1983-04-26 | Fujitsu Limited | Selective epitaxy by beam energy and devices thereon |
US5399234A (en) * | 1993-09-29 | 1995-03-21 | Motorola Inc. | Acoustically regulated polishing process |
US5670387A (en) * | 1995-01-03 | 1997-09-23 | Motorola, Inc. | Process for forming semiconductor-on-insulator device |
US6391695B1 (en) * | 2000-08-07 | 2002-05-21 | Advanced Micro Devices, Inc. | Double-gate transistor formed in a thermal process |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4467518A (en) * | 1981-05-19 | 1984-08-28 | Ibm Corporation | Process for fabrication of stacked, complementary MOS field effect transistor circuits |
US4489478A (en) * | 1981-09-29 | 1984-12-25 | Fujitsu Limited | Process for producing a three-dimensional semiconductor device |
US5278093A (en) * | 1989-09-23 | 1994-01-11 | Canon Kabushiki Kaisha | Method for forming semiconductor thin film |
JPH0824193B2 (en) * | 1990-10-16 | 1996-03-06 | 工業技術院長 | Manufacturing method of semiconductor device for driving flat plate type light valve |
US5273921A (en) * | 1991-12-27 | 1993-12-28 | Purdue Research Foundation | Methods for fabricating a dual-gated semiconductor-on-insulator field effect transistor |
TW215967B (en) * | 1992-01-17 | 1993-11-11 | Seiko Electron Co Ltd | MOS Poly-Si thin film transistor with a flattened channel interface and method of producing same |
US5318663A (en) * | 1992-12-23 | 1994-06-07 | International Business Machines Corporation | Method for thinning SOI films having improved thickness uniformity |
US6197623B1 (en) * | 1998-10-16 | 2001-03-06 | Seungki Joo | Method for crystallizing amorphous silicon thin-film for use in thin-film transistors and thermal annealing apparatus therefor |
-
2002
- 2002-07-29 US US10/208,890 patent/US6919238B2/en not_active Expired - Fee Related
-
2003
- 2003-04-29 US US10/426,261 patent/US20040016969A1/en not_active Abandoned
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4381202A (en) * | 1980-03-27 | 1983-04-26 | Fujitsu Limited | Selective epitaxy by beam energy and devices thereon |
US5399234A (en) * | 1993-09-29 | 1995-03-21 | Motorola Inc. | Acoustically regulated polishing process |
US5670387A (en) * | 1995-01-03 | 1997-09-23 | Motorola, Inc. | Process for forming semiconductor-on-insulator device |
US6391695B1 (en) * | 2000-08-07 | 2002-05-21 | Advanced Micro Devices, Inc. | Double-gate transistor formed in a thermal process |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040199183A1 (en) * | 1997-06-27 | 2004-10-07 | Oz Mehmet C. | Method and apparatus for circulatory valve repair |
US20050104072A1 (en) * | 2003-08-14 | 2005-05-19 | Slater David B.Jr. | Localized annealing of metal-silicon carbide ohmic contacts and devices so formed |
US9608166B2 (en) | 2003-08-14 | 2017-03-28 | Cree, Inc. | Localized annealing of metal-silicon carbide ohmic contacts and devices so formed |
US20060211262A1 (en) * | 2005-03-18 | 2006-09-21 | Samsung Electronics Co., Ltd. | Methods of laterally forming single crystalline thin film regions from seed layers |
US7459353B2 (en) * | 2005-03-18 | 2008-12-02 | Samsung Electronics Co., Ltd. | Methods of laterally forming single crystalline thin film regions from seed layers |
US20070066023A1 (en) * | 2005-09-20 | 2007-03-22 | Randhir Thakur | Method to form a device on a soi substrate |
US20080311736A1 (en) * | 2007-06-14 | 2008-12-18 | Cree, Inc. | Methods of forming ohmic layers through ablation capping layers |
US7851343B2 (en) | 2007-06-14 | 2010-12-14 | Cree, Inc. | Methods of forming ohmic layers through ablation capping layers |
Also Published As
Publication number | Publication date |
---|---|
US6919238B2 (en) | 2005-07-19 |
US20040018672A1 (en) | 2004-01-29 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6919238B2 (en) | Silicon on insulator (SOI) transistor and methods of fabrication | |
US6475869B1 (en) | Method of forming a double gate transistor having an epitaxial silicon/germanium channel region | |
US8344453B2 (en) | Method of manufacturing localized semiconductor-on-insulator (SOI) structures in a bulk semiconductor wafer | |
KR100737336B1 (en) | Semiconductor device and method for fabricating the same | |
US7777275B2 (en) | Silicon-on-insulator structures | |
US7259048B2 (en) | Vertical replacement-gate silicon-on-insulator transistor | |
US6429484B1 (en) | Multiple active layer structure and a method of making such a structure | |
US6403981B1 (en) | Double gate transistor having a silicon/germanium channel region | |
KR100572647B1 (en) | Process for fabricating vertical transistors | |
US7244990B2 (en) | Semiconductor device | |
JP4058751B2 (en) | Method for manufacturing field effect transistor | |
JP4202563B2 (en) | Semiconductor device | |
US4654958A (en) | Process for forming isolated silicon regions and field-effect devices on a silicon substrate | |
US8710588B2 (en) | Implant free extremely thin semiconductor devices | |
US7271446B2 (en) | Ultra-thin channel device with raised source and drain and solid source extension doping | |
US7413939B2 (en) | Method of growing a germanium epitaxial film on insulator for use in fabrication of CMOS integrated circuit | |
JP2008085357A (en) | Manufacturing method of fet | |
US6624486B2 (en) | Method for low topography semiconductor device formation | |
JP2004221530A (en) | Semiconductor device | |
JP2002043581A (en) | Dual/wrap-around gate field effect transistor and its manufacturing method | |
JP2004119636A (en) | Semiconductor device and method of manufacturing the same | |
KR100618796B1 (en) | Method for fabricating SOI MOS transistor | |
JP3805917B2 (en) | Manufacturing method of semiconductor device | |
JP2004296744A (en) | Process for fabricating semiconductor device | |
JP4076930B2 (en) | Manufacturing method of semiconductor device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |