|Publication number||US20040036129 A1|
|Application number||US 10/225,605|
|Publication date||Feb 26, 2004|
|Filing date||Aug 22, 2002|
|Priority date||Aug 22, 2002|
|Also published as||CN1689143A, CN100359640C, EP1532669A1, US7351628, US20040140513, US20050032342, US20050179097, WO2004019394A1|
|Publication number||10225605, 225605, US 2004/0036129 A1, US 2004/036129 A1, US 20040036129 A1, US 20040036129A1, US 2004036129 A1, US 2004036129A1, US-A1-20040036129, US-A1-2004036129, US2004/0036129A1, US2004/036129A1, US20040036129 A1, US20040036129A1, US2004036129 A1, US2004036129A1|
|Inventors||Leonard Forbes, Kie Ahn|
|Original Assignee||Micron Technology, Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (98), Referenced by (69), Classifications (21), Legal Events (1)|
|External Links: USPTO, USPTO Assignment, Espacenet|
 The present invention relates generally to semiconductor integrated circuits and, more particularly, to atomic layer deposition of CMOS gates with variable work functions.
 Conventional n-type doped polysilicon gate electrodes in CMOS technology have two problems. Firstly, the polysilicon is conductive but there can still be a surface region which can be depleted of carriers under bias conditions. This appears as an extra gate insulator thickness and is commonly referred to as gate depletion and contributes to the equivalent oxide thickness. While this region is thin, in the order of a few angstroms (Å), it becomes appreciable as gate oxide thicknesses are reduced below 2 nm or 20 Å. Another problem is that the work function is not optimum for both n-MOS and p-MOS devices, historically this was compensated for by threshold voltage adjustment implantations. However, as the devices become smaller, with channel lengths of less than 1000 Å and consequently surface space charge regions of less than 100 Å, it becomes more and more difficult to do these implantations. Threshold voltage control becomes an important consideration as power supplies are reduced to the range of one volt. Optimum threshold voltages for both PMOS and NMOS transistors need to have a magnitude of around 0.3 Volts.
 A solution to the polysilicon gate depletion problem is to replace the semiconducting gate material with a metal or highly conductive metallic nitrides. (See generally; Y. Yee-Chia et al., “Dual-metal gate CMOS technology with ultrathin silicon nitride gate dielectric IEEE Electron Device Letters, Volume: 22 Issue: 5, May, 2001, pp. 227229; L Qiang, Y. Yee Chia, et al., “Dual-metal gate technology for deep-submicron CMOS transistors,” VLSI Technology, 2000; Digest of Technical Papers. 2000 Symposium on, 2000, pp. 72-73.; and H. Wakabayashi et al., “A dual-metal gate CMOS technology using nitrogen-concentration-controlled TiNx film,” Electron Devices, IEEE Transactions on, Volume: 48 Issue: 10, October 2001, Page(s): 2363-2369.).
 As with any new circuit material, the gate electrode must be chemically and thermally compatible with both the transistor and the process. Different metals can be employed or the properties of the conductive nitride modified to provide an optimum work function. (See generally; above cited reference).
 The work function of the gate electrode—the energy needed to extract an electron—must be compatible with the barrier height of the semiconductor material. For PMOS transistors, the required work function is about 5.0 eV. Achieving the lower work function needed by NMOS transistors, about 4.1 eV, has been more difficult. FIGS. 1A and 1B illustrate the desired energy band diagrams and work functions for NMOS and PMOS transistors respectively. Refractory metals like titanium (Ti) and tantalum (Ta) oxidize rapidly under typical process conditions. One proposed solution to the problem relies on a “tuned” ruthenium—tantalum (Ru—Ta) alloy, which is stable under process conditions. When the Ta concentration is below 20 percent, the alloy's electrical properties resemble Rhubidium (Ru), a good PMOS gate electrode. When the Ta concentration is between 40 percent and 54 percent, the alloy is a good NMOS gate electrode. (See generally; H. Zhong et al., “Properties of Ru—Ta Alloys as gate electrodes for NMOS and PMOS silicon devices,” Digest of IEEE Int. Electron Devices Meeting, Washington D.C., 2001, paper 20.05; V. Misra, H. Zhong et al., “Electrical properties of Ru-based alloy gate electrodes for dual metal gate Si-CMOS,” IEEE Electron Device Letters, Volume: 23 Issue: 6, June 2002 Page(s): 354-356; and H. Zhong et al., “Electrical properties of RuO/sub 2/gate electrodes for dual metal gate Si-CMOS,” IEEE Electron Device Letters, Volume: 21 Issue: 12, December 2000 Page(s): 593-595).
 Promising candidates include metallic nitrides, such as tantalum nitride (TaN) and titanium nitride (TiN). Tantalum nitride, titanium nitride, and tungsten nitride are mid-gap work function metallic conductors commonly described for use in CMOS devices. (See generally, H. Shimada et al., “Low resistivity bcc-Ta/TaN/sub x/metal gate MNSFETs having plane gate structure featuring fully low-temperature processing below 450 degrees C.,” 2001 Symposium on VLSI Technology, Jun. 12-14 2001, Kyoto, Japan Page: 67-68; H. Shimada et al., “Tantalum nitride metal gate FD-SOI CMOS FETs using low resistivity self-grown bcc-tantalum, layer,” IEEE Trans. on Electron Devices, vol. 48, no. 8, pp. 1619-26, August 2001; B. Claflin et al., “Investigation of the growth and chemical stability of composite metal gates on ultra-thin gate dielectrics,” MRS Symposium on Silicon Front-End Technology-Materials Processing and Modelling, Apr. 13-15 1998, San Francisco, Calif., Page: 171-176; A. Yagishita et al., “Dynamic threshold voltage damascene metal gate MOSFET(DT-DMG-MOS) with low threshold voltage, high drive current and uniform electrical characteristics,” Digest Technical Papers Int. Electron Devices Meeting, San Francisco, December 2000, pp. 663-6; B. Claflin et al., “Investigation of the growth and chemical stability of composite metal gates on ultra-thin gate dielectrics,” MRS Symposium on Silicon Front-End Technology-Materials Processing and Modelling, Apr. 13-15 1998, San Francisco, Calif., Page: 171-176; and M. Moriwaki et al., “Improved metal gate process by simultaneous gate-oxide nitridation during W/WN/sub x/gate formation,” Jpn. J. Appl. Phys., vol. 39. No. 4B, pp. 2177-80, 2000). The use of a mid-gap work function makes the threshold voltages of NMOS and PMOS devices symmetrical in that the magnitudes of the threshold voltages will be the same, but both will have a magnitude larger than that which is optimum with low power supply voltages.
 Recently physical deposition, evaporation, has been used to investigate the suitability of some ternary metallic nitrides for use as gate electrodes, these included TiAlN and TaSiN. (See generally, Dae-Gyu Park et al., “Robust ternary metal gate electrodes for dual gate CMOS devices,” Electron Devices Meeting, 2001. IEDM Technical Digest. International, 2001 Page(s): 30.6.1-30.6.4). However, these were deposited by physical deposition not atomic layer deposition and only capacitor structures were fabricated, not transistors with gate structures.
 Thus, there is an ongoing need for improved CMOS transistor design.
 The above mentioned problems CMOS transistor design as well as other problems are addressed by the present invention and will be understood by reading and studying the following specification. This disclosure describes the use of atomic layer deposition of ternary metallic conductors where the composition and work function are varied to control the threshold voltage of both the NMOS and PMOS transistors in CMOS technology to provide optimum performance.
 In particular, an embodiment of the present invention includes a transistor having a source region a drain region and a channel therebetween. A gate is separated from the channel region by a gate insulator. The gate includes a ternary metallic conductor formed by atomic layer deposition. In one embodiment the ternary metallic conductor includes Tantalum Aluminum Nitride (TaAlN). In one embodiment the ternary metallic conductor includes Titanium Aluminum Nitride (TiAlN). In one embodiment the ternary metallic conductor includes Titanium Silicon Nitride (TiSiN). In one embodiment the ternary metallic conductor includes Tungsten Aluminum Nitride (WAlN). In some embodiments the gate further includes a refractory metal formed on the ternary metallic conductor.
 These and other embodiments, aspects, advantages, and features of the present invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art by reference to the following description of the invention and referenced drawings or by practice of the invention. The aspects, advantages, and features of the invention are realized and attained by means of the instrumentalities, procedures, and combinations particularly pointed out in the appended claims.
FIGS. 1A and 1B illustrate the desired energy band diagrams and work functions for NMOS and PMOS transistors respectively.
FIG. 2 is a graph which plots electron affinity versus the energy bandgap for various metallic nitrides employed in various embodiments of the present invention.
FIG. 3 illustrates an embodiment of a transistor structure formed according to the teachings of the present invention.
FIG. 4 illustrates an embodiment of a memory device, utilizing ternary metallic gates formed by atomic layer deposition, according to embodiments of the present invention.
FIG. 5 is a block diagram of an electrical system, or processor-based system, utilizing ternary metallic gates formed by atomic layer deposition, according to embodiments of the present invention.
 In the following detailed description of the invention, reference is made to the accompanying drawings which form a part hereof, and in which is shown, by way of illustration, specific embodiments in which the invention may be practiced. In the drawings, like numerals describe substantially similar components throughout the several views. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present invention.
 The terms wafer and substrate used in the following description include any structure having an exposed surface with which to form the integrated circuit (IC) structure of the invention. The term substrate is understood to include semiconductor wafers. The term substrate is also used to refer to semiconductor structures during processing, and may include other layers that have been fabricated thereupon. Both wafer and substrate include doped and undoped semiconductors, epitaxial semiconductor layers supported by a base semiconductor or insulator, as well as other semiconductor structures well known to one skilled in the art. The term conductor is understood to include semiconductors, and the term insulator is defined to include any material that is less electrically conductive than the materials referred to as conductors. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims, along with the full scope of equivalents to which such claims are entitled.
 This disclosure describes the use of atomic layer deposition of ternary metallic conductors where the composition is varied and work function varied, see FIG. 2, to control the threshold voltage of both the NMOS and PMOS transistors in CMOS technology to provide optimum performance. In the several embodiments, these include the use of:
 (i) TaAlN;
 (ii) TiAlN;
 (iii) TiSiN; and
 (iv) WAlN
 As the ternary metallic conductors. Conventional highly doped polysilicon or refractory metals as W, Ta, Ti are deposited over the metallic conductors to give the gate structure shown in FIG. 3. As shown in FIG. 3, the transistor 301 structure includes a source region 302, a drain region 304, and a channel 306 therebetween. A gate 310 is separated from the channel region by a gate insulator 308. According to the teachings of the present invention, the gate 310 includes a ternary metallic conductor formed by atomic layer deposition. In one embodiment the ternary metallic conductor includes Tantalum Aluminum Nitride (TaAlN). In one embodiment the ternary metallic conductor includes Titanium Aluminum Nitride (TiAlN). In one embodiment the ternary metallic conductor includes Titanium Silicon Nitride (TiSiN). In one embodiment the ternary metallic conductor includes Tungsten Aluminum Nitride (WAlN). As shown in FIG. 3, in some embodiments the gate further includes a layer of highly conductive polysilicon 312, or alternatively a refractory metal layer 312, formed on the ternary metallic conductor 310. In embodiments having a refractory metal layer, the layer 312 includes for example, and not by way of limitation, refractory metals such as tantalum, titanium and tungsten.
 Methods of Formation
 Atomic Layer Deposition developed in the early 70s is a modification of CVD and can also be called as “alternately pulsed-CVD”. (See generally, Ofer Sneh et al., “Thin film atomic layer deposition equipment for semiconductor processing”, Thin Solid Films, 402 (2002) 248-261). In this technique, gaseous precursors are introduced one at a time to the substrate surface, and between the pulses the reactor is purged with an inert gas or evacuated. In the first reaction step the precursor is saturatively chemisorbed at the substrate surface, and during the subsequent purging the precursor is removed from the reactor. In the second step, other precursor is introduced on the substrate and the desired films growth reaction takes place. After that the reaction byproducts and the precursor excess are purged out from the reactor. When the precursor chemistry is favorable, i.e. the precursor adsorb and react with each other aggressively, one ALD cycle can be preformed in less than one second in the properly designed flow type reactors.
 The striking feature of ALD is the saturation of all the reaction and purging steps which makes the growth self-limiting. This brings the large area uniformity and conformality, the most important properties of ALD, as shown in very different cases, viz. planar substrates, deep trenches, and in the extreme cases of porous silicon and high surface area silica and alumina powers. Also the control of the film thickness is straightforward and can be made by simply calculating the growth cycles. ALD was originally developed to manufacture luminescent and dielectric films needed in electroluminescent displays, and a lot of effort has been put to the growth of doped zinc sulfide and alkaline earth metal sulfide films. Later ALD has been studied for the growth of different epitaxial II-V and II-VI films, nonepitaxial crystalline or amorphous oxide and nitride films are their multilayer structures.
 There has been considerable interest towards the ALD growth of silicon and germanium films but due to the difficult precursor chemistry the results have not been very successful.
 Reaction sequence ALD (RS-ALD) films have several unique and unmatched advantages:
 Continuity at the interface avoiding poorly defined nucleating regions that are typical for CVD (<20 Å) and PVD (<50 Å) films. To achieve this continuity, the substrate surface must be activated to react directly with the first exposure of RS-ALD precursor.
 Unmatched conformality over toughest substrate topologies with robust processes that can only be achieved with a layer-by-layer deposition technique.
 Typically, low temperature and mildly oxidizing processes. This is thought to be a major advantage for gate insulator processing where deposition of non-silicon based dielectrics without oxidizing the substrate (with the oxidation-precursor) is a major concern.
 RS-ALD ability to engineer multilayer laminate films, possibly down to monolayer resolution, as well as alloy composite films appear to be unique. This ability comes from the combination of being able to control deposition with monolayer precision and the ability to deposit continuous monolayers of amorphous films (that is unique to RS-ALD).
 Unprecedented process robustness. RS-ALD processes are free of first wafer effects and the chamber dependence. Accordingly, RS-ALD processes will be easier to transfer from development to production and from 200 to 300 mm wafer size.
 Thickness depends solely on the number of cycles. Thickness can be “dialed in” as a simple recipe change bearing no need for additional process development upon technology generation advance.
 (See generally, Shunsuke Morishita et al., “Atomic-Layer Chemical-Vapor-Deposition of SiO2 by Cyclic Exposure of CHOSi(NCO)3 and H2O2,” Jpn. J. Appl. Phys. Vol. 34 (1955) pp. 5738-5742.).
 Atomic Layer Deposition of Nitrides
 Ta—N: Plasma-enhanced atomic layer deposition (PEALD) of tantalum nitride (Ta—N) thin films at a deposition temperature of 260° C. using hydrogen radicals as a reducing agent for Tertbutylimidotris(diethylamido) tantalum have been described. (See generally, Jin-Seong Park et al, “Plasma-Enhanced Atomic Layer Deposition of Tantalum Nitrides Using Hydrogen Radicals as a Reducing Agent”, Electrochemical and Solid-State Lett., 4(4) C17-C19, 2001). The PEALD yields superior Ta—N films with an electric resistivity of 400 μΩcm and no aging effect under exposure to air. The film density is higher than that of Ta—N films formed by typical ALD, in which NH3 is used instead of hydrogen radicals. In addition, the as-deposited films are not amorphous, but rather polycrystalline structure of cubit TaN. The density and crystallinity of the films increases with the pulse time of hydrogen plasma. The films are Ta-rich in composition and contain around 15 atomic % of carbon impurity. In the PEALD of Ta—N films, hydrogen radicals are used a reducing agent instead of NH3, which is used as a reactant gas in typical Ta—N ALD. Films are deposited on SiO2 (100 nm)/Si wafers at a deposition temperature of 260° C. and a deposition pressure of 133 Pa in a cold-walled reactor using (Net2)3 Ta=Nbut [tertbutylimidotris(diethylamido)tantalum, TBTDET] as a precursor of Ta. The liquid precursor is contained in a bubbler heated at 70° C. and carried by 35 sccm argon. One deposition cycle consist of an exposure to a metallorganic precursor of TBTDET, a purge period with Ar, and an exposure to hydrogen plasma, followed by another purge period with Ar. The Ar purge period of 15 seconds instead between each reactant gas pulse isolates the reactant gases from each other. To ignite and maintain the hydrogen plasma synchronized with the deposition cycle, a rectangular shaped electrical power is applied between the upper and lower electrode. The showerhead for uniform distribution of the reactant gases in the reactor, capacitively coupled with an rf (13.56 MHz) plasma source operated at a power of 100 W, is used as the upper electrode. The lower electrode, on which a wafer resides, is grounded. Film thickness and morphology were analyzed by field emission scanning electron microscopy.
 Ta (Al)N( C): Technical work on thin films have been studied using TaCl5 or TaBr5 and NH3 as precursors and Al(CH3)3 as an additional reducing agent. (See generally, Petra Alen et al., “Atomic Layer Deposition of Ta (Al) N (C) Thin Films Using Trimethylaluminum as a Reducing Agent”, Jour, of the Electrochemical Society, 148 (10), G566-G571 (2001)). The deposition temperature is varied between 250 and 400° C. The films contained aluminum, carbon, and chlorine impurities. The chlorine content decreased drastically as the deposition temperature is increased. The film deposited at 400° C. contained less than 4 atomic % chlorine and also had the lowest resistivity, 1300 μΩcm. Five different deposition processes with the pulsing orders TaCl5—TMA—NH3, TMA—TaCl5—NH3, TaBr5—NH3, TaBr5—Zn—NH3, and TaBr5—TMA—NH3 are used. TaCl5, TaBr5, and Zn are evaporated from open boats held inside the reactor. The evaporation temperatures for TaCl4, TaBr5, and Zn are 90, 140, 380° C., respectively. Ammonia is introduced into the reactor through a mass flowmeter, a needle valve, and a solenoid valve. The flow rate is adjusted to 14 sccm during a continuous flow. TMA is kept at a constant temperature of 16° C. and pulsed through the needle and solenoid valve. Pulse times are 0.5 s for TaCl5, TaBr5, NH3, and Zn whereas the pulse length of TMA is varied between 0.2 and 0.8 s. The length of the purge pulse is always 0.3 s. Nitrogen gas is used for the transportation of the precursor and as a purging gas. The flow rate of nitrogen is 400 sccm.
 TiN: Atomic layer deposition (ALD) of amorphous TiN films on SiO2 between 170° C. and 210° C. has been achieved by the alternate supply of reactant sources, Ti[N(C2H5CH3)2]4 [tetrakis(ethylmethylamino)titanium: TEMAT] and NH3. These reactant sources are injected into the reactor in the following order: TEMAT vapor pulse, Ar gas pulse, NH3 gas pulse and Ar gas pulse. Film thickness per cycle saturated at around 1.6 monolayers per cycle with sufficient pulse times of reactant sources at 200° C. The results suggest that film thickness per cycle could exceed 1 ML/cycle in ALD, and are explained by the rechemisorption mechanism of the reactant sources. An ideal linear relationship between number of cycles and film thickness is confirmed. (See generally, J. -S. Min et al., “Atomic layer deposition of TiN films by alternate supply on Tetrakis (ethylmethyllamino)-titanium and ammonia,” Jpn. J. Appl. Phys., Vol. 37, Part 1, No. 9A, pp. 4999-5004, Sept. 15 1998).
 TiAlN: Koo et al published paper on the study of the characteristics of TiAlN thin film deposited by atomic layer deposition method. (See generally, Jaehyong Koo et al., “Study on the characteristics of TiAlN thin film deposited by atomic layer deposition method,” J. Vac. Sci. Technol. A, 19(6), 2831-2834 (2001)). The series of metal-Si—N barriers have high resistivity above 1000 μΩcm. They proposed another ternary diffusion barrier of TiAlN. TiAlN film exhibited a NaCl structure in spite of considerable Al contents. TiAlN films are deposited using the TiCl4 and dimethylaluminum hydride ethypiperdine (DMAH-EPP) as the titanium and aluminum precursors, respectively. TiCl4 is vaporized from the liquid at 13-15° C. and introduced into the ALD chamber, which is supplied by a bubbler using the Ar carrier gas with a flow rate of 30 sccm. The DMAH-EPP precursor is evaporated at 60° C. and introduced into the ALD chamber with the same flow rate of TiCI4. The NH3 gas is also used as a reactant gas and its flow rate is about 60 sccm. Ar purging gas is introduced for the complete separation of the source and reactant gases. TiAlN films are deposited at the temperatures between 350 and 400° C. and total pressure is kept constant to be two torr.
 TiSiN: Metal-organic atomic-layer deposition (MOALD) achieves near-perfect step coverage step and control precisely the thickness and composition of grown thin films. A MOALD technique for ternary Ti—Si—N films using a sequential supply of Ti[N(CH3)2]4 [tetrakis (dimethylamido) titanium: TDMAT], silane (SiH4), and ammonia (NH3), has been developed and evaluated the Cu diffusion barrier characteristics of a 10 nm Ti—Si—N film with high-frequency C—V measurements. (See generally, Jae-Sik Min et al, “Metal-organic atomic-layer deposition of titanium-silicon-nitride films”, Appl. Phys, Lett., Vol. 75, No. 11, 1521-1523 (1999)). At 180° C. deposition temperature, silane is supplied separately in the sequence of the TDMAT pulse, silane pulse, and the ammonia pulse. The silicon content is the deposited films and the deposition thickness per cycle remained almost constant at 18 at. % and 0.22 nm/cycle, even though the silane partial pressure varied from 0.27 to 13.3 Pa. Especially, the Si content dependence is strikingly different from the conventional chemical-vapor deposition. Step coverage is approximately 100% even on the 0.3 μm diameter hole with slightly negative slope and 10:1 aspect ratio.
 WN: Tungsten nitride films have been deposited with the atomic layer control using sequential surface reactions. The tungsten nitride film growth is accomplished by separating the binary reaction 2WF6+NH3→W2N+3HF+9/2 F2 into two half-reactions. (See generally, J. W. Kraus et al, “Atomic Layer Deposition of Tungsten Nitride Films Using Sequential Surface Reactions”, 147 (3) 1175-1181 (2000)). Successive application of the WF6 and NH3 half-reactions in an ABAB . . . sequence produced tungsten nitride deposition at substrate temperatures between 600 and 800 K. Transmission Fourier transform infrared (FTIR) spectroscopy monitored the coverage of WFx* and NHy* surface species on high surface area particles during the WF6 and NH3 half-reactions. The FTIR spectroscope results demonstrated the WF6 and NH3 half-reactions are complete and self-limiting at temperatures >600 K. In situ spectroscopic ellipsometry monitored the film growth on Si(100) substrate vs. temperature and reactant exposure. A tungsten nitride deposition rate of 2.55 Å/AB cycle is measured at 600-800 K for WF6 and NH3 reactant exposure >3000 L and 10,000 L, respectively. X-ray photoelectron spectroscopy depth-profiling experiments determined that the films had a W2N stoichiometry with low C and O impurity concentrations. X-ray diffraction investigations revealed that the tungsten nitride films are microcrystalline. Atomic force microscopy measurements of the deposited films observed remarkably flat surface indicating smooth film growth. These smooth tungsten nitride films deposited with atomic layer control should be used as diffusion control for Cu on contact and via holes.
 AlN: Aluminum nitride (AlN) has been grown on porous silica by atomic layer chemical vapor deposition (ALCVD) from trimethylaluminum (TMA) and ammonia precursors. (See generally, R. L. Pruurunen et al, “Growth of aluminum nitride on porous silica by atomic layer chemical vapor deposition”, Applied Surface Science, 165, 193-202 (2000)). The ALCVD growth is based on alternating, separated, saturating reactions of the gaseous precursors with the solid substrates. TMA and ammonia are reacted at 423 and 623 Kelvin (K), respectively, on silica which has been dehydroxylated at 1023 K pretreated with ammonia at 823 K. The growth in three reaction cycles is investigated quantitatively by elemental analysis, and the surface reaction products are identified by IR and solid state and Si NMR measurements. Steady growth of about 2 aluminum atoms/nm2 silica/reaction cycle is obtained. The growth mainly took place through (I) the reaction of TMA which resulted in surface Al—Me and Si Me groups, and (II) the reaction of ammonia which replaced aluminium-bonded methyl groups with amino groups. Ammonia also reacted in part with the silicon-bonded methyl groups formed in the dissociated reaction of TMA with siloxane bridges. TMA reacted with the amino groups, as it did with surface silanol groups and siloxane bridges. In general, the Al—N layer interacted strongly with the silica substrates, but in the third reaction cycle AlN-type sites may have formed.
 In FIG. 4 a memory device is illustrated according to the teachings of the present invention. The memory device 440 contains a memory array 442, row and column decoders 444, 448 and a sense amplifier circuit 446. The memory array 442 consists of a number of transistor cells 400, having ternary metallic gates formed by atomic layer deposition, whose word lines 480 and bit lines 460 are commonly arranged into rows and columns, respectively. The bit lines 460 of the memory array 442 are connected to the sense amplifier circuit 446, while its word lines 480 are connected to the row decoder 444. Address and control signals are input on address/control lines 461 into the memory device 440 and connected to the column decoder 448, sense amplifier circuit 446 and row decoder 444 and are used to gain read and write access, among other things, to the memory array 442.
 The column decoder 448 is connected to the sense amplifier circuit 446 via control and column select signals on column select lines 462. The sense amplifier circuit 446 receives input data destined for the memory array 442 and outputs data read from the memory array 442 over input/output (I/O) data lines 463. Data is read from the cells of the memory array 442 by activating a word line 480 (via the row decoder 444), which couples all of the memory cells corresponding to that word line to respective bit lines 460, which define the columns of the array. One or more bit lines 460 are also activated. When a particular word line 480 and bit lines 460 are activated, the sense amplifier circuit 446 connected to a bit line column detects and amplifies the conduction sensed through a given transistor cell and transferred to its bit line 460 by measuring the potential difference between the activated bit line 460 and a reference line which may be an inactive bit line. Again, in the read operation the source region of a given cell is couple to a grounded sourceline or array plate (not shown). The operation of Memory device sense amplifiers is described, for example, in U.S. Pat. Nos. 5,627,785; 5,280,205; and 5,042,011, all assigned to Micron Technology Inc., and incorporated by reference herein.
FIG. 5 is a block diagram of an electrical system, or processor-based system, 500 utilizing transistor cells having ternary metallic gates formed by atomic layer deposition according to the teachings of the present invention. For example, by way of example and not by way of limitation, memory 512 is constructed in accordance with the present invention to have transistor cells having ternary metallic gates formed by atomic layer deposition. However, the invention is not so limited and the same can apply to transistors in the CPU, etc. The processor-based system 500 may be a computer system, a process control system or any other system employing a processor and associated memory. The system 500 includes a central processing unit (CPU) 502, e.g., a microprocessor, that communicates with the memory 512 and an I/O device 508 over a bus 520. It must be noted that the bus 520 may be a series of buses and bridges commonly used in a processor-based system, but for convenience purposes only, the bus 520 has been illustrated as a single bus. A second I/O device 510 is illustrated, but is not necessary to practice the invention. The processor-based system 500 can also includes read-only memory (ROM) 514 and may include peripheral devices such as a floppy disk drive 504 and a compact disk (CD) ROM drive 506 that also communicates with the CPU 502 over the bus 520 as is well known in the art.
 It will be appreciated by those skilled in the art that additional circuitry and control signals can be provided, and that the processor-based system 500 has been simplified to help focus on the invention.
 It will be understood that the embodiment shown in FIG. 5 illustrates an embodiment for electronic system circuitry in which the novel ternary metallic gate transistor cells, formed by atomic layer deposition, are used. The illustration of system 500, as shown in FIG. 5, is intended to provide a general understanding of one application for the structure and circuitry of the present invention, and is not intended to serve as a complete description of all the elements and features of an electronic system using the novel ternary metallic gate transistor cells, formed by atomic layer deposition. Further, the invention is equally applicable to any size and type of system 500 using the novel ternary metallic gate transistor cells, formed by atomic layer deposition, and is not intended to be limited to that described above. As one of ordinary skill in the art will understand, such an electronic system can be fabricated in single-package processing units, or even on a single semiconductor chip, in order to reduce the communication time between the processor and the memory device.
 Applications containing the novel ternary metallic gate transistor cells, formed by atomic layer deposition as described in this disclosure, include electronic systems for use in memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules, and may include multilayer, multichip modules. Such circuitry can further be a subcomponent of a variety of electronic systems, such as a clock, a television, a cell phone, a personal computer, an automobile, an industrial control system, an aircraft, and others.
 This disclosure describes the use of atomic layer deposition of ternary metallic conductors as transistor gates. The composition is varied and work function varied to control the threshold voltage of both the NMOS and PMOS transistors in CMOS technology to provide optimum performance.
 It is to be understood that the above description is intended to be illustrative, and not restrictive. Many other embodiments will be apparent to those of skill in the art upon reviewing the above description. The scope of the invention should, therefore, be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US4058430 *||Nov 25, 1975||Nov 15, 1977||Tuomo Suntola||Method for producing compound thin films|
|US4389973 *||Dec 11, 1981||Jun 28, 1983||Oy Lohja Ab||Apparatus for performing growth of compound thin films|
|US4413022 *||Jun 21, 1979||Nov 1, 1983||Canon Kabushiki Kaisha||Method for performing growth of compound thin films|
|US4920071 *||Aug 18, 1987||Apr 24, 1990||Fairchild Camera And Instrument Corporation||High temperature interconnect system for an integrated circuit|
|US5042011 *||May 22, 1989||Aug 20, 1991||Micron Technology, Inc.||Sense amplifier pulldown device with tailored edge input|
|US5153144 *||Nov 18, 1991||Oct 6, 1992||Hitachi, Ltd.||Method of making tunnel EEPROM|
|US5192589 *||Sep 5, 1991||Mar 9, 1993||Micron Technology, Inc.||Low-pressure chemical vapor deposition process for depositing thin titanium nitride films having low and stable resistivity|
|US5246881 *||Apr 14, 1993||Sep 21, 1993||Micron Semiconductor, Inc.||Low-pressure chemical vapor deposition process for depositing high-density, highly-conformal, titanium nitride films of low bulk resistivity|
|US5262199 *||Apr 17, 1992||Nov 16, 1993||Center For Innovative Technology||Coating porous materials with metal oxides and other ceramics by MOCVD|
|US5280205 *||Apr 16, 1992||Jan 18, 1994||Micron Technology, Inc.||Fast sense amplifier|
|US5399379 *||May 11, 1994||Mar 21, 1995||Micron Semiconductor, Inc.||Low-pressure chemical vapor deposition process for depositing high-density, highly-conformal titanium nitride films of low bulk resistivity|
|US5627785 *||Mar 15, 1996||May 6, 1997||Micron Technology, Inc.||Memory device with a sense amplifier|
|US5659057 *||Feb 9, 1996||Aug 19, 1997||Micron Technology, Inc.||Five- and six-coordinate precursors for titanium nitride deposition|
|US5735960 *||Apr 2, 1996||Apr 7, 1998||Micron Technology, Inc.||Apparatus and method to increase gas residence time in a reactor|
|US5747116 *||Jan 16, 1996||May 5, 1998||Micron Technology, Inc.||Method of forming an electrical contact to a silicon substrate|
|US5796166 *||Jun 21, 1996||Aug 18, 1998||Ibm Corporation||Tasin oxygen diffusion barrier in multilayer structures|
|US5866205 *||Dec 13, 1996||Feb 2, 1999||Micron Technology, Inc.||Process for titanium nitride deposition using five- and six-coordinate titanium complexes|
|US5916365 *||Aug 16, 1996||Jun 29, 1999||Sherman; Arthur||Sequential chemical vapor deposition|
|US5972430 *||Nov 26, 1997||Oct 26, 1999||Advanced Technology Materials, Inc.||Digital chemical vapor deposition (CVD) method for forming a multi-component oxide layer|
|US5990559 *||Mar 30, 1999||Nov 23, 1999||Micron Technology, Inc.||Circuitry comprising roughened platinum layers, platinum-containing materials, capacitors comprising roughened platinum layers, methods forming roughened layers of platinum, and methods of forming capacitors|
|US6020024 *||Aug 4, 1997||Feb 1, 2000||Motorola, Inc.||Method for forming high dielectric constant metal oxides|
|US6027961 *||Jun 30, 1998||Feb 22, 2000||Motorola, Inc.||CMOS semiconductor devices and method of formation|
|US6081034 *||Jan 23, 1998||Jun 27, 2000||Micron Technology, Inc.||Low-resistance contact to silicon having a titanium silicide interface and an amorphous titanium carbonitride barrier layer|
|US6107656 *||Oct 28, 1997||Aug 22, 2000||Oki Electric Industry Co., Ltd.||Ferroelectric transistors, semiconductor storage devices, method of operating ferroelectric transistors and method of manufacturing ferromagnetic transistors|
|US6110529 *||Jun 7, 1995||Aug 29, 2000||Advanced Tech Materials||Method of forming metal films on a substrate by chemical vapor deposition|
|US6171900 *||Apr 15, 1999||Jan 9, 2001||Taiwan Semiconductor Manufacturing Company||CVD Ta2O5/oxynitride stacked gate insulator with TiN gate electrode for sub-quarter micron MOSFET|
|US6174377 *||Jan 4, 1999||Jan 16, 2001||Genus, Inc.||Processing chamber for atomic layer deposition processes|
|US6175129 *||Mar 23, 1999||Jan 16, 2001||Micron Technology, Inc.||Capacitor structures, DRAM cell structures, methods of forming capacitors, methods of forming DRAM cells, and integrated circuits incorporating capacitor structures and DRAM cell structures|
|US6197628 *||Aug 27, 1998||Mar 6, 2001||Micron Technology, Inc.||Ruthenium silicide diffusion barrier layers and methods of forming same|
|US6200893 *||Mar 11, 1999||Mar 13, 2001||Genus, Inc||Radical-assisted sequential CVD|
|US6203613 *||Oct 19, 1999||Mar 20, 2001||International Business Machines Corporation||Atomic layer deposition with nitrate containing precursors|
|US6204172 *||Sep 3, 1998||Mar 20, 2001||Micron Technology, Inc.||Low temperature deposition of barrier layers|
|US6218293 *||Nov 13, 1998||Apr 17, 2001||Micron Technology, Inc.||Batch processing for semiconductor wafers to form aluminum nitride and titanium aluminum nitride|
|US6225168 *||Jun 4, 1998||May 1, 2001||Advanced Micro Devices, Inc.||Semiconductor device having metal gate electrode and titanium or tantalum nitride gate dielectric barrier layer and process of fabrication thereof|
|US6291340 *||Jan 31, 2000||Sep 18, 2001||Micron Technology, Inc.||Method of forming low-resistance contact to silicon having a titanium silicide interface and an amorphous titanium carbonitride barrier layer|
|US6323081 *||Sep 3, 1998||Nov 27, 2001||Micron Technology, Inc.||Diffusion barrier layers and methods of forming same|
|US6325017 *||Aug 25, 1999||Dec 4, 2001||Micron Technology, Inc.||Apparatus for forming a high dielectric film|
|US6338880 *||Sep 4, 1998||Jan 15, 2002||Micron Technology, Inc.||Chemical vapor deposition process for depositing titanium nitride films from an organometallic compound|
|US6342277 *||Apr 14, 1999||Jan 29, 2002||Licensee For Microelectronics: Asm America, Inc.||Sequential chemical vapor deposition|
|US6365519 *||Apr 16, 2001||Apr 2, 2002||Micron Technology, Inc.||Batch processing for semiconductor wafers to form aluminum nitride and titanium aluminum nitride|
|US6410432 *||Apr 27, 1999||Jun 25, 2002||Tokyo Electron Limited||CVD of integrated Ta and TaNx films from tantalum halide precursors|
|US6420279 *||Jun 28, 2001||Jul 16, 2002||Sharp Laboratories Of America, Inc.||Methods of using atomic layer deposition to deposit a high dielectric constant material on a substrate|
|US6423619 *||Nov 30, 2001||Jul 23, 2002||Motorola, Inc.||Transistor metal gate structure that minimizes non-planarity effects and method of formation|
|US6445023 *||Mar 16, 1999||Sep 3, 2002||Micron Technology, Inc.||Mixed metal nitride and boride barrier layers|
|US6448192 *||Apr 16, 2001||Sep 10, 2002||Motorola, Inc.||Method for forming a high dielectric constant material|
|US6458701 *||Oct 12, 2000||Oct 1, 2002||Samsung Electronics Co., Ltd.||Method for forming metal layer of semiconductor device using metal halide gas|
|US6468924 *||May 31, 2001||Oct 22, 2002||Samsung Electronics Co., Ltd.||Methods of forming thin films by atomic layer deposition|
|US6475276 *||Oct 13, 2000||Nov 5, 2002||Asm Microchemistry Oy||Production of elemental thin films using a boron-containing reducing agent|
|US6482733 *||Apr 26, 2001||Nov 19, 2002||Asm Microchemistry Oy||Protective layers prior to alternating layer deposition|
|US6482740 *||May 15, 2001||Nov 19, 2002||Asm Microchemistry Oy||Method of growing electrical conductors by reducing metal oxide film with organic compound containing -OH, -CHO, or -COOH|
|US6531192 *||Oct 28, 2001||Mar 11, 2003||Micron Technology, Inc.||Chemical vapor deposition process for depositing titanium nitride films from an organo-metallic compound|
|US6534395 *||Mar 6, 2001||Mar 18, 2003||Asm Microchemistry Oy||Method of forming graded thin films using alternating pulses of vapor phase reactants|
|US6534420 *||Jul 18, 2001||Mar 18, 2003||Micron Technology, Inc.||Methods for forming dielectric materials and methods for forming semiconductor devices|
|US6548405 *||Apr 2, 2002||Apr 15, 2003||Micron Technology, Inc.||Batch processing for semiconductor wafers to form aluminum nitride and titanium aluminum nitride|
|US6551399 *||Jan 10, 2000||Apr 22, 2003||Genus Inc.||Fully integrated process for MIM capacitors using atomic layer deposition|
|US6576053 *||Oct 6, 2000||Jun 10, 2003||Samsung Electronics Co., Ltd.||Method of forming thin film using atomic layer deposition method|
|US6590251 *||Jul 23, 2001||Jul 8, 2003||Samsung Electronics Co., Ltd.||Semiconductor devices having metal layers as barrier layers on upper or lower electrodes of capacitors|
|US6605549 *||Sep 29, 2001||Aug 12, 2003||Intel Corporation||Method for improving nucleation and adhesion of CVD and ALD films deposited onto low-dielectric-constant dielectrics|
|US6617634 *||Feb 12, 2002||Sep 9, 2003||Micron Technology, Inc.||RuSixOy-containing adhesion layers and process for fabricating the same|
|US6620670 *||Jan 18, 2002||Sep 16, 2003||Applied Materials, Inc.||Process conditions and precursors for atomic layer deposition (ALD) of AL2O3|
|US6624517 *||Feb 16, 2000||Sep 23, 2003||Micron Technology, Inc.||Low-resistance contact to silicon having a titanium silicide interface and an amorphous titanium carbonitride barrier layer|
|US6630201 *||Oct 24, 2001||Oct 7, 2003||Angstron Systems, Inc.||Adsorption process for atomic layer deposition|
|US6630391 *||Apr 20, 2001||Oct 7, 2003||Micron Technology, Inc.||Boron incorporated diffusion barrier material|
|US6630718 *||Jul 26, 1999||Oct 7, 2003||Micron Technology, Inc.||Transistor gate and local interconnect|
|US6632736 *||Aug 3, 2001||Oct 14, 2003||Micron Technology, Inc.||Method of forming low-resistance contact to silicon having a titanium silicide interface and an amorphous titanium carbonitride barrier layer|
|US6635939 *||Aug 24, 1999||Oct 21, 2003||Micron Technology, Inc.||Boron incorporated diffusion barrier material|
|US6674109 *||Sep 28, 2000||Jan 6, 2004||Rohm Co., Ltd.||Nonvolatile memory|
|US6723642 *||Feb 27, 2003||Apr 20, 2004||Electronics And Telecommunications Research Institute||Method for forming nitrogen-containing oxide thin film using plasma enhanced atomic layer deposition|
|US6734061 *||Jun 25, 2001||May 11, 2004||Hynix Semiconductor Inc.||Semiconductor memory device having a plug contacted to a capacitor electrode and method for fabricating the capacitor|
|US6737317 *||Feb 12, 2002||May 18, 2004||Micron Technology, Inc.||Method of manufacturing a capacitor having RuSixOy-containing adhesion layers|
|US6812139 *||Oct 25, 2002||Nov 2, 2004||Micron Technology, Inc.||Method for metal fill by treatment of mobility layers|
|US6873020 *||Feb 22, 2002||Mar 29, 2005||North Carolina State University||High/low work function metal alloys for integrated circuit electrodes|
|US6881667 *||Aug 8, 2003||Apr 19, 2005||Micron Technology, Inc.||Low-resistance contact to silicon having a titanium silicide interface and an amorphous titanium carbonitride barrier layer|
|US6908849 *||Sep 1, 2004||Jun 21, 2005||Micron Technology, Inc.||High aspect ratio contact structure with reduced silicon consumption|
|US6911381 *||Oct 6, 2003||Jun 28, 2005||Micron Technology Inc.||Boron incorporated diffusion barrier material|
|US6919273 *||Dec 9, 1999||Jul 19, 2005||Tokyo Electron Limited||Method for forming TiSiN film, diffusion preventive film comprising TiSiN film, semiconductor device and its production method, and apparatus for forming TiSiN film|
|US6921702 *||Jul 30, 2002||Jul 26, 2005||Micron Technology Inc.||Atomic layer deposited nanolaminates of HfO2/ZrO2 films as gate dielectrics|
|US6953730 *||Dec 20, 2001||Oct 11, 2005||Micron Technology, Inc.||Low-temperature grown high quality ultra-thin CoTiO3 gate dielectrics|
|US6953743 *||Aug 8, 2003||Oct 11, 2005||Micron Technology, Inc.|
|US6958302 *||Dec 4, 2002||Oct 25, 2005||Micron Technology, Inc.||Atomic layer deposited Zr-Sn-Ti-O films using TiI4|
|US6967154 *||Aug 26, 2002||Nov 22, 2005||Micron Technology, Inc.||Enhanced atomic layer deposition|
|US7018933 *||Apr 30, 2003||Mar 28, 2006||Samsung Electronics, Co., Ltd.||Method of forming a metal-insulator-metal capacitor|
|US20010014521 *||Apr 16, 2001||Aug 16, 2001||Kraus Brenda D.||Batch processing for semiconductor wafers to form aluminum nitride and titanium aluminum nitride|
|US20010050039 *||Jun 5, 2001||Dec 13, 2001||Park Chang-Soo||Method of forming a thin film using atomic layer deposition method|
|US20020001906 *||Jun 15, 2001||Jan 3, 2002||Park Dae Gyu||Method of manufacturing a gate in a semiconductor device|
|US20020106896 *||Apr 2, 2002||Aug 8, 2002||Kraus Brenda D.||Batch processing for semiconductor wafers to form aluminum nitride and titanium aluminum nitride|
|US20020155688 *||Apr 20, 2001||Oct 24, 2002||Ahn Kie Y.||Highly reliable gate oxide and method of fabrication|
|US20020155689 *||Feb 11, 2002||Oct 24, 2002||Ahn Kie Y.||Highly reliable gate oxide and method of fabrication|
|US20020192974 *||Jun 13, 2001||Dec 19, 2002||Ahn Kie Y.||Dielectric layer forming method and devices formed therewith|
|US20020195683 *||Mar 27, 2000||Dec 26, 2002||Kim Yeong-Kwan||Semiconductor device and method for manufacturing the same|
|US20030017717 *||Jul 18, 2001||Jan 23, 2003||Ahn Kie Y.||Methods for forming dielectric materials and methods for forming semiconductor devices|
|US20030162342 *||Feb 23, 2002||Aug 28, 2003||Taiwan Semiconductor Manufacturing Co., Ltd.||Method for fabricating metal gates in deep sub-micron devices|
|US20040140513 *||Jan 9, 2004||Jul 22, 2004||Micron Technology, Inc.||Atomic layer deposition of CMOS gates with variable work functions|
|US20040164362 *||Feb 23, 2004||Aug 26, 2004||Conley John F.||Reactive gate electrode conductive barrier|
|US20040217410 *||May 26, 2004||Nov 4, 2004||Micron Technology, Inc.||Enhanced atomic layer deposition|
|US20050032342 *||Aug 30, 2004||Feb 10, 2005||Micron Technology, Inc.||Atomic layer deposition of CMOS gates with variable work functions|
|US20050042373 *||Aug 18, 2003||Feb 24, 2005||Kraus Brenda D.||Atomic layer deposition methods of forming conductive metal nitride comprising layers|
|US20050179097 *||Jan 20, 2005||Aug 18, 2005||Micron Technology, Inc.||Atomic layer deposition of CMOS gates with variable work functions|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US6967131 *||Oct 29, 2003||Nov 22, 2005||International Business Machines Corp.||Field effect transistor with electroplated metal gate|
|US6970053||May 22, 2003||Nov 29, 2005||Micron Technology, Inc.||Atomic layer deposition (ALD) high permeability layered magnetic films to reduce noise in high speed interconnection|
|US7045406 *||May 5, 2003||May 16, 2006||Asm International, N.V.||Method of forming an electrode with adjusted work function|
|US7154354||Feb 22, 2005||Dec 26, 2006||Micron Technology, Inc.||High permeability layered magnetic films to reduce noise in high speed interconnection|
|US7189287||Jun 29, 2004||Mar 13, 2007||Micron Technology, Inc.||Atomic layer deposition using electron bombardment|
|US7332433||Sep 22, 2005||Feb 19, 2008||Sematech Inc.||Methods of modulating the work functions of film layers|
|US7628855||Feb 9, 2007||Dec 8, 2009||Micron Technology, Inc.||Atomic layer deposition using electron bombardment|
|US7662729||Apr 28, 2005||Feb 16, 2010||Micron Technology, Inc.||Atomic layer deposition of a ruthenium layer to a lanthanide oxide dielectric layer|
|US7670646||Jan 5, 2007||Mar 2, 2010||Micron Technology, Inc.||Methods for atomic-layer deposition|
|US7687409||Mar 29, 2005||Mar 30, 2010||Micron Technology, Inc.||Atomic layer deposited titanium silicon oxide films|
|US7709402||Feb 16, 2006||May 4, 2010||Micron Technology, Inc.||Conductive layers for hafnium silicon oxynitride films|
|US7719065||Aug 29, 2005||May 18, 2010||Micron Technology, Inc.||Ruthenium layer for a dielectric layer containing a lanthanide oxide|
|US7745348 *||Sep 15, 2005||Jun 29, 2010||Dongbu Electronics Co., Ltd.||Manufacturing method of a semiconductor device|
|US7867919||Dec 8, 2006||Jan 11, 2011||Micron Technology, Inc.||Method of fabricating an apparatus having a lanthanum-metal oxide dielectric layer|
|US7915174||Jul 22, 2008||Mar 29, 2011||Micron Technology, Inc.||Dielectric stack containing lanthanum and hafnium|
|US7972977||Oct 5, 2007||Jul 5, 2011||Asm America, Inc.||ALD of metal silicate films|
|US8067794||May 3, 2010||Nov 29, 2011||Micron Technology, Inc.||Conductive layers for hafnium silicon oxynitride films|
|US8071476||Aug 31, 2005||Dec 6, 2011||Micron Technology, Inc.||Cobalt titanium oxide dielectric films|
|US8076249||Mar 24, 2010||Dec 13, 2011||Micron Technology, Inc.||Structures containing titanium silicon oxide|
|US8084370||Oct 19, 2009||Dec 27, 2011||Micron Technology, Inc.||Hafnium tantalum oxynitride dielectric|
|US8084808||May 20, 2008||Dec 27, 2011||Micron Technology, Inc.||Zirconium silicon oxide films|
|US8154066||Dec 1, 2006||Apr 10, 2012||Micron Technology, Inc.||Titanium aluminum oxide films|
|US8237216||Oct 29, 2010||Aug 7, 2012||Micron Technology, Inc.||Apparatus having a lanthanum-metal oxide semiconductor device|
|US8278225||Oct 12, 2009||Oct 2, 2012||Micron Technology, Inc.||Hafnium tantalum oxide dielectrics|
|US8399365||Dec 12, 2011||Mar 19, 2013||Micron Technology, Inc.||Methods of forming titanium silicon oxide|
|US8455959||Dec 5, 2011||Jun 4, 2013||Micron Technology, Inc.||Apparatus containing cobalt titanium oxide|
|US8466016||Dec 20, 2011||Jun 18, 2013||Micron Technolgy, Inc.||Hafnium tantalum oxynitride dielectric|
|US8501563||Sep 13, 2012||Aug 6, 2013||Micron Technology, Inc.||Devices with nanocrystals and methods of formation|
|US8524618||Sep 13, 2012||Sep 3, 2013||Micron Technology, Inc.||Hafnium tantalum oxide dielectrics|
|US8541276||Apr 9, 2012||Sep 24, 2013||Micron Technology, Inc.||Methods of forming an insulating metal oxide|
|US8557702||Jan 7, 2010||Oct 15, 2013||Asm America, Inc.||Plasma-enhanced atomic layers deposition of conductive material over dielectric layers|
|US8558325||May 17, 2010||Oct 15, 2013||Micron Technology, Inc.||Ruthenium for a dielectric containing a lanthanide|
|US8563444||Jul 1, 2011||Oct 22, 2013||Asm America, Inc.||ALD of metal silicate films|
|US8633110||Nov 14, 2011||Jan 21, 2014||Micron Technology, Inc.||Titanium nitride films|
|US8759170||Jun 11, 2013||Jun 24, 2014||Micron Technology, Inc.||Hafnium tantalum oxynitride dielectric|
|US8785312||Nov 28, 2011||Jul 22, 2014||Micron Technology, Inc.||Conductive layers for hafnium silicon oxynitride|
|US8786031||Feb 28, 2011||Jul 22, 2014||Canon Anelva Corporation||Metal nitride film, semiconductor device using the metal nitride film, and manufacturing method of semiconductor device|
|US8895442||Jun 3, 2013||Nov 25, 2014||Micron Technology, Inc.||Cobalt titanium oxide dielectric films|
|US8901674 *||Feb 25, 2013||Dec 2, 2014||International Business Machines Corporation||Scaling of metal gate with aluminum containing metal layer for threshold voltage shift|
|US8907486||Oct 11, 2013||Dec 9, 2014||Micron Technology, Inc.||Ruthenium for a dielectric containing a lanthanide|
|US8921914||Aug 5, 2013||Dec 30, 2014||Micron Technology, Inc.||Devices with nanocrystals and methods of formation|
|US8945675||May 29, 2008||Feb 3, 2015||Asm International N.V.||Methods for forming conductive titanium oxide thin films|
|US9029253 *||May 1, 2013||May 12, 2015||Asm Ip Holding B.V.||Phase-stabilized thin films, structures and devices including the thin films, and methods of forming same|
|US9096931||Dec 6, 2011||Aug 4, 2015||Asm America, Inc||Deposition valve assembly and method of heating the same|
|US9117866||Jul 31, 2012||Aug 25, 2015||Asm Ip Holding B.V.||Apparatus and method for calculating a wafer position in a processing chamber under process conditions|
|US9139906||Feb 27, 2008||Sep 22, 2015||Asm America, Inc.||Doping with ALD technology|
|US20040106261 *||May 5, 2003||Jun 3, 2004||Asm International N.V.||Method of forming an electrode with adjusted work function|
|US20040233010 *||May 22, 2003||Nov 25, 2004||Salman Akram||Atomic layer deposition (ALD) high permeability layered magnetic films to reduce noise in high speed interconnection|
|US20050023624 *||Aug 31, 2004||Feb 3, 2005||Micron Technology, Inc.||Atomic layer-deposited HfAlO3 films for gate dielectrics|
|US20050095852 *||Oct 29, 2003||May 5, 2005||International Business Machines||Field effect transistor with electroplated metal gate|
|US20050140462 *||Feb 22, 2005||Jun 30, 2005||Micron Technology, Inc.||High permeability layered magnetic films to reduce noise in high speed interconnection|
|US20050179097 *||Jan 20, 2005||Aug 18, 2005||Micron Technology, Inc.||Atomic layer deposition of CMOS gates with variable work functions|
|US20050284360 *||Jun 29, 2004||Dec 29, 2005||Micron Technology, Inc.||Atomic layer deposition using electron bombardment|
|US20060043492 *||Aug 29, 2005||Mar 2, 2006||Micron Technology, Inc.||Ruthenium gate for a lanthanide oxide dielectric layer|
|US20060043504 *||Aug 31, 2004||Mar 2, 2006||Micron Technology, Inc.||Atomic layer deposited titanium aluminum oxide films|
|US20060046522 *||Aug 31, 2004||Mar 2, 2006||Micron Technology, Inc.||Atomic layer deposited lanthanum aluminum oxide dielectric layer|
|US20060063395 *||Sep 15, 2005||Mar 23, 2006||Dongbuanam Semiconductor Inc.||Manufacturing method of a semiconductor device|
|US20060111147 *||May 20, 2005||May 25, 2006||Nextel Communications, Inc.||Sim card data transfer system and methods|
|US20060128168 *||Dec 13, 2004||Jun 15, 2006||Micron Technology, Inc.||Atomic layer deposited lanthanum hafnium oxide dielectrics|
|US20060131702 *||Jan 26, 2006||Jun 22, 2006||Micron Technology, Inc.||Novel transmission lines for CMOS integrated circuits|
|US20060214207 *||Mar 27, 2006||Sep 28, 2006||Toshihide Nabatame||Semiconductor device and manufacturing method thereof|
|US20060223337 *||Mar 29, 2005||Oct 5, 2006||Micron Technology, Inc.||Atomic layer deposited titanium silicon oxide films|
|US20070048926 *||Aug 31, 2005||Mar 1, 2007||Micron Technology, Inc.||Lanthanum aluminum oxynitride dielectric films|
|US20070049054 *||Aug 31, 2005||Mar 1, 2007||Micron Technology, Inc.||Cobalt titanium oxide dielectric films|
|US20070063296 *||Sep 22, 2005||Mar 22, 2007||Sematech, Inc.||Methods of modulating the work functions of film layers|
|US20070090440 *||Dec 1, 2006||Apr 26, 2007||Micron Technology, Inc.||Lanthanum aluminum oxynitride dielectric films|
|US20130175642 *||Feb 25, 2013||Jul 11, 2013||International Business Machines Corporation||Scaling of metal gate with aluminum containing metal layer for threshold voltage shift|
|US20130292676 *||May 1, 2013||Nov 7, 2013||Asm Ip Holding B.V.||Phase-stabilized thin films, structures and devices including the thin films, and methods of forming same|
|WO2011051015A2 *||Aug 27, 2010||May 5, 2011||International Business Machines Corporation||Aluminum containing metal layer for threshold voltage shift|
|U.S. Classification||257/407, 257/E29.16, 257/E21.635, 257/E21.204, 257/E21.171|
|International Classification||H01L29/423, H01L21/285, H01L29/49, H01L21/8238, H01L27/10, H01L21/28, H01L29/78, H01L27/092|
|Cooperative Classification||H01L29/4966, H01L21/823828, H01L21/28562, H01L21/28088|
|European Classification||H01L21/8238G, H01L21/285B4H2, H01L21/28E2B6, H01L29/49E|
|Aug 22, 2002||AS||Assignment|
Owner name: MICRON TECHNOLOGY, INC., IDAHO
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:FORBES, LEONARD;AHN, KIE Y.;REEL/FRAME:013226/0006;SIGNING DATES FROM 20020806 TO 20020810