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Publication numberUS20040072400 A1
Publication typeApplication
Application numberUS 10/270,348
Publication dateApr 15, 2004
Filing dateOct 15, 2002
Priority dateOct 15, 2002
Also published asUS6727160
Publication number10270348, 270348, US 2004/0072400 A1, US 2004/072400 A1, US 20040072400 A1, US 20040072400A1, US 2004072400 A1, US 2004072400A1, US-A1-20040072400, US-A1-2004072400, US2004/0072400A1, US2004/072400A1, US20040072400 A1, US20040072400A1, US2004072400 A1, US2004072400A1
InventorsChian-Kai Huang, Fung-Hsu Cheng, Jui-Ping Li
Original AssigneeChian-Kai Huang, Fung-Hsu Cheng, Jui-Ping Li
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Method of forming a shallow trench isolation structure
US 20040072400 A1
Abstract
A method of forming a STI structure. First, a substrate having a trench is provided. Next, a conformable silicon oxide layer is grown on the surface of the trench by wet oxidation using single wafer process to serve as a liner oxide layer. Thereafter, the substrate and the silicon oxide layer is in-situ annealed. Finally, an insulating layer is completely filled into the trench.
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Claims(18)
What is claimed is:
1. A method of forming a shallow trench isolation structure, comprising the steps of:
providing a substrate covered by a mask layer;
etching the mask layer to form a least one opening to expose the substrate;
etching the substrate under the opening to form a trench in the substrate;
growing a conformable silicon oxide layer on the surface of the trench at a predetermined temperature by wet oxidation using single wafer process to serve as a liner oxide layer;
in-situ annealing the substrate and the silicon oxide layer at the predetermined temperature;
forming an insulating layer over the mask layer and filling in the trench;
removing the insulating layer over the mask layer; and
removing the mask layer.
2. The method as claimed in claim 1, wherein the wet oxidation is performed using hydrogen and oxygen as reaction gases.
3. The method as claimed in claim 2, wherein the flow rates of the hydrogen and oxygen are about 10˜16 slm and 5˜8 slm, respectively.
4. The method as claimed in claim 1, wherein the silicon oxide layer has a thickness of about 150˜250 Å.
5. The method as claimed in claim 1, wherein the predetermined temperature is at about 1100˜1200° C.
6. The method as claimed in claim 1, wherein the annealing is performed in an atmosphere of nitrogen or nitrous oxide.
7. The method as claimed in claim 1, wherein the annealing is performed for 20˜60 sec.
8. The method as claimed in claim 1, wherein the insulating layer is high density plasma oxide.
9. The method as claimed in claim 1, wherein the insulating layer over the mask layer is removed by chemical mechanic polishing.
10. A method of forming a shallow trench isolation structure, comprising the steps of:
providing a substrate having a trench;
growing a conformable silicon oxide layer on the surface of the trench by wet oxidation using single wafer process to serve as a liner oxide layer;
in-situ annealing the substrate and the silicon oxide layer; and
filling an insulating layer into the trench.
11. The method as claimed in claim 10, wherein the wet oxidation is performed using hydrogen and oxygen as reaction gases.
12. The method as claimed in claim 11, wherein the flow rates of the hydrogen and oxygen are about 10˜16 slm and 5˜8 slm, respectively.
13. The method as claimed in claim 10, wherein the silicon oxide layer has a thickness of about 150˜250 Å.
14. The method as claimed in claim 10, wherein the silicon oxide layer is grown at about 1100˜1200° C.
15. The method as claimed in claim 10, wherein the annealing is performed in an atmosphere of nitrogen or nitrous oxide.
16. The method as claimed in claim 10, wherein the annealing is performed for 20˜60 sec.
17. The method as claimed in claim 10, wherein the annealing is performed at about 1100˜1200° C.
18. The method as claimed in claim 10, wherein the insulating layer is high density plasma oxide.
Description
BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates in general to a semiconductor technology. More particularly, it relates to a method of forming a shallow trench isolation (STI) structure.

[0003] 2. Description of the Related Art

[0004] An isolation region is formed in an integrated circuit for the purpose of separating neighboring device regions thereof and preventing carriers from penetrating the substrate to neighboring devices.

[0005] Among different element isolation techniques, LOCOS and shallow trench isolation manufacturing methods are the two most used methods. In particular, as the latter has a small isolation region and can keep the substrate level after the process is finished, it is the semiconductor manufacturing method obtaining the most attention.

[0006]FIG. 1 is a schematic cross-section showing a conventional shallow trench isolation structure. In FIG. 1, a pad oxide layer and a silicon nitride layer (not shown) are formed on a silicon substrate 10. The silicon nitride layer and the pad oxide layer are patterned by lithography and etching, and a trench is then formed in the substrate 10 by etching using the silicon nitride layer as a mask. A liner oxide layer 14 is formed by thermal oxidation on the surface of the trench. Chemical vapor deposition (CVD) oxide layer is deposited and filled into the trench. The excess oxide layer over the silicon nitride layer is removed by chemical mechanical polishing (CMP) to complete the shallow trench isolation structure 16. The silicon nitride layer and the pad oxide layer are then removed.

[0007] Because the property of the element isolation structure 16 is similar to that of the pad oxide layer and liner oxide layer 14, when etching liquid is used to remove pad oxide layer, the element isolation structure 16 is inevitably etched so that the liner oxide layer 14 at the top corner 20 of the trench develops a sharp edge, increasingly attracting the focus of the electric field, hence the the insulating properties of the top corner 20 degrades, resulting in abnormal element characteristics.

[0008] Moreover, the etching used for forming the trench in the substrate 10 and the thermally grown liner oxide layer 14 induce stresses into the substrate 10. For example, the stresses concentrate at the top corner 20 and bottom corner 22 of the trench, resulting in inducing leakage current. In addition, more operation time is required for growing liner oxide by thermal oxidation, thus reducing the throughput. Moreover, since typical semiconductor factories use batch furnaces for thermal oxidation, the thin film uniformity is varied, reducing the reliability of the devices.

SUMMARY OF THE INVENTION

[0009] Accordingly, an object of the invention is to provide a method of forming a shallow trench isolation structure, wherein a liner oxide layer is formed by wet oxidation using single wafer process at high temperatures to obtain a rounder liner oxide layer at the top corner of the trench and increase the uniformity of the liner oxide layers in each wafer to be fabricated.

[0010] Another object of the invention is to provide a method of forming a shallow trench isolation structure, wherein in-situ annealing is performed after the liner oxide growth to release stress and prevent dopant diffusion to the STI structure from the device region.

[0011] To achieve these and other advantages, the invention provides a method of forming a shallow trench isolation structure. First, a substrate having a trench is provided. Next, a conformable silicon oxide layer is grown on the surface of the trench by wet oxidation using single wafer process to serve as a liner oxide layer. Thereafter, the substrate and the silicon oxide layer is in-situ annealed. Finally, an insulating layer is completely filled into the trench.

[0012] The silicon oxide layer has a thickness of about 150˜250 Å and can be formed at about 1100˜1200° C. using hydrogen and oxygen as reaction gases. Moreover, the flow rates of the hydrogen and oxygen are about 10˜16 slm and 5˜8 slm, respectively.

[0013] Moreover, the annealing is performed in an atmosphere of nitrogen or nitrous oxide at about 1100˜1200° C. for 20˜60 sec. The insulating layer is high density plasma oxide.

BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The present invention can be more fully understood by reading the subsequent detailed description in conjunction with the examples and references made to the accompanying drawings, wherein:

[0015]FIG. 1 is a schematic cross-section showing a conventional shallow trench isolation structure; and

[0016]FIGS. 2a through 2 g are cross-sections showing a method of forming a shallow trench isolation structure according to the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0017] A preferred embodiment of the present invention is now described with reference to FIGS. 2a through 2 g.

[0018] First, in FIG. 2a, a semiconductor substrate, such as a silicon wafer 30, is provided. A mask layer 35 is formed on the substrate 30. The mask layer 35 preferably has a thickness of about 200˜3500 Å and can be a single layer or a plurality of layers. As shown in FIG. 1, the mask layer 35 is preferably composed of a pad oxide layer 32 and a thicker silicon nitride layer 34. In this invention, the pad oxide layer 32 has a thickness of about 100 Å and can be formed by thermal oxidation or conventional CVD, such as atmospheric pressure CVD (APCVD) and low pressure CVD (LPCVD). The silicon nitride layer 34 overlying the pad oxide layer 32 has a thickness of about 1000˜2000 Å and can be formed by LPCVD using SiCl2H2 and NH3 as reaction source. Next, a photoresist layer 36 is coated on the mask layer 35. Thereafter, lithography is performed on the photoresist layer 36 to form an opening 37 inside. The opening 37 defines shallow trench isolation region.

[0019] Subsequently, in FIG. 2b, the photoresist layer 36 having the opening 37 is used as a mask to anisotropically etch the mask layer 35, for example, reactive ion etching (RIE), to transfer the opening 37 pattern of the photoresist layer 36 to the mask layer 35 inside. Next, suitable wet etching or ashing is performed to remove the photoresist layer 36. Next, anisotropic etching is performed using the mask layer 35 as an etch mask, for example, the RIE, etching silicon substrate 30 under the opening in the mask layer 35 to a predetermined depth, such as about 3000˜6000 Å, to form a trench 38 in the silicon substrate 30.

[0020] Next, FIGS. 2c to 2 d show the critical steps of the invention. In FIG. 2c, a conformable silicon oxide layer 40 with a thickness of about 150˜250 Å grows on the surface of the trench 38 to serve as a liner oxide layer. In this invention, in order to obtain a rounder portion of the silicon oxide layer 40 at the top corner 38 a of the trench 38, the silicon oxide layer 40 is not formed by conventional thermal oxidation using a batch furnace, but is formed by wet oxidation using single wafer system. For example, this single wafer process can be performed using Thermal Process Common Centura (TPCC), a deposition apparatus fabricated by APPLIED MATERIAL, using hydrogen and oxygen as reaction gases. The flow rates of hydrogen and oxygen are 10˜16 slm and 5˜8 slm, respectively. Preferred flow rates of hydrogen and oxygen are 12 slm and 6 slm, respectively. The working pressure is about 7˜12 Torr, and preferred pressure is 9˜10 Torr. The growth time of the silicon oxide layer 40 is 60˜70 sec. In addition, TPCC has a higher growth temperature (1000˜1200° C.) than conventional thermal furnace (800˜900° C.), a higher temperature raising rate, and a higher growth rate to decrease the process time. Preferably, the growth temperature of the invention is 1150° C.

[0021] Next, in FIG. 2d, the substrate 30 and the silicon oxide layer 40 are in-situ annealed 41 in an atmosphere of nitrogen (N2) or nitrous oxide (N2O) for 20˜60 sec. In-situ here indicates that there is no breach in the chamber vacuum. In this invention, in-situ annealing 41 is performed at the growth temperature mentioned above. That is, the annealing temperature is at 1100˜1200° C. and the preferred annealing temperature is held at 1150° C. Here, there are three purposes for in-situ annealing 41 in an atmosphere of N2 or N2O after growing the liner oxide layer 40. The first is to repair the rough interface between the trench 38 surface and the liner oxide layer 40 through silicon atoms from the substrate 30 completely bonding with the oxygen atoms from the liner oxide layer 40 to enhance the insulating properties of the liner oxide layer 40. The second is to realize stresses formed at the top corner 38 a and bottom corner 38 b of the trench 38 during etching trench 38 and growing liner oxide layer 40 to prevent electric field concentration while devices are operating. The third is to diffuse nitrogen atoms into the silicon oxide layer 40 and bond with silicon atoms and oxygen atoms therein. The Si—O—N bonds can barrier the dopant in the device region (not shown), diffusing into the STI structure in subsequent process to increase the reliability of the devices. In addition, the annealing 41 may form a thin sealing layer 39, such as silicon oxynitride (SiON), over the liner oxide layer 40 to enhance the diffusion barrier effect.

[0022] Next, in FIG. 2e, an insulating layer 42 is formed over the mask layer 35 and completely fills the trench 38. For example, the insulating layer 42 can be doped or undoped silicon oxide. Some doped silicon oxides include phosphor-silicate glass (PSG), boro-silicate glass (BSG), phosphorus boron silicate glass (BPSG), and the like. Some undoped silicon oxides include thermal tetraethyl orthosilicate (TEOS) and high-density plasma (HDP) silicon oxides. In this invention, the preferred insulating layer 42 is HDP silicon oxide formed by HDPCVD.

[0023] Subsequently, annealing or rapid thermal process (RTP) is performed to densitize the insulating layer 42.

[0024] Next, in FIG. 2f, the excess insulating layer 42 over the mask layer 35 is removed to form shallow trench isolation (STI) structure 42 a. The method for removing the excess insulating layer 44 is, for example, CMP.

[0025] Finally, in FIG. 2g, the mask layer 35 is removed. The method of removing the silicon nitride layer 34, for example, is soaking with hot H3PO4, and the method of removing pad oxide layer 32, for example, is soaking with HF liquid. In addition, when removing pad oxide layer 32, part of STI structure 42 a will be removed at the same time to form recess 43 at the top corner 38 a of the STI structure 42 a. However, as mentioned above, since the portion of the liner oxide layer 40 at the top corner 38 a is rounder, the recess effect can be minimized to avoid leakage current induced.

[0026] Compared with the prior art, the liner oxide layer of the invention is formed by single wafer process. Accordingly, it can increase the uniformity of the liner oxide layers in each wafer to be fabricated. Moreover, according to the invention, the throughput can be increased due to the shorter process time required. In addition, the step of in-situ annealing of the invention can increase the quality of the line oxide to ensure the insulating properties of the STI structure.

[0027] The foregoing description has been presented for purposes of illustration and description. Obvious modifications or variations are possible in light of the above teaching. The embodiments were chosen and described to provide the best illustration of the principles of this invention and its practical application to thereby enable those skilled in the art to utilize the invention in various embodiments and with various modifications as are suited to the particular use contemplated. All such modifications and variations are within the scope of the present invention as determined by the appended claims when interpreted in accordance with the breadth to which they are fairly, legally, and equitably entitled.

Classifications
U.S. Classification438/221, 257/E21.546
International ClassificationH01L21/762
Cooperative ClassificationH01L21/76224
European ClassificationH01L21/762C
Legal Events
DateCodeEventDescription
Sep 20, 2011FPAYFee payment
Year of fee payment: 8
Sep 5, 2007FPAYFee payment
Year of fee payment: 4
Jan 27, 2005ASAssignment
Owner name: UNITED MICROELECTRONICS CORP., TAIWAN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:SILICON INTEGRATED SYSTEMS CORP.;REEL/FRAME:015621/0932
Effective date: 20050126
Owner name: UNITED MICROELECTRONICS CORP. NO. 3, LI-HSIN RD. I
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:SILICON INTEGRATED SYSTEMS CORP. /AR;REEL/FRAME:015621/0932
Oct 15, 2002ASAssignment
Owner name: SILICON INTEGRATED SYSTEMS CORP., TAIWAN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:HUANG, CHIAN-KAI;CHENG, FUNG-HSU;LI, JUI-PING;REEL/FRAME:013388/0274;SIGNING DATES FROM 20020918 TO 20020919