TECHNICAL FIELD OF THE INVENTION
The technical field of this invention is integrated circuit programming by selective activation of electrical fuses.
BACKGROUND OF THE INVENTION
Programmable devices have made a great impact on integrated circuit devices. The possibility of programming a device to do a specific task efficiently has made modest cost ‘special purpose processors’ a reality. Programmable devices are available from a wide variety manufacturers having mass production capability for the parent device. Programmation most often depends on a reliable methodology for ‘customizing’ a device in a repeatable, non-complex manner. ‘Fusing’ of the connections within the programmable logic is the most common process of programmation. Many fusible interconnect links are constructed of materials such as doped polysilicon.
These electrical fuses (eFuses) in VLSI silicon devices have been programmed conventionally by applying a large amount of power to the fuse body to melt and separate the fuse body material. This changes the fuse resistance from a low pre-blow resistance to a high post-blow resistance. This result can be sensed to determine the state of the eFuse: unblown or blown. As process technology has progressed to smaller and smaller geometry the maximum operating voltages have also scaled downward, making it more difficult to get massive power to the eFuses. Also, it is always desirable to minimize the amount of current the programming operation requires so that metallization power buses that deliver the current to the eFuses do not have to be large.
One of the common difficulties encountered in programming eFuses in sub-nanometer technologies for example, where there are significant voltage limitations, is that of providing enough power to reliably blow the fuse in a single programming pulse. It has been shown that multiple programming pulses may be employed to achieve the desired resistance.
The eFuse for a conventional programmable device application is normally configured as a linear array or two dimensional array containing sometimes hundreds of eFuses and supporting logic. Several definitions will be helpful in clarifying the descriptions of eFuse implementation to follow.
1. The ‘eFuse’ itself is a circuit element, which has a natural un-programmed state, but may be permanently programmed to the opposite state.
2. An ‘eFuse element’ is comprised of an eFuse along with its programming and sensing circuits.
3. An ‘eFuse cell’ is comprised of an eFuse element plus the local logic required to integrate it into an eFuse array.
4. An ‘eFuse array’ is a collection of one or more eFuse cells connected in series or arrays. An eFuse controller is comprised of the control logic designed to access the eFuse arrays.
5. An un-programmed eFuse is defined as having a pre-defined maximum ‘low’ resistance value.
6. A programmed eFuse is defined as having a pre-defined minimum ‘high’ resistance value.
The eFuse array is programmed by loading the desired ‘fused state’ and ‘non-fused state’ locations into a ‘programming database’ containing a record for the individual elements of the entire array. Then programming those values into each eFuse sequentially can commence.
Because several pulses may be required to successfully blow eFuses, a normal approach is to experiment with applying the eFuse programming data set to program the desired eFuses in a array multiple times to attempt to increase the yield. Due to the physical properties of the fuse body four possible results are observed, two desirable and two undesirable.
Desired Result Possibilities
1. The eFuse was not desired to be programmed and it stayed low resistance after completion of the programming process.
2. The eFuse blew to an acceptable high value of resistance after the pulses were applied.
Undesired Result Possibilities
3. The eFuse blew to an acceptably high resistance after some of the pulses, but degraded after the completion of all of the pulses, and the resistance had become lower than acceptable.
4. The eFuse never blew to an acceptably high resistance, and caused the programming process to incur yield loss.
Case 3 above represents a most significant problem area, which can be mitigated by a special programming algorithm, the focus of this invention. Putting a high enough electrical field across a blown eFuse can cause it to heat the body enough to allow the material to re-melt and grow back creating an unacceptably lower resistance. Good eFuses can in this manner become bad after successive programming pulses. The focus of this invention is a solution to the problem of fuses growing back into an un-fused condition.
FIG. 1 illustrates the conventional eFuse cell circuit configuration, which is comprised of an eFuse element 101 plus the local logic required to integrate it into an eFuse array. This logic includes a CData flip-flop 103 that is clocked by the Enable Clock 108 and stores cell data in the array and a PData flip-flop 102 that is clocked by the Data Clock 106 and latches program data being passed into the eFuse cell.
In the ‘program’ mode, incoming PData In 107 is latched into the PData flip-flop 102 and programmed into the eFuse element on the occurrence of one or more program pulses initiated at Program input 110. PData passes to the eFuse cell via path 115. In the ‘program’ mode also, PData Out is passed through multiplexers 104 and 105 and is latched into the CData flip-flop 102. VPP 109 is the input for the programming power source. Program data is passed serially to the next cell in the array at PData Out line 115.
In the ‘test’ mode, the CData flip-flop latches the data from the present cell and passes it to Cell Data Out 116. This data from the present cell is passed through multiplexer 104 and multiplexer 105 as directed by the Test input 111.
Initz input 112 acts to initialize all flip-flops in the cell array prior to the programming cycle. Margin input 114 allows adjustment to the reference input for a differential amplifier so that the desired ‘high’ resistance values for a program element may be modified.
FIG. 2 illustrates a simplified view of a conventional eFuse system having an eFuse controller 200, a number of series-connected eFuse cells represented at the input and output ends of the array by 201 and 210 Each cell 201 and 210 have the local logic of FIG. 1 for integrating the cells into an eFuse array. At the last stage of the array 210 PData Out 208 and CData Out 209 are passed back to the controller as required in the ‘program’ and ‘test’ modes.
SUMMARY OF THE INVENTION
This invention describes a means for preventing the opportunity for eFuses to become lower resistance due to successive programming pulses after being successfully blown by an earlier set of programming pulses. The solution is achieved through the use of an adaptive programming algorithm for blowing the eFuses. In the adaptive algorithm once a high enough resistance on a blown eFuse has been attained it will not receive additional programming pulses that could cause it to become lower resistance.