Search Images Maps Play YouTube News Gmail Drive More »
Sign in
Screen reader users: click this link for accessible mode. Accessible mode has the same essential features but works better with your reader.

Patents

  1. Advanced Patent Search
Publication numberUS20040110358 A1
Publication typeApplication
Application numberUS 10/622,351
Publication dateJun 10, 2004
Filing dateJul 18, 2003
Priority dateDec 9, 2002
Also published asUS6746936
Publication number10622351, 622351, US 2004/0110358 A1, US 2004/110358 A1, US 20040110358 A1, US 20040110358A1, US 2004110358 A1, US 2004110358A1, US-A1-20040110358, US-A1-2004110358, US2004/0110358A1, US2004/110358A1, US20040110358 A1, US20040110358A1, US2004110358 A1, US2004110358A1
InventorsJoon Lee
Original AssigneeLee Joon Hyeon
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Method for forming isolation film for semiconductor devices
US 20040110358 A1
Abstract
The present invention relates to a method for forming an isolation film for semiconductor devices. This method comprises the steps of: successively forming a first oxide film and a nitride film on a semiconductor substrate; patterning the nitride film and the first oxide film to expose a portion of the semiconductor substrate, which corresponds to an isolation region; implanting impurity ions into the exposed portion of the semiconductor substrate to form an impurity ion-implanted layer; forming a spacer at the sidewall of the patterned nitride film, and at the same time, etching the ion-implanted layer using the spacer as a mask; etching a portion of the semiconductor substrate exposed by the etching of the ion-implanted layer, using the spacer as a mask, thereby forming a trench; removing the spacer; annealing the trench so that the corner of the trench is rounded; forming a second oxide film along the inner wall of the trench; depositing a polarizing oxide film on the entire surface of the resulting substrate in such a manner as to gap fill the trench; subjecting the polarizing oxide film to chemical mechanical polishing (CMP) using the nitride film as a polishing stopper film, thereby polarizing the polarizing oxide film; and removing the nitride and first nitride films remaining after the polarizing step.
Images(7)
Previous page
Next page
Claims(17)
What is claimed is:
1. A method for forming an isolation film for semiconductor devices, which comprises the steps of:
successively forming a first oxide film and a nitride film on a semiconductor substrate;
patterning the nitride film and the first oxide film to expose a portion of the semiconductor substrate, which corresponds to an isolation region;
implanting impurity ions into the exposed portion of the semiconductor substrate to form an impurity ion-implanted layer;
forming a spacer at the sidewall of the patterned nitride film, and at the same time, etching the ion-implanted layer using the spacer as a mask;
etching a portion of the semiconductor substrate exposed by the etching of the ion-implanted layer, using the spacer as a mask, thereby forming a trench;
removing the spacer;
annealing the trench so that the corner of the trench is rounded;
forming a second oxide film along the inner wall of the trench;
depositing a polarizing oxide film on the entire surface of the resulting substrate in such a manner as to gap fill the trench;
subjecting the polarizing oxide film to chemical mechanical polishing (CMP) using the nitride film as a polishing stopper film, thereby polarizing the polarizing oxide film; and
removing the nitride and first nitride films remaining after the polarizing step.
2. The method of claim 1, wherein the step of patterning the nitride film and the first oxide film is carried out by dry-etching with an activated plasma consisting of a gas mixture of CHF3, CF4, Ar and O2.
3. The method of claim 1, wherein the step of patterning the nitride film and the first oxide film is carried out by dry-etching with an activated plasma consisting of a gas mixture of CHF3, CF4, Ar, O2 and CxFy.
4. The method of claim 1, wherein the impurity ions are phosphorus or boron ions.
5. The method of claim 1, wherein the spacer is made of polymer.
6. The method of claim 1, wherein the etching of the ion-implanted layer provides an ion-implanted residual layer, which is formed by a multi-step dry etching process using the spacer as a mask.
7. The method of claim 6, wherein the surface of the ion-implanted residual layer is rounded.
8. The method of claim 6, wherein the multi-step dry etching process is carried out using a gas containing fluorine of a given amount as a main component.
9. The method of claim 8, wherein the flow rate of fluorine is gradually increased as the multi-step dry etching process is progressed.
10. The method of claim 8, wherein the flow rate of fluorine is gradually reduced as the multi-step dry etching process is progressed.
11. The method of claim 1, wherein the step of etching the ion-implanted layer is carried out by dry etching with an activated plasma consisting of a gas mixture of CHF3, CF4, Ar and O2.
12. The method of claim 1, wherein the step of etching the ion-implanted layer is carried out by dry etching with an activated plasma consisting of a gas mixture of CHF3, CF4, Ar, CxFy, N2 and H2.
13. The method of claim 1, wherein the step of forming the trench is carried out by dry-etching the substrate with an activated plasma consisting of a gas mixture of HBr, Cl2, O2 and H2.
14. The method of claim 1, wherein the step of removing the spacer is carried out with a cleaning solution containing HF or H2SO4.
15. The method of claim 1, wherein the second oxide film is a sacrificial oxide film acting to compensate for the damage of the trench inner wall.
16. The method of claim 1, wherein the remaining nitride film is removed by phosphoric acid dipping.
17. The method of claim 1, wherein the isolation film is formed along the rounded corner of the trench.
Description
    BACKGROUND OF THE INVENTION
  • [0001]
    1. Field of the Invention
  • [0002]
    The present invention relates to a method for forming an isolation film for semiconductor devices, and more particularly, to a method for forming an isolation film for semiconductor devices, which prevents the formation of an edge moat.
  • [0003]
    2. Description of the Prior Art
  • [0004]
    With the advancement of semiconductor technology, the high speed and high integration level of semiconductor devices are rapidly increased, and at the same time, requirements for a fine pattern are gradually increased. These requirements are also applied to an isolation region, which occupies a relatively large area in a semiconductor substrate.
  • [0005]
    Currently, as an isolation film providing the isolation between semiconductor devices, there is generally used a LOCOS oxide film. This LOCOS isolation film is formed by local oxidation of silicon (LOCOS).
  • [0006]
    However, the LOCOS isolation film is disadvantageous in hat a bird's beak is formed at the edge of the isolation film such that the area of the isolation film is increased and leakage current is induced.
  • [0007]
    Thus, in an attempt to solve the problem occurring in the LOCOS isolation film, there was proposed a method wherein an isolation film having reduced width and excellent isolation characteristics is formed using shallow trench isolation (STI).
  • [0008]
    [0008]FIG. 1 is a cross-sectional view illustrating a method for forming an isolation film for semiconductor devices according to a general STI technology. As shown in FIG. 1, a pad oxide film and a pad nitride film are formed on a semiconductor substrate and patterned to expose a portion of the substrate, which corresponds to a field region. Then, the exposed portion of the substrate is etched to a given depth to form a trench 17. Next, the resulting substrate is subjected to sacrificial sidewall oxidation and liner oxidation, after which a high-density plasma oxide film as a field oxide film is formed on the substrate in such a manner as to fill the trench. Thereafter, the resulting substrate is subjected to chemical mechanical polishing (CMP) to complete the formation of a field oxide film 20 filling the trench, and then the pad nitride film is removed.
  • [0009]
    Then, the surface of the substrate is cleaned with a cleaning solution containing HF, HF/H2O, buffer oxide etchant (BOE) or the like, before deposition of a gate oxide film.
  • [0010]
    In other words, since the deposition of the gate oxide film is very critical to the characteristics of semiconductor transistors, the remaining foreign substances are removed with HF or a mixture of HF and other substances, before deposition of the gate oxide film.
  • [0011]
    However, during this cleaning process, an edge moat can be formed. If this edge moat occurs, sub-threshold current (Hump) and inverse narrow width effect (INWE) will occur to cause the abnormal operation of semiconductor devices.
  • SUMMARY OF THE INVENTION
  • [0012]
    Accordingly, the present invention has been made to solve the above-mentioned problems occurring in the prior art, and an object of the present invention is to provide a method for forming an isolation film for semiconductor devices, which can maximize the corner rounding of a trench and improve device characteristics, such as Hump and INWE.
  • [0013]
    To achieve the above object, the present invention provides a method for forming an isolation film for semiconductor devices, which comprises the steps of: successively forming a first oxide film and a nitride film on a semiconductor substrate; patterning the nitride film and the first oxide film to expose a portion of the semiconductor substrate, which corresponds to an isolation region; implanting impurity ions into the exposed portion of the semiconductor substrate to form an impurity ion-implanted layer; forming a spacer at the sidewall of the patterned nitride film, and at the same time, etching the ion-implanted layer using the spacer as a mask; etching a portion of the semiconductor substrate exposed by the etching of the ion-implanted layer, using the spacer as a mask, thereby forming a trench; removing the spacer; annealing the trench; forming a second oxide film at the inner wall of the trench; depositing a polarizing oxide film on the entire surface of the resulting substrate in such a manner as to gap fill the trench; subjecting the polarizing oxide film to chemical mechanical polishing (CMP) using the nitride film as a polishing stopper film, thereby polarizing the polarizing oxide film; and removing the nitride and first nitride films remaining after the polarizing step.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • [0014]
    The above and other objects, features and advantages of the present invention will be more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which:
  • [0015]
    [0015]FIG. 1 is a cross-sectional view illustrating a method for forming an isolation film for semiconductor devices according to prior art; and
  • [0016]
    [0016]FIGS. 2A to 2J are cross-sectional views illustrating a method for forming an isolation film for semiconductor devices according to the present invention.
  • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • [0017]
    Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings.
  • [0018]
    As shown in FIG. 2A, a pad oxide film 120, a pad nitride film 140 and a photoresist film are formed on a semiconductor substrate 100, after which the photoresist film is patterned to form a photoresist pattern 150 defining an isolation region.
  • [0019]
    Then, as shown in FIG. 2B, the nitride film 140 and the pad oxide film 120 are dry-etched to expose a portion of the semiconductor substrate 100, which corresponds to the isolation region. In this case, the nitride film 140 and the pad oxide film 120 are dry-etched with an activated plasma of a gas mixture consisting of CHF3, CF4, Ar and O2. Alternatively, the nitride film 140 and the pad oxide film 120 may also be dry-etched with an activated plasma consisting of a gas mixture of CHF3, CF4, Ar, O2 and CxFy
  • [0020]
    Next, as shown in FIG. 2C, impurity ions are implanted into the exposed portion of the semiconductor substrate 100 to form an impurity ion-implanted layer 180. In this case, pentavalent phosphorus (P) or trivalent boron (B) is preferably used as the impurity ions.
  • [0021]
    By this implantation of phosphorus (P) or boron (B) ions, the semiconductor substrate 100 has Si—P bonds or Si—B bonds such that the oxidation rate of the substrate in the subsequent oxidation process is more increased. Generally, in an oxidation process, a silicon substrate containing impurity is easily oxidized as compared to a silicon substrate containing no impurity.
  • [0022]
    Impurity ions, which can be used to accelerate the oxidation of the semiconductor substrate 100, are not limited only to pentavalent phosphorus or trivalent boron.
  • [0023]
    Next, as shown in FIG. 2D, a spacer 200 is formed on a sidewall of the nitride film 140, and at the same time, the ion-implanted layer 180 is dry-etched using the spacer 200 as a mask, thereby forming an ion-implanted residual layer 180 a. In this case, the spacer 200 is made of polymer, and the ion-implanted layer 180 is dry-etched with an activated plasma consisting of a gas mixture of CHF3, CF4, Ar and CxFy. Alternatively, the ion-implanted layer 180 may also be dry-etched with an activated plasma consisting of a gas mixture of CHF3, CF4, Ar, CxFy, N2 and H2.
  • [0024]
    As a result of the dry-etching of the ion-implanted layer 180, the ion-implanted residual layer 180 a remains below the spacer 200. By the formation of the ion-implanted residual layer 180 a, in the subsequent vacuum-hydrogen annealing process, silicon in the ion-implanted residual layer 180 a flows at a larger amount than silicon in a portion of the substrate, which was not implanted with impurity ions. This makes a corner of the trench round. This corner rounding becomes an important factor of preventing an edge moat. Hereinafter, the process of dry-etching the ion-implanted layer 180, including forming the spacer 200, is referred to as top corner rounding (TCP) dry etching process.
  • [0025]
    Although the ion-implanted residual layer 180 a may be formed by a single-step TCR dry etching process using the spacer 200 as a mask, this layer 180 a is preferably formed by a multi-step TCR dry etching process using a gas containing a given amount of fluorine as a main component. This is because the multi-step TCR dry etching process is more effective in making the trench corner round in the subsequent annealing process.
  • [0026]
    Hereinafter, the multi-step TCR dry etching process will be described in more detail.
  • [0027]
    First, polymer is deposited on the sidewall of the nitride film 140 to form a first spacer, and at the same time, a first TCR dry etching step of etching the ion-implanted layer 180 using the first spacer as a mask is carried out. This first TCR dry etching step is carried out using a given flow rate of fluorine (F).
  • [0028]
    Then, polymer is deposited on the sidewall of the spacer to form a second spacer, and at the same time, a second TCR dry etching step of the ion-implanted layer 180 is carried out. This second TCR dry etching step is carried out using fluorine (F) having an increased flow rate as compared to the first TCR dry etching process.
  • [0029]
    When the multi-step TCR dry etching process is carried out at gradually increasing flow rates of fluorine as described above, a portion of the semiconductor substrate, which was not masked, is etched to a given thickness together with the ion-implanted layer 180 in a final TCR dry etching step. Thus, the ion-implanted residual layer 180 a remaining after dry-etching the ion-implanted layer 180 is slightly rounded.
  • [0030]
    As described above, in order to increase an efficiency of rounding the trench corner, there can be used a method wherein the flow rate of fluorine is gradually increased as the multi-step TCR dry etching process is progressed. On the contrary, there may also be used a method wherein the flow rate of fluorine is gradually reduced as the multi-step TCR dry etching process is progressed. The latter method attributes to a facet phenomenon.
  • [0031]
    Although not shown in the drawings, it is understood that, as the multi-step TCR dry etching process is progressed, the thickness of the spacer is gradually increased and the etch rate of the ion-implanted layer 180 at the trench corner is finely controlled, so that an effect of rounding the trench corner is increased.
  • [0032]
    Thereafter, as shown in FIG. 2E, the semiconductor substrate 100 is etched to a given depth to form a trench 220. The trench 220 is formed by dry-etching the substrate 100 with an activated plasma consisting of a gas mixture of HBr, Cl2, O2 and H2.
  • [0033]
    In forming the trench 220, the spacer 200 acts as an etch barrier. Thus, a portion of the ion-implanted layer 180 below the spacer 200, i.e., the ion-implanted residual layer 180 a, is not etched, and the surface portion A of the ion-implanted residual layer 180 a and the lower corner B of the trench 220 are rounded.
  • [0034]
    Then, a cleaning process of removing the spacer 200 is carried out. In this cleaning process, a solution containing HF or H2SO4 is used as a cleaning solution.
  • [0035]
    Thereafter, as shown in FIG. 2F, the entire upper surface of the resulting substrate is subjected to a vacuum-hydrogen annealing process at high temperature.
  • [0036]
    By this vacuum-hydrogen annealing process, silicon (Si) reacts with hydrogen (H), so that the bonding force between silicon atoms is reduced and unstable hydrogen (H)-silicon (Si) bonds are formed. Thus, the substrate has unstable energy conditions where the bonding between hydrogen and silicon is easily cleaved.
  • [0037]
    By a tendency to convert from unstable energy conditions into stable energy conditions, the flow phenomenon of the upper corner A and the lower corner B of the trench 220 occurs so that the upper corner A and the lower corner B are rounded. Such unstable energy conditions mainly occur at the upper corner A and lower corner B.
  • [0038]
    Furthermore, the upper corner A having Si—B or Si—P bonds, which corresponds to the surface of the ion-implanted residual layer 180 a, is more unstable than a region having Si—Si bonds. Thus, when the vacuum-hydrogen annealing process is carried out, the upper corner A has more unstable energy conditions so that the flow phenomenon more rapidly occurs and the upper corner A of the trench 240 is more effectively rounded. This becomes a critical factor to prevent the formation of an edge moat in the subsequent process.
  • [0039]
    Next, as shown in FIG. 2G, the upper portion of the resulting substrate is subjected to a sacrificial oxidation process to form a sacrificial oxide film 240 within the trench 220. This sacrificial oxide film 240 acts to compensate for the damage of the trench inner wall damaged by the etching process and the vacuum-hydrogen annealing process.
  • [0040]
    Then, as shown in FIG. 2H, a polarizing oxide film 260 is deposited on the upper portion of the resulting substrate in such a manner that the trench 220 is filled with the polarizing oxide film 260.
  • [0041]
    Thereafter, as shown in FIG. 2I, the nitride film 140 and the polarizing oxide film 260 are polarized by a CMP process using the nitride film as a polishing stopper film. Thus, an isolation film 260 a and a nitride film 140 a are formed.
  • [0042]
    After this, as shown in FIG. 2J, the remaining pad oxide 120 and the remaining nitride film 140 a are removed by phosphoric acid dipping, so that an isolation film 260 a is formed within the trench along the rounded portion A of the trench corner.
  • [0043]
    Then, in order to remove foreign substances remaining on the surface of the silicon substrate, the silicon substrate is subjected to a HF cleaning process before deposition of a gate oxide film. In this cleaning process, even if the loss of the isolation film 260 a occurs, a final isolation film 260 b having no edge moat region can be obtained.
  • [0044]
    As described above, according to the present invention, the corner of the trench is rounded and the isolation film is formed along the rounded corner. Thus, the formation of an edge moat caused by the cleaning process is prevented to improve device characteristics, such as Hump, INWE and the like, thereby securing the reliability of devices.
  • [0045]
    Although a preferred embodiment of the present invention has been described for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims.
Patent Citations
Cited PatentFiling datePublication dateApplicantTitle
US5801083 *Oct 20, 1997Sep 1, 1998Chartered Semiconductor Manufacturing, Ltd.Use of polymer spacers for the fabrication of shallow trench isolation regions with rounded top corners
US5904538 *Sep 4, 1997May 18, 1999Lg Semicon Co., LtdMethod for developing shallow trench isolation in a semiconductor memory device
US6001707 *Feb 1, 1999Dec 14, 1999United Semiconductor Corp.Method for forming shallow trench isolation structure
US6099647 *Sep 30, 1999Aug 8, 2000Applied Materials, Inc.Methods and apparatus for forming ultra-shallow doped regions using doped silicon oxide films
US6165870 *Jun 29, 1999Dec 26, 2000Hyundai Electronics Industries Co., Ltd.Element isolation method for semiconductor devices including etching implanted region under said spacer to form a stepped trench structure
US6228727 *Sep 27, 1999May 8, 2001Chartered Semiconductor Manufacturing, Ltd.Method to form shallow trench isolations with rounded corners and reduced trench oxide recess
US6265282 *Aug 17, 1998Jul 24, 2001Micron Technology, Inc.Process for making an isolation structure
US6274500 *Oct 12, 1999Aug 14, 2001Chartered Semiconductor Manufacturing Ltd.Single wafer in-situ dry clean and seasoning for plasma etching process
US6414364 *Jul 24, 2001Jul 2, 2002Micron Technology, Inc.Isolation structure and process therefor
US6437417 *Aug 16, 2000Aug 20, 2002Micron Technology, Inc.Method for making shallow trenches for isolation
US6495424 *Oct 18, 2001Dec 17, 2002Mitsubishi Denki Kabushiki KaishaSemiconductor device
US6562696 *Mar 6, 2002May 13, 2003Taiwan Semiconductor Manufacturing Co., LtdMethod for forming an STI feature to avoid acidic etching of trench sidewalls
US6569750 *Jan 2, 2001May 27, 2003Hyundai Electronics Industries Co., Ltd.Method for forming device isolation film for semiconductor device
US20030045079 *Jul 24, 2002Mar 6, 2003Chang Hun HanMethod for manufacturing mask ROM
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US6921705 *Dec 22, 2003Jul 26, 2005Hynix Semiconductor Inc.Method for forming isolation layer of semiconductor device
US7537994Aug 28, 2006May 26, 2009Micron Technology, Inc.Methods of forming semiconductor devices, assemblies and constructions
US7928005 *Sep 27, 2005Apr 19, 2011Advanced Micro Devices, Inc.Method for forming narrow structures in a semiconductor device
US7935602Jun 28, 2005May 3, 2011Micron Technology, Inc.Semiconductor processing methods
US7939403Nov 17, 2006May 10, 2011Micron Technology, Inc.Methods of forming a field effect transistors, pluralities of field effect transistors, and DRAM circuitry comprising a plurality of individual memory cells
US7981806 *Nov 30, 2007Jul 19, 2011Hynix Semiconductor Inc.Method for forming trench and method for fabricating semiconductor device using the same
US8044479Apr 15, 2009Oct 25, 2011Micron Technology, Inc.Transistors, semiconductor devices, assemblies and constructions
US8222102Mar 23, 2011Jul 17, 2012Micron Technology, Inc.Methods of forming field effect transistors, pluralities of field effect transistors, and DRAM circuitry comprising a plurality of individual memory cells
US8409946Jun 20, 2012Apr 2, 2013Micron Technology, Inc.Methods of forming field effect transistors, pluralities of field effect transistors, and DRAM circuitry comprising a plurality of individual memory cells
US8742483Jun 6, 2012Jun 3, 2014Micron Technology, Inc.DRAM arrays
US8791506Sep 2, 2011Jul 29, 2014Micron Technology, Inc.Semiconductor devices, assemblies and constructions
US8853089 *Jul 5, 2012Oct 7, 2014Denso CorporationManufacturing method of semiconductor substrate
US8901720Mar 9, 2011Dec 2, 2014Advanced Micro Devices, Inc.Method for forming narrow structures in a semiconductor device
US8921909Apr 16, 2014Dec 30, 2014Micron Technology, Inc.Semiconductor constructions, DRAM arrays, and methods of forming semiconductor constructions
US9142445 *Nov 15, 2013Sep 22, 2015Marvell World Trade Ltd.Method and apparatus for forming shallow trench isolation structures having rounded corners
US9263455Jul 23, 2013Feb 16, 2016Micron Technology, Inc.Methods of forming an array of conductive lines and methods of forming an array of recessed access gate lines
US20050009292 *Dec 22, 2003Jan 13, 2005Myung Gyu ChoiMethod for forming isolation layer of semiconductor device
US20060240636 *Feb 21, 2006Oct 26, 2006Ryu Hyuk-JuTrench isolation methods of semiconductor device
US20060292787 *Jun 28, 2005Dec 28, 2006Hongmei WangSemiconductor processing methods, and semiconductor constructions
US20070072437 *Sep 27, 2005Mar 29, 2007Michael BrennanMethod for forming narrow structures in a semiconductor device
US20070117347 *Jan 17, 2007May 24, 2007Hongmei WangSemiconductor constructions
US20080032483 *Oct 5, 2007Feb 7, 2008Samsung Electronics Co., Ltd.Trench isolation methods of semiconductor device
US20080048298 *Aug 28, 2006Feb 28, 2008Micron Technology, Inc.Semiconductor devices, assemblies and constructions, and methods of forming semiconductor devices, assemblies and constructions
US20080119020 *Nov 17, 2006May 22, 2008Micron Technology, Inc.Methods of forming a field effect transistors, pluralities of field effect transistors, and DRAM circuitry comprising a plurality of individual memory cells
US20080211037 *Dec 21, 2007Sep 4, 2008Hynix Semiconductor Inc.Semiconductor Device and Method of Forming Isolation Layer Thereof
US20080233758 *Nov 30, 2007Sep 25, 2008Hynix Semiconductor Inc.Method for forming trench and method for fabricating semiconductor device using the same
US20090200614 *Apr 15, 2009Aug 13, 2009Micron Technology, Inc.Transistors, Semiconductor Devices, Assemblies And Constructions
US20110156130 *Mar 9, 2011Jun 30, 2011Advanced Micro Devices, Inc.Method for forming narrow structures in a semiconductor device
US20110169086 *Mar 23, 2011Jul 14, 2011Micron Technology, Inc.Methods of Forming Field Effect Transistors, Pluralities of Field Effect Transistors, and DRAM Circuitry Comprising a Plurality of Individual Memory Cells
US20130012004 *Jul 5, 2012Jan 10, 2013Denso CorporationManufacturing method of semiconductor substrate
US20140080285 *Nov 15, 2013Mar 20, 2014Marvell World Trade Ltd.Method and apparatus for forming shallow trench isolation structures having rounded corners
WO2007001722A1 *May 24, 2006Jan 4, 2007Micron Technology, Inc.Semiconductor processing methods, and semiconductor constructions
Classifications
U.S. Classification438/437, 257/E21.549
International ClassificationH01L21/762, H01L21/76
Cooperative ClassificationH01L21/76232
European ClassificationH01L21/762C6
Legal Events
DateCodeEventDescription
Jul 18, 2003ASAssignment
Owner name: HYNIX SEMICONDUCTOR INC., KOREA, REPUBLIC OF
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:LEE, JOON HYEON;REEL/FRAME:014316/0189
Effective date: 20030702
Jan 10, 2005ASAssignment
Owner name: MAGNACHIP SEMICONDUCTOR, LTD., KOREA, REPUBLIC OF
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:HYNIX SEMICONDUCTOR, INC.;REEL/FRAME:016216/0649
Effective date: 20041004
Sep 21, 2007FPAYFee payment
Year of fee payment: 4
Feb 18, 2009ASAssignment
Owner name: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL TRUS
Free format text: AFTER-ACQUIRED INTELLECTUAL PROPERTY KUN-PLEDGE AGREEMENT;ASSIGNOR:MAGNACHIP SEMICONDUCTOR, LTD.;REEL/FRAME:022277/0133
Effective date: 20090217
Jun 22, 2010ASAssignment
Owner name: MAGNACHIP SEMICONDUCTOR LTD.,KOREA, DEMOCRATIC PEO
Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:U.S. BANK NATIONAL ASSOCIATION;REEL/FRAME:024563/0807
Effective date: 20100527
Oct 11, 2011FPAYFee payment
Year of fee payment: 8
Nov 25, 2014ASAssignment
Owner name: MAGNACHIP SEMICONDUCTOR LTD., KOREA, REPUBLIC OF
Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE RECEIVING PARTY ADDRESS PREVIOUSLY RECORDED AT REEL: 024563 FRAME: 0807. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE BY SECURED PARTY;ASSIGNOR:US BANK NATIONAL ASSOCIATION;REEL/FRAME:034469/0001
Effective date: 20100527
Dec 7, 2015FPAYFee payment
Year of fee payment: 12