US 20040130466 A1 Abstract A scrambler includes a linear shift register having logic suitable for generating a scrambling sequence according to a predetermined generator sequence, a plurality of logic gates that allow for parallel input to the shift register, and a multiplexer for switching inputs of the shift register. The multiplexer switches inputs so that the shift register can be loaded with a predetermined initial value, and shifted a single bit or shifted a predetermined number of bits though the generator sequence.
Claims(17) 1. A scrambler for generating a scrambling sequence, the scrambler comprising:
an X-tap linear feedback shift register having X registers arranged in a linear series for outputting the scrambling sequence according to a predetermined generator sequence; a multiplexer having outputs connected to the registers of the X-tap linear feedback shift register, the multiplexer further having a first set of inputs, a second set of inputs, and a third set of inputs, the third set of inputs being connected to outputs of registers of the X-tap linear feedback shift register for performing a single step shift operation of the X-tap linear feedback register; and a plurality of logic gates connected to the second set of inputs of the multiplexer and to outputs of the registers for performing an n-step shift operation of the X-tap linear feedback register; wherein the sets of inputs correspond to states of selection ends of the multiplexer; and the selection ends of the multiplexer are capable of being set to select the first set of inputs to load the registers of the X-tap linear feedback shift register with a predetermined state, select the second set of inputs to perform the n-step shift operation of the X-tap linear feedback shift register, and select the third set of inputs to perform the single shift operation of the X-tap linear feedback shift register. 2. The scrambler of 3. The scrambler of 4. The scrambler of ^{17}+D^{14}+1. 5. The scrambler of 6. The scrambler of 7. A scrambler for generating a scrambling sequence, the scrambler comprising:
a series of registers, each register having an input and an output; a series of multiplexing means, each multiplexing means for selecting one of a first input, a second input and a third input, and to provide the selected input to a corresponding register; wherein each first input is connected to an initial value input to perform an initial value loading operation, and each third input is fed from the output of a previous register to perform a single step shift operation; a series of paralleling XOR means for performing an n-step shift operation, each paralleling XOR means having an output connected to the second input of a corresponding multiplexing means; and a tap XOR means with output connected to the third input of the multiplexing means corresponding to a first register for performing the single step shift operation; wherein inputs to the series of paralleling XOR means and the tap XOR means are outputs of the series of registers arranged such that the series of registers form a series-parallel linear feedback shift register; and the series of multiplexing means is capable of being set so that the series-parallel linear feedback shift register is capable of performing the single step shift operation, performing the n-step shift operation, or performing the initial value loading operation. 8. The scrambler of 9. The scrambler of ^{17}+D^{14}+1. 10. The scrambler of 11. The scrambler of 12. The scrambler of 13. A method for generating a scrambling sequence, the method comprising:
providing a series-parallel linear feedback shift register capable of performing a single step shift operation, performing an n-step shift operation, and being loaded with initial values; loading the series-parallel linear feedback shift register with initial values; performing a predetermined number of n-step shift operations with the series-parallel linear feedback shift register; and performing a predetermined number of single step shift operations with the series-parallel linear feedback shift register. 14. The method of 15. The method of 16. The method of ^{17}+D^{14}+1, the n-step shift operations are 24-bit shift operations, and the predetermined number of n-step shift operations is between 3 and 324. 17. A device for performing the method of Description [0001] 1. Field of the Invention [0002] The present invention relates to an electronic device, and more specifically to an electronic scrambler/de-scrambler and related method for generating a scrambling sequence. [0003] 2. Description of the Prior Art [0004] Modern communications systems have developed rapidly and become a fixture of the information age. Mobile (or cellular) phones are a prime example of how new technology can change people's lives. Mobile phones offer an inexpensive and convenient way to stay in touch with family, friends, and colleagues. The popularity of mobile phones has led to widespread use, which has created a demand for new functionality and associated advances in technology. [0005] Recently, industry and standardization groups have developed the code division multiple access specification (cdma2000) for third generation (3G) wireless communication systems. The cdma2000system offers expanded functionality to mobile phones such as capabilities for sending pictures, Internet access, and expanded voice functionality. [0006] A key element in most communications devices, including 3G mobile phones, is a scrambler/de-scrambler. A scrambler encodes data so that it can be safely transmitted. From the base station transmitter path, the channel interleaved symbols are scrambled before being fed into a subpacket symbol selection device. A source unit uses a scrambler to scramble data, and then transmits the scrambled data to a destination unit that uses a similar scrambler to descramble the data. The de-scrambler needs to generate the same scrambling sequence as the scrambler. The subpacket symbol selection selects a scrambled sequence start from an Fk value, wherein k is the subpacket index and the Fk value ranges from 72 to 7776 in steps of 24 (i.e. 72, 96 . . . 7752, 7776). According to cdma2000, the Fk value depends on a host of parameters including: an index of a subpacket being scrambled, a number of bits in an encoder packet (a plurality of subpackets), a number of 32-bit Walsh channels indexed by subpacket, a number of 1.25 ms slots for a subpacket, and a modulation order of each subpacket. All of these parameters and how they correlate are well known to those working in the cdma2000 field and are prescribed by the relevant cdma2000 specifications. If an unintended destination unit receives the scrambled data, it is likely that the unintended destination cannot readily descramble or understand the data. Encrypting data using a scrambler serves to protect privacy and commercial interests of data transmissions. [0007] Consider a typical 17-tap linear feedback shift register [0008] For the F-PDCH of cdma2000 the operation of the scrambler [0009] When the de-scrambler is being clocked by the Fk value it is in a non-performing mode. Naturally, slower overall performance caused by this is more pronounced with higher Fk values. Slower performance of the de-scrambler affects the entire surrounding system and can introduce bottlenecks into otherwise streamlined systems. As it is desirable to avoid delay and increase data transfer rates in mobile phones and other communications systems, the scrambler as described above lacks efficiency. Prior art solutions to this problem include increasing the clock speed of the scrambler, which tends to introduce errors into a transmission. [0010] It is therefore a primary objective of the claimed invention to provide a scrambler and related method that can quickly step though a sequence of unnecessary intermediate states to solve the problems of the prior art. [0011] Briefly summarized, the claimed invention includes an X-tap linear feedback shift register having X registers, a multiplexer having outputs connected to the registers; of the X-tap linear feedback shift register, and a plurality of logic gates connected to inputs of the multiplexers defining a generator sequence. Through the multiplexer, the plurality of logic gates provide parallel input to the X-tap linear feedback shift register that allows for an n-step shift operation of the X-tap linear feedback shift register. Also through the multiplexer, the X-tap linear feedback shift register can perform a single shift operation and can be loaded with a predetermined state. [0012] According to the claimed invention, a method provides a series-parallel linear feedback shift register capable of performing a single step shift operation, performing an n-step shift operation, and being loaded with initial values. The method further loads the series-parallel linear feedback shift register with initial values, performs a predetermined number of n-step shift operations with the series-parallel linear feedback shift register, and performs a predetermined number of single step shift operations with the series-parallel linear feedback shift register. The method finally outputs contents of the series-parallel linear feedback shift register as the scrambling sequence while performing at least a portion of the predetermined number of the single step shift operations. [0013] It is an advantage of the claimed invention that the multiplexer offers the X-tap linear feedback shift register three-mode functionality so that the shift register can be initialized, shifted by n-steps, and the shifted by a single step. [0014] It is a further advantage of the claimed invention that a desired point in the generator sequence can be reached more quickly in proportion to the size of the n-step shift operation. [0015] These and other objectives of the claimed invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. [0016]FIG. 1 is a block diagram of a 17-tap linear feedback shift register used as a scrambler according to the prior art. [0017]FIG. 2 is a block diagram of a scrambler according to a first embodiment of the present invention. [0018]FIG. 3 is a block diagram of a scrambler according to a second embodiment of the present invention. [0019]FIG. 4 is a flowchart of a method for generating a scrambling sequence according to the present invention. [0020] Although the present invention will be described in the context a scrambler used in the forward packet data channel (F-PDCH) of cdma2000, this is not limiting. For example, the present invention applies equally to a de-scrambler, which is a similar device differing mainly by direction of application. Furthermore, the present invention can be applied to other communications systems where data scrambling is required such as computer networks, and further to data encryption in general. [0021] Please refer to FIG. 2 illustrating a block diagram of a scrambler [0022] The scrambler [0023] The structures of the logic [0024] wherein each row defines an on-state (binary “1”) of a corresponding one of the registers D [0025] Continuing the example, the logic [0026] Thus, the logic [0027] Generally, the shift register [0028] Please refer to FIG. 3 showing a block diagram of a scrambler
[0029] The scrambler [0030] An example will now be described to clarify the second embodiment. If a subpacket symbol selection device selects a scrambling sequence to start from an Fk value of 120, the “load” signal is initially set to “1”, which allows the multiplexers [0031] In both embodiments the logic [0032] Please refer to FIG. 4 showing a flowchart of a method for generating a scrambling sequence according to the present invention. The method is described in conjunction with the scrambler [0033] Step [0034] Step [0035] Select input “1” of the multiplexers [0036] Step [0037] Set the counter [0038] Step [0039] Step [0040] Step [0041] Is the state of the counter [0042] Step [0043] Set the multiplexers [0044] Step [0045] Perform a single bit shift by clocking the registers D [0046] Step [0047] Is the end of the scrambling sequence reached? If it is, go to step [0048] Step [0049] The end of the scrambling sequence is determined by a component or user external to the scrambler [0050] In contrast to the prior art, the present invention can load registers with initial values, generate a series of n-step jumps of a generator sequence, and generate a single step output of the generator sequence as a scrambling sequence. Where the prior art scrambler must be advanced linearly in single steps to reach a desired state, the present invention scrambler can be quickly advanced though parallel input. Considering the above-mentioned cmda2000 example. If the prior art scrambler is to reach an Fk value of 5088, it must undergo at least 5088 clock cycles. In contrast, the present invention in the same example would merely have to undergo 212 clock cycles, and thus is 24 times faster. Thus, the present invention scrambler offers the improvement of high-speed performance. [0051] Those skilled in the art will readily observe that numerous modifications and alterations of the device may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims. Referenced by
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