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Publication numberUS20040140508 A1
Publication typeApplication
Application numberUS 10/752,684
Publication dateJul 22, 2004
Filing dateJan 8, 2004
Priority dateJan 14, 2003
Also published asCN1316559C, CN1518061A, US7851891, US20090206454
Publication number10752684, 752684, US 2004/0140508 A1, US 2004/140508 A1, US 20040140508 A1, US 20040140508A1, US 2004140508 A1, US 2004140508A1, US-A1-20040140508, US-A1-2004140508, US2004/0140508A1, US2004/140508A1, US20040140508 A1, US20040140508A1, US2004140508 A1, US2004140508A1
InventorsMichikazu Matsumoto, Naohisa Sengoku
Original AssigneeMatsushita Electric Industrial Co., Ltd.
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Semiconductor device and method for fabricating the same
US 20040140508 A1
Abstract
A method for fabricating a semiconductor device includes the steps of: forming a first insulating film on a semiconductor substrate; removing part of the first insulating film; forming a second insulating film having a leakage current density higher than that of the first insulating film on a region where the part of the first insulating film has been removed on the semiconductor substrate; forming an undoped semiconductor film on the first and second insulating films; implanting an impurity into part of the undoped semiconductor film, thereby defining semiconductor regions of a first conductivity type dotted as discrete islands; forming a third insulating film on the semiconductor regions of the first conductivity type and the undoped semiconductor film; and removing part of the third insulating film by wet etching. At least the second insulating film is formed under the semiconductor regions of the first conductivity type.
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Claims(27)
What is claimed is:
1. A method for fabricating a semiconductor device, comprising the steps of:
forming a first insulating film on a semiconductor substrate;
removing part of the first insulating film;
forming a second insulating film having a leakage current density higher than that of the first insulating film on a region where the part of the first insulating film has been removed on the semiconductor substrate;
forming an undoped semiconductor film on the first and second insulating films;
implanting an impurity into part of the undoped semiconductor film, thereby defining semiconductor regions of a first conductivity type dotted as discrete islands;
forming a third insulating film on the semiconductor regions of the first conductivity type and the undoped semiconductor film; and
removing part of the third insulating film by wet etching, wherein at least the second insulating film is formed under the semiconductor regions of the first conductivity type.
2. The method of claim 1, further comprising the step of implanting an impurity into the undoped semiconductor film to define a semiconductor region of a second conductivity type such that the semiconductor region of the second conductivity type is adjacent to the semiconductor regions of the first conductivity type,
wherein the step of forming the third insulating film is the step of forming the third insulating film on the semiconductor regions of the first conductivity type, the semiconductor region of the second conductivity type and the undoped semiconductor film, and
at least the second insulating film is formed under the semiconductor region of the second conductivity type.
3. The method of claim 1, wherein the average density of leakage current from the semiconductor regions of the first conductivity type to the outside of the first and second insulating films has an absolute value of 110−10 (A/mm2) or more in at least one polarity when the potential difference between the semiconductor regions of the first conductivity type and the outside of the first and second insulating films has an absolute value of 1.5 V.
4. The method of claim 2, wherein the average density of leakage current from the semiconductor region of the second conductivity type to the outside of the first and second insulating films has an absolute value of 110−10 (A/mm2) or more in at least one polarity when the potential difference between the semiconductor region of the second conductivity type and the outside of the first and second insulating films has an absolute value of 1.5 V.
5. The method of claim 1, wherein the wet etching is performed with a chemical solution containing fluorine ions.
6. A method for fabricating a semiconductor device, comprising the steps of:
forming a first insulating film on a semiconductor substrate;
forming an undoped semiconductor film on the first insulating film;
implanting an impurity into part of the undoped semiconductor film, thereby defining semiconductor regions of a first conductivity type dotted as discrete islands;
forming, at least on the semiconductor regions of the first conductivity type, a second insulating film having a leakage current density higher than that of the first insulating film; and
removing part of the second insulating film by wet etching.
7. The method of claim 6, further comprising the step of implanting an impurity into the undoped semiconductor film to define a semiconductor region of a second conductivity type such that the semiconductor region of the second conductivity type is adjacent to the semiconductor regions of the first conductivity type,
wherein the step of forming the second insulating film is performed at least on the semiconductor regions of the first conductivity type and the semiconductor region of the second conductivity type.
8. The method of claim 6, wherein the average density of leakage current from the semiconductor regions of the first conductivity type to the outside of the second insulating film has an absolute value of 110−10 (A/mm2) or more in at least one polarity when the potential difference between the semiconductor regions of the first conductivity type and the outside of the second insulating film has an absolute value of 1.5 V.
9. The method of claim 6, wherein the wet etching is performed with a chemical solution containing fluorine ions.
10. A method for fabricating a semiconductor device, comprising the steps of:
forming a first insulating film on a semiconductor substrate;
removing part of the first insulating film;
forming a second insulating film having a leakage current density higher than that of the first insulating film on a region where the part of the first insulating film has been removed on the semiconductor substrate;
forming an undoped semiconductor film on the first and second insulating films;
implanting at least one impurity into part of the undoped semiconductor film, thereby defining a semiconductor region of at least one conductivity type;
removing part of the semiconductor region of at least one conductivity type and the undoped semiconductor film, thereby forming a patterned semiconductor region of at least one conductivity type;
forming a third insulating film on the first and second insulating films such that the third insulating film covers the patterned semiconductor region of at least one conductivity type; and
removing part of the third insulating film by wet etching,
wherein at least the second insulating film is formed under the patterned semiconductor region of at least one conductivity type.
11. The method of claim 10, wherein the step of defining the semiconductor region of at least one conductivity type includes the step of defining a semiconductor region of a first conductivity type, and then defining a semiconductor region of a second conductivity type such that the semiconductor region of the second conductivity type is adjacent to the semiconductor region of the first conductivity type.
12. The method of claim 10, wherein the average density of leakage current from the semiconductor region of at least one conductivity type to the outside of the first and second insulating films has an absolute value of 110−10 (A/mm2) or more in at least one polarity when the potential difference between the patterned semiconductor region of at least one conductivity type and the outside of the fist and second insulating films has an absolute value of 1.5 V.
13. The method of claim 10, wherein the wet etching is performed with a chemical solution containing fluorine ions.
14. A method for fabricating a semiconductor device, comprising the steps of:
forming a first insulating film on a semiconductor substrate;
forming an undoped semiconductor film on the first insulating film;
implanting at least one impurity into the undoped semiconductor film, thereby defining a semiconductor region of at least one conductivity type;
removing part of the semiconductor region of at least one conductivity type and the undoped semiconductor film, thereby forming a patterned semiconductor region of at least one conductivity type;
forming a second insulating film having a leakage current density higher than that of the first insulating film on the first insulating film such that the second insulating film covers the patterned semiconductor region of at least one conductivity type; and
removing part of the second insulating film by wet etching.
15. The method of claim 14, wherein the semiconductor region of at least one conductivity type includes a semiconductor region of a first conductivity type and a semiconductor region of a second conductivity type.
16. The method of claim 14, wherein the average density of leakage current from the semiconductor region of at least one conductivity type to the outside of the second insulating film has an absolute value of 110−10 (A/mm2) or more in at least one polarity when the potential difference between the patterned semiconductor region of at least one conductivity type and the outside of the second insulating film has an absolute value of 1.5 V.
17. The method of claim 14, wherein the wet etching is performed with a chemical solution containing fluorine ions.
18. A semiconductor device, comprising:
a first insulating film formed on a semiconductor substrate;
a semiconductor film of a conductivity type formed on the first insulating film;
a second insulating film formed on the semiconductor film of the conductivity type such that both ends of the second insulating film are exposed on the semiconductor film of the conductivity type; and
a conductive film formed on each of the ends of the second insulating film on the semiconductor film of the conductivity type,
wherein the second insulating film has a leakage current density higher than that of the first insulating film.
19. The semiconductor device of claim 18, wherein the second insulating film is a silicon oxide film, a silicon nitride film, an undoped silicon oxide film formed under sub atmospheric conditions, a TEOS film formed under a reduced pressure, or a thermal oxidation film.
20. The semiconductor device of claim 18, wherein the second insulating film has a thickness smaller than that of the first insulating film.
21. The semiconductor device of claim 18, wherein the second insulating film has a film density lower than that of the first insulating film.
22. The semiconductor device of claim 18, wherein the conductive film is a metal silicide film or a metal film having a high melting point.
23. The semiconductor device of claim 18, wherein the leakage current density has an absolute value of 110−10 (A/mm2) or more in at least one polarity when the potential difference between the semiconductor film of the conductivity type and the outside of the second insulating film has an absolute value of 1.5 V.
24. A semiconductor device, comprising:
first and second insulating films formed to be in contact with each other on a semiconductor substrate;
a semiconductor film of a conductivity type formed on the first and second insulating films;
a third insulating film formed on the semiconductor film of the conductivity type such that both ends of the third insulating film are exposed on the semiconductor film of the conductivity type; and
a conductive film formed on each of the ends of the third insulating film on the semiconductor film of the conductivity type,
wherein the second insulating film has a leakage current density higher than that of the first insulating film.
25. The semiconductor device of claim 24, wherein the second insulating film has a thickness smaller than that of the first insulating film.
26. The semiconductor device of claim 24, wherein the conductive film is a metal silicide film or a metal film having a high melting point.
27. The semiconductor device of claim 24, wherein the leakage current density has an absolute value of 110−10 (A/mm2) or more in at least one polarity when the potential difference between the semiconductor film of the conductivity type and the outside of the first and second insulating films has an absolute value of 1.5 V.
Description
BACKGROUND OF THE INVENTION

[0001] A conventional semiconductor device and a conventional method for fabricating the device will be described with reference to FIGS. 16A through 16D.

[0002]FIGS. 16A through 16D are cross-sectional views showing respective process steps of a method for fabricating the conventional semiconductor device.

[0003] First, as shown in FIG. 16A, a silicon oxide film 12 is formed on a silicon substrate 11, a polysilicon film 13 is deposited over the silicon oxide film 12, and then dopants such as boron and phosphorus are implanted, thereby defining a p-type semiconductor region 13A and an n-type semiconductor region 13B in the polysilicon film 13. Subsequently, a silicon oxide film 14 is deposited over the polysilicon film 13, and then patterning is performed such that part of the silicon oxide film 14 remains only on a portion where a polysilicon resistor or a capacitor is to be formed. Thereafter, as shown in FIG. 16B, a TiN film 15 and a W film 16 are deposited in this order as a metal film, and then a SiN film 17 is deposited under a reduced pressure. Then, as shown in FIG. 16C, patterning is performed such that a resist 18 remains on portions to be both edges of a polysilicon resistor, a portion to be a gate electrode and a portion to be a capacitor. Thereafter, the SiN film 17 is patterned by dry etching to serve as a hard mask.

[0004] Next, as shown in FIG. 16D, the resist 18 is removed, and then dry etching is performed, so that a gate electrode with a normal polymetal gate structure is formed on a portion where the SiN film 17 remains and the silicon oxide film 14 does not remain after the patterning (see right-hand end of FIG. 16D), a polysilicon resistor in which the polysilicon film 13 is located under the silicon oxide film 14 with the silicon oxide film 14 serving as a hard mask is formed on a portion where the SiN film 17 does not remain and the silicon oxide film 14 remains after the patterning (see the middle of FIG. 16D), and a capacitor is formed together with the gate electrode and the polysilicon resistor (see the light-hand end of FIG. 16D). The polysilicon resistor has polymetal gate structures at both ends thereof, and wiring is connected to these ends in a subsequent process step (not shown). With respect to the capacitor, the silicon oxide film 14 is used as a capacitive insulating film by connecting wiring to the metal film.

[0005] In this manner, the polysilicon resistor, the capacitor and the gate electrode are formed (up to this process, see Japanese Laid-Open Publication No. 09-82896, for example).

[0006] However, we further studied the process for fabricating the polysilicon resistor, the capacitor and the gate electrode to find out the following problems.

[0007]FIGS. 17A through 17C are views for explaining problems arising in the process for fabricating the conventional polysilicon resistor, capacitor and gate electrode. FIGS. 17A and 17B are cross-sectional views and FIG. 17C shows an SEM image and an FIB image.

[0008] First, as shown in FIG. 17A, a silicon oxide film 22 is formed on a silicon substrate 21, a polysilicon film 23 is deposited over the silicon oxide film 22, and boron ions are implanted using a resist pattern as a mask, thereby defining a p-type semiconductor region 23A in the shape of an island in the polysilicon film 23. Subsequently, a silicon oxide film 24 is deposited on the polysilicon film 23 and is subjected to heat treatment at 750 C. At this time, the p-type semiconductor region 23A is vertically sandwiched between the underlying silicon oxide film 22 and the overlying silicon oxide film 24 and is horizontally surrounded with an undoped semiconductor region 23B. That is to say, considering that an undoped silicon film constituting the undoped semiconductor region 23B is substantially considered as an insulating film, the p-type semiconductor region 23A is completely surrounded with insulating films on all sides vertically and horizontally.

[0009] In this case, we found that when a resist 25 is patterned and then the silicon oxide film 24 on the p-type semiconductor region 23A is etched using the resist pattern as a mask, polysilicon in the p-type semiconductor region 23A disappears to form a hole 26, as shown in FIG. 17B. This disappearance of polysilicon is noticeable in a case where an undoped silicon oxide film formed under sub atmospheric conditions is used as the silicon oxide film 24.

[0010] As shown in FIG. 17C, according to observation results from the SEM image and the FIB image which show the hole 26 formed due to the disappearance of polysilicon, polysilicon disappears over a distance of several microns, and this disappearance of polysilicon is observed in the p-type semiconductor region 23A or at the boundary between the p-type semiconductor region 23A and the no-doped semiconductor region 23B. The disappearance of polysilicon is observed at a surface density of about 20 (cm−2). The disappearance of polysilicon causes the fault that the gate opens and a short-circuit fault at the gate due to entering of metal into a portion where polysilicon has disappeared. The disappearance of polysilicon also reduces the thickness of the gate oxide film to make the insulating property deteriorate so that reliability is reduced as well as a short-circuit fault between the gate electrode and the silicon substrate 21 occurs.

SUMMARY OF THE INVENTION

[0011] It is therefore an object of the present invention to provide a semiconductor device in which the disappearance of polysilicon is prevented and a method for fabricating the semiconductor device.

[0012] In order to achieve this object, we examined conditions under which the disappearance of polysilicon occurs.

[0013] We prepared a sample by the following manner. First, a polysilicon film was deposited over a silicon substrate with an oxide film with a thickness of 7 nm interposed therebetween, and then boron ions were implanted using a resist pattern as a mask, thereby defining an island p-type polysilicon region. Subsequently, a silicon oxide film was deposited and then the resultant sample was subjected to heat treatment at 750 C. and then to a process using a buffered hydrofluoric acid. At this time, a part of polysilicon had disappeared over the entire surface of the sample at a surface density of about 20 (cm−2). However, we found that, when the thickness of the oxide film under the polysilicon film was 2.6 nm, polysilicon did not disappear at all.

[0014] From the foregoing finding, it turned out that polysilicon does not disappear if the oxide film under the polysilicon film is very thin.

[0015] In view of this, we concluded that confinement of charge within the p-type polysilicon region is a cause of the disappearance of polysilicon. Specifically, our conclusion is as follows: when a wafer is charged with the p-type polysilicon region surrounded with thick insulating films and an undoped silicon film on all sides vertically and horizontally, charge is confined within the p-type polysilicon region and will not be emitted from the region in subsequent process steps, so that the confined charge becomes a cause of the disappearance of polysilicon. However, in a case where the oxide film is so thin as to allow tunneling of charge, even if charge is confined within the p-type polysilicon region, the charge is emitted toward the silicon substrate through the thin oxide film, resulting in that the p-type polysilicon region is not charged any more and polysilicon does not disappear. It is considered that the silicon substrate is charged by friction or the like in various processes such as plasma processing or in transferring the silicon substrate.

[0016] The reason why charge is a cause of the disappearance of polysilicon is not clear but it can be concluded that the disappearance of polysilicon is caused by the same mechanism as that of silicon anodization, i.e., formation of porous silicon or electro polishing.

[0017] Anodization is a phenomenon in which silicon is etched when a silicon substrate and an electrode of a noble metal such as Pt are disposed at the anode and cathode, respectively, and then are energized in a hydrofluoric acid. The mechanism thereof is considered to be that strong covalent bonds between silicon atoms are weakened by the presence of charge and thereby silicon is etched with the hydrofluoric acid (ref. R. L. Smith and S. D. Collins, J. Appl. Phys. 71 (1992) R1).

[0018] The disappearance of polysilicon described above is considered to be caused by a mechanism similar to that of the above phenomenon. Specifically, if the p-type polysilicon region is surrounded with insulating films and an undoped silicon film, charge generated through processing is not emitted from the p-type polysilicon region but confined within this region. If etching is performed using a buffered hydrofluoric acid in this state, the insulating film on top of the polysilicon film is etched first, but at the moment at which any portion of the p-type polysilicon region is exposed, the charge is emitted toward the buffered hydrofluoric acid and polysilicon is etched simultaneously with this emission. It is considered that the disappearance of polysilicon occurs as a result of the above process.

[0019] In addition, it is also considered that the disappearance of polysilicon described above also occurs in a case where there is no net electrification in the p-type polysilicon region. This is considered to be basically because of anodization based on emission of charge from the p-type polysilicon region toward the etchant. That is to say, it is considered that a difference in Fermi-level between the etchant and the p-type polysilicon region causes transfer of charge at the moment of the contact therebetween, so that charge is emitted and polysilicon disappears.

[0020] The disappearance of polysilicon in this case occurs not only in a case where the p-type polysilicon region is surrounded with the undoped polysilicon region but also in cases where an n-type polysilicon region is surrounded with an undoped polysilicon region, where a p-type polysilicon region is surrounded with an n-type polysilicon region and where an n-type polysilicon region is surrounded with a p-type polysilicon region.

[0021] In view of this, to achieve the above object, an inventive first method for fabricating a semiconductor device includes the steps of: forming a first insulating film on a semiconductor substrate; removing part of the first insulating film; forming a second insulating film having a leakage current density higher than that of the first insulating film on a region where the part of the first insulating film has been removed on the semiconductor substrate; forming an undoped semiconductor film on the first and second insulating films; implanting an impurity into part of the undoped semiconductor film, thereby defining semiconductor regions of a first conductivity type dotted as discrete islands; forming a third insulating film on the semiconductor regions of the first conductivity type and the undoped semiconductor film; and removing part of the third insulating film by wet etching, wherein at least the second insulating film is formed under the semiconductor regions of the first conductivity type.

[0022] With the first inventive method, the second insulating film allows charge in the semiconductor regions of the first conductivity type to be emitted to the outside of the first and second insulating films, so that it is possible to prevent the disappearance of polysilicon which occurs when any part of the semiconductor regions of the first conductivity type is exposed during the removal of part of the third insulating film by wet etching.

[0023] The first inventive method preferably further includes the step of implanting an impurity into the undoped semiconductor film to define a semiconductor region of a second conductivity type such that the semiconductor region of the second conductivity type is adjacent to the semiconductor regions of the first conductivity type. The step of forming the third insulating film is preferably the step of forming the third insulating film on the semiconductor regions of the first conductivity type, the semiconductor region of the second conductivity type and the undoped semiconductor film. At least the second insulating film is preferably formed under the semiconductor region of the second conductivity type.

[0024] Then, the second insulating film also allows charge in the semiconductor region of the second conductivity type to be emitted to the outside of the first and second insulating films, so that it is possible to prevent the disappearance of polysilicon which occurs when any part of the semiconductor region of the second conductivity type is exposed during the removal of part of the third insulating film by wet etching.

[0025] In the first inventive method, the average density of leakage current from the semiconductor regions of the first conductivity type to the outside of the first and second insulating films preferably has an absolute value of 110−10 (A/mm2) or more in at least one polarity when the potential difference between the semiconductor regions of the first conductivity type and the outside of the first and second insulating films has an absolute value of 1.5 V.

[0026] Then, the disappearance of polysilicon is prevented effectively.

[0027] In the first inventive method, the average density of leakage current from the semiconductor region of the second conductivity type to the outside of the first and second insulating films preferably has an absolute value of 110−10 (A/mm2) or more in at least one polarity when the potential difference between the semiconductor region of the second conductivity type and the outside of the first and second insulating films has an absolute value of 1.5 V.

[0028] Then, the disappearance of polysilicon is prevented effectively.

[0029] In the first inventive method, the wet etching is preferably performed with a chemical solution containing fluorine ions.

[0030] A second inventive method for fabricating a semiconductor device includes the steps of: forming a first insulating film on a semiconductor substrate; forming an undoped semiconductor film on the first insulating film; implanting an impurity into part of the undoped semiconductor film, thereby defining semiconductor regions of a first conductivity type dotted as discrete islands; forming, at least on the semiconductor regions of the first conductivity type, a second insulating film having a leakage current density higher than that of the first insulating film; and removing part of the second insulating film by wet etching.

[0031] With the second inventive method, the second insulating film allows charge in the semiconductor regions of the first conductivity type to be emitted to the outside of the second insulating film, so that it is possible to prevent the disappearance of polysilicon which occurs when any part of the semiconductor regions of the first conductivity type is exposed during the removal of part of the second insulating film by wet etching.

[0032] The second inventive method preferably further includes the step of implanting an impurity into the undoped semiconductor film to define a semiconductor region of a second conductivity type such that the semiconductor region of the second conductivity type is adjacent to the semiconductor regions of the first conductivity type. The step of forming the second insulating film is preferably performed at least on the semiconductor regions of the first conductivity type and the semiconductor region of the second conductivity type.

[0033] Then, the second insulating film also allows charge in the semiconductor region of the second conductivity type to be emitted to the outside of the second insulating film, so that it is possible to prevent the disappearance of polysilicon which occurs when any part of the semiconductor region of the second conductivity type is exposed during the removal of part of the second insulating film by wet etching.

[0034] In the second inventive method, average leakage current density from the semiconductor regions of the first conductivity type to the outside of the second insulating film preferably has an absolute value of 110−10 (A/mm2) or more in at least one polarity when the potential difference between the semiconductor regions of the first conductivity type and the outside of the second insulating film has an absolute value of 1.5 V.

[0035] Then, the disappearance of polysilicon is prevented effectively.

[0036] In the second inventive method, the wet etching is preferably performed with a chemical solution containing fluorine ions.

[0037] A third inventive method for fabricating a semiconductor device includes the steps of: forming a first insulating film on a semiconductor substrate; removing part of the first insulating film; forming a second insulating film having a leakage current density higher than that of the first insulating film on a region where the part of the first insulating film has been removed on the semiconductor substrate; forming an undoped semiconductor film on the first and second insulating films; implanting at least one impurity into part of the undoped semiconductor film, thereby defining a semiconductor region of at least one conductivity type; removing part of the semiconductor region of at least one conductivity type and the undoped semiconductor film, thereby forming a patterned semiconductor region of at least one conductivity type; forming a third insulating film on the first and second insulating films such that the third insulating film covers the patterned semiconductor region of at least one conductivity type; and removing part of the third insulating film by wet etching, wherein at least the second insulating film is formed under the patterned semiconductor region of at least one conductivity type.

[0038] With the third inventive method, the second insulating film allows charge in the patterned semiconductor region of at least one conductivity type to be emitted to the outside of the first and second insulating films, so that it is possible to prevent the disappearance of polysilicon which occurs when any part of the patterned semiconductor region of at least one conductivity type is exposed during the removal of part of the third insulating film by wet etching.

[0039] The third inventive method may further include the step of defining the semiconductor region of at least one conductivity type includes the step of defining a semiconductor region of a first conductivity type, and then defining a semiconductor region of a second conductivity type such that the semiconductor region of the second conductivity type is adjacent to the semiconductor region of the first conductivity type.

[0040] In the third inventive method, the average density of leakage current from the semiconductor region of at least one conductivity type to the outside of the first and second insulating films preferably has an absolute value of 110−10 (A/mm2) or more in at least one polarity when the potential difference between the patterned semiconductor region of at least one conductivity type and the outside of the fist and second insulating films has an absolute value of 1.5 V.

[0041] Then, the disappearance of polysilicon is prevented effectively.

[0042] In the third inventive method, the wet etching is preferably performed with a chemical solution containing fluorine ions.

[0043] A fourth inventive method for fabricating a semiconductor device includes the steps of: forming a first insulating film on a semiconductor substrate; forming an undoped semiconductor film on the first insulating film; implanting at least one impurity into the undoped semiconductor film, thereby defining a semiconductor region of at least one conductivity type; removing part of the semiconductor region of at least one conductivity type and the undoped semiconductor film, thereby forming a patterned semiconductor region of at least one conductivity type; forming a second insulating film having a leakage current density higher than that of the first insulating film on the first insulating film such that the second insulating film covers the patterned semiconductor region of at least one conductivity type; and removing part of the second insulating film by wet etching.

[0044] With the forth inventive method, the second insulating film allows charge in the patterned semiconductor region of at least one conductivity type to be emitted to the outside of the second insulating film, so that it is possible to prevent the disappearance of polysilicon which occurs when any part of the patterned semiconductor region of at least one conductivity type is exposed during the removal of part of the second insulating film by wet etching.

[0045] In the fourth inventive method, the semiconductor region of at least one conductivity type may include a semiconductor region of a first conductivity type and a semiconductor region of a second conductivity type.

[0046] In the fourth inventive method, the average density of leakage current from the semiconductor region of at least one conductivity type to the outside of the second insulating film preferably has an absolute value of 110−10 (A/mm2) or more in at least one polarity when the potential difference between the patterned semiconductor region of at least one conductivity type and the outside of the second insulating film has an absolute value of 1.5 V.

[0047] Then, the disappearance of polysilicon is prevented effectively.

[0048] In the fourth inventive method, the wet etching is preferably performed with a chemical solution containing fluorine ions.

[0049] To solve the problems described above, a first inventive semiconductor device includes: a first insulating film formed on a semiconductor substrate; a semiconductor film of a conductivity type formed on the first insulating film; a second insulating film formed on the semiconductor film of the conductivity type such that both ends of the second insulating film are exposed on the semiconductor film of the conductivity type; and a conductive film formed on each of the ends of the second insulating film on the semiconductor film of the conductivity type, wherein the second insulating film has a leakage current density higher than that of the first insulating film.

[0050] Since the first inventive semiconductor device includes the second insulating film allowing charge in the semiconductor film of the conductivity type to be emitted to the outside of the second insulating film, it is possible to prevent the disappearance of polysilicon which occurs when part of the second insulating film is removed such that both ends of the semiconductor film of the conductivity type are exposed.

[0051] In the first inventive semiconductor device, the second insulating film is preferably a silicon oxide film, a silicon nitride film, an undoped silicon oxide film formed under sub atmospheric conditions, a TEOS film formed under a reduced pressure, or a thermal oxidation film.

[0052] In the first inventive semiconductor device, the second insulating film preferably has a thickness smaller than that of the first insulating film.

[0053] Then, charge in the semiconductor film of the conductivity type is more effectively emitted to the outside of the second insulating film.

[0054] In the first inventive semiconductor device, the second insulating film preferably has a film density lower than that of the first insulating film.

[0055] Then, charge in the semiconductor film of the conductivity type is more effectively emitted to the outside of the second insulating film.

[0056] In the first inventive semiconductor device, the conductive film is preferably a metal silicide film or a metal film having a high melting point.

[0057] In the first inventive semiconductor device, the leakage current density preferably has an absolute value of 110−10 (A/mm2) or more in at least one polarity when the potential difference between the semiconductor film of the conductivity type and the outside of the second insulating film has an absolute value of 1.5 V.

[0058] Then, the disappearance of polysilicon is prevented effectively.

[0059] A second inventive semiconductor device includes: first and second insulating films formed to be in contact with each other on a semiconductor substrate; a semiconductor film of a conductivity type formed on the first and second insulating films; a third insulating film formed on the semiconductor film of the conductivity type such that both ends of the third insulating film are exposed on the semiconductor film of the conductivity type; and a conductive film formed on each of the ends of the third insulating film on the semiconductor film of the conductivity type, wherein the second insulating film has a leakage current density higher than that of the first insulating film.

[0060] Since the second inventive semiconductor device includes the second insulating film allowing charge in the semiconductor film of the conductivity type to be emitted to the outside of the first and second insulating films, it is possible to prevent the disappearance of polysilicon which occurs when part of the third insulating film is removed such that both ends of the third insulating film are exposed.

[0061] In the second inventive semiconductor device, the second insulating film preferably has a thickness smaller than that of the first insulating film.

[0062] Then, charge in the semiconductor film of the conductivity type is more effectively emitted to the outside of the first and second insulating films.

[0063] In the second inventive semiconductor device, the conductive film is preferably a metal silicide film or a metal film having a high melting point.

[0064] In the second inventive semiconductor device, the leakage current density preferably has an absolute value of 110−10 (A/mm2) or more in at least one polarity when the potential difference between the semiconductor film of the conductivity type and the outside of the first and second insulating films has an absolute value of 1.5 V.

[0065] Then, the disappearance of polysilicon is prevented effectively.

BRIEF DESCRIPTION OF THE DRAWINGS

[0066]FIG. 1A is a cross-sectional view for describing a semiconductor device and a method for fabricating the device according to a first embodiment of the present invention. FIG. 1B is a plan view for describing the semiconductor device and the method for fabricating the device of the first embodiment.

[0067]FIGS. 2A and 2B are cross-sectional views for describing the semiconductor device and the method for fabricating the device of the first embodiment.

[0068]FIG. 3 is a plan view for describing the semiconductor device and the method for fabricating the device of the first embodiment.

[0069]FIG. 4 is a graph showing a relationship between the average current density of leakage current and the surface density of the disappearance of polysilicon.

[0070]FIG. 5A is a cross-sectional view for describing a semiconductor device and a method for fabricating the device according to a second embodiment of the present invention. FIGS. 5B and 5C are plan views for describing the semiconductor device and the method for fabricating the device of the second embodiment.

[0071]FIG. 6A is a cross-sectional view for describing a semiconductor device and a method for fabricating the device according to a third embodiment of the present invention.

[0072]FIG. 6B is a plan view for describing the semiconductor device and the method for fabricating the device of the third embodiment.

[0073]FIGS. 7A and 7B are cross-sectional views for describing the semiconductor device and the method for fabricating the device of the third embodiment.

[0074]FIG. 8 is a plan view for describing the semiconductor device and the method for fabricating the device of the third embodiment.

[0075]FIG. 9A is a cross-sectional view for describing a semiconductor device and a method for fabricating the device according to a fourth embodiment of the present invention. FIGS. 9B and 9C are plan views for describing the semiconductor device and the method for fabricating the device of the fourth embodiment.

[0076]FIGS. 10A through 10D are cross-sectional views for describing a semiconductor device and a method for fabricating the device according to a fifth embodiment of the present invention.

[0077]FIGS. 11A through 11D are cross-sectional views for describing a semiconductor device and a method for fabricating the device according to a sixth embodiment of the present invention.

[0078]FIG. 12 is a cross-sectional view for describing a semiconductor device and a method for fabricating the device according to a seventh embodiment of the present invention.

[0079]FIG. 13 is a cross-sectional view for describing a semiconductor device and a method for fabricating the device according to an eighth embodiment of the present invention.

[0080]FIGS. 14A and 14B are cross-sectional views for describing a semiconductor device and a method for fabricating the device according to a ninth embodiment of the present invention.

[0081]FIGS. 15A and 15B are cross-sectional views for describing a semiconductor device and a method for fabricating the device according to a tenth embodiment of the present invention.

[0082]FIGS. 16A through 16D are cross-sectional views for describing a conventional semiconductor device and a method for fabricating the device.

[0083]FIGS. 17A and 17B are cross-sectional views for describing the conventional semiconductor device and the method for fabricating the device. FIG. 17C is photographs showing an SEM image and an FIB image.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0084] Embodiment 1

[0085] Hereinafter, a semiconductor device and a method for fabricating the semiconductor device according to a first embodiment of the present invention will be described with reference to FIGS. 1A, 1B, 2A, 2B, 3 and 4.

[0086]FIGS. 1A, 1B, 2A, 2B, 3 and 4 are views for describing the semiconductor device and the method for fabricating the device of the first embodiment. FIGS. 1A, 2A and 2B are cross-sectional views and FIGS. 1B and 3 are plan views.

[0087] As shown in FIG. 1A, a silicon oxide film is formed on a silicon substrate 101, and then the silicon oxide film is etched with a hydrofluoric acid using a resist pattern as a mask, thereby partly removing the silicon oxide film and exposing the silicon substrate 101. Subsequently, the resist is removed, and then high-temperature heat treatment is performed in an oxygen atmosphere. In this manner, the exposed portion of the silicon substrate 101 is oxidized to form a second silicon oxide film 103. In this case, the thermal oxidation increases the thickness of the silicon oxide film firstly formed, thereby forming a first silicon oxide film 102. At this time, the second silicon oxide film 103 is formed to have a thickness which allows easy tunneling of charge.

[0088] Next, a polysilicon film 104 is deposited over the first silicon oxide film 102 and the second silicon oxide film 103. Thereafter, boron (B) ions are implanted using a resist pattern as a mask, thereby defining a p-type semiconductor region 104A in the polysilicon film 104. At this time, as shown in FIG. 1B, the p-type semiconductor region 104A is surrounded with an undoped semiconductor region 104B and isolated in the shape of an island. The second silicon oxide film 103 is present under the isolated p-type semiconductor region 104A. Subsequently, a third silicon oxide film 105 is formed on the polysilicon film 104, is subjected to heat treatment at 750 C., and then is etched with a buffered hydrofluoric acid using a resist pattern as a mask, so that the third silicon oxide film 105 is removed except for portions where a resistor and a capacitor are to be formed, thereby forming a silicon oxide film 105A (see FIGS. 2A and 2B). In this case, the second silicon oxide film 103 serves as a leakage path so that charge in the p-type semiconductor region 104 is emitted toward the silicon substrate 101 through the second silicon oxide film 103. Accordingly, it is possible to prevent polysilicon from disappearing during etching.

[0089] Thereafter, in the case of forming a polymetal gate, a TiN film 106, a W film 107 and a SiN film 108 are deposited and then patterned, thereby forming a polymetal gate electrode together with a polysilicon resistor and a capacitor, as shown in FIGS. 2A and 2B. Specifically, the TiN film 106 and the W film 107 are deposited in this order, and then the SiN film 108 is deposited under a reduced pressure. Then, a resist is formed over the SiN film 108 and then patterning is performed in the manner that the resist remains on portions to be both edges of a polysilicon resistor, a portion to be a gate electrode and a portion to be a capacitor. Thereafter, the SiN film 108 is patterned by dry etching to serve as a hard mask. Then, after the resist has been removed, dry etching is performed, thereby forming a polymetal gate electrode, a polysilicon resistor and a capacitor.

[0090] The second silicon oxide film 103 serving as a leakage path for charge may be formed under the isolated island p-type semiconductor region 104A and located at a position where a polysilicon resistor is to be formed, as shown in FIG. 2A, or may be formed at a position where a gate electrode or a capacitor is to be formed. Alternatively, as shown in FIG. 2B, the second silicon oxide film 103 may be formed at a position where no gate is present after gate dry etching or may be formed at a position where a dummy gate is to be formed.

[0091] In the foregoing description, the p-type semiconductor region 104A is defined in the polysilicon film 104. Alternatively, an n-type semiconductor region may be defined instead of the p-type semiconductor region 104A. In such a case, the n-type semiconductor region is surrounded with the undoped semiconductor region, and the second silicon oxide film 103 needs to be formed under the isolated island n-type semiconductor region, as in the case of the p-type semiconductor region 104A.

[0092] As long as the semiconductor region of a conductivity type defined in the polysilicon film 104 is surrounded with the undoped semiconductor region, silicon constituting the semiconductor region of the conductivity type is not limited to either one of n-type and p-type in general. As shown in FIG. 3, a mixed structure of one or more n-type semiconductor regions 104C and one or more p-type semiconductor regions 104A may be surrounded with the undoped semiconductor region 104B. In such a case, the second silicon oxide film 103 is preferably formed under each of the p-type semiconductor regions 104A and the n-type semiconductor regions 104C.

[0093] Now, FIG. 4 shows a relationship between the average current density of leakage current from the p-type semiconductor region 104A to the silicon substrate 101 and the surface density of the disappearance of polysilicon. In FIG. 4, evaluation is made using devices fabricated with the area ratio between the first and second silicon oxide films 102 and 103 and the thickness of the second silicon oxide film 103 changed variously and with the area of the p-type semiconductor region 104A kept constant.

[0094] As shown in FIG. 4, the surface density of the disappearance of polysilicon decreases as the average current density of leakage current increases. When the average current density is 110−10 (A/mm2) or more, no disappearance of polysilicon occurs. In this evaluation, the silicon substrate 101 is p-type and a voltage of 1.5 V is applied as a measurement voltage in a direction that makes charge accumulated in the silicon substrate 101. The average current density of leakage current is herein obtained by dividing current flowing from each island p-type semiconductor region by the area occupied by this semiconductor region.

[0095] Embodiment 2

[0096] Hereinafter, a semiconductor device and a method for fabricating the semiconductor device according to a second embodiment of the present invention will be described with reference to FIGS. 5A through 5C.

[0097]FIGS. 5A through 5C are views for describing the semiconductor device and the method for fabricating the device of the second embodiment. FIG. 5A is a cross-sectional view and FIGS. 5B and 5C are plan views.

[0098] As shown in FIG. 5A, a first silicon oxide film 202 is formed on a silicon substrate 201, and then a polysilicon film 203 is deposited over the first silicon oxide film 202. Subsequently, boron (B) ions are implanted using a resist pattern as a mask, thereby defining a p-type semiconductor region 203A in the polysilicon film 203. At this time, as shown in FIG. 5B, the p-type semiconductor region 203A is surrounded with an undoped semiconductor region 203B and isolated in the shape of an island. Thereafter, a second silicon oxide film 204 is formed on the polysilicon oxide film 203. Then, etching is performed with a hydrofluoric acid using a resist pattern as a mask, thereby removing the second silicon oxide film 204 except for portions where a resistor and a capacitor are to be formed. In this case, no beat treatment is performed on the second silicon oxide film 204 so that the second silicon oxide film 204 has a high leakage current density, while being an insulating film. Accordingly, the second silicon oxide film 204 serves as a leakage path for charge in the p-type semiconductor region 203A so that charge in the p-type semiconductor region 203A is emitted to the outside through the second silicon oxide film 204. As a result, it is possible to prevent polysilicon from disappearing during etching.

[0099] Thereafter, in the case of forming a polymetal gate, a TiN film, a W film and a SiN film are deposited and then patterned, thereby forming a polymetal gate electrode together with a polysilicon resistor and a capacitor (not shown). Specifically, the TiN film and the W film are deposited in this order, and then the SiN film is deposited under a reduced pressure. Then, a resist is formed over the SiN film and then patterning is performed in the manner that the resist remains on portions to be both edges of a polysilicon resistor, a portion to be a gate electrode and a portion to be a capacitor. Thereafter, the SiN film is patterned by dry etching to serve as a hard mask. Then, after the resist has been removed, dry etching is performed, thereby forming a polymetal gate electrode, a polysilicon resistor and a capacitor.

[0100] In the foregoing description, the p-type semiconductor region 203A is defined in the polysilicon film 203. Alternatively, an n-type semiconductor region may be defined instead of the p-type semiconductor region 203A. In such a case, the n-type semiconductor region is surrounded with the undoped semiconductor region.

[0101] As long as the semiconductor region of a conductivity type defined in the polysilicon film 203 is surrounded with the undoped semiconductor region, silicon constituting the semiconductor region of the conductivity type is not limited to either one of n-type and p-type in general. As shown in FIG. 5C, a mixed structure of one or more n-type semiconductor regions 203C and one or more p-type semiconductor regions 203A may be surrounded with the undoped semiconductor region 203B.

[0102] Embodiment 3

[0103] Hereinafter, a semiconductor device and a method for fabricating the semiconductor device according to a third embodiment of the present invention will be described with reference to FIGS. 6A, 6B, 7A, 7B and 8.

[0104]FIGS. 6A, 6B, 7A, 7B and 8 are views for describing the semiconductor device and the method for fabricating the device of the third embodiment. FIGS. 6A, 7A and 7B are cross-sectional views and FIGS. 6B and 8 are plan views.

[0105] As shown in FIG. 6A, a silicon oxide film is formed on a silicon substrate 301, and then the silicon oxide film is etched with a hydrofluoric acid using a resist pattern as a mask, thereby partly removing the silicon oxide film and exposing the silicon substrate 301. Subsequently, the resist is removed, and then high-temperature heat treatment is performed in an oxygen atmosphere. In this manner, the exposed portion of the silicon substrate 301 is oxidized to form a second silicon oxide film 303. In this case, the thermal oxidation increases the thickness of the silicon oxide film firstly formed, thereby forming a first silicon oxide film 302. At this time, the second silicon oxide film 303 is formed to have a thickness which allows easy tunneling of charge.

[0106] Next, a polysilicon film 304 is deposited over the first silicon oxide film 302 and the second silicon oxide film 303. Thereafter, boron (B) ions are implanted using a resist pattern as a mask, thereby defining a p-type semiconductor region 304A in the polysilicon film 304. Subsequently, phosphorus (P) ions are implanted using a resist pattern as a mask, thereby defining an n-type semiconductor region 304B in the polysilicon film 304. At this time, as shown in FIG. 6B, the p-type semiconductor region 304A is surrounded with the n-type semiconductor region 304B and isolated in the shape of an island. The second silicon oxide film 303 is present under the isolated p-type semiconductor region 304A. Subsequently, a third silicon oxide film 305 is formed on the polysilicon film 304, is subjected to heat treatment at 750 C., and then is etched with a buffered hydrofluoric acid using a resist pattern as a mask so that the third silicon oxide film 305 is removed except for portions where a resistor and a capacitor are to be formed, thereby forming a silicon oxide film 305A (see FIGS. 7A and 7B). In this case, the second silicon oxide film 303 serves as a leakage path so that charge in the p-type semiconductor region 304 is emitted toward the silicon substrate 301 through the second silicon oxide film 303. Accordingly, it is possible to prevent polysilicon from disappearing during etching.

[0107] Thereafter, in the case of forming a polymetal gate, a TiN film 306, a W film 307 and a SiN film 308 are deposited and then patterned, thereby forming a polymetal gate electrode together with a polysilicon resistor and a capacitor, as shown in FIGS. 7A and 7B. Specifically, the TiN film 306 and the W film 307 are deposited in this order, and then the SiN film 308 is deposited under a reduced pressure. Then, a resist is formed over the SiN film 308 and then patterning is performed in the manner that the resist remains on portions to be both edges of a polysilicon resistor, a portion to be a gate electrode and a portion to be a capacitor. Thereafter, the SiN film 308 is patterned by dry etching to serve as a hard mask. Then, after the resist has been removed, dry etching is performed, thereby forming a polymetal gate electrode, a polysilicon resistor and a capacitor.

[0108] The second silicon oxide film 303 serving as a leakage path for charge may be formed under the isolated island p-type semiconductor region 304A to be located at a position where a polysilicon resistor is to be formed as shown in FIG. 7A, or may be formed at a position where a gate electrode or a capacitor is to be formed. Alternatively, as shown in FIG. 7B, the second silicon oxide film 303 may be formed at a position where no gate is present after gate dry etching or may be formed at a position where a dummy gate is to be formed.

[0109] In the foregoing description, the p-type semiconductor region 304A is defined within the n-type semiconductor region 304B. Alternatively, the n-type semiconductor region 304B and the p-type semiconductor region 304A may be replaced with each other. In such a case, as shown in FIG. 8, the n-type semiconductor region 304B is surrounded with the p-type semiconductor region 304A, and the second silicon oxide film 303 needs to be formed under the isolated island n-type semiconductor region 304B.

[0110] Embodiment 4

[0111] Hereinafter, a semiconductor device and a method for fabricating the semiconductor device according to a fourth embodiment of the present invention will be described with reference to FIGS. 9A through 9C.

[0112]FIGS. 9A through 9C are views for describing the semiconductor device and the method for fabricating the device of the fourth embodiment. FIG. 9A is a cross-sectional view and FIGS. 91 and 9C are plan views.

[0113] As shown in FIG. 9A, a first silicon oxide film 402 is formed on a silicon substrate 401, and then a polysilicon film 403 is deposited over the first silicon oxide film 402. Subsequently, boron (B) ions are implanted using a resist pattern as a mask, thereby defining a p-type semiconductor region 403A in the polysilicon film 403. Thereafter, phosphorus (P) ions are implanted using a resist pattern as a mask, thereby defining an n-type semiconductor region 403B in the polysilicon film 403. At this time, as shown in FIG. 9B, the p-type semiconductor region 403A is surrounded with the n-type semiconductor region 403B and isolated in the shape of an island. Thereafter, a second silicon oxide film 404 is formed on the polysilicon oxide film 403. Then, etching is performed with a hydrofluoric acid using a resist pattern as a mask, thereby removing the second silicon oxide film 404 except for portions where a resistor and a capacitor are to be formed. In this case, no heat treatment is performed on the second silicon oxide film 404 so that the second silicon oxide film 404 has a high leakage current density, while being an insulating film. Accordingly, the second silicon oxide film 404 serves as a leakage path for charge in the p-type semiconductor region 403A so that charge in the p-type semiconductor region 403A is emitted to the outside through the second silicon oxide film 404. As a result, it is possible to prevent polysilicon from disappearing during etching.

[0114] Thereafter, in the case of forming a polymetal gate, a TiN film, a W film and a SiN film are deposited and then patterned, thereby forming a polymetal gate electrode together with a polysilicon resistor and a capacitor (not shown). Specifically, the TiN film and the W film are deposited in this order, and then the SiN film is deposited under a reduced pressure. Then, a resist is formed over the SiN film and then patterning is performed in the manner that the resist remains on portions to be both edges of a polysilicon resistor, a portion to be a gate electrode and a portion to be a capacitor. Thereafter, the SiN film is patterned by dry etching to serve as a hard mask. Then, after the resist has been removed, dry etching is performed, thereby forming a polymetal gate electrode, a polysilicon resistor and a capacitor.

[0115] In the foregoing description, the p-type semiconductor region 404A is defined within the n-type semiconductor region 404B. Alternatively, the n-type semiconductor region 404B and the p-type semiconductor region 404A may be replaced with each other. In such a case, as shown in FIG. 9C, the n-type semiconductor region 404B is surrounded with the p-type semiconductor region 404A.

[0116] Embodiment 5

[0117] Hereinafter, a semiconductor device and a method for fabricating the semiconductor device according to a fifth embodiment of the present invention will be described with reference to FIGS. 10A through 10D.

[0118]FIGS. 10A through 10D are cross-sectional views showing the semiconductor device and the method for fabricating the device of the fifth embodiment.

[0119] As shown in FIG. 10A, a silicon oxide film is formed on a silicon substrate 501, and then the silicon oxide film is etched with a hydrofluoric acid using a resist pattern as a mask, thereby partly removing the silicon oxide film and exposing the silicon substrate 501. Subsequently, the resist is removed, and then high-temperature heat treatment is performed in an oxygen atmosphere. In this manner, the exposed portion of the silicon substrate 501 is oxidized to form a second silicon oxide film 503. In this case, the thermal oxidation increases the thickness of the silicon oxide film firstly formed, thereby forming a first silicon oxide film 502. At this time, the second silicon oxide film 503 is formed to have a thickness which allows easy tunneling of charge.

[0120] Next, a polysilicon film 504 is deposited over the first silicon oxide film 502 and the second silicon oxide film 503. Thereafter, boron (B) ions are implanted using a resist pattern as a mask, thereby defining a p-type semiconductor region 504A in the polysilicon film 504. Subsequently, phosphorus (P) ions are implanted using a resist pattern as a mask, thereby defining an n-type semiconductor region 504B in the polysilicon film 504. Then, as shown in FIG. 10B, patterning is performed to form patterned p-type and n-type semiconductor regions 504A′ and 504B′ out of the p-type and n-type semiconductor regions 504A and 504B shown in FIG. 10A, respectively. Thereafter, a third silicon oxide film 505 is deposited and subjected to heat treatment at 750 C. At this time, as shown in FIG. 10B, each of the patterned p-type and n-type semiconductor regions 504A′ and 504B′ is surrounded with the first silicon oxide film 502, the second silicon oxide film 503 and the third silicon oxide film 505 on all sides vertically and horizontally, and the second silicon oxide film 503 is present under each of the isolated patterned p-type and n-type semiconductor regions 504A′ and 504B′. In this case, the second silicon oxide film 503 serves as a leakage path so that charge in the patterned p-type and n-type semiconductor regions 504A′ and 504B′ is emitted toward the silicon substrate 501 through the second silicon oxide film 503. Accordingly, it is possible to prevent polysilicon from disappearing during etching.

[0121] As shown in FIG. 10C, if there is a region in which the patterned p-type and n-type semiconductor regions 504A′ and 504B′ are continuous, the second silicon oxide film 503 is preferably formed under each of the patterned p-type and n-type semiconductor regions 504A′ and 504B′.

[0122] Then, as shown in FIG. 10D, etching is performed with a buffered hydrofluoric acid using a resist pattern as a mask, thereby partly removing the third silicon oxide film 505. In this case, the second silicon oxide film 503 serves as a leakage path so that it is possible to prevent polysilicon from disappearing during etching.

[0123] Embodiment 6

[0124] Hereinafter, a semiconductor device and a method for fabricating the semiconductor device according to a sixth embodiment of the present invention will be described with reference to FIGS. 1A through 111D.

[0125]FIGS. 11A through 11D are cross-sectional views showing the semiconductor device and the method for fabricating the device of the sixth embodiment.

[0126] As shown in FIG. 11A, a first silicon oxide film 602 is formed on a silicon substrate 601, and then a polysilicon film 603 is deposited over the first silicon oxide film 602. Thereafter, boron (B) ions are implanted using a resist pattern as a mask, thereby defining a p-type semiconductor region 603A in the polysilicon film 603. Subsequently, phosphorus (P) ions are implanted using a resist pattern as a mask, thereby defining an n-type semiconductor region 603B in the polysilicon film 603. Then, as shown in FIG. 11B, patterning is performed to form patterned p-type and n-type semiconductor regions 603A′ and 603B′ out of the p-type and n-type semiconductor regions 603A and 603B shown in FIG. 11A, respectively. Thereafter, a second silicon oxide film 604 is deposited. At this time, as shown in FIG. 11B, each of the patterned p-type and n-type semiconductor regions 603A′ and 603B′ is surrounded with the first silicon oxide film 602, the second silicon oxide film 604 on all sides vertically and horizontally. In this case, no heat treatment is performed on the second silicon oxide film 604 so that the second silicon oxide film 604 has a high leakage current density, while being an insulating film. Accordingly, the second silicon oxide film 604 serves as a leakage path for charge in the patterned p-type and n-type semiconductor regions 603A′ and 603B′. That is to say, charge in the patterned p-type and n-type semiconductor regions 603A′ and 603B′ is emitted to the outside through the second silicon oxide film 604. As shown in FIG. 11C, there may be a region in which the patterned p-type and n-type semiconductor regions 603A′ and 603B′ are continuous.

[0127] Then, as shown in FIG. 11D, etching is performed with a buffered hydrofluoric acid using a resist pattern as a mask, thereby partly removing the second silicon oxide film 604. During this etching, the second silicon oxide film 604 serves as a leakage path so that it is possible to prevent polysilicon from disappearing.

[0128] Embodiment 7

[0129] Hereinafter, a semiconductor device and a method for fabricating the semiconductor device according to a seventh embodiment of the present invention will be described with reference to FIG. 12.

[0130]FIG. 12 is a cross-sectional view for describing the semiconductor device and the method for fabricating the device of the seventh embodiment.

[0131] As shown in FIG. 12, isolations 701 are formed in a silicon substrate 700, and then a polymetal gate electrode and a polysilicon resistor are formed in the same manner as in the third embodiment.

[0132] Specifically, a silicon oxide film is formed on the silicon substrate 700, and then the silicon oxide film is etched with a hydrofluoric acid using a resist pattern as a mask, thereby partly removing the silicon oxide film and exposing the silicon substrate 700. Subsequently, the resist is removed, and then high-temperature heat treatment is performed in an oxygen atmosphere. In this manner, the exposed portion of the silicon substrate 700 is oxidized to form a second silicon oxide film 703. In this case, the thermal oxidation increases the thickness of the silicon oxide film firstly formed, thereby forming a first silicon oxide film 702. At this time, the second silicon oxide film 703 is formed to have a thickness which allows easy tunneling of charge.

[0133] Next, a polysilicon film 704 is deposited over the first silicon oxide film 702 and the second silicon oxide film 703. Thereafter, boron (B) ions are implanted using a resist pattern as a mask, thereby defining a p-type semiconductor region in the polysilicon film 704. Subsequently, phosphorus (P) ions are implanted using a resist pattern as a mask, thereby defining an n-type semiconductor region in the polysilicon film 704. Thereafter, a third silicon oxide film is formed on the p-type semiconductor region, is subjected to heat treatment at 750 C., and then is etched with a buffered hydrofluoric acid using a resist pattern as a mask so that the third silicon oxide film is removed except for portions where a resistor and a capacitor are to be formed, thereby forming a silicon oxide film 705. At this time, the second silicon oxide film 703 serves as a leakage path so that charge in the p-type semiconductor region (or n-type semiconductor region) is emitted toward the silicon substrate 700 through the second silicon oxide film 703. Accordingly, it is possible to prevent polysilicon from disappearing during etching. This effect is the same if the polysilicon film 704 formed under the silicon oxide film 705 is an n-type semiconductor region.

[0134] Thereafter, a TiN film 706, a W film 707 and a SiN film 708 are deposited and then patterned, thereby forming a polysilicon resistor, a polymetal gate electrode and a capacitor (not shown). Specifically, the TiN film 706 and the W film 707 are deposited in this order, and then the SiN film 708 is deposited under a reduced pressure. Then, a resist is formed over the SiN film 708 and then patterning is performed in the manner that the resist remains on portions to be both edges of a polysilicon resistor, a portion to be a gate electrode and a portion to be a capacitor. Thereafter, the SiN film 708 is patterned by dry etching to serve as a hard mask. Then, after the resist has been removed, dry etching is performed, thereby forming a polysilicon resistor, a polymetal gate electrode and a capacitor.

[0135] Then, the silicon substrate 700 is doped with an impurity using the polymetal gate electrode as a mask, thereby forming a lightly doped layer 709. Subsequently, a silicon nitride film is deposited over the entire surface of the silicon substrate 700, and then is subjected to anisotropic etching, thereby forming a sidewall 710 on the side of the gate electrode. Thereafter, the silicon substrate 700 is doped with an impurity using the polymetal gate electrode and the sidewall 710 as a mask, thereby forming a heavily doped layer 711.

[0136] Then, heat treatment is performed on the silicon substrate 700 to activate the lightly doped layer 709 and the heavily doped layer 711. Thereafter, a cobalt film is formed, and finally a cobalt silicide film 712 is formed by heat treatment in the surface of source and drain regions. In this manner, a semiconductor device including an MOS transistor, a polysilicon resistor or a capacitor is fabricated.

[0137] Embodiment 8

[0138] Hereinafter, a semiconductor device and a method for fabricating the semiconductor device according to an eighth embodiment of the present invention will be described with reference to FIG. 13.

[0139]FIG. 13 is a cross-sectional view for describing the semiconductor device and the method for fabricating the device of the eighth embodiment.

[0140] As shown in FIG. 13, isolations 801 are formed in a silicon substrate 800, and then a polymetal gate electrode and a polysilicon resistor are formed in the same manner as in the fourth embodiment.

[0141] Specifically, a first silicon oxide film 802 is formed on the silicon substrate 800, and then a polysilicon film 803 is deposited over the first silicon oxide film 802. Thereafter, boron (B) ions are implanted using a resist pattern as a mask, thereby defining a p-type semiconductor region in the polysilicon film 803. Subsequently, phosphorus (P) ions are implanted using a resist pattern as a mask, thereby defining an n-type semiconductor region in the polysilicon film 803. At this time, the p-type semiconductor region is surrounded with the n-type semiconductor region and isolated in the shape of an island. Subsequently, a second silicon oxide film is formed on the polysilicon film 803, and then is etched with a buffered hydrofluoric acid using a resist pattern as a mask so that the second silicon oxide film is removed except for portions where a resistor and a capacitor are to be formed, thereby forming a silicon oxide film 804. In this case, no heat treatment is performed on the second silicon oxide film so that the second silicon oxide film has a high leakage current density, while being an insulating film. Accordingly, the second silicon oxide film serves as a leakage path for charge in the p-type semiconductor region so that charge in the p-type semiconductor region is emitted to the outside through the second silicon oxide film. As a result, it is possible to prevent polysilicon from disappearing during etching. This effect is the same if the polysilicon film 803 formed under the silicon oxide film 804 is an n-type semiconductor region.

[0142] Thereafter, a TiN film 805, a W film 806 and a SiN film 807 are deposited and then patterned, thereby forming a polysilicon resistor, a polymetal gate electrode and a capacitor (not shown). Specifically, the TiN film 805 and the W film 806 are deposited in this order, and then the SiN film 807 is deposited under a reduced pressure. Then, a resist is formed over the SiN film 807 and then patterning is performed in the manner that the resist remains on portions to be both edges of a polysilicon resistor, a portion to be a gate electrode and a portion to be a capacitor. Thereafter, the SiN film 807 is patterned by dry etching to serve as a hard mask. Then, after the resist has been removed, dry etching is performed, thereby forming a polysilicon resistor, a polymetal gate electrode and a capacitor.

[0143] Then, the silicon substrate 800 is doped with an impurity using the polymetal gate electrode as a mask, thereby forming a lightly doped layer 808. Subsequently, a silicon nitride film is deposited over the entire surface of the silicon substrate 800, and then is subjected to anisotropic etching, thereby forming a sidewall 809 on the side of the gate electrode. Thereafter, the silicon substrate 800 is doped with an impurity using the polymetal gate electrode and the sidewall 809 as a mask, thereby forming a heavily doped layer 810.

[0144] Then, heat treatment is performed on the silicon substrate 800 to activate the lightly doped layer 808 and the heavily doped layer 810. Thereafter, a cobalt film is formed, and finally a cobalt silicide film 811 is formed by heat treatment in the surface of source and drain regions. In this manner, a semiconductor device including an MOS transistor, a polysilicon resistor or a capacitor is formed.

[0145] Embodiment 9

[0146] Hereinafter, a semiconductor device and a method for fabricating the semiconductor device according to a ninth embodiment of the present invention will be described with reference to FIGS. 14A and 14B.

[0147]FIGS. 14A and 14B are cross-sectional views for describing the semiconductor device and the method for fabricating the device of the ninth embodiment.

[0148] As shown in FIG. 14A, isolations 901 are formed in a silicon substrate 900. Subsequently, a silicon oxide film is formed on the silicon substrate 900 and then is etched with a hydrofluoric acid using a resist pattern as a mask, thereby partly removing the silicon oxide film and exposing the substrate 900. Thereafter, the resist is removed, and then high-temperature heat treatment is performed in an oxygen atmosphere. In this manner, the exposed portion of the silicon substrate 900 is oxidized to form a second silicon oxide film 903. In this case, the thermal oxidation increases the thickness of the silicon oxide film firstly formed, thereby forming a first silicon oxide film 902. At this time, the second silicon oxide film 903 is formed to have a thickness which allows easy tunneling of charge.

[0149] Next, a polysilicon film 904 is deposited over the first silicon oxide film 902 and the second silicon oxide film 903. Thereafter, boron (B) ions are implanted using a resist pattern as a mask, thereby defining a p-type semiconductor region 904A in the polysilicon film 904. Subsequently, phosphorus (P) ions are implanted using a resist pattern as a mask, thereby defining an n-type semiconductor region 904B in the polysilicon film 904. Subsequently, patterning is performed to form patterned p-type and n-type semiconductor regions 904A and 904B.

[0150] Then, as shown in FIG. 14B, the silicon substrate 900 is doped with an impurity using the patterned p-type and n-type semiconductor regions 904A and 904B as a mask, thereby forming a lightly doped layer 905. Subsequently, a silicon nitride film is deposited over the entire surface of the silicon substrate 900, and then is subjected to anisotropic etching, thereby forming sidewalls 906 on the sides of the patterned p-type and n-type semiconductor regions 904A and 904B. Thereafter, the silicon substrate 900 is doped with an impurity using the patterned p-type and n-type semiconductor regions 904A and 904B and the sidewalls 906 as a mask, thereby forming a heavily doped layer 907.

[0151] Then, heat treatment is performed on the silicon substrate 900 to activate the lightly doped layer 905 and the heavily doped layer 907. With respect to the patterned p-type and n-type semiconductor regions 904A and 904B, implantation of, for example, boron ions may be performed before patterning. That is to say, implantation is not necessarily performed before patterning, and the implantation of the high-concentration impurity may also serve as the implantation for the patterned p-type or n-type semiconductor region 904A or 904B instead. Thereafter, a third silicon oxide film is formed on the p-type and n-type semiconductor regions 904A and 904B and then is heated rapidly at 850 C.

[0152] At this time, the patterned p-type and n-type semiconductor regions 904A and 904B are surrounded with the insulating films, which are oxide films, on all sides vertically and horizontally, and the second silicon oxide film 903 is formed under each of the patterned p-type and n-type semiconductor regions 904A and 904B. In this case, the second silicon oxide film 903 serves as a leakage path so that charge in the patterned p-type and n-type semiconductor regions 904A and 904B is emitted toward the silicon substrate 900 through the second silicon oxide film 903. Although not shown, in a case where there is a region in which the patterned p-type and n-type semiconductor regions 904A and 904B are continuous, the second silicon oxide film 903 is preferably formed under each of the patterned p-type and n-type semiconductor regions 904A and 904B.

[0153] Then, etching is performed with a hydrofluoric acid using a resist pattern as a mask, thereby removing the third silicon oxide film except for a portion where a resistor is to be formed, thereby forming a silicon oxide film 908. At this time, the second silicon oxide film 903 serves as a leakage path so that charge in the p-type semiconductor region 904A is emitted toward the silicon substrate 900 through the second silicon oxide film 903. As a result, it is possible to prevent polysilicon from disappearing during etching.

[0154] Subsequently, a cobalt silicide film 909 is formed in the heavily doped layer 907 and the patterned p-type and n-type semiconductor regions 904A and 904B from which the third silicon oxide film has been removed, thus forming a semiconductor device including an MOS transistor or a polysilicon resistor. Since the silicon oxide film 908 prevents formation of a cobalt silicide, a polysilicon resistor is formed at the left-hand side of FIG. 14B. Thereafter, contacts (not shown) are formed on the cobalt silicide film 909 at both ends of the polysilicon resistor. At the right-hand side of FIG. 14B, the patterned n-type semiconductor region 904B serves as a cobalt silicide gate electrode.

[0155] In the foregoing description, the patterned n-type semiconductor region 904B serves as a cobalt silicide gate electrode, and no cobalt silicide is formed in part of the patterned p-type semiconductor region 904A which serves as a polysilicon resistor. Alternatively, the patterned p-type semiconductor region 904A may serve as a cobalt silicide gate electrode and the patterned n-type semiconductor region 904B may have a region in which no cobalt silicide is formed and which serves as a polysilicon resistor.

[0156] Embodiment 10

[0157] Hereinafter, a semiconductor device and a method for fabricating the semiconductor device according to a tenth embodiment of the present invention will be described with reference to FIGS. 15A and 15B.

[0158]FIGS. 15A and 15B are cross-sectional views for describing the semiconductor device and the method for fabricating the device of the tenth embodiment.

[0159] As shown in FIG. 15A, isolations 1001 are formed in a silicon substrate 1000. Subsequently, a first silicon oxide film 1002 is formed on the silicon substrate 1000, and then a polysilicon film 1003 is deposited over the first silicon oxide film 1002. Thereafter, boron (B) ions are implanted using a resist pattern as a mask, thereby defining a p-type semiconductor region 1003A in the polysilicon film 1003. Subsequently, phosphorus (P) ions are implanted using a resist pattern as a mask, thereby defining an n-type semiconductor region 1003B in the polysilicon film 1003. Thereafter, patterning is performed to form patterned p-type and n-type semiconductor regions 1003A and 1003B.

[0160] Then, as shown in FIG. 15B, the silicon substrate 1000 is doped with an impurity using the patterned p-type and n-type semiconductor regions 1003A and 1003B as a mask, thereby forming a lightly doped layer 1004. Subsequently, a silicon nitride film is deposited over the entire surface of the silicon substrate 1000, and then is subjected to anisotropic etching, thereby forming sidewalls 1005 on the sides of the patterned p-type and n-type semiconductor regions 1003A and 1003B. Thereafter, the silicon substrate 1000 is doped with an impurity using the patterned p-type and n-type semiconductor regions 1003A and 1003B and the sidewalls 1005 as a mask, thereby forming a heavily doped layer 1006.

[0161] Then, heat treatment is performed on the silicon substrate 1000 to activate the lightly doped layer 1004 and the heavily doped layer 1006. With respect to the patterned p-type and n-type semiconductor regions 1003A and 1003B, implantation of, for example, boron ions may be performed before the patterning. That is to say, the implantation is not necessarily performed before patterning, and the implantation of the high-concentration impurity may also serve as the implantation for the patterned p-type or n-type semiconductor region 1003A or 1003B instead. Thereafter, a second silicon oxide film is formed over the p-type and n-type semiconductor regions 1003A and 1003B.

[0162] At this time, the patterned p-type and n-type semiconductor regions 1003A and 1003B are surrounded with the insulating films, which are oxide films, on all sides vertically and horizontally. In this case, no heat treatment is performed on the second silicon oxide film so that the second silicon oxide film has a high leakage current density, while being an insulating film. Accordingly, the second silicon oxide film serves as a leakage path for charge in the patterned p-type semiconductor region 1003A so that charge in the patterned p-type semiconductor regions 1003A is emitted to the outside of the second silicon oxide film through the second silicon oxide film. Although not shown, there may be a region in which the patterned p-type and n-type semiconductor regions 1003A and 1003B are continuous.

[0163] Then, etching is performed with a hydrofluoric acid using a resist pattern as a mask, thereby partly removing the second silicon oxide film except for a portion where a resistor is to be formed, thereby forming a silicon oxide film 1007. At this time, the second silicon oxide film serves as a leakage path so that charge in the patterned p-type semiconductor region 1003A is emitted to the outside through the second silicon oxide film. As a result, it is possible to prevent polysilicon from disappearing during etching.

[0164] Subsequently, a cobalt silicide film 1008 is formed in the heavily doped layer 1006 and the patterned p-type and n-type semiconductor regions 1003A and 1003B from which the second silicon oxide film has been removed, thus forming a semiconductor device including an MOS transistor or a polysilicon resistor. Since the silicon oxide film 1007 prevents formation of a cobalt silicide, a polysilicon resistor is formed at the left-hand side of FIG. 15B. Thereafter, contacts (not shown) are formed on the cobalt silicide film 1008 at both ends of the polysilicon resistor. At the right-hand side of FIG. 15B, the patterned n-type semiconductor region 1003B serves as a cobalt silicide gate electrode.

[0165] In the foregoing description, the patterned n-type semiconductor region 1003B serves as a cobalt silicide gate electrode, and no cobalt silicide is formed in part of the patterned p-type semiconductor region 1003A which serves as a polysilicon resistor. Alternatively, the patterned p-type semiconductor region 1003A may serve as a cobalt silicide gate electrode and the patterned n-type semiconductor region 1003B may have a region in which no cobalt silicide is formed and which serves as a polysilicon resistor.

[0166] It is sufficient for the second silicon oxide film of the first, third, fifth, seventh and ninth embodiments to have a high leakage current density, and the thickness thereof is not necessarily small. Accordingly, the second silicon oxide film may be a film with a different property or a film of a different type, or may be made of a plurality of films having two or more different leakage current densities.

[0167] It is sufficient that the silicon oxide film deposited on polysilicon described in the first, third, fifth, seventh and ninth embodiments is an insulating film. Accordingly, for example, the silicon oxide film may be an undoped silicon oxide film formed under sub atmospheric conditions (SA-NSG film), a silicon nitride film, or a silicon oxide film made of a TEOS film or the like formed under a reduced pressure.

[0168] The silicon oxide film serving as a leakage path for charge described in the second, fourth, sixth, eighth and tenth embodiments is typified by an undoped silicon oxide film formed under sub atmospheric conditions (SA-NSG film) having a high leakage current density. However, the silicon oxide film may be a film with a different property or a film of a different type so long as the silicon oxide film is an insulating film having a high leakage current density. For example, the leakage current density also changes depending on whether or not the insulating film is annealed after formation of a CVD insulating film. If the insulating film is not annealed, a high leakage current density is obtained.

[0169] As described above, according to the inventive semiconductor devices and the methods for fabricating the devices, a leakage insulating film for emitting charge in a semiconductor region of a conductivity type is provided, so that it is possible to prevent the disappearance of polysilicon occurring when any part of the semiconductor region of the conductivity type is exposed to the outside during wet etching. Accordingly, the fault that the gate opens due to the disappearance of polysilicon is prevented. In addition, a short-circuit fault at the gate due to entering of metal into a portion where polysilicon has disappeared is also prevented. Moreover, reduction in the insulating property of a gate insulating film is prevented, resulting in improving the reliability.

Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US7332403 *Jul 11, 2005Feb 19, 2008National Semiconductor CorporationSystem and method for providing a buried thin film resistor having end caps defined by a dielectric mask
US7808048Oct 15, 2007Oct 5, 2010National Semiconductor CorporationSystem and method for providing a buried thin film resistor having end caps defined by a dielectric mask
US7829428Aug 26, 2008Nov 9, 2010National Semiconductor CorporationMethod for eliminating a mask layer during thin film resistor manufacturing
US7906816 *Feb 3, 2006Mar 15, 2011Kabushiki Kaisha ToshibaSemiconductor integrated circuit device including memory cells having floating gates and resistor elements
US7960240Jul 9, 2008Jun 14, 2011National Semiconductor CorporationSystem and method for providing a dual via architecture for thin film resistors
US8436424 *Jul 30, 2008May 7, 2013Sony CorporationSemiconductor device and method of manufacturing the same
US20130307084 *Jul 24, 2013Nov 21, 2013United Microelectronics Corp.Resistor integrated with transistor having metal gate
Classifications
U.S. Classification257/379, 257/364, 438/210, 438/200, 257/536, 257/E27.016
International ClassificationH01L21/822, H01L21/8234, H01L27/088, H01L27/06, H01L27/04
Cooperative ClassificationH01L27/0629
European ClassificationH01L27/06D4V
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